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Merge branch 'for-v6.15/samsung-clk-dt-bindings' into next/clk
This commit is contained in:
Krzysztof Kozlowski
commit
d434e7851c
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@ -0,0 +1,247 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos2200 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos2200 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clocks in that root tree
|
||||
are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be
|
||||
defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos2200-cmu-alive
|
||||
- samsung,exynos2200-cmu-cmgp
|
||||
- samsung,exynos2200-cmu-hsi0
|
||||
- samsung,exynos2200-cmu-peric0
|
||||
- samsung,exynos2200-cmu-peric1
|
||||
- samsung,exynos2200-cmu-peric2
|
||||
- samsung,exynos2200-cmu-peris
|
||||
- samsung,exynos2200-cmu-top
|
||||
- samsung,exynos2200-cmu-ufs
|
||||
- samsung,exynos2200-cmu-vts
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 6
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-alive
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_ALIVE NOC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-cmgp
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_CMGP NOC clock (from CMU_TOP)
|
||||
- description: CMU_CMGP PERI clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: peri
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: External RTC clock (32768 Hz)
|
||||
- description: CMU_HSI0 NOC clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPOSC clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USB32DRD clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: rtcclk
|
||||
- const: noc
|
||||
- const: dpgtc
|
||||
- const: dposc
|
||||
- const: usb
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos2200-cmu-peric0
|
||||
- samsung,exynos2200-cmu-peric1
|
||||
- samsung,exynos2200-cmu-peric2
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_PERICn NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP0 clock (from CMU_TOP)
|
||||
- description: CMU_PERICn IP1 clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: ip0
|
||||
- const: ip1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-peris
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (25.6 MHz)
|
||||
- description: CMU_PERIS NOC clock (from CMU_TOP)
|
||||
- description: CMU_PERIS GIC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: tcxo_div3
|
||||
- const: noc
|
||||
- const: gic
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-ufs
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_UFS NOC clock (from CMU_TOP)
|
||||
- description: CMU_UFS MMC clock (from CMU_TOP)
|
||||
- description: CMU_UFS UFS clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: noc
|
||||
- const: mmc
|
||||
- const: ufs
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos2200-cmu-vts
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (76.8 MHz)
|
||||
- description: CMU_VTS DMIC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: dmic
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos2200-cmu.h>
|
||||
|
||||
cmu_vts: clock-controller@15300000 {
|
||||
compatible = "samsung,exynos2200-cmu-vts";
|
||||
reg = <0x15300000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_VTS_DMIC>;
|
||||
clock-names = "oscclk", "dmic";
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,227 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos7870 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Kaustabh Chakraborty <kauschluss@disroot.org>
|
||||
|
||||
description: |
|
||||
Exynos7870 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
include/dt-bindings/clock/samsung,exynos7870-cmu.h header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos7870-cmu-mif
|
||||
- samsung,exynos7870-cmu-dispaud
|
||||
- samsung,exynos7870-cmu-fsys
|
||||
- samsung,exynos7870-cmu-g3d
|
||||
- samsung,exynos7870-cmu-isp
|
||||
- samsung,exynos7870-cmu-mfcmscl
|
||||
- samsung,exynos7870-cmu-peri
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-mif
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-dispaud
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_DISPAUD bus clock (from CMU_MIF)
|
||||
- description: DECON external clock (from CMU_MIF)
|
||||
- description: DECON vertical clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: decon_eclk
|
||||
- const: decon_vclk
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-fsys
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_FSYS bus clock (from CMU_MIF)
|
||||
- description: USB20DRD clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: usb20drd
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-g3d
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: G3D switch clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: switch
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-isp
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: ISP camera clock (from CMU_MIF)
|
||||
- description: ISP clock (from CMU_MIF)
|
||||
- description: ISP VRA clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: cam
|
||||
- const: isp
|
||||
- const: vra
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-mfcmscl
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: MSCL clock (from CMU_MIF)
|
||||
- description: MFC clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: mfc
|
||||
- const: mscl
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos7870-cmu-peri
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_PERI bus clock (from CMU_MIF)
|
||||
- description: SPI0 clock (from CMU_MIF)
|
||||
- description: SPI1 clock (from CMU_MIF)
|
||||
- description: SPI2 clock (from CMU_MIF)
|
||||
- description: SPI3 clock (from CMU_MIF)
|
||||
- description: SPI4 clock (from CMU_MIF)
|
||||
- description: UART0 clock (from CMU_MIF)
|
||||
- description: UART1 clock (from CMU_MIF)
|
||||
- description: UART2 clock (from CMU_MIF)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: spi0
|
||||
- const: spi1
|
||||
- const: spi2
|
||||
- const: spi3
|
||||
- const: spi4
|
||||
- const: uart0
|
||||
- const: uart1
|
||||
- const: uart2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos7870-cmu.h>
|
||||
|
||||
cmu_peri: clock-controller@101f0000 {
|
||||
compatible = "samsung,exynos7870-cmu-peri";
|
||||
reg = <0x101f0000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clock-names = "oscclk", "bus", "spi0", "spi1", "spi2",
|
||||
"spi3", "spi4", "uart0", "uart1", "uart2";
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>,
|
||||
<&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>;
|
||||
};
|
||||
|
||||
...
|
||||
431
include/dt-bindings/clock/samsung,exynos2200-cmu.h
Normal file
431
include/dt-bindings/clock/samsung,exynos2200-cmu.h
Normal file
|
|
@ -0,0 +1,431 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2025 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
*
|
||||
* Device Tree binding constants for Exynos2200 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS2200_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SHARED4_PLL 5
|
||||
#define CLK_FOUT_MMC_PLL 6
|
||||
#define CLK_FOUT_SHARED_MIF_PLL 7
|
||||
|
||||
#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER 8
|
||||
#define CLK_MOUT_CMU_CP_MPLL_CLK_USER 9
|
||||
#define CLK_MOUT_CMU_AUD_AUDIF0 10
|
||||
#define CLK_MOUT_CMU_AUD_AUDIF1 11
|
||||
#define CLK_MOUT_CMU_AUD_CPU 12
|
||||
#define CLK_MOUT_CMU_CPUCL0_DBG_NOC 13
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 14
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 15
|
||||
#define CLK_MOUT_CMU_CPUCL2_SWITCH 16
|
||||
#define CLK_MOUT_CMU_DNC_NOC 17
|
||||
#define CLK_MOUT_CMU_DPUB_NOC 18
|
||||
#define CLK_MOUT_CMU_DPUF_NOC 19
|
||||
#define CLK_MOUT_CMU_DSP_NOC 20
|
||||
#define CLK_MOUT_CMU_DSU_SWITCH 21
|
||||
#define CLK_MOUT_CMU_G3D_SWITCH 22
|
||||
#define CLK_MOUT_CMU_GNPU_NOC 23
|
||||
#define CLK_MOUT_CMU_UFS_MMC_CARD 24
|
||||
#define CLK_MOUT_CMU_M2M_NOC 25
|
||||
#define CLK_MOUT_CMU_NOCL0_NOC 26
|
||||
#define CLK_MOUT_CMU_NOCL1A_NOC 27
|
||||
#define CLK_MOUT_CMU_NOCL1B_NOC0 28
|
||||
#define CLK_MOUT_CMU_NOCL1C_NOC 29
|
||||
#define CLK_MOUT_CMU_SDMA_NOC 30
|
||||
#define CLK_MOUT_CMU_CP_HISPEEDY_CLK 31
|
||||
#define CLK_MOUT_CMU_CP_SHARED0_CLK 32
|
||||
#define CLK_MOUT_CMU_CP_SHARED2_CLK 33
|
||||
#define CLK_MOUT_CMU_MUX_ALIVE_NOC 34
|
||||
#define CLK_MOUT_CMU_MUX_AUD_AUDIF0 35
|
||||
#define CLK_MOUT_CMU_MUX_AUD_AUDIF1 36
|
||||
#define CLK_MOUT_CMU_MUX_AUD_CPU 37
|
||||
#define CLK_MOUT_CMU_MUX_AUD_NOC 38
|
||||
#define CLK_MOUT_CMU_MUX_BRP_NOC 39
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK0 40
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK1 41
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK2 42
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK3 43
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK4 44
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK5 45
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK6 46
|
||||
#define CLK_MOUT_CMU_MUX_CIS_CLK7 47
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST 48
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM 49
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU 50
|
||||
#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF 51
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC 52
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP 53
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH 54
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH 55
|
||||
#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH 56
|
||||
#define CLK_MOUT_CMU_MUX_CSIS_DCPHY 57
|
||||
#define CLK_MOUT_CMU_MUX_CSIS_NOC 58
|
||||
#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU 59
|
||||
#define CLK_MOUT_CMU_MUX_CSTAT_NOC 60
|
||||
#define CLK_MOUT_CMU_MUX_DNC_NOC 61
|
||||
#define CLK_MOUT_CMU_MUX_DPUB 62
|
||||
#define CLK_MOUT_CMU_MUX_DPUB_ALT 63
|
||||
#define CLK_MOUT_CMU_MUX_DPUB_DSIM 64
|
||||
#define CLK_MOUT_CMU_MUX_DPUF 65
|
||||
#define CLK_MOUT_CMU_MUX_DPUF_ALT 66
|
||||
#define CLK_MOUT_CMU_MUX_DSP_NOC 67
|
||||
#define CLK_MOUT_CMU_MUX_DSU_SWITCH 68
|
||||
#define CLK_MOUT_CMU_MUX_G3D_NOCP 69
|
||||
#define CLK_MOUT_CMU_MUX_G3D_SWITCH 70
|
||||
#define CLK_MOUT_CMU_MUX_GNPU_NOC 71
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_DPGTC 72
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_DPOSC 73
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_NOC 74
|
||||
#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD 75
|
||||
#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD 76
|
||||
#define CLK_MOUT_CMU_MUX_HSI1_NOC 77
|
||||
#define CLK_MOUT_CMU_MUX_HSI1_PCIE 78
|
||||
#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD 79
|
||||
#define CLK_MOUT_CMU_MUX_LME_LME 80
|
||||
#define CLK_MOUT_CMU_MUX_LME_NOC 81
|
||||
#define CLK_MOUT_CMU_MUX_M2M_NOC 82
|
||||
#define CLK_MOUT_CMU_MUX_MCSC_MCSC 83
|
||||
#define CLK_MOUT_CMU_MUX_MCSC_NOC 84
|
||||
#define CLK_MOUT_CMU_MUX_MFC0_MFC0 85
|
||||
#define CLK_MOUT_CMU_MUX_MFC0_WFD 86
|
||||
#define CLK_MOUT_CMU_MUX_MFC1_MFC1 87
|
||||
#define CLK_MOUT_CMU_MUX_MIF_NOCP 88
|
||||
#define CLK_MOUT_CMU_MUX_MIF_SWITCH 89
|
||||
#define CLK_MOUT_CMU_MUX_NOCL0_NOC 90
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1A_NOC 91
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0 92
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1 93
|
||||
#define CLK_MOUT_CMU_MUX_NOCL1C_NOC 94
|
||||
#define CLK_MOUT_CMU_MUX_PERIC0_IP0 95
|
||||
#define CLK_MOUT_CMU_MUX_PERIC0_IP1 96
|
||||
#define CLK_MOUT_CMU_MUX_PERIC0_NOC 97
|
||||
#define CLK_MOUT_CMU_MUX_PERIC1_IP0 98
|
||||
#define CLK_MOUT_CMU_MUX_PERIC1_IP1 99
|
||||
#define CLK_MOUT_CMU_MUX_PERIC1_NOC 100
|
||||
#define CLK_MOUT_CMU_MUX_PERIC2_IP0 101
|
||||
#define CLK_MOUT_CMU_MUX_PERIC2_IP1 102
|
||||
#define CLK_MOUT_CMU_MUX_PERIC2_NOC 103
|
||||
#define CLK_MOUT_CMU_MUX_PERIS_GIC 104
|
||||
#define CLK_MOUT_CMU_MUX_PERIS_NOC 105
|
||||
#define CLK_MOUT_CMU_MUX_SDMA_NOC 106
|
||||
#define CLK_MOUT_CMU_MUX_SSP_NOC 107
|
||||
#define CLK_MOUT_CMU_MUX_VTS_DMIC 108
|
||||
#define CLK_MOUT_CMU_MUX_YUVP_NOC 109
|
||||
#define CLK_MOUT_CMU_MUX_CMU_CMUREF 110
|
||||
#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK 111
|
||||
#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK 112
|
||||
#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK 113
|
||||
#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK 114
|
||||
#define CLK_MOUT_CMU_M2M_FRC 115
|
||||
#define CLK_MOUT_CMU_MCSC_MCSC 116
|
||||
#define CLK_MOUT_CMU_MCSC_NOC 117
|
||||
#define CLK_MOUT_CMU_MUX_M2M_FRC 118
|
||||
#define CLK_MOUT_CMU_MUX_UFS_NOC 119
|
||||
|
||||
#define CLK_DOUT_CMU_ALIVE_NOC 120
|
||||
#define CLK_DOUT_CMU_AUD_NOC 121
|
||||
#define CLK_DOUT_CMU_BRP_NOC 122
|
||||
#define CLK_DOUT_CMU_CMU_BOOST 123
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CAM 124
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CPU 125
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_MIF 126
|
||||
#define CLK_DOUT_CMU_CPUCL0_NOCP 127
|
||||
#define CLK_DOUT_CMU_CSIS_DCPHY 128
|
||||
#define CLK_DOUT_CMU_CSIS_NOC 129
|
||||
#define CLK_DOUT_CMU_CSIS_OIS_MCU 130
|
||||
#define CLK_DOUT_CMU_CSTAT_NOC 131
|
||||
#define CLK_DOUT_CMU_DPUB_DSIM 132
|
||||
#define CLK_DOUT_CMU_LME_LME 133
|
||||
#define CLK_DOUT_CMU_G3D_NOCP 134
|
||||
#define CLK_DOUT_CMU_HSI0_DPGTC 135
|
||||
#define CLK_DOUT_CMU_HSI0_DPOSC 136
|
||||
#define CLK_DOUT_CMU_HSI0_NOC 137
|
||||
#define CLK_DOUT_CMU_HSI0_USB32DRD 138
|
||||
#define CLK_DOUT_CMU_HSI1_NOC 139
|
||||
#define CLK_DOUT_CMU_HSI1_PCIE 140
|
||||
#define CLK_DOUT_CMU_UFS_UFS_EMBD 141
|
||||
#define CLK_DOUT_CMU_LME_NOC 142
|
||||
#define CLK_DOUT_CMU_MFC0_MFC0 143
|
||||
#define CLK_DOUT_CMU_MFC0_WFD 144
|
||||
#define CLK_DOUT_CMU_MFC1_MFC1 145
|
||||
#define CLK_DOUT_CMU_MIF_NOCP 146
|
||||
#define CLK_DOUT_CMU_NOCL1B_NOC1 147
|
||||
#define CLK_DOUT_CMU_PERIC0_IP0 148
|
||||
#define CLK_DOUT_CMU_PERIC0_IP1 149
|
||||
#define CLK_DOUT_CMU_PERIC0_NOC 150
|
||||
#define CLK_DOUT_CMU_PERIC1_IP0 151
|
||||
#define CLK_DOUT_CMU_PERIC1_IP1 152
|
||||
#define CLK_DOUT_CMU_PERIC1_NOC 153
|
||||
#define CLK_DOUT_CMU_PERIC2_IP0 154
|
||||
#define CLK_DOUT_CMU_PERIC2_IP1 155
|
||||
#define CLK_DOUT_CMU_PERIC2_NOC 156
|
||||
#define CLK_DOUT_CMU_PERIS_GIC 157
|
||||
#define CLK_DOUT_CMU_PERIS_NOC 158
|
||||
#define CLK_DOUT_CMU_SSP_NOC 159
|
||||
#define CLK_DOUT_CMU_VTS_DMIC 160
|
||||
#define CLK_DOUT_CMU_YUVP_NOC 161
|
||||
#define CLK_DOUT_CMU_CP_SHARED1_CLK 162
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF0 163
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM 164
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF1 165
|
||||
#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM 166
|
||||
#define CLK_DOUT_CMU_DIV_AUD_CPU 167
|
||||
#define CLK_DOUT_CMU_DIV_AUD_CPU_SM 168
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK0 169
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK1 170
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK2 171
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK3 172
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK4 173
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK5 174
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK6 175
|
||||
#define CLK_DOUT_CMU_DIV_CIS_CLK7 176
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC 177
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM 178
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH 179
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM 180
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH 181
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM 182
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH 183
|
||||
#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM 184
|
||||
#define CLK_DOUT_CMU_DIV_DNC_NOC 185
|
||||
#define CLK_DOUT_CMU_DIV_DNC_NOC_SM 186
|
||||
#define CLK_DOUT_CMU_DIV_DPUB 187
|
||||
#define CLK_DOUT_CMU_DIV_DPUB_ALT 188
|
||||
#define CLK_DOUT_CMU_DIV_DPUF 189
|
||||
#define CLK_DOUT_CMU_DIV_DPUF_ALT 190
|
||||
#define CLK_DOUT_CMU_DIV_DSP_NOC 191
|
||||
#define CLK_DOUT_CMU_DIV_DSP_NOC_SM 192
|
||||
#define CLK_DOUT_CMU_DIV_DSU_SWITCH 193
|
||||
#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM 194
|
||||
#define CLK_DOUT_CMU_DIV_G3D_SWITCH 195
|
||||
#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM 196
|
||||
#define CLK_DOUT_CMU_DIV_GNPU_NOC 197
|
||||
#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM 198
|
||||
#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD 199
|
||||
#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM 200
|
||||
#define CLK_DOUT_CMU_DIV_M2M_NOC 201
|
||||
#define CLK_DOUT_CMU_DIV_M2M_NOC_SM 202
|
||||
#define CLK_DOUT_CMU_DIV_NOCL0_NOC 203
|
||||
#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM 204
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1A_NOC 205
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM 206
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0 207
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM 208
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1C_NOC 209
|
||||
#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM 210
|
||||
#define CLK_DOUT_CMU_DIV_SDMA_NOC 211
|
||||
#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM 212
|
||||
#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK 213
|
||||
#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM 214
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK 215
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM 216
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK 217
|
||||
#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM 218
|
||||
#define CLK_DOUT_CMU_UFS_NOC 219
|
||||
#define CLK_DOUT_CMU_DIV_M2M_FRC 220
|
||||
#define CLK_DOUT_CMU_DIV_M2M_FRC_SM 221
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_MCSC 222
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM 223
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_NOC 224
|
||||
#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM 225
|
||||
#define CLK_DOUT_SHARED0_DIV1 226
|
||||
#define CLK_DOUT_SHARED0_DIV2 227
|
||||
#define CLK_DOUT_SHARED0_DIV4 228
|
||||
#define CLK_DOUT_SHARED1_DIV1 229
|
||||
#define CLK_DOUT_SHARED1_DIV2 230
|
||||
#define CLK_DOUT_SHARED1_DIV4 231
|
||||
#define CLK_DOUT_SHARED2_DIV1 232
|
||||
#define CLK_DOUT_SHARED2_DIV2 233
|
||||
#define CLK_DOUT_SHARED2_DIV4 234
|
||||
#define CLK_DOUT_SHARED3_DIV1 235
|
||||
#define CLK_DOUT_SHARED3_DIV2 236
|
||||
#define CLK_DOUT_SHARED3_DIV4 237
|
||||
#define CLK_DOUT_SHARED4_DIV1 238
|
||||
#define CLK_DOUT_SHARED4_DIV2 239
|
||||
#define CLK_DOUT_SHARED4_DIV4 240
|
||||
#define CLK_DOUT_SHARED_MIF_DIV1 241
|
||||
#define CLK_DOUT_SHARED_MIF_DIV2 242
|
||||
#define CLK_DOUT_SHARED_MIF_DIV4 243
|
||||
#define CLK_DOUT_TCXO_DIV3 244
|
||||
#define CLK_DOUT_TCXO_DIV4 245
|
||||
|
||||
/* CMU_ALIVE */
|
||||
#define CLK_MOUT_ALIVE_NOC_USER 1
|
||||
#define CLK_MOUT_ALIVE_RCO_SPMI_USER 2
|
||||
#define CLK_MOUT_RCO_ALIVE_USER 3
|
||||
#define CLK_MOUT_ALIVE_CHUB_PERI 4
|
||||
#define CLK_MOUT_ALIVE_CMGP_NOC 5
|
||||
#define CLK_MOUT_ALIVE_CMGP_PERI 6
|
||||
#define CLK_MOUT_ALIVE_DBGCORE_NOC 7
|
||||
#define CLK_MOUT_ALIVE_DNC_NOC 8
|
||||
#define CLK_MOUT_ALIVE_CHUBVTS_NOC 9
|
||||
#define CLK_MOUT_ALIVE_GNPU_NOC 10
|
||||
#define CLK_MOUT_ALIVE_GNSS_NOC 11
|
||||
#define CLK_MOUT_ALIVE_SDMA_NOC 12
|
||||
#define CLK_MOUT_ALIVE_UFD_NOC 13
|
||||
#define CLK_MOUT_ALIVE_DBGCORE_UART 14
|
||||
#define CLK_MOUT_ALIVE_NOC 15
|
||||
#define CLK_MOUT_ALIVE_PMU_SUB 16
|
||||
#define CLK_MOUT_ALIVE_SPMI 17
|
||||
#define CLK_MOUT_ALIVE_TIMER 18
|
||||
#define CLK_MOUT_ALIVE_CSIS_NOC 19
|
||||
#define CLK_MOUT_ALIVE_DSP_NOC 20
|
||||
|
||||
#define CLK_DOUT_ALIVE_CHUB_PERI 21
|
||||
#define CLK_DOUT_ALIVE_CMGP_NOC 22
|
||||
#define CLK_DOUT_ALIVE_CMGP_PERI 23
|
||||
#define CLK_DOUT_ALIVE_DBGCORE_NOC 24
|
||||
#define CLK_DOUT_ALIVE_DNC_NOC 25
|
||||
#define CLK_DOUT_ALIVE_CHUBVTS_NOC 26
|
||||
#define CLK_DOUT_ALIVE_GNPU_NOC 27
|
||||
#define CLK_DOUT_ALIVE_SDMA_NOC 28
|
||||
#define CLK_DOUT_ALIVE_UFD_NOC 29
|
||||
#define CLK_DOUT_ALIVE_DBGCORE_UART 30
|
||||
#define CLK_DOUT_ALIVE_NOC 31
|
||||
#define CLK_DOUT_ALIVE_PMU_SUB 32
|
||||
#define CLK_DOUT_ALIVE_SPMI 33
|
||||
#define CLK_DOUT_ALIVE_CSIS_NOC 34
|
||||
#define CLK_DOUT_ALIVE_DSP_NOC 35
|
||||
|
||||
/* CMU_PERIS */
|
||||
#define CLK_MOUT_PERIS_GIC_USER 1
|
||||
#define CLK_MOUT_PERIS_NOC_USER 2
|
||||
#define CLK_MOUT_PERIS_GIC 3
|
||||
|
||||
#define CLK_DOUT_PERIS_OTP 4
|
||||
#define CLK_DOUT_PERIS_DDD_CTRL 5
|
||||
|
||||
/* CMU_CMGP */
|
||||
#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER 1
|
||||
#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER 2
|
||||
#define CLK_MOUT_CMGP_I2C 3
|
||||
#define CLK_MOUT_CMGP_SPI_I2C0 4
|
||||
#define CLK_MOUT_CMGP_SPI_I2C1 5
|
||||
#define CLK_MOUT_CMGP_SPI_MS_CTRL 6
|
||||
#define CLK_MOUT_CMGP_USI0 7
|
||||
#define CLK_MOUT_CMGP_USI1 8
|
||||
#define CLK_MOUT_CMGP_USI2 9
|
||||
#define CLK_MOUT_CMGP_USI3 10
|
||||
#define CLK_MOUT_CMGP_USI4 11
|
||||
#define CLK_MOUT_CMGP_USI5 12
|
||||
#define CLK_MOUT_CMGP_USI6 13
|
||||
|
||||
#define CLK_DOUT_CMGP_I2C 14
|
||||
#define CLK_DOUT_CMGP_SPI_I2C0 15
|
||||
#define CLK_DOUT_CMGP_SPI_I2C1 16
|
||||
#define CLK_DOUT_CMGP_SPI_MS_CTRL 17
|
||||
#define CLK_DOUT_CMGP_USI0 18
|
||||
#define CLK_DOUT_CMGP_USI1 19
|
||||
#define CLK_DOUT_CMGP_USI2 20
|
||||
#define CLK_DOUT_CMGP_USI3 21
|
||||
#define CLK_DOUT_CMGP_USI4 22
|
||||
#define CLK_DOUT_CMGP_USI5 23
|
||||
#define CLK_DOUT_CMGP_USI6 24
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER 1
|
||||
#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER 2
|
||||
#define CLK_MOUT_CLKCMU_HSI0_NOC_USER 3
|
||||
#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER 4
|
||||
#define CLK_MOUT_HSI0_NOC 5
|
||||
#define CLK_MOUT_HSI0_RTCCLK 6
|
||||
#define CLK_MOUT_HSI0_USB32DRD 7
|
||||
|
||||
#define CLK_DOUT_DIV_CLK_HSI0_EUSB 8
|
||||
|
||||
/* CMU_PERIC0 */
|
||||
#define CLK_MOUT_PERIC0_IP0_USER 1
|
||||
#define CLK_MOUT_PERIC0_IP1_USER 2
|
||||
#define CLK_MOUT_PERIC0_NOC_USER 3
|
||||
#define CLK_MOUT_PERIC0_I2C 4
|
||||
#define CLK_MOUT_PERIC0_USI04 5
|
||||
|
||||
#define CLK_DOUT_PERIC0_I2C 6
|
||||
#define CLK_DOUT_PERIC0_USI04 7
|
||||
|
||||
/* CMU_PERIC1 */
|
||||
#define CLK_MOUT_PERIC1_IP0_USER 1
|
||||
#define CLK_MOUT_PERIC1_IP1_USER 2
|
||||
#define CLK_MOUT_PERIC1_NOC_USER 3
|
||||
#define CLK_MOUT_PERIC1_I2C 4
|
||||
#define CLK_MOUT_PERIC1_SPI_MS_CTRL 5
|
||||
#define CLK_MOUT_PERIC1_UART_BT 6
|
||||
#define CLK_MOUT_PERIC1_USI07 7
|
||||
#define CLK_MOUT_PERIC1_USI07_SPI_I2C 8
|
||||
#define CLK_MOUT_PERIC1_USI08 9
|
||||
#define CLK_MOUT_PERIC1_USI08_SPI_I2C 10
|
||||
#define CLK_MOUT_PERIC1_USI09 11
|
||||
#define CLK_MOUT_PERIC1_USI10 12
|
||||
|
||||
#define CLK_DOUT_PERIC1_I2C 13
|
||||
#define CLK_DOUT_PERIC1_SPI_MS_CTRL 14
|
||||
#define CLK_DOUT_PERIC1_UART_BT 15
|
||||
#define CLK_DOUT_PERIC1_USI07 16
|
||||
#define CLK_DOUT_PERIC1_USI07_SPI_I2C 17
|
||||
#define CLK_DOUT_PERIC1_USI08 18
|
||||
#define CLK_DOUT_PERIC1_USI08_SPI_I2C 19
|
||||
#define CLK_DOUT_PERIC1_USI09 20
|
||||
#define CLK_DOUT_PERIC1_USI10 21
|
||||
|
||||
/* CMU_PERIC2 */
|
||||
#define CLK_MOUT_PERIC2_IP0_USER 1
|
||||
#define CLK_MOUT_PERIC2_IP1_USER 2
|
||||
#define CLK_MOUT_PERIC2_NOC_USER 3
|
||||
#define CLK_MOUT_PERIC2_I2C 4
|
||||
#define CLK_MOUT_PERIC2_SPI_MS_CTRL 5
|
||||
#define CLK_MOUT_PERIC2_UART_DBG 6
|
||||
#define CLK_MOUT_PERIC2_USI00 7
|
||||
#define CLK_MOUT_PERIC2_USI00_SPI_I2C 8
|
||||
#define CLK_MOUT_PERIC2_USI01 9
|
||||
#define CLK_MOUT_PERIC2_USI01_SPI_I2C 10
|
||||
#define CLK_MOUT_PERIC2_USI02 11
|
||||
#define CLK_MOUT_PERIC2_USI03 12
|
||||
#define CLK_MOUT_PERIC2_USI05 13
|
||||
#define CLK_MOUT_PERIC2_USI06 14
|
||||
#define CLK_MOUT_PERIC2_USI11 15
|
||||
|
||||
#define CLK_DOUT_PERIC2_I2C 16
|
||||
#define CLK_DOUT_PERIC2_SPI_MS_CTRL 17
|
||||
#define CLK_DOUT_PERIC2_UART_DBG 18
|
||||
#define CLK_DOUT_PERIC2_USI00 19
|
||||
#define CLK_DOUT_PERIC2_USI00_SPI_I2C 20
|
||||
#define CLK_DOUT_PERIC2_USI01 21
|
||||
#define CLK_DOUT_PERIC2_USI01_SPI_I2C 22
|
||||
#define CLK_DOUT_PERIC2_USI02 23
|
||||
#define CLK_DOUT_PERIC2_USI03 24
|
||||
#define CLK_DOUT_PERIC2_USI05 25
|
||||
#define CLK_DOUT_PERIC2_USI06 26
|
||||
#define CLK_DOUT_PERIC2_USI11 27
|
||||
|
||||
/* CMU_UFS */
|
||||
#define CLK_MOUT_UFS_MMC_CARD_USER 1
|
||||
#define CLK_MOUT_UFS_NOC_USER 2
|
||||
#define CLK_MOUT_UFS_UFS_EMBD_USER 3
|
||||
|
||||
/* CMU_VTS */
|
||||
#define CLK_MOUT_CLKALIVE_VTS_NOC_USER 1
|
||||
#define CLK_MOUT_CLKALIVE_VTS_RCO_USER 2
|
||||
#define CLK_MOUT_CLKCMU_VTS_DMIC_USER 3
|
||||
#define CLK_MOUT_CLKVTS_AUD_DMIC1 4
|
||||
#define CLK_MOUT_CLKVTS_NOC 5
|
||||
#define CLK_MOUT_CLKVTS_DMIC_PAD 6
|
||||
|
||||
#define CLK_DOUT_CLKVTS_AUD_DMIC0 7
|
||||
#define CLK_DOUT_CLKVTS_AUD_DMIC1 8
|
||||
#define CLK_DOUT_CLKVTS_CPU 9
|
||||
#define CLK_DOUT_CLKVTS_DMIC_IF 10
|
||||
#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2 11
|
||||
#define CLK_DOUT_CLKVTS_NOC 12
|
||||
#define CLK_DOUT_CLKVTS_SERIAL_LIF 13
|
||||
#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE 14
|
||||
|
||||
#endif
|
||||
324
include/dt-bindings/clock/samsung,exynos7870-cmu.h
Normal file
324
include/dt-bindings/clock/samsung,exynos7870-cmu.h
Normal file
|
|
@ -0,0 +1,324 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2015 Samsung Electronics Co., Ltd.
|
||||
* Author: Kaustabh Chakraborty <kauschluss@disroot.org>
|
||||
*
|
||||
* Device Tree binding constants for Exynos7870 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS7870_H
|
||||
|
||||
/* CMU_MIF */
|
||||
#define CLK_DOUT_MIF_APB 1
|
||||
#define CLK_DOUT_MIF_BUSD 2
|
||||
#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3
|
||||
#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4
|
||||
#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_BUS 6
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9
|
||||
#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10
|
||||
#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11
|
||||
#define CLK_DOUT_MIF_CMU_ISP_CAM 12
|
||||
#define CLK_DOUT_MIF_CMU_ISP_ISP 13
|
||||
#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14
|
||||
#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15
|
||||
#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16
|
||||
#define CLK_DOUT_MIF_CMU_ISP_VRA 17
|
||||
#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18
|
||||
#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19
|
||||
#define CLK_DOUT_MIF_CMU_PERI_BUS 20
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI0 21
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI1 22
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI2 23
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI3 24
|
||||
#define CLK_DOUT_MIF_CMU_PERI_SPI4 25
|
||||
#define CLK_DOUT_MIF_CMU_PERI_UART0 26
|
||||
#define CLK_DOUT_MIF_CMU_PERI_UART1 27
|
||||
#define CLK_DOUT_MIF_CMU_PERI_UART2 28
|
||||
#define CLK_DOUT_MIF_HSI2C 29
|
||||
#define CLK_FOUT_MIF_BUS_PLL 30
|
||||
#define CLK_FOUT_MIF_MEDIA_PLL 31
|
||||
#define CLK_FOUT_MIF_MEM_PLL 32
|
||||
#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33
|
||||
#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34
|
||||
#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_BUS 36
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39
|
||||
#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40
|
||||
#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41
|
||||
#define CLK_GOUT_MIF_CMU_ISP_CAM 42
|
||||
#define CLK_GOUT_MIF_CMU_ISP_ISP 43
|
||||
#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44
|
||||
#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45
|
||||
#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46
|
||||
#define CLK_GOUT_MIF_CMU_ISP_VRA 47
|
||||
#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48
|
||||
#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49
|
||||
#define CLK_GOUT_MIF_CMU_PERI_BUS 50
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI0 51
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI1 52
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI2 53
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI3 54
|
||||
#define CLK_GOUT_MIF_CMU_PERI_SPI4 55
|
||||
#define CLK_GOUT_MIF_CMU_PERI_UART0 56
|
||||
#define CLK_GOUT_MIF_CMU_PERI_UART1 57
|
||||
#define CLK_GOUT_MIF_CMU_PERI_UART2 58
|
||||
#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59
|
||||
#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60
|
||||
#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61
|
||||
#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62
|
||||
#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63
|
||||
#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64
|
||||
#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65
|
||||
#define CLK_GOUT_MIF_HSI2C_IPCLK 66
|
||||
#define CLK_GOUT_MIF_HSI2C_ITCLK 67
|
||||
#define CLK_GOUT_MIF_MUX_BUSD 68
|
||||
#define CLK_GOUT_MIF_MUX_BUS_PLL 69
|
||||
#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70
|
||||
#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71
|
||||
#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72
|
||||
#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77
|
||||
#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83
|
||||
#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84
|
||||
#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85
|
||||
#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94
|
||||
#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95
|
||||
#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96
|
||||
#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97
|
||||
#define CLK_GOUT_MIF_MUX_MEM_PLL 98
|
||||
#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99
|
||||
#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100
|
||||
#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101
|
||||
#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102
|
||||
#define CLK_MOUT_MIF_BUSD 103
|
||||
#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104
|
||||
#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105
|
||||
#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_BUS 107
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110
|
||||
#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111
|
||||
#define CLK_MOUT_MIF_CMU_ISP_CAM 112
|
||||
#define CLK_MOUT_MIF_CMU_ISP_ISP 113
|
||||
#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114
|
||||
#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115
|
||||
#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116
|
||||
#define CLK_MOUT_MIF_CMU_ISP_VRA 117
|
||||
#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118
|
||||
#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119
|
||||
#define CLK_MOUT_MIF_CMU_PERI_BUS 120
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI0 121
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI1 122
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI2 123
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI3 124
|
||||
#define CLK_MOUT_MIF_CMU_PERI_SPI4 125
|
||||
#define CLK_MOUT_MIF_CMU_PERI_UART0 126
|
||||
#define CLK_MOUT_MIF_CMU_PERI_UART1 127
|
||||
#define CLK_MOUT_MIF_CMU_PERI_UART2 128
|
||||
#define MIF_NR_CLK 129
|
||||
|
||||
/* CMU_DISPAUD */
|
||||
#define CLK_DOUT_DISPAUD_APB 1
|
||||
#define CLK_DOUT_DISPAUD_DECON_ECLK 2
|
||||
#define CLK_DOUT_DISPAUD_DECON_VCLK 3
|
||||
#define CLK_DOUT_DISPAUD_MI2S 4
|
||||
#define CLK_DOUT_DISPAUD_MIXER 5
|
||||
#define CLK_FOUT_DISPAUD_AUD_PLL 6
|
||||
#define CLK_FOUT_DISPAUD_PLL 7
|
||||
#define CLK_GOUT_DISPAUD_APB_AUD 8
|
||||
#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9
|
||||
#define CLK_GOUT_DISPAUD_APB_DISP 10
|
||||
#define CLK_GOUT_DISPAUD_BUS 11
|
||||
#define CLK_GOUT_DISPAUD_BUS_DISP 12
|
||||
#define CLK_GOUT_DISPAUD_BUS_PPMU 13
|
||||
#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14
|
||||
#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15
|
||||
#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16
|
||||
#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17
|
||||
#define CLK_GOUT_DISPAUD_DECON_ECLK 18
|
||||
#define CLK_GOUT_DISPAUD_DECON_VCLK 19
|
||||
#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20
|
||||
#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21
|
||||
#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22
|
||||
#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23
|
||||
#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24
|
||||
#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28
|
||||
#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29
|
||||
#define CLK_GOUT_DISPAUD_MUX_MI2S 30
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33
|
||||
#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34
|
||||
#define CLK_GOUT_DISPAUD_MUX_PLL 35
|
||||
#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36
|
||||
#define CLK_MOUT_DISPAUD_BUS_USER 37
|
||||
#define CLK_MOUT_DISPAUD_DECON_ECLK 38
|
||||
#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39
|
||||
#define CLK_MOUT_DISPAUD_DECON_VCLK 40
|
||||
#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41
|
||||
#define CLK_MOUT_DISPAUD_MI2S 42
|
||||
#define DISPAUD_NR_CLK 43
|
||||
|
||||
/* CMU_FSYS */
|
||||
#define CLK_FOUT_FSYS_USB_PLL 1
|
||||
#define CLK_GOUT_FSYS_BUSP3_HCLK 2
|
||||
#define CLK_GOUT_FSYS_MMC0_ACLK 3
|
||||
#define CLK_GOUT_FSYS_MMC1_ACLK 4
|
||||
#define CLK_GOUT_FSYS_MMC2_ACLK 5
|
||||
#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6
|
||||
#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7
|
||||
#define CLK_GOUT_FSYS_MUX_USB_PLL 8
|
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#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9
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#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10
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#define CLK_GOUT_FSYS_PPMU_ACLK 11
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#define CLK_GOUT_FSYS_PPMU_PCLK 12
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#define CLK_GOUT_FSYS_SROMC_HCLK 13
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#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14
|
||||
#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15
|
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#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16
|
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#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17
|
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#define FSYS_NR_CLK 18
|
||||
|
||||
/* CMU_G3D */
|
||||
#define CLK_DOUT_G3D_APB 1
|
||||
#define CLK_DOUT_G3D_BUS 2
|
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#define CLK_FOUT_G3D_PLL 3
|
||||
#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4
|
||||
#define CLK_GOUT_G3D_ASYNC_PCLKM 5
|
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#define CLK_GOUT_G3D_CLK 6
|
||||
#define CLK_GOUT_G3D_MUX 7
|
||||
#define CLK_GOUT_G3D_MUX_PLL 8
|
||||
#define CLK_GOUT_G3D_MUX_PLL_CON 9
|
||||
#define CLK_GOUT_G3D_MUX_SWITCH_USER 10
|
||||
#define CLK_GOUT_G3D_PPMU_ACLK 11
|
||||
#define CLK_GOUT_G3D_PPMU_PCLK 12
|
||||
#define CLK_GOUT_G3D_QE_ACLK 13
|
||||
#define CLK_GOUT_G3D_QE_PCLK 14
|
||||
#define CLK_GOUT_G3D_SYSREG_PCLK 15
|
||||
#define CLK_MOUT_G3D 16
|
||||
#define CLK_MOUT_G3D_SWITCH_USER 17
|
||||
#define G3D_NR_CLK 18
|
||||
|
||||
/* CMU_ISP */
|
||||
#define CLK_DOUT_ISP_APB 1
|
||||
#define CLK_DOUT_ISP_CAM_HALF 2
|
||||
#define CLK_FOUT_ISP_PLL 3
|
||||
#define CLK_GOUT_ISP_CAM 4
|
||||
#define CLK_GOUT_ISP_CAM_HALF 5
|
||||
#define CLK_GOUT_ISP_ISPD 6
|
||||
#define CLK_GOUT_ISP_ISPD_PPMU 7
|
||||
#define CLK_GOUT_ISP_MUX_CAM 8
|
||||
#define CLK_GOUT_ISP_MUX_CAM_USER 9
|
||||
#define CLK_GOUT_ISP_MUX_ISP 10
|
||||
#define CLK_GOUT_ISP_MUX_ISPD 11
|
||||
#define CLK_GOUT_ISP_MUX_PLL 12
|
||||
#define CLK_GOUT_ISP_MUX_PLL_CON 13
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16
|
||||
#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17
|
||||
#define CLK_GOUT_ISP_MUX_USER 18
|
||||
#define CLK_GOUT_ISP_MUX_VRA 19
|
||||
#define CLK_GOUT_ISP_MUX_VRA_USER 20
|
||||
#define CLK_GOUT_ISP_VRA 21
|
||||
#define CLK_MOUT_ISP_CAM 22
|
||||
#define CLK_MOUT_ISP_CAM_USER 23
|
||||
#define CLK_MOUT_ISP_ISP 24
|
||||
#define CLK_MOUT_ISP_ISPD 25
|
||||
#define CLK_MOUT_ISP_USER 26
|
||||
#define CLK_MOUT_ISP_VRA 27
|
||||
#define CLK_MOUT_ISP_VRA_USER 28
|
||||
#define ISP_NR_CLK 29
|
||||
|
||||
/* CMU_MFCMSCL */
|
||||
#define CLK_DOUT_MFCMSCL_APB 1
|
||||
#define CLK_GOUT_MFCMSCL_MFC 2
|
||||
#define CLK_GOUT_MFCMSCL_MSCL 3
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_BI 4
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_D 5
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_POLY 7
|
||||
#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8
|
||||
#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9
|
||||
#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10
|
||||
#define CLK_MOUT_MFCMSCL_MFC_USER 11
|
||||
#define CLK_MOUT_MFCMSCL_MSCL_USER 12
|
||||
#define MFCMSCL_NR_CLK 13
|
||||
|
||||
/* CMU_PERI */
|
||||
#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1
|
||||
#define CLK_GOUT_PERI_GPIO2_PCLK 2
|
||||
#define CLK_GOUT_PERI_GPIO5_PCLK 3
|
||||
#define CLK_GOUT_PERI_GPIO6_PCLK 4
|
||||
#define CLK_GOUT_PERI_GPIO7_PCLK 5
|
||||
#define CLK_GOUT_PERI_HSI2C1_IPCLK 6
|
||||
#define CLK_GOUT_PERI_HSI2C2_IPCLK 7
|
||||
#define CLK_GOUT_PERI_HSI2C3_IPCLK 8
|
||||
#define CLK_GOUT_PERI_HSI2C4_IPCLK 9
|
||||
#define CLK_GOUT_PERI_HSI2C5_IPCLK 10
|
||||
#define CLK_GOUT_PERI_HSI2C6_IPCLK 11
|
||||
#define CLK_GOUT_PERI_I2C0_PCLK 12
|
||||
#define CLK_GOUT_PERI_I2C1_PCLK 13
|
||||
#define CLK_GOUT_PERI_I2C2_PCLK 14
|
||||
#define CLK_GOUT_PERI_I2C3_PCLK 15
|
||||
#define CLK_GOUT_PERI_I2C4_PCLK 16
|
||||
#define CLK_GOUT_PERI_I2C5_PCLK 17
|
||||
#define CLK_GOUT_PERI_I2C6_PCLK 18
|
||||
#define CLK_GOUT_PERI_I2C7_PCLK 19
|
||||
#define CLK_GOUT_PERI_I2C8_PCLK 20
|
||||
#define CLK_GOUT_PERI_MCT_PCLK 21
|
||||
#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22
|
||||
#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23
|
||||
#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24
|
||||
#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25
|
||||
#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26
|
||||
#define CLK_GOUT_PERI_SPI0_PCLK 27
|
||||
#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28
|
||||
#define CLK_GOUT_PERI_SPI1_PCLK 29
|
||||
#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30
|
||||
#define CLK_GOUT_PERI_SPI2_PCLK 31
|
||||
#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32
|
||||
#define CLK_GOUT_PERI_SPI3_PCLK 33
|
||||
#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34
|
||||
#define CLK_GOUT_PERI_SPI4_PCLK 35
|
||||
#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36
|
||||
#define CLK_GOUT_PERI_TMU_CLK 37
|
||||
#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38
|
||||
#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39
|
||||
#define CLK_GOUT_PERI_UART0_EXT_UCLK 40
|
||||
#define CLK_GOUT_PERI_UART0_PCLK 41
|
||||
#define CLK_GOUT_PERI_UART1_EXT_UCLK 42
|
||||
#define CLK_GOUT_PERI_UART1_PCLK 43
|
||||
#define CLK_GOUT_PERI_UART2_EXT_UCLK 44
|
||||
#define CLK_GOUT_PERI_UART2_PCLK 45
|
||||
#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46
|
||||
#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47
|
||||
#define PERI_NR_CLK 48
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */
|
||||
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Reference in New Issue
Block a user