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perf vendor events intel: Update arrowlake events to v1.13

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Update arrowlake events to v1.13 released in:

  718cdcec8b

Event JSON automatically generated by:

  https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py

Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2025-09-25 10:27:28 -07:00 committed by Arnaldo Carvalho de Melo
parent 76619e81a8
commit d41129fe54
4 changed files with 46 additions and 10 deletions
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46
tools/perf/pmu-events/arch/x86/arrowlake/cache.json
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@ -1435,9 +1435,33 @@
"UMask": "0xf",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.COREWB_M.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7E001E00008",
"PublicDescription": "Counts writebacks of modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.COREWB_NONM.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7E001E01000",
"PublicDescription": "Counts writebacks of non-modified cachelines that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -1449,7 +1473,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -1461,7 +1485,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
@ -1473,7 +1497,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
@ -1485,7 +1509,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
"MSRIndex": "0x1a6,0x1a7",
@ -1495,6 +1519,18 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.READS_TO_CORE.L3_HIT",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x7E001E04477",
"PublicDescription": "Counts all data read, code read, RFO and ITOM requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches. Available PDIST counters: 0",
"SampleAfterValue": "100003",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
"Counter": "0,1,2,3,4,5,6,7,8,9",

6
tools/perf/pmu-events/arch/x86/arrowlake/memory.json
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@ -334,7 +334,7 @@
},
{
"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
@ -346,7 +346,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
@ -358,7 +358,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",

2
tools/perf/pmu-events/arch/x86/arrowlake/other.json
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@ -66,7 +66,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",

2
tools/perf/pmu-events/arch/x86/mapfile.csv
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@ -1,7 +1,7 @@
Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.34,alderlake,core
GenuineIntel-6-BE,v1.34,alderlaken,core
GenuineIntel-6-C[56],v1.12,arrowlake,core
GenuineIntel-6-C[56],v1.13,arrowlake,core
GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
GenuineIntel-6-(3D|47),v30,broadwell,core
GenuineIntel-6-56,v12,broadwellde,core

1 Family-model Version Filename EventType
2 GenuineIntel-6-(97|9A|B7|BA|BF) v1.34 alderlake core
3 GenuineIntel-6-BE v1.34 alderlaken core
4 GenuineIntel-6-C[56] v1.12 v1.13 arrowlake core
5 GenuineIntel-6-(1C|26|27|35|36) v5 bonnell core
6 GenuineIntel-6-(3D|47) v30 broadwell core
7 GenuineIntel-6-56 v12 broadwellde core