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Clock fixes for rk3328 and rk3288 and a new sub-type for an upcoming
soc where mux and divider are not necessarily in the same register anymore. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAly/jNMQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgbyKCAC0+NF8e3Ov9HwW5BizuEcp8GoN5zzFJjwl 20gJRtCxQODTG3zih36B3KbOzzeqsb3q3UG7yqhvgkT9LSI0bjX9YR2hXtM2YkQK 1f9LAS0rX5KNrRfE8hAoJcrCBzCm3eWDPK7IUdvr3DIxL45/0624jzkAkIzjqLPf BQENu8sGn65Lp9n9vvPh5q+jriPoOQH0rrG+hDdeSf5fOu1pVfRgq1OrKfL+CUBB 97nfXMWj0tFVjhQHxv+aGtJoNUCl00R42JgmKvwPI+8uDYS0gXqQmTM4//7uGr1s u3A9NUqqTJtmXEuCk8Nipwlvla0aXldk71SeLZMRUlVTmO0cJH7N =tPPg -----END PGP SIGNATURE----- Merge tag 'v5.2-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Fixes for rk3328 and rk3288 - New sub-type for an upcoming SoC where mux and divider are not necessarily in the same register anymore * tag 'v5.2-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: undo several noc and special clocks as critical on rk3288 clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 clk: rockchip: Limit use of USB PHY clock to USB on rk3288 clk: rockchip: Fix video codec clocks on rk3288 clk: rockchip: Make rkpwm a critical clock on rk3288 clk: rockchip: fix wrong clock definitions for rk3328
This commit is contained in:
Stephen Boyd
commit
d3dfc16f8f
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@ -200,8 +200,8 @@ PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
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PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
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PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
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PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
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PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
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PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
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PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "unstable:usbphy480m_src" };
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PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "unstable:usbphy480m_src", "npll" };
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PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
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PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
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@ -219,7 +219,7 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
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PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
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PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
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PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vepu", "aclk_vdpu" };
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PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" };
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PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m",
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"sclk_otgphy0_480m" };
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PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
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@ -313,13 +313,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
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RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
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RK3288_CLKGATE_CON(12), 6, GFLAGS),
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COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
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COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
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RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
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RK3288_CLKGATE_CON(12), 7, GFLAGS),
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COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
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RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
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RK3288_CLKGATE_CON(12), 8, GFLAGS),
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GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
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GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
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RK3288_CLKGATE_CON(12), 9, GFLAGS),
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GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
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RK3288_CLKGATE_CON(12), 10, GFLAGS),
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@ -420,7 +420,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
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RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
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RK3288_CLKGATE_CON(3), 11, GFLAGS),
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MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, 0,
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MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
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RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
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GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
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RK3288_CLKGATE_CON(9), 0, GFLAGS),
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@ -647,7 +647,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
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RK3288_CLKSEL_CON(22), 7, IFLAGS),
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GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
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GATE(0, "jtag", "ext_jtag", 0,
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RK3288_CLKGATE_CON(4), 14, GFLAGS),
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COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
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@ -656,7 +656,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
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RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
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RK3288_CLKGATE_CON(3), 6, GFLAGS),
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GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
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GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
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RK3288_CLKGATE_CON(13), 9, GFLAGS),
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DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
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RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
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@ -697,7 +697,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
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GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
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GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
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GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
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GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
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/* ddrctrl [DDR Controller PHY clock] gates */
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GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
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@ -837,12 +837,9 @@ static const char *const rk3288_critical_clocks[] __initconst = {
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"pclk_alive_niu",
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"pclk_pd_pmu",
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"pclk_pmu_niu",
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"pclk_core_niu",
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"pclk_ddrupctl0",
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"pclk_publ0",
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"pclk_ddrupctl1",
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"pclk_publ1",
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"pmu_hclk_otg0",
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/* pwm-regulators on some boards, so handoff-critical later */
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"pclk_rkpwm",
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};
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static void __iomem *rk3288_cru_base;
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@ -859,6 +856,9 @@ static const int rk3288_saved_cru_reg_ids[] = {
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RK3288_CLKSEL_CON(10),
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RK3288_CLKSEL_CON(33),
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RK3288_CLKSEL_CON(37),
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/* We turn aclk_dmac1 on for suspend; this will restore it */
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RK3288_CLKGATE_CON(10),
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};
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static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
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@ -874,6 +874,14 @@ static int rk3288_clk_suspend(void)
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readl_relaxed(rk3288_cru_base + reg_id);
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}
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/*
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* Going into deep sleep (specifically setting PMU_CLR_DMA in
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* RK3288_PMU_PWRMODE_CON1) appears to fail unless
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* "aclk_dmac1" is on.
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*/
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writel_relaxed(1 << (12 + 16),
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rk3288_cru_base + RK3288_CLKGATE_CON(10));
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/*
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* Switch PLLs other than DPLL (for SDRAM) to slow mode to
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* avoid crashes on resume. The Mask ROM on the system will
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@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
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RK3328_CLKGATE_CON(2), 12, GFLAGS),
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COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
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RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
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RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
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RK3328_CLKGATE_CON(2), 4, GFLAGS),
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COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
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RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
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@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
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RK3328_CLKGATE_CON(25), 1, GFLAGS),
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GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
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RK3328_CLKGATE_CON(25), 0, GFLAGS),
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RK3328_CLKGATE_CON(25), 2, GFLAGS),
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GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
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RK3328_CLKGATE_CON(25), 1, GFLAGS),
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RK3328_CLKGATE_CON(25), 3, GFLAGS),
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GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
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RK3328_CLKGATE_CON(25), 0, GFLAGS),
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RK3328_CLKGATE_CON(25), 4, GFLAGS),
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GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
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RK3328_CLKGATE_CON(25), 1, GFLAGS),
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RK3328_CLKGATE_CON(25), 5, GFLAGS),
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GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
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RK3328_CLKGATE_CON(25), 0, GFLAGS),
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RK3328_CLKGATE_CON(25), 6, GFLAGS),
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COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
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RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
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@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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/* PD_GMAC */
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COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
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RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
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RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
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RK3328_CLKGATE_CON(3), 2, GFLAGS),
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COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
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RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
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@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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/* PD_PERI */
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GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
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GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
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GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
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GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
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GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
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@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
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&rk3328_cpuclk_data, rk3328_cpuclk_rates,
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ARRAY_SIZE(rk3328_cpuclk_rates));
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rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
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rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
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@ -46,7 +46,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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const char *const *parent_names, u8 num_parents,
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void __iomem *base,
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int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
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u8 div_shift, u8 div_width, u8 div_flags,
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int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
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struct clk_div_table *div_table, int gate_offset,
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u8 gate_shift, u8 gate_flags, unsigned long flags,
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spinlock_t *lock)
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@ -95,7 +95,10 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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}
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div->flags = div_flags;
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div->reg = base + muxdiv_offset;
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if (div_offset)
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div->reg = base + div_offset;
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else
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div->reg = base + muxdiv_offset;
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div->shift = div_shift;
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div->width = div_width;
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div->lock = lock;
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@ -516,7 +519,7 @@ void __init rockchip_clk_register_branches(
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ctx->reg_base, list->muxdiv_offset,
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list->mux_shift,
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list->mux_width, list->mux_flags,
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list->div_shift, list->div_width,
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list->div_offset, list->div_shift, list->div_width,
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list->div_flags, list->div_table,
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list->gate_offset, list->gate_shift,
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list->gate_flags, flags, &ctx->lock);
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@ -407,6 +407,7 @@ struct rockchip_clk_branch {
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u8 mux_shift;
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u8 mux_width;
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u8 mux_flags;
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int div_offset;
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u8 div_shift;
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u8 div_width;
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u8 div_flags;
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@ -438,6 +439,28 @@ struct rockchip_clk_branch {
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.gate_flags = gf, \
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}
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#define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
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mf, do, ds, dw, df, go, gs, gf) \
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{ \
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.id = _id, \
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.branch_type = branch_composite, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = f, \
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.muxdiv_offset = mo, \
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.mux_shift = ms, \
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.mux_width = mw, \
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.mux_flags = mf, \
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.div_offset = do, \
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.div_shift = ds, \
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.div_width = dw, \
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.div_flags = df, \
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.gate_offset = go, \
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.gate_shift = gs, \
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.gate_flags = gf, \
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}
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#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
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go, gs, gf) \
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{ \
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