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clk: renesas: r9a09g047: Add CLK_PLLETH_LPCLK support

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Add CLK_PLLETH_LPCLK clock support.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/dcb0cab96e2ff3e23eafac061b2952c74622d1f8.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Tommaso Merciai 2026-04-08 12:36:47 +02:00 committed by Geert Uytterhoeven
parent 3afccee4a3
commit d394d8342d
1 changed files with 14 additions and 0 deletions
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14
drivers/clk/renesas/r9a09g047-cpg.c
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@ -64,6 +64,8 @@ enum clk_ids {
CLK_PLLDTY_DIV16,
CLK_PLLVDO_CRU0,
CLK_PLLVDO_GPU,
CLK_PLLETH_DIV4_LPCLK,
CLK_PLLETH_LPCLK,
/* Module Clocks */
MOD_CLK_BASE,
@ -107,6 +109,14 @@ static const struct clk_div_table dtable_2_100[] = {
{0, 0},
};
static const struct clk_div_table dtable_16_128[] = {
{0, 16},
{1, 32},
{2, 64},
{3, 128},
{0, 0},
};
/* Mux clock tables */
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@ -171,6 +181,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
DEF_FIXED(".plleth_div4_lpclk", CLK_PLLETH_DIV4_LPCLK, CLK_PLLETH, 1, 4),
DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK,
CSDIV0_DIVCTL2, dtable_16_128),
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,