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net: stmmac: intel: convert speed_mode_2500() to get_interfaces()

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TGL platforms support either SGMII or 2500BASE-X, which is determined
by reading a SERDES register.

Thus, plat->phy_interface (and phylink's supported_interfaces) depend
on this. Use the new .get_interfaces() method to set both
plat->phy_interface and the supported_interfaces bitmap.

This removes the only user of the .speed_mode_2500() method.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/E1uASLx-0021Qs-Uz@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Russell King (Oracle) 2025-05-01 12:45:21 +01:00 committed by Jakub Kicinski
parent 0f455d2d1b
commit d3836052fe
2 changed files with 16 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
View File

@ -284,25 +284,28 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
} }
} }
static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data) static void tgl_get_interfaces(struct stmmac_priv *priv, void *bsp_priv,
unsigned long *interfaces)
{ {
struct intel_priv_data *intel_priv = intel_data; struct intel_priv_data *intel_priv = bsp_priv;
struct stmmac_priv *priv = netdev_priv(ndev); phy_interface_t interface;
int serdes_phy_addr = 0; int data;
u32 data = 0;
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
/* Determine the link speed mode: 2.5Gbps/1Gbps */ /* Determine the link speed mode: 2.5Gbps/1Gbps */
data = mdiobus_read(priv->mii, serdes_phy_addr, data = mdiobus_read(priv->mii, intel_priv->mdio_adhoc_addr, SERDES_GCR);
SERDES_GCR); if (data < 0)
return;
if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) == if (FIELD_GET(SERDES_LINK_MODE_MASK, data) == SERDES_LINK_MODE_2G5) {
SERDES_LINK_MODE_2G5) {
dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
priv->plat->mdio_bus_data->default_an_inband = false; priv->plat->mdio_bus_data->default_an_inband = false;
interface = PHY_INTERFACE_MODE_2500BASEX;
} else {
interface = PHY_INTERFACE_MODE_SGMII;
} }
__set_bit(interface, interfaces);
priv->plat->phy_interface = interface;
} }
/* Program PTP Clock Frequency for different variant of /* Program PTP Clock Frequency for different variant of
@ -929,8 +932,7 @@ static int tgl_common_data(struct pci_dev *pdev,
plat->rx_queues_to_use = 6; plat->rx_queues_to_use = 6;
plat->tx_queues_to_use = 4; plat->tx_queues_to_use = 4;
plat->clk_ptp_rate = 204800000; plat->clk_ptp_rate = 204800000;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII; plat->get_interfaces = tgl_get_interfaces;
plat->speed_mode_2500 = intel_speed_mode_2500;
plat->safety_feat_cfg->tsoee = 1; plat->safety_feat_cfg->tsoee = 1;
plat->safety_feat_cfg->mrxpee = 0; plat->safety_feat_cfg->mrxpee = 0;

1
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
View File

@ -21,7 +21,6 @@
#define SERDES_RATE_MASK GENMASK(9, 8) #define SERDES_RATE_MASK GENMASK(9, 8)
#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */ #define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
#define SERDES_LINK_MODE_MASK GENMASK(2, 1) #define SERDES_LINK_MODE_MASK GENMASK(2, 1)
#define SERDES_LINK_MODE_SHIFT 1
#define SERDES_PWR_ST_SHIFT 4 #define SERDES_PWR_ST_SHIFT 4
#define SERDES_PWR_ST_P0 0x0 #define SERDES_PWR_ST_P0 0x0
#define SERDES_PWR_ST_P3 0x3 #define SERDES_PWR_ST_P3 0x3