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- Remove the shared threshold bank hack on AMD and streamline and simplify it
- Cleanup and sanitize MCA code -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmeOR1oACgkQEsHwGGHe VUo06hAAlUk3F5sp+53djAKInHdbUoHZdGX4vy5dppjnDfu5JQcg/OwO0l6RbfhA YUTytWHT0SdkyoJG7CnxQOteOkmimeHMfVTZw9LWm9xLMtulNMxsxJnKHlpvBbfR P/1eot/R+wLMzZoqqf6O8MfF1Gs/S3WjO2+T3wbdgwW7YXprbTSwW51FXhLOaObR PR+PfDXqcu4u4+b+bC0HSo3dN0Sc4J71cdb0tt7VIeQwVUAcfEZgdM1opXSxtQJJ G/Ekbjg5dJo4ZRFXXrxVNWxOXJsKbuubc6mw0C+cgCcbDklcF1gmQYvL9+NSExeP vDyhmMhuEDbtvUBJPQFnFywqYH/a1neo00RJUqw6xVXsn+ebBHVGLik8mgbQOaHt fh8bATsQ1aETAk6nx3RMPk9saiqFHk8t4qIV9FwjskXzuKDh5LzM1rGuiFLl5py/ 5hazmwn7/jYTxYJyG2ZEHD1ro2jcZFevu9dPTOSaJL3ODtlH4fQUugBcoukq6re3 OEf/v+J8LcX+fvo8ylJYyXXT9ZDTpckjTNipU8JiEjVcro0MrxEzTnTWma4tcn+w Hp7lZ+/AEmHwKQcNab7frKhTPdxLFRbJyYIGiRAt9mwxXz49IBTDpoVFpXUf56zV Djcd6wmG1gKvM+27or/tuuiDyCZlK0+s7twRYxP50cMuvFcvmNk= =hSqE -----END PGP SIGNATURE----- Merge tag 'ras_core_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 RAS updates from Borislav Petkov: - Remove the shared threshold bank hack on AMD and streamline and simplify it - Cleanup and sanitize MCA code * tag 'ras_core_for_v6.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce/amd: Remove shared threshold bank plumbing x86/mce: Remove the redundant mce_hygon_feature_init() x86/mce: Convert family/model mixed checks to VFM-based checks x86/mce: Break up __mcheck_cpu_apply_quirks() x86/mce: Make four functions return bool x86/mce/threshold: Remove the redundant this_cpu_dec_return() x86/mce: Make several functions return bool
This commit is contained in:
Linus Torvalds
commit
d3504411a4
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@ -1188,7 +1188,7 @@ config X86_MCE_INTEL
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config X86_MCE_AMD
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def_bool y
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prompt "AMD MCE features"
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depends on X86_MCE && X86_LOCAL_APIC && AMD_NB
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depends on X86_MCE && X86_LOCAL_APIC
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help
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Additional support for AMD specific MCE features such as
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the DRAM Error Threshold.
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@ -4,7 +4,6 @@
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/refcount.h>
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struct amd_nb_bus_dev_range {
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u8 bus;
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@ -29,41 +28,11 @@ struct amd_l3_cache {
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u8 subcaches[4];
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};
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struct threshold_block {
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unsigned int block; /* Number within bank */
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unsigned int bank; /* MCA bank the block belongs to */
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unsigned int cpu; /* CPU which controls MCA bank */
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u32 address; /* MSR address for the block */
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u16 interrupt_enable; /* Enable/Disable APIC interrupt */
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bool interrupt_capable; /* Bank can generate an interrupt. */
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u16 threshold_limit; /*
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* Value upon which threshold
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* interrupt is generated.
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*/
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struct kobject kobj; /* sysfs object */
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struct list_head miscj; /*
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* List of threshold blocks
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* within a bank.
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*/
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};
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struct threshold_bank {
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struct kobject *kobj;
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struct threshold_block *blocks;
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/* initialized to the number of CPUs on the node sharing this bank */
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refcount_t cpus;
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unsigned int shared;
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};
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struct amd_northbridge {
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struct pci_dev *root;
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struct pci_dev *misc;
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struct pci_dev *link;
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struct amd_l3_cache l3_cache;
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struct threshold_bank *bank4;
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};
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struct amd_northbridge_info {
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@ -276,7 +276,7 @@ static inline void cmci_rediscover(void) {}
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static inline void cmci_recheck(void) {}
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#endif
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int mce_available(struct cpuinfo_x86 *c);
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bool mce_available(struct cpuinfo_x86 *c);
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bool mce_is_memory_error(struct mce *m);
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bool mce_is_correctable(struct mce *m);
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bool mce_usable_address(struct mce *m);
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@ -296,7 +296,7 @@ enum mcp_flags {
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void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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int mce_notify_irq(void);
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bool mce_notify_irq(void);
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DECLARE_PER_CPU(struct mce, injectm);
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@ -386,8 +386,6 @@ static inline bool amd_mce_is_memory_error(struct mce *m) { return false; };
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); }
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unsigned long copy_mc_fragile_handle_tail(char *to, char *from, unsigned len);
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#endif /* _ASM_X86_MCE_H */
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@ -4,8 +4,6 @@
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*
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* Written by Jacob Shin - AMD, Inc.
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* Maintained by: Borislav Petkov <bp@alien8.de>
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*
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* All MC4_MISCi registers are shared between cores on a node.
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*/
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#include <linux/interrupt.h>
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#include <linux/notifier.h>
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@ -20,7 +18,6 @@
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#include <linux/smp.h>
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#include <linux/string.h>
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#include <asm/amd_nb.h>
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#include <asm/traps.h>
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#include <asm/apic.h>
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#include <asm/mce.h>
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@ -221,6 +218,32 @@ static const struct smca_hwid smca_hwid_mcatypes[] = {
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#define MAX_MCATYPE_NAME_LEN 30
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static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
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struct threshold_block {
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/* This block's number within its bank. */
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unsigned int block;
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/* MCA bank number that contains this block. */
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unsigned int bank;
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/* CPU which controls this block's MCA bank. */
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unsigned int cpu;
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/* MCA_MISC MSR address for this block. */
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u32 address;
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/* Enable/Disable APIC interrupt. */
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bool interrupt_enable;
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/* Bank can generate an interrupt. */
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bool interrupt_capable;
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/* Value upon which threshold interrupt is generated. */
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u16 threshold_limit;
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/* sysfs object */
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struct kobject kobj;
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/* List of threshold blocks within this block's MCA bank. */
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struct list_head miscj;
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};
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struct threshold_bank {
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struct kobject *kobj;
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struct threshold_block *blocks;
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};
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static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
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/*
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@ -333,19 +356,6 @@ struct thresh_restart {
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u16 old_limit;
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};
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static inline bool is_shared_bank(int bank)
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{
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/*
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* Scalable MCA provides for only one core to have access to the MSRs of
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* a shared bank.
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*/
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if (mce_flags.smca)
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return false;
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/* Bank 4 is for northbridge reporting and is thus shared */
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return (bank == 4);
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}
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static const char *bank4_names(const struct threshold_block *b)
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{
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switch (b->address) {
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@ -381,7 +391,7 @@ static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
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return msr_high_bits & BIT(28);
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}
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static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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{
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int msr = (hi & MASK_LVTOFF_HI) >> 20;
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@ -389,7 +399,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
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"for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
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b->bank, b->block, b->address, hi, lo);
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return 0;
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return false;
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}
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if (apic != msr) {
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@ -399,15 +409,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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* was set is reserved. Return early here:
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*/
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if (mce_flags.smca)
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return 0;
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return false;
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pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
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"for bank %d, block %d (MSR%08X=0x%x%08x)\n",
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b->cpu, apic, b->bank, b->block, b->address, hi, lo);
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return 0;
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return false;
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}
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return 1;
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return true;
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};
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/* Reprogram MCx_MISC MSR behind this threshold bank. */
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@ -1198,35 +1208,10 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
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return err;
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}
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static int __threshold_add_blocks(struct threshold_bank *b)
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{
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struct list_head *head = &b->blocks->miscj;
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struct threshold_block *pos = NULL;
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struct threshold_block *tmp = NULL;
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int err = 0;
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err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
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if (err)
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return err;
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list_for_each_entry_safe(pos, tmp, head, miscj) {
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err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
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if (err) {
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list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
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kobject_del(&pos->kobj);
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return err;
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}
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}
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return err;
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}
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static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
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unsigned int bank)
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{
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struct device *dev = this_cpu_read(mce_device);
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struct amd_northbridge *nb = NULL;
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struct threshold_bank *b = NULL;
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const char *name = get_name(cpu, bank, NULL);
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int err = 0;
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@ -1234,26 +1219,6 @@ static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
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if (!dev)
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return -ENODEV;
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if (is_shared_bank(bank)) {
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nb = node_to_amd_nb(topology_amd_node_id(cpu));
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/* threshold descriptor already initialized on this node? */
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if (nb && nb->bank4) {
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/* yes, use it */
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b = nb->bank4;
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err = kobject_add(b->kobj, &dev->kobj, name);
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if (err)
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goto out;
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bp[bank] = b;
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refcount_inc(&b->cpus);
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err = __threshold_add_blocks(b);
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goto out;
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}
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}
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b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
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if (!b) {
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err = -ENOMEM;
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@ -1267,17 +1232,6 @@ static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
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goto out_free;
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}
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if (is_shared_bank(bank)) {
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b->shared = 1;
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refcount_set(&b->cpus, 1);
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/* nb is already initialized, see above */
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if (nb) {
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WARN_ON(nb->bank4);
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nb->bank4 = b;
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}
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}
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err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));
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if (err)
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goto out_kobj;
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@ -1310,40 +1264,11 @@ static void deallocate_threshold_blocks(struct threshold_bank *bank)
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kobject_put(&bank->blocks->kobj);
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}
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static void __threshold_remove_blocks(struct threshold_bank *b)
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{
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struct threshold_block *pos = NULL;
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struct threshold_block *tmp = NULL;
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kobject_put(b->kobj);
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list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
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kobject_put(b->kobj);
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}
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|
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static void threshold_remove_bank(struct threshold_bank *bank)
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{
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struct amd_northbridge *nb;
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|
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if (!bank->blocks)
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goto out_free;
|
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|
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if (!bank->shared)
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goto out_dealloc;
|
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|
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if (!refcount_dec_and_test(&bank->cpus)) {
|
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__threshold_remove_blocks(bank);
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return;
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} else {
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/*
|
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* The last CPU on this node using the shared bank is going
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* away, remove that bank now.
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*/
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nb = node_to_amd_nb(topology_amd_node_id(smp_processor_id()));
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nb->bank4 = NULL;
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}
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|
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out_dealloc:
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deallocate_threshold_blocks(bank);
|
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|
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out_free:
|
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|
|
|
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|
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@ -151,7 +151,7 @@ EXPORT_PER_CPU_SYMBOL_GPL(injectm);
|
|||
|
||||
void mce_log(struct mce_hw_err *err)
|
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{
|
||||
if (!mce_gen_pool_add(err))
|
||||
if (mce_gen_pool_add(err))
|
||||
irq_work_queue(&mce_irq_work);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mce_log);
|
||||
|
|
@ -492,10 +492,10 @@ static noinstr void mce_gather_info(struct mce_hw_err *err, struct pt_regs *regs
|
|||
}
|
||||
}
|
||||
|
||||
int mce_available(struct cpuinfo_x86 *c)
|
||||
bool mce_available(struct cpuinfo_x86 *c)
|
||||
{
|
||||
if (mca_cfg.disabled)
|
||||
return 0;
|
||||
return false;
|
||||
return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
|
||||
}
|
||||
|
||||
|
|
@ -1778,7 +1778,7 @@ static void mce_timer_delete_all(void)
|
|||
* Can be called from interrupt context, but not from machine check/NMI
|
||||
* context.
|
||||
*/
|
||||
int mce_notify_irq(void)
|
||||
bool mce_notify_irq(void)
|
||||
{
|
||||
/* Not more than two messages every minute */
|
||||
static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
|
||||
|
|
@ -1789,9 +1789,9 @@ int mce_notify_irq(void)
|
|||
if (__ratelimit(&ratelimit))
|
||||
pr_info(HW_ERR "Machine check events logged\n");
|
||||
|
||||
return 1;
|
||||
return true;
|
||||
}
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mce_notify_irq);
|
||||
|
||||
|
|
@ -1910,101 +1910,120 @@ static void __mcheck_cpu_check_banks(void)
|
|||
}
|
||||
}
|
||||
|
||||
/* Add per CPU specific workarounds here */
|
||||
static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
|
||||
static void apply_quirks_amd(struct cpuinfo_x86 *c)
|
||||
{
|
||||
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
|
||||
struct mca_config *cfg = &mca_cfg;
|
||||
|
||||
if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
|
||||
pr_info("unknown CPU type - not enabling MCE support\n");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
/* This should be disabled by the BIOS, but isn't always */
|
||||
if (c->x86_vendor == X86_VENDOR_AMD) {
|
||||
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
|
||||
/*
|
||||
* disable GART TBL walk error reporting, which
|
||||
* trips off incorrectly with the IOMMU & 3ware
|
||||
* & Cerberus:
|
||||
*/
|
||||
clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
|
||||
}
|
||||
if (c->x86 < 0x11 && cfg->bootlog < 0) {
|
||||
/*
|
||||
* Lots of broken BIOS around that don't clear them
|
||||
* by default and leave crap in there. Don't log:
|
||||
*/
|
||||
cfg->bootlog = 0;
|
||||
}
|
||||
if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
|
||||
/*
|
||||
* Various K7s with broken bank 0 around. Always disable
|
||||
* by default.
|
||||
* disable GART TBL walk error reporting, which
|
||||
* trips off incorrectly with the IOMMU & 3ware
|
||||
* & Cerberus:
|
||||
*/
|
||||
if (c->x86 == 6 && this_cpu_read(mce_num_banks) > 0)
|
||||
mce_banks[0].ctl = 0;
|
||||
|
||||
/*
|
||||
* overflow_recov is supported for F15h Models 00h-0fh
|
||||
* even though we don't have a CPUID bit for it.
|
||||
*/
|
||||
if (c->x86 == 0x15 && c->x86_model <= 0xf)
|
||||
mce_flags.overflow_recov = 1;
|
||||
|
||||
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
|
||||
mce_flags.zen_ifu_quirk = 1;
|
||||
|
||||
clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
|
||||
}
|
||||
|
||||
if (c->x86_vendor == X86_VENDOR_INTEL) {
|
||||
if (c->x86 < 0x11 && mca_cfg.bootlog < 0) {
|
||||
/*
|
||||
* SDM documents that on family 6 bank 0 should not be written
|
||||
* because it aliases to another special BIOS controlled
|
||||
* register.
|
||||
* But it's not aliased anymore on model 0x1a+
|
||||
* Don't ignore bank 0 completely because there could be a
|
||||
* valid event later, merely don't write CTL0.
|
||||
* Lots of broken BIOS around that don't clear them
|
||||
* by default and leave crap in there. Don't log:
|
||||
*/
|
||||
|
||||
if (c->x86 == 6 && c->x86_model < 0x1A && this_cpu_read(mce_num_banks) > 0)
|
||||
mce_banks[0].init = false;
|
||||
|
||||
/*
|
||||
* All newer Intel systems support MCE broadcasting. Enable
|
||||
* synchronization with a one second timeout.
|
||||
*/
|
||||
if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
|
||||
cfg->monarch_timeout < 0)
|
||||
cfg->monarch_timeout = USEC_PER_SEC;
|
||||
|
||||
/*
|
||||
* There are also broken BIOSes on some Pentium M and
|
||||
* earlier systems:
|
||||
*/
|
||||
if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0)
|
||||
cfg->bootlog = 0;
|
||||
|
||||
if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
|
||||
mce_flags.snb_ifu_quirk = 1;
|
||||
|
||||
/*
|
||||
* Skylake, Cascacde Lake and Cooper Lake require a quirk on
|
||||
* rep movs.
|
||||
*/
|
||||
if (c->x86_vfm == INTEL_SKYLAKE_X)
|
||||
mce_flags.skx_repmov_quirk = 1;
|
||||
mca_cfg.bootlog = 0;
|
||||
}
|
||||
|
||||
if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
|
||||
/*
|
||||
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
|
||||
* synchronization with a one second timeout.
|
||||
*/
|
||||
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
|
||||
if (cfg->monarch_timeout < 0)
|
||||
cfg->monarch_timeout = USEC_PER_SEC;
|
||||
}
|
||||
/*
|
||||
* Various K7s with broken bank 0 around. Always disable
|
||||
* by default.
|
||||
*/
|
||||
if (c->x86 == 6 && this_cpu_read(mce_num_banks))
|
||||
mce_banks[0].ctl = 0;
|
||||
|
||||
/*
|
||||
* overflow_recov is supported for F15h Models 00h-0fh
|
||||
* even though we don't have a CPUID bit for it.
|
||||
*/
|
||||
if (c->x86 == 0x15 && c->x86_model <= 0xf)
|
||||
mce_flags.overflow_recov = 1;
|
||||
|
||||
if (c->x86 >= 0x17 && c->x86 <= 0x1A)
|
||||
mce_flags.zen_ifu_quirk = 1;
|
||||
}
|
||||
|
||||
static void apply_quirks_intel(struct cpuinfo_x86 *c)
|
||||
{
|
||||
struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
|
||||
|
||||
/* Older CPUs (prior to family 6) don't need quirks. */
|
||||
if (c->x86_vfm < INTEL_PENTIUM_PRO)
|
||||
return;
|
||||
|
||||
/*
|
||||
* SDM documents that on family 6 bank 0 should not be written
|
||||
* because it aliases to another special BIOS controlled
|
||||
* register.
|
||||
* But it's not aliased anymore on model 0x1a+
|
||||
* Don't ignore bank 0 completely because there could be a
|
||||
* valid event later, merely don't write CTL0.
|
||||
*/
|
||||
if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks))
|
||||
mce_banks[0].init = false;
|
||||
|
||||
/*
|
||||
* All newer Intel systems support MCE broadcasting. Enable
|
||||
* synchronization with a one second timeout.
|
||||
*/
|
||||
if (c->x86_vfm >= INTEL_CORE_YONAH && mca_cfg.monarch_timeout < 0)
|
||||
mca_cfg.monarch_timeout = USEC_PER_SEC;
|
||||
|
||||
/*
|
||||
* There are also broken BIOSes on some Pentium M and
|
||||
* earlier systems:
|
||||
*/
|
||||
if (c->x86_vfm < INTEL_CORE_YONAH && mca_cfg.bootlog < 0)
|
||||
mca_cfg.bootlog = 0;
|
||||
|
||||
if (c->x86_vfm == INTEL_SANDYBRIDGE_X)
|
||||
mce_flags.snb_ifu_quirk = 1;
|
||||
|
||||
/*
|
||||
* Skylake, Cascacde Lake and Cooper Lake require a quirk on
|
||||
* rep movs.
|
||||
*/
|
||||
if (c->x86_vfm == INTEL_SKYLAKE_X)
|
||||
mce_flags.skx_repmov_quirk = 1;
|
||||
}
|
||||
|
||||
static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
|
||||
{
|
||||
/*
|
||||
* All newer Zhaoxin CPUs support MCE broadcasting. Enable
|
||||
* synchronization with a one second timeout.
|
||||
*/
|
||||
if (c->x86 > 6 || (c->x86_model == 0x19 || c->x86_model == 0x1f)) {
|
||||
if (mca_cfg.monarch_timeout < 0)
|
||||
mca_cfg.monarch_timeout = USEC_PER_SEC;
|
||||
}
|
||||
}
|
||||
|
||||
/* Add per CPU specific workarounds here */
|
||||
static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
|
||||
{
|
||||
struct mca_config *cfg = &mca_cfg;
|
||||
|
||||
switch (c->x86_vendor) {
|
||||
case X86_VENDOR_UNKNOWN:
|
||||
pr_info("unknown CPU type - not enabling MCE support\n");
|
||||
return false;
|
||||
case X86_VENDOR_AMD:
|
||||
apply_quirks_amd(c);
|
||||
break;
|
||||
case X86_VENDOR_INTEL:
|
||||
apply_quirks_intel(c);
|
||||
break;
|
||||
case X86_VENDOR_ZHAOXIN:
|
||||
apply_quirks_zhaoxin(c);
|
||||
break;
|
||||
}
|
||||
|
||||
if (cfg->monarch_timeout < 0)
|
||||
|
|
@ -2012,28 +2031,28 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
|
|||
if (cfg->bootlog != 0)
|
||||
cfg->panic_timeout = 30;
|
||||
|
||||
return 0;
|
||||
return true;
|
||||
}
|
||||
|
||||
static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
|
||||
static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
|
||||
{
|
||||
if (c->x86 != 5)
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
switch (c->x86_vendor) {
|
||||
case X86_VENDOR_INTEL:
|
||||
intel_p5_mcheck_init(c);
|
||||
mce_flags.p5 = 1;
|
||||
return 1;
|
||||
return true;
|
||||
case X86_VENDOR_CENTAUR:
|
||||
winchip_mcheck_init(c);
|
||||
mce_flags.winchip = 1;
|
||||
return 1;
|
||||
return true;
|
||||
default:
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -2099,13 +2118,9 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
|
|||
mce_intel_feature_init(c);
|
||||
break;
|
||||
|
||||
case X86_VENDOR_AMD: {
|
||||
mce_amd_feature_init(c);
|
||||
break;
|
||||
}
|
||||
|
||||
case X86_VENDOR_AMD:
|
||||
case X86_VENDOR_HYGON:
|
||||
mce_hygon_feature_init(c);
|
||||
mce_amd_feature_init(c);
|
||||
break;
|
||||
|
||||
case X86_VENDOR_CENTAUR:
|
||||
|
|
@ -2279,12 +2294,12 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
|
|||
|
||||
__mcheck_cpu_cap_init();
|
||||
|
||||
if (__mcheck_cpu_apply_quirks(c) < 0) {
|
||||
if (!__mcheck_cpu_apply_quirks(c)) {
|
||||
mca_cfg.disabled = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
if (mce_gen_pool_init()) {
|
||||
if (!mce_gen_pool_init()) {
|
||||
mca_cfg.disabled = 1;
|
||||
pr_emerg("Couldn't allocate MCE records pool!\n");
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -94,64 +94,63 @@ bool mce_gen_pool_empty(void)
|
|||
return llist_empty(&mce_event_llist);
|
||||
}
|
||||
|
||||
int mce_gen_pool_add(struct mce_hw_err *err)
|
||||
bool mce_gen_pool_add(struct mce_hw_err *err)
|
||||
{
|
||||
struct mce_evt_llist *node;
|
||||
|
||||
if (filter_mce(&err->m))
|
||||
return -EINVAL;
|
||||
return false;
|
||||
|
||||
if (!mce_evt_pool)
|
||||
return -EINVAL;
|
||||
return false;
|
||||
|
||||
node = (void *)gen_pool_alloc(mce_evt_pool, sizeof(*node));
|
||||
if (!node) {
|
||||
pr_warn_ratelimited("MCE records pool full!\n");
|
||||
return -ENOMEM;
|
||||
return false;
|
||||
}
|
||||
|
||||
memcpy(&node->err, err, sizeof(*err));
|
||||
llist_add(&node->llnode, &mce_event_llist);
|
||||
|
||||
return 0;
|
||||
return true;
|
||||
}
|
||||
|
||||
static int mce_gen_pool_create(void)
|
||||
static bool mce_gen_pool_create(void)
|
||||
{
|
||||
int mce_numrecords, mce_poolsz, order;
|
||||
struct gen_pool *gpool;
|
||||
int ret = -ENOMEM;
|
||||
void *mce_pool;
|
||||
|
||||
order = order_base_2(sizeof(struct mce_evt_llist));
|
||||
gpool = gen_pool_create(order, -1);
|
||||
if (!gpool)
|
||||
return ret;
|
||||
return false;
|
||||
|
||||
mce_numrecords = max(MCE_MIN_ENTRIES, num_possible_cpus() * MCE_PER_CPU);
|
||||
mce_poolsz = mce_numrecords * (1 << order);
|
||||
mce_pool = kmalloc(mce_poolsz, GFP_KERNEL);
|
||||
if (!mce_pool) {
|
||||
gen_pool_destroy(gpool);
|
||||
return ret;
|
||||
return false;
|
||||
}
|
||||
ret = gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1);
|
||||
if (ret) {
|
||||
|
||||
if (gen_pool_add(gpool, (unsigned long)mce_pool, mce_poolsz, -1)) {
|
||||
gen_pool_destroy(gpool);
|
||||
kfree(mce_pool);
|
||||
return ret;
|
||||
return false;
|
||||
}
|
||||
|
||||
mce_evt_pool = gpool;
|
||||
|
||||
return ret;
|
||||
return true;
|
||||
}
|
||||
|
||||
int mce_gen_pool_init(void)
|
||||
bool mce_gen_pool_init(void)
|
||||
{
|
||||
/* Just init mce_gen_pool once. */
|
||||
if (mce_evt_pool)
|
||||
return 0;
|
||||
return true;
|
||||
|
||||
return mce_gen_pool_create();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS];
|
|||
*/
|
||||
#define CMCI_STORM_THRESHOLD 32749
|
||||
|
||||
static int cmci_supported(int *banks)
|
||||
static bool cmci_supported(int *banks)
|
||||
{
|
||||
u64 cap;
|
||||
|
||||
if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce)
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
/*
|
||||
* Vendor check is not strictly needed, but the initial
|
||||
|
|
@ -89,10 +89,11 @@ static int cmci_supported(int *banks)
|
|||
*/
|
||||
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL &&
|
||||
boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN)
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)
|
||||
return 0;
|
||||
return false;
|
||||
|
||||
rdmsrl(MSR_IA32_MCG_CAP, cap);
|
||||
*banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK);
|
||||
return !!(cap & MCG_CMCI_P);
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@ struct mce_evt_llist {
|
|||
|
||||
void mce_gen_pool_process(struct work_struct *__unused);
|
||||
bool mce_gen_pool_empty(void);
|
||||
int mce_gen_pool_add(struct mce_hw_err *err);
|
||||
int mce_gen_pool_init(void);
|
||||
bool mce_gen_pool_add(struct mce_hw_err *err);
|
||||
bool mce_gen_pool_init(void);
|
||||
struct llist_node *mce_gen_pool_prepare_records(void);
|
||||
|
||||
int mce_severity(struct mce *a, struct pt_regs *regs, char **msg, bool is_excp);
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ void cmci_storm_end(unsigned int bank)
|
|||
storm->banks[bank].in_storm_mode = false;
|
||||
|
||||
/* If no banks left in storm mode, stop polling. */
|
||||
if (!this_cpu_dec_return(storm_desc.stormy_bank_count))
|
||||
if (!--storm->stormy_bank_count)
|
||||
mce_timer_kick(false);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user