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drm/i915/cx0: Set ssc_enabled for c20 too

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ssc_enabled does not get set for c20 phy.
We makes sure we set ssc_enabled for both c10 and c20.

Bspec: 74491
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250122053022.1544881-1-suraj.kandpal@intel.com
Link: https://patchwork.freedesktop.org/patch/msgid/20250122053022.1544881-1-suraj.kandpal@intel.com
This commit is contained in:
Suraj Kandpal 2025-01-22 11:00:23 +05:30
parent b5d97b2db0
commit d33847a0fe
1 changed files with 17 additions and 9 deletions
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26
drivers/gpu/drm/i915/display/intel_cx0_phy.c
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@ -2021,6 +2021,21 @@ intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
return NULL;
}
static void intel_cx0pll_update_ssc(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_panel_use_ssc(display)) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
pll_state->ssc_enabled =
(intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
}
}
}
static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@ -2028,15 +2043,6 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
int i;
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_panel_use_ssc(display)) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
pll_state->ssc_enabled =
(intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
}
}
if (pll_state->ssc_enabled)
return;
@ -2058,6 +2064,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
intel_cx0pll_update_ssc(crtc_state, encoder);
intel_c10pll_update_pll(crtc_state, encoder);
crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
@ -2327,6 +2334,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
intel_cx0pll_update_ssc(crtc_state, encoder);
crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
return 0;
}