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phy: renesas: r8a779f0-ether-serdes: add USXGMII mode

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The initial driver implementation was limited to SGMII and 1GBit/s. The
new mode allows speeds up to 2.5GBit/s on R-Car S4-8 SOCs.

Signed-off-by: Michael Dege <michael.dege@renesas.com>
Link: https://lore.kernel.org/r/20250703-renesas-serdes-update-v4-1-1db5629cac2b@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Michael Dege 2025-07-03 13:07:23 +02:00 committed by Vinod Koul
parent f0c6d776f7
commit d337c55758
1 changed files with 57 additions and 12 deletions
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69
drivers/phy/renesas/r8a779f0-ether-serdes.c
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@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Renesas Ethernet SERDES device driver
*
* Copyright (C) 2022 Renesas Electronics Corporation
* Copyright (C) 2022-2025 Renesas Electronics Corporation
*/
#include <linux/delay.h>
@ -92,17 +92,18 @@ r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel)
{
struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
switch (channel->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097);
r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
return 0;
default:
return -EOPNOTSUPP;
}
/* Set combination mode */
r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x00d7);
r8a779f0_eth_serdes_write32(dd->addr, 0x01cc, 0x180, 0xc200);
r8a779f0_eth_serdes_write32(dd->addr, 0x01c4, 0x180, 0x0042);
r8a779f0_eth_serdes_write32(dd->addr, 0x01c8, 0x180, 0x0000);
r8a779f0_eth_serdes_write32(dd->addr, 0x01dc, 0x180, 0x002f);
r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060);
r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200);
r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000);
r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d);
return 0;
}
static int
@ -155,6 +156,42 @@ r8a779f0_eth_serdes_chan_setting(struct r8a779f0_eth_serdes_channel *channel)
r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1);
r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208);
break;
case PHY_INTERFACE_MODE_USXGMII:
r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0000);
r8a779f0_eth_serdes_write32(channel->addr, 0x0014, 0x380, 0x0050);
r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2200);
r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x380, 0x0400);
r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0001);
r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x056a);
r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015);
r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x1100);
r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0001);
r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0001);
r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0001);
r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0300);
r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0300);
r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000);
r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0004);
r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000);
r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310);
r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0301);
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x180, BIT(0), 0);
if (ret)
return ret;
r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0301);
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x180, BIT(0), 0);
if (ret)
return ret;
r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000);
r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2300);
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(8), 0);
if (ret)
return ret;
break;
default:
return -EOPNOTSUPP;
}
@ -179,6 +216,14 @@ r8a779f0_eth_serdes_chan_speed(struct r8a779f0_eth_serdes_channel *channel)
return ret;
r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000);
break;
case PHY_INTERFACE_MODE_USXGMII:
r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0120);
usleep_range(10, 20);
r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2600);
ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(10), 0);
if (ret)
return ret;
break;
default:
return -EOPNOTSUPP;
}