mirror of
https://github.com/torvalds/linux.git
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Merge branch 'for-6.18/core' into for-linus
- allow HID-BPF to rebind a driver to hid-multitouch (Benjamin Tissoires) - Change hid_driver to use a const char* for .name (Rahul Rameshbabu)
This commit is contained in:
Benjamin Tissoires
commit
d325efac59
3
.mailmap
3
.mailmap
|
|
@ -226,6 +226,8 @@ Domen Puncer <domen@coderock.org>
|
|||
Douglas Gilbert <dougg@torque.net>
|
||||
Drew Fustini <fustini@kernel.org> <drew@pdp7.com>
|
||||
<duje@dujemihanovic.xyz> <duje.mihanovic@skole.hr>
|
||||
Easwar Hariharan <easwar.hariharan@linux.microsoft.com> <easwar.hariharan@intel.com>
|
||||
Easwar Hariharan <easwar.hariharan@linux.microsoft.com> <eahariha@linux.microsoft.com>
|
||||
Ed L. Cashin <ecashin@coraid.com>
|
||||
Elliot Berman <quic_eberman@quicinc.com> <eberman@codeaurora.org>
|
||||
Enric Balletbo i Serra <eballetbo@kernel.org> <enric.balletbo@collabora.com>
|
||||
|
|
@ -673,6 +675,7 @@ Muchun Song <muchun.song@linux.dev> <smuchun@gmail.com>
|
|||
Ross Zwisler <zwisler@kernel.org> <ross.zwisler@linux.intel.com>
|
||||
Rudolf Marek <R.Marek@sh.cvut.cz>
|
||||
Rui Saraiva <rmps@joel.ist.utl.pt>
|
||||
Sachin Mokashi <sachin.mokashi@intel.com> <sachinx.mokashi@intel.com>
|
||||
Sachin P Sant <ssant@in.ibm.com>
|
||||
Sai Prakash Ranjan <quic_saipraka@quicinc.com> <saiprakash.ranjan@codeaurora.org>
|
||||
Sakari Ailus <sakari.ailus@linux.intel.com> <sakari.ailus@iki.fi>
|
||||
|
|
|
|||
13
CREDITS
13
CREDITS
|
|
@ -3222,6 +3222,10 @@ D: AIC5800 IEEE 1394, RAW I/O on 1394
|
|||
D: Starter of Linux1394 effort
|
||||
S: ask per mail for current address
|
||||
|
||||
N: Boris Pismenny
|
||||
E: borisp@mellanox.com
|
||||
D: Kernel TLS implementation and offload support.
|
||||
|
||||
N: Nicolas Pitre
|
||||
E: nico@fluxnic.net
|
||||
D: StrongARM SA1100 support integrator & hacker
|
||||
|
|
@ -4168,6 +4172,9 @@ S: 1513 Brewster Dr.
|
|||
S: Carrollton, TX 75010
|
||||
S: USA
|
||||
|
||||
N: Dave Watson
|
||||
D: Kernel TLS implementation.
|
||||
|
||||
N: Tim Waugh
|
||||
E: tim@cyberelk.net
|
||||
D: Co-architect of the parallel-port sharing system
|
||||
|
|
@ -4378,6 +4385,12 @@ S: 542 West 112th Street, 5N
|
|||
S: New York, New York 10025
|
||||
S: USA
|
||||
|
||||
N: Masahiro Yamada
|
||||
E: masahiroy@kernel.org
|
||||
D: Kbuild Maintainer 2017-2025
|
||||
D: Kconfig Maintainer 2018-2025
|
||||
S: Japan
|
||||
|
||||
N: Li Yang
|
||||
E: leoli@freescale.com
|
||||
D: Freescale Highspeed USB device driver
|
||||
|
|
|
|||
20
Documentation/ABI/obsolete/automount-tracefs-debugfs
Normal file
20
Documentation/ABI/obsolete/automount-tracefs-debugfs
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
What: /sys/kernel/debug/tracing
|
||||
Date: May 2008
|
||||
KernelVersion: 2.6.27
|
||||
Contact: linux-trace-kernel@vger.kernel.org
|
||||
Description:
|
||||
|
||||
The ftrace was first added to the kernel, its interface was placed
|
||||
into the debugfs file system under the "tracing" directory. Access
|
||||
to the files were in /sys/kernel/debug/tracing. As systems wanted
|
||||
access to the tracing interface without having to enable debugfs, a
|
||||
new interface was created called "tracefs". This was a stand alone
|
||||
file system and was usually mounted in /sys/kernel/tracing.
|
||||
|
||||
To allow older tooling to continue to operate, when mounting
|
||||
debugfs, the tracefs file system would automatically get mounted in
|
||||
the "tracing" directory of debugfs. The tracefs interface was added
|
||||
in January 2015 in the v4.1 kernel.
|
||||
|
||||
All tooling should now be using tracefs directly and the "tracing"
|
||||
directory in debugfs should be removed by January 2030.
|
||||
|
|
@ -731,7 +731,7 @@ Contact: linux-block@vger.kernel.org
|
|||
Description:
|
||||
[RW] If the device is registered for writeback throttling, then
|
||||
this file shows the target minimum read latency. If this latency
|
||||
is exceeded in a given window of time (see wb_window_usec), then
|
||||
is exceeded in a given window of time (see curr_win_nsec), then
|
||||
the writeback throttling will start scaling back writes. Writing
|
||||
a value of '0' to this file disables the feature. Writing a
|
||||
value of '-1' to this file resets the value to the default
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ Description:
|
|||
visible for devices supporting the capability.
|
||||
|
||||
|
||||
What: /sys/kernel/debug/memX/clear_poison
|
||||
What: /sys/kernel/debug/cxl/memX/clear_poison
|
||||
Date: April, 2023
|
||||
KernelVersion: v6.4
|
||||
Contact: linux-cxl@vger.kernel.org
|
||||
|
|
|
|||
|
|
@ -36,3 +36,10 @@ Description: Displays the content of the Runtime Configuration Interface
|
|||
Table version 2 on Dell EMC PowerEdge systems in binary format
|
||||
Users: It is used by Dell EMC OpenManage Server Administrator tool to
|
||||
populate BIOS setup page.
|
||||
|
||||
What: /sys/firmware/efi/ovmf_debug_log
|
||||
Date: July 2025
|
||||
Contact: Gerd Hoffmann <kraxel@redhat.com>, linux-efi@vger.kernel.org
|
||||
Description: Displays the content of the OVMF debug log buffer. The file is
|
||||
only present in case the firmware supports logging to a memory
|
||||
buffer.
|
||||
|
|
|
|||
|
|
@ -861,3 +861,25 @@ Description: This is a read-only entry to show the value of sb.s_encoding_flags,
|
|||
SB_ENC_STRICT_MODE_FL 0x00000001
|
||||
SB_ENC_NO_COMPAT_FALLBACK_FL 0x00000002
|
||||
============================ ==========
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/reserved_pin_section
|
||||
Date: June 2025
|
||||
Contact: "Chao Yu" <chao@kernel.org>
|
||||
Description: This threshold is used to control triggering garbage collection while
|
||||
fallocating on pinned file, so, it can guarantee there is enough free
|
||||
reserved section before preallocating on pinned file.
|
||||
By default, the value is ovp_sections, especially, for zoned ufs, the
|
||||
value is 1.
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/gc_boost_gc_multiple
|
||||
Date: June 2025
|
||||
Contact: "Daeho Jeong" <daehojeong@google.com>
|
||||
Description: Set a multiplier for the background GC migration window when F2FS GC is
|
||||
boosted. The range should be from 1 to the segment count in a section.
|
||||
Default: 5
|
||||
|
||||
What: /sys/fs/f2fs/<disk>/gc_boost_gc_greedy
|
||||
Date: June 2025
|
||||
Contact: "Daeho Jeong" <daehojeong@google.com>
|
||||
Description: Control GC algorithm for boost GC. 0: cost benefit, 1: greedy
|
||||
Default: 1
|
||||
|
|
|
|||
|
|
@ -203,3 +203,18 @@ controllers, it is advisable to skip this testcase using this
|
|||
command::
|
||||
|
||||
# pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -v dma
|
||||
|
||||
Kselftest EP Doorbell
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
If the Endpoint MSI controller is used for the doorbell usecase, run below
|
||||
command for testing it:
|
||||
|
||||
# pci_endpoint_test -f pcie_ep_doorbell
|
||||
|
||||
# Starting 1 tests from 1 test cases.
|
||||
# RUN pcie_ep_doorbell.DOORBELL_TEST ...
|
||||
# OK pcie_ep_doorbell.DOORBELL_TEST
|
||||
ok 1 pcie_ep_doorbell.DOORBELL_TEST
|
||||
# PASSED: 1 / 1 tests passed.
|
||||
# Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
|
||||
|
|
|
|||
|
|
@ -131,3 +131,59 @@ Get IO accounting for pid 1, it works only with -p::
|
|||
linuxrc: read=65536, write=0, cancelled_write=0
|
||||
|
||||
The above command can be used with -v to get more debug information.
|
||||
|
||||
After the system starts, use `delaytop` to get the system-wide delay information,
|
||||
which includes system-wide PSI information and Top-N high-latency tasks.
|
||||
|
||||
`delaytop` supports sorting by CPU latency in descending order by default,
|
||||
displays the top 20 high-latency tasks by default, and refreshes the latency
|
||||
data every 2 seconds by default.
|
||||
|
||||
Get PSI information and Top-N tasks delay, since system boot::
|
||||
|
||||
bash# ./delaytop
|
||||
System Pressure Information: (avg10/avg60/avg300/total)
|
||||
CPU some: 0.0%/ 0.0%/ 0.0%/ 345(ms)
|
||||
CPU full: 0.0%/ 0.0%/ 0.0%/ 0(ms)
|
||||
Memory full: 0.0%/ 0.0%/ 0.0%/ 0(ms)
|
||||
Memory some: 0.0%/ 0.0%/ 0.0%/ 0(ms)
|
||||
IO full: 0.0%/ 0.0%/ 0.0%/ 65(ms)
|
||||
IO some: 0.0%/ 0.0%/ 0.0%/ 79(ms)
|
||||
IRQ full: 0.0%/ 0.0%/ 0.0%/ 0(ms)
|
||||
Top 20 processes (sorted by CPU delay):
|
||||
PID TGID COMMAND CPU(ms) IO(ms) SWAP(ms) RCL(ms) THR(ms) CMP(ms) WP(ms) IRQ(ms)
|
||||
----------------------------------------------------------------------------------------------
|
||||
161 161 zombie_memcg_re 1.40 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
130 130 blkcg_punt_bio 1.37 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
444 444 scsi_tmf_0 0.73 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
1280 1280 rsyslogd 0.53 0.04 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
12 12 ksoftirqd/0 0.47 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
1277 1277 nbd-server 0.44 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
308 308 kworker/2:2-sys 0.41 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
55 55 netns 0.36 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
1187 1187 acpid 0.31 0.03 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
6184 6184 kworker/1:2-sys 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
186 186 kaluad 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
18 18 ksoftirqd/1 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
185 185 kmpath_rdacd 0.23 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
190 190 kstrp 0.23 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
2759 2759 agetty 0.20 0.03 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
1190 1190 kworker/0:3-sys 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
1272 1272 sshd 0.15 0.04 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
1156 1156 license 0.15 0.11 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
134 134 md 0.13 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
6142 6142 kworker/3:2-xfs 0.13 0.00 0.00 0.00 0.00 0.00 0.00 0.00
|
||||
|
||||
Dynamic interactive interface of delaytop::
|
||||
|
||||
# ./delaytop -p pid
|
||||
Print delayacct stats
|
||||
|
||||
# ./delaytop -P num
|
||||
Display the top N tasks
|
||||
|
||||
# ./delaytop -n num
|
||||
Set delaytop refresh frequency (num times)
|
||||
|
||||
# ./delaytop -d secs
|
||||
Specify refresh interval as secs
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ zone_capacity_mb Device zone capacity (must always be equal to or lower than
|
|||
the zone size. Default: zone size.
|
||||
conv_zones Total number of conventioanl zones starting from sector 0.
|
||||
Default: 8.
|
||||
base_dir Path to the base directoy where to create the directory
|
||||
base_dir Path to the base directory where to create the directory
|
||||
containing the zone files of the device.
|
||||
Default=/var/local/zloop.
|
||||
The device directory containing the zone files is always
|
||||
|
|
|
|||
|
|
@ -435,8 +435,8 @@ both cgroups.
|
|||
Controlling Controllers
|
||||
-----------------------
|
||||
|
||||
Availablity
|
||||
~~~~~~~~~~~
|
||||
Availability
|
||||
~~~~~~~~~~~~
|
||||
|
||||
A controller is available in a cgroup when it is supported by the kernel (i.e.,
|
||||
compiled in, not disabled and not attached to a v1 hierarchy) and listed in the
|
||||
|
|
|
|||
|
|
@ -80,11 +80,11 @@ less sharing than average you'll need a larger-than-average metadata device.
|
|||
|
||||
As a guide, we suggest you calculate the number of bytes to use in the
|
||||
metadata device as 48 * $data_dev_size / $data_block_size but round it up
|
||||
to 2MB if the answer is smaller. If you're creating large numbers of
|
||||
to 2MiB if the answer is smaller. If you're creating large numbers of
|
||||
snapshots which are recording large amounts of change, you may find you
|
||||
need to increase this.
|
||||
|
||||
The largest size supported is 16GB: If the device is larger,
|
||||
The largest size supported is 16GiB: If the device is larger,
|
||||
a warning will be issued and the excess space will not be used.
|
||||
|
||||
Reloading a pool table
|
||||
|
|
@ -107,13 +107,13 @@ Using an existing pool device
|
|||
|
||||
$data_block_size gives the smallest unit of disk space that can be
|
||||
allocated at a time expressed in units of 512-byte sectors.
|
||||
$data_block_size must be between 128 (64KB) and 2097152 (1GB) and a
|
||||
multiple of 128 (64KB). $data_block_size cannot be changed after the
|
||||
$data_block_size must be between 128 (64KiB) and 2097152 (1GiB) and a
|
||||
multiple of 128 (64KiB). $data_block_size cannot be changed after the
|
||||
thin-pool is created. People primarily interested in thin provisioning
|
||||
may want to use a value such as 1024 (512KB). People doing lots of
|
||||
snapshotting may want a smaller value such as 128 (64KB). If you are
|
||||
may want to use a value such as 1024 (512KiB). People doing lots of
|
||||
snapshotting may want a smaller value such as 128 (64KiB). If you are
|
||||
not zeroing newly-allocated data, a larger $data_block_size in the
|
||||
region of 256000 (128MB) is suggested.
|
||||
region of 262144 (128MiB) is suggested.
|
||||
|
||||
$low_water_mark is expressed in blocks of size $data_block_size. If
|
||||
free space on the data device drops below this level then a dm event
|
||||
|
|
@ -291,7 +291,7 @@ i) Constructor
|
|||
error_if_no_space:
|
||||
Error IOs, instead of queueing, if no space.
|
||||
|
||||
Data block size must be between 64KB (128 sectors) and 1GB
|
||||
Data block size must be between 64KiB (128 sectors) and 1GiB
|
||||
(2097152 sectors) inclusive.
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -214,7 +214,7 @@ Spectre_v1 X
|
|||
Spectre_v2 X X
|
||||
Spectre_v2_user X X * (Note 1)
|
||||
SRBDS X X X X
|
||||
SRSO X X
|
||||
SRSO X X X X
|
||||
SSB (Note 4)
|
||||
TAA X X X X * (Note 2)
|
||||
TSA X X X X
|
||||
|
|
|
|||
|
|
@ -311,6 +311,27 @@ crashkernel syntax
|
|||
|
||||
crashkernel=0,low
|
||||
|
||||
4) crashkernel=size,cma
|
||||
|
||||
Reserve additional crash kernel memory from CMA. This reservation is
|
||||
usable by the first system's userspace memory and kernel movable
|
||||
allocations (memory balloon, zswap). Pages allocated from this memory
|
||||
range will not be included in the vmcore so this should not be used if
|
||||
dumping of userspace memory is intended and it has to be expected that
|
||||
some movable kernel pages may be missing from the dump.
|
||||
|
||||
A standard crashkernel reservation, as described above, is still needed
|
||||
to hold the crash kernel and initrd.
|
||||
|
||||
This option increases the risk of a kdump failure: DMA transfers
|
||||
configured by the first kernel may end up corrupting the second
|
||||
kernel's memory.
|
||||
|
||||
This reservation method is intended for systems that can't afford to
|
||||
sacrifice enough memory for standard crashkernel reservation and where
|
||||
less reliable and possibly incomplete kdump is preferable to no kdump at
|
||||
all.
|
||||
|
||||
Boot into System Kernel
|
||||
-----------------------
|
||||
1) Update the boot loader (such as grub, yaboot, or lilo) configuration
|
||||
|
|
|
|||
|
|
@ -994,6 +994,28 @@
|
|||
0: to disable low allocation.
|
||||
It will be ignored when crashkernel=X,high is not used
|
||||
or memory reserved is below 4G.
|
||||
crashkernel=size[KMG],cma
|
||||
[KNL, X86] Reserve additional crash kernel memory from
|
||||
CMA. This reservation is usable by the first system's
|
||||
userspace memory and kernel movable allocations (memory
|
||||
balloon, zswap). Pages allocated from this memory range
|
||||
will not be included in the vmcore so this should not
|
||||
be used if dumping of userspace memory is intended and
|
||||
it has to be expected that some movable kernel pages
|
||||
may be missing from the dump.
|
||||
|
||||
A standard crashkernel reservation, as described above,
|
||||
is still needed to hold the crash kernel and initrd.
|
||||
|
||||
This option increases the risk of a kdump failure: DMA
|
||||
transfers configured by the first kernel may end up
|
||||
corrupting the second kernel's memory.
|
||||
|
||||
This reservation method is intended for systems that
|
||||
can't afford to sacrifice enough memory for standard
|
||||
crashkernel reservation and where less reliable and
|
||||
possibly incomplete kdump is preferable to no kdump at
|
||||
all.
|
||||
|
||||
cryptomgr.notests
|
||||
[KNL] Disable crypto self-tests
|
||||
|
|
@ -1806,6 +1828,27 @@
|
|||
backtraces on all cpus.
|
||||
Format: 0 | 1
|
||||
|
||||
hash_pointers=
|
||||
[KNL,EARLY]
|
||||
By default, when pointers are printed to the console
|
||||
or buffers via the %p format string, that pointer is
|
||||
"hashed", i.e. obscured by hashing the pointer value.
|
||||
This is a security feature that hides actual kernel
|
||||
addresses from unprivileged users, but it also makes
|
||||
debugging the kernel more difficult since unequal
|
||||
pointers can no longer be compared. The choices are:
|
||||
Format: { auto | always | never }
|
||||
Default: auto
|
||||
|
||||
auto - Hash pointers unless slab_debug is enabled.
|
||||
always - Always hash pointers (even if slab_debug is
|
||||
enabled).
|
||||
never - Never hash pointers. This option should only
|
||||
be specified when debugging the kernel. Do
|
||||
not use on production kernels. The boot
|
||||
param "no_hash_pointers" is an alias for
|
||||
this mode.
|
||||
|
||||
hashdist= [KNL,NUMA] Large hashes allocated during boot
|
||||
are distributed across NUMA nodes. Defaults on
|
||||
for 64-bit NUMA, off otherwise.
|
||||
|
|
@ -4194,18 +4237,7 @@
|
|||
|
||||
no_hash_pointers
|
||||
[KNL,EARLY]
|
||||
Force pointers printed to the console or buffers to be
|
||||
unhashed. By default, when a pointer is printed via %p
|
||||
format string, that pointer is "hashed", i.e. obscured
|
||||
by hashing the pointer value. This is a security feature
|
||||
that hides actual kernel addresses from unprivileged
|
||||
users, but it also makes debugging the kernel more
|
||||
difficult since unequal pointers can no longer be
|
||||
compared. However, if this command-line option is
|
||||
specified, then all normal pointers will have their true
|
||||
value printed. This option should only be specified when
|
||||
debugging the kernel. Please do not use on production
|
||||
kernels.
|
||||
Alias for "hash_pointers=never".
|
||||
|
||||
nohibernate [HIBERNATION] Disable hibernation and resume.
|
||||
|
||||
|
|
@ -4557,7 +4589,7 @@
|
|||
bit 2: print timer info
|
||||
bit 3: print locks info if CONFIG_LOCKDEP is on
|
||||
bit 4: print ftrace buffer
|
||||
bit 5: print all printk messages in buffer
|
||||
bit 5: replay all messages on consoles at the end of panic
|
||||
bit 6: print all CPUs backtrace (if available in the arch)
|
||||
bit 7: print only tasks in uninterruptible (blocked) state
|
||||
*Be aware* that this option may print a _lot_ of lines,
|
||||
|
|
@ -4565,6 +4597,25 @@
|
|||
Use this option carefully, maybe worth to setup a
|
||||
bigger log buffer with "log_buf_len" along with this.
|
||||
|
||||
panic_sys_info= A comma separated list of extra information to be dumped
|
||||
on panic.
|
||||
Format: val[,val...]
|
||||
Where @val can be any of the following:
|
||||
|
||||
tasks: print all tasks info
|
||||
mem: print system memory info
|
||||
timers: print timers info
|
||||
locks: print locks info if CONFIG_LOCKDEP is on
|
||||
ftrace: print ftrace buffer
|
||||
all_bt: print all CPUs backtrace (if available in the arch)
|
||||
blocked_tasks: print only tasks in uninterruptible (blocked) state
|
||||
|
||||
This is a human readable alternative to the 'panic_print' option.
|
||||
|
||||
panic_console_replay
|
||||
When panic happens, replay all kernel messages on
|
||||
consoles at the end of panic.
|
||||
|
||||
parkbd.port= [HW] Parallel port number the keyboard adapter is
|
||||
connected to, default is 0.
|
||||
Format: <parport#>
|
||||
|
|
@ -6603,6 +6654,10 @@
|
|||
Documentation/admin-guide/mm/slab.rst.
|
||||
(slub_debug legacy name also accepted for now)
|
||||
|
||||
Using this option implies the "no_hash_pointers"
|
||||
option which can be undone by adding the
|
||||
"hash_pointers=always" option.
|
||||
|
||||
slab_max_order= [MM]
|
||||
Determines the maximum allowed order for slabs.
|
||||
A high setting may cause OOMs due to memory
|
||||
|
|
@ -7032,6 +7087,11 @@
|
|||
consumed by the stack hash table. By default this is set
|
||||
to false.
|
||||
|
||||
stack_depot_max_pools= [KNL,EARLY]
|
||||
Specify the maximum number of pools to use for storing
|
||||
stack traces. Pools are allocated on-demand up to this
|
||||
limit. Default value is 8191 pools.
|
||||
|
||||
stacktrace [FTRACE]
|
||||
Enabled the stack tracer on boot up.
|
||||
|
||||
|
|
|
|||
|
|
@ -890,7 +890,7 @@ bit 1 print system memory info
|
|||
bit 2 print timer info
|
||||
bit 3 print locks info if ``CONFIG_LOCKDEP`` is on
|
||||
bit 4 print ftrace buffer
|
||||
bit 5 print all printk messages in buffer
|
||||
bit 5 replay all messages on consoles at the end of panic
|
||||
bit 6 print all CPUs backtrace (if available in the arch)
|
||||
bit 7 print only tasks in uninterruptible (blocked) state
|
||||
===== ============================================
|
||||
|
|
@ -900,6 +900,24 @@ So for example to print tasks and memory info on panic, user can::
|
|||
echo 3 > /proc/sys/kernel/panic_print
|
||||
|
||||
|
||||
panic_sys_info
|
||||
==============
|
||||
|
||||
A comma separated list of extra information to be dumped on panic,
|
||||
for example, "tasks,mem,timers,...". It is a human readable alternative
|
||||
to 'panic_print'. Possible values are:
|
||||
|
||||
============= ===================================================
|
||||
tasks print all tasks info
|
||||
mem print system memory info
|
||||
timer print timers info
|
||||
lock print locks info if CONFIG_LOCKDEP is on
|
||||
ftrace print ftrace buffer
|
||||
all_bt print all CPUs backtrace (if available in the arch)
|
||||
blocked_tasks print only tasks in uninterruptible (blocked) state
|
||||
============= ===================================================
|
||||
|
||||
|
||||
panic_on_rcu_stall
|
||||
==================
|
||||
|
||||
|
|
|
|||
|
|
@ -133,4 +133,3 @@ More Memory Management Functions
|
|||
.. kernel-doc:: mm/mmu_notifier.c
|
||||
.. kernel-doc:: mm/balloon_compaction.c
|
||||
.. kernel-doc:: mm/huge_memory.c
|
||||
.. kernel-doc:: mm/io-mapping.c
|
||||
|
|
|
|||
|
|
@ -76,20 +76,21 @@ unit as preprocessor statement. The above example would then read::
|
|||
within the corresponding compilation unit before the #include for
|
||||
<linux/export.h>. Typically it's placed before the first #include statement.
|
||||
|
||||
Using the EXPORT_SYMBOL_GPL_FOR_MODULES() macro
|
||||
-----------------------------------------------
|
||||
Using the EXPORT_SYMBOL_FOR_MODULES() macro
|
||||
-------------------------------------------
|
||||
|
||||
Symbols exported using this macro are put into a module namespace. This
|
||||
namespace cannot be imported.
|
||||
namespace cannot be imported. These exports are GPL-only as they are only
|
||||
intended for in-tree modules.
|
||||
|
||||
The macro takes a comma separated list of module names, allowing only those
|
||||
modules to access this symbol. Simple tail-globs are supported.
|
||||
|
||||
For example::
|
||||
|
||||
EXPORT_SYMBOL_GPL_FOR_MODULES(preempt_notifier_inc, "kvm,kvm-*")
|
||||
EXPORT_SYMBOL_FOR_MODULES(preempt_notifier_inc, "kvm,kvm-*")
|
||||
|
||||
will limit usage of this symbol to modules whoes name matches the given
|
||||
will limit usage of this symbol to modules whose name matches the given
|
||||
patterns.
|
||||
|
||||
How to use Symbols exported in Namespaces
|
||||
|
|
|
|||
|
|
@ -60,7 +60,6 @@ properties:
|
|||
- const: bus
|
||||
- const: core
|
||||
- const: vsync
|
||||
- const: lut
|
||||
- const: tbu
|
||||
- const: tbu_rt
|
||||
# MSM8996 has additional iommu clock
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
* Broadcom SBA RAID engine
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following
|
||||
"brcm,iproc-sba"
|
||||
"brcm,iproc-sba-v2"
|
||||
The "brcm,iproc-sba" has support for only 6 PQ coefficients
|
||||
The "brcm,iproc-sba-v2" has support for only 30 PQ coefficients
|
||||
- mboxes: List of phandle and mailbox channel specifiers
|
||||
|
||||
Example:
|
||||
|
||||
raid_mbox: mbox@67400000 {
|
||||
...
|
||||
#mbox-cells = <3>;
|
||||
...
|
||||
};
|
||||
|
||||
raid0 {
|
||||
compatible = "brcm,iproc-sba-v2";
|
||||
mboxes = <&raid_mbox 0 0x1 0xffff>,
|
||||
<&raid_mbox 1 0x1 0xffff>,
|
||||
<&raid_mbox 2 0x1 0xffff>,
|
||||
<&raid_mbox 3 0x1 0xffff>,
|
||||
<&raid_mbox 4 0x1 0xffff>,
|
||||
<&raid_mbox 5 0x1 0xffff>,
|
||||
<&raid_mbox 6 0x1 0xffff>,
|
||||
<&raid_mbox 7 0x1 0xffff>;
|
||||
};
|
||||
41
Documentation/devicetree/bindings/dma/brcm,iproc-sba.yaml
Normal file
41
Documentation/devicetree/bindings/dma/brcm,iproc-sba.yaml
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/brcm,iproc-sba.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom SBA RAID engine
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,iproc-sba
|
||||
- brcm,iproc-sba-v2
|
||||
|
||||
mboxes:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- mboxes
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
raid0 {
|
||||
compatible = "brcm,iproc-sba-v2";
|
||||
mboxes = <&raid_mbox 0 0x1 0xffff>,
|
||||
<&raid_mbox 1 0x1 0xffff>,
|
||||
<&raid_mbox 2 0x1 0xffff>,
|
||||
<&raid_mbox 3 0x1 0xffff>,
|
||||
<&raid_mbox 4 0x1 0xffff>,
|
||||
<&raid_mbox 5 0x1 0xffff>,
|
||||
<&raid_mbox 6 0x1 0xffff>,
|
||||
<&raid_mbox 7 0x1 0xffff>;
|
||||
};
|
||||
|
|
@ -23,6 +23,35 @@ allOf:
|
|||
properties:
|
||||
power-domains: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx23-dma-apbx
|
||||
then:
|
||||
properties:
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: audio-adc
|
||||
- const: audio-dac
|
||||
- const: spdif-tx
|
||||
- const: i2c
|
||||
- const: saif0
|
||||
- const: empty0
|
||||
- const: auart0-rx
|
||||
- const: auart0-tx
|
||||
- const: auart1-rx
|
||||
- const: auart1-tx
|
||||
- const: saif1
|
||||
- const: empty1
|
||||
- const: empty2
|
||||
- const: empty3
|
||||
- const: empty4
|
||||
- const: empty5
|
||||
else:
|
||||
properties:
|
||||
interrupt-names: false
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
|
|
@ -54,6 +83,10 @@ properties:
|
|||
minItems: 4
|
||||
maxItems: 16
|
||||
|
||||
interrupt-names:
|
||||
minItems: 4
|
||||
maxItems: 16
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
|
||||
|
|
|
|||
84
Documentation/devicetree/bindings/dma/marvell,orion-xor.yaml
Normal file
84
Documentation/devicetree/bindings/dma/marvell,orion-xor.yaml
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/marvell,orion-xor.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell XOR engine
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: marvell,armada-380-xor
|
||||
- const: marvell,orion-xor
|
||||
- enum:
|
||||
- marvell,armada-3700-xor
|
||||
- marvell,orion-xor
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Low registers for the XOR engine
|
||||
- description: High registers for the XOR engine
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"^(channel|xor)[0-9]+$":
|
||||
description: XOR channel sub-node
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
interrupts:
|
||||
description: Interrupt specifier for the XOR channel
|
||||
items:
|
||||
- description: Interrupt for this channel
|
||||
|
||||
dmacap,memcpy:
|
||||
type: boolean
|
||||
deprecated: true
|
||||
description:
|
||||
Indicates that the XOR channel is capable of memcpy operations
|
||||
|
||||
dmacap,memset:
|
||||
type: boolean
|
||||
deprecated: true
|
||||
description:
|
||||
Indicates that the XOR channel is capable of memset operations
|
||||
|
||||
dmacap,xor:
|
||||
type: boolean
|
||||
deprecated: true
|
||||
description:
|
||||
Indicates that the XOR channel is capable of xor operations
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
xor@d0060900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xd0060900 0x100>,
|
||||
<0xd0060b00 0x100>;
|
||||
clocks = <&coreclk 0>;
|
||||
|
||||
xor00 {
|
||||
interrupts = <51>;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <52>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
* Marvell XOR engines
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following:
|
||||
- "marvell,orion-xor"
|
||||
- "marvell,armada-380-xor"
|
||||
- "marvell,armada-3700-xor".
|
||||
- reg: Should contain registers location and length (two sets)
|
||||
the first set is the low registers, the second set the high
|
||||
registers for the XOR engine.
|
||||
- clocks: pointer to the reference clock
|
||||
|
||||
The DT node must also contains sub-nodes for each XOR channel that the
|
||||
XOR engine has. Those sub-nodes have the following required
|
||||
properties:
|
||||
- interrupts: interrupt of the XOR channel
|
||||
|
||||
The sub-nodes used to contain one or several of the following
|
||||
properties, but they are now deprecated:
|
||||
- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
|
||||
- dmacap,memset to indicate that the XOR channel is capable of memset operations
|
||||
- dmacap,xor to indicate that the XOR channel is capable of xor operations
|
||||
- dmacap,interrupt to indicate that the XOR channel is capable of
|
||||
generating interrupts
|
||||
|
||||
Example:
|
||||
|
||||
xor@d0060900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xd0060900 0x100
|
||||
0xd0060b00 0x100>;
|
||||
clocks = <&coreclk 0>;
|
||||
|
||||
xor00 {
|
||||
interrupts = <51>;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <52>;
|
||||
};
|
||||
};
|
||||
|
|
@ -24,12 +24,14 @@ properties:
|
|||
- qcom,sm6350-gpi-dma
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,milos-gpi-dma
|
||||
- qcom,qcm2290-gpi-dma
|
||||
- qcom,qcs8300-gpi-dma
|
||||
- qcom,qdu1000-gpi-dma
|
||||
- qcom,sa8775p-gpi-dma
|
||||
- qcom,sar2130p-gpi-dma
|
||||
- qcom,sc7280-gpi-dma
|
||||
- qcom,sc8280xp-gpi-dma
|
||||
- qcom,sdx75-gpi-dma
|
||||
- qcom,sm6115-gpi-dma
|
||||
- qcom,sm6375-gpi-dma
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/sophgo,cv1800b-dmamux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Sophgo CV1800/SG200 Series DMA multiplexer
|
||||
|
||||
maintainers:
|
||||
- Inochi Amaoto <inochiama@gmail.com>
|
||||
|
||||
description:
|
||||
The DMA multiplexer of CV1800 is a subdevice of the system
|
||||
controller. It support mapping 8 channels, but each channel
|
||||
can be mapped only once.
|
||||
|
||||
allOf:
|
||||
- $ref: dma-router.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sophgo,cv1800b-dmamux
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: DMA channal remapping register
|
||||
- description: DMA channel interrupt mapping register
|
||||
|
||||
'#dma-cells':
|
||||
const: 2
|
||||
description:
|
||||
The first cells is device id. The second one is the cpu id.
|
||||
|
||||
dma-masters:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- '#dma-cells'
|
||||
- dma-masters
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
dma-router@154 {
|
||||
compatible = "sophgo,cv1800b-dmamux";
|
||||
reg = <0x154 0x8>, <0x298 0x4>;
|
||||
#dma-cells = <2>;
|
||||
dma-masters = <&dmac>;
|
||||
};
|
||||
|
|
@ -22,6 +22,11 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- apple,s5l8960x-i2c
|
||||
- apple,t7000-i2c
|
||||
- apple,s8000-i2c
|
||||
- apple,t8010-i2c
|
||||
- apple,t8015-i2c
|
||||
- apple,t8103-i2c
|
||||
- apple,t8112-i2c
|
||||
- apple,t6000-i2c
|
||||
|
|
|
|||
179
Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
Normal file
179
Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface
|
||||
|
||||
maintainers:
|
||||
- Wolfram Sang <wsa+renesas@sang-engineering.com>
|
||||
- Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a08g045-i3c # RZ/G3S
|
||||
- renesas,r9a09g047-i3c # RZ/G3E
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: Non-recoverable internal error interrupt
|
||||
- description: Normal transfer error interrupt
|
||||
- description: Normal transfer abort interrupt
|
||||
- description: Normal response status buffer full interrupt
|
||||
- description: Normal command buffer empty interrupt
|
||||
- description: Normal IBI status buffer full interrupt
|
||||
- description: Normal Rx data buffer full interrupt
|
||||
- description: Normal Tx data buffer empty interrupt
|
||||
- description: Normal receive status buffer full interrupt
|
||||
- description: START condition detection interrupt
|
||||
- description: STOP condition detection interrupt
|
||||
- description: Transmit end interrupt
|
||||
- description: NACK detection interrupt
|
||||
- description: Arbitration lost interrupt
|
||||
- description: Timeout detection interrupt
|
||||
- description: Wake-up condition detection interrupt
|
||||
- description: HDR Exit Pattern detection interrupt
|
||||
minItems: 16
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: ierr
|
||||
- const: terr
|
||||
- const: abort
|
||||
- const: resp
|
||||
- const: cmd
|
||||
- const: ibi
|
||||
- const: rx
|
||||
- const: tx
|
||||
- const: rcv
|
||||
- const: st
|
||||
- const: sp
|
||||
- const: tend
|
||||
- const: nack
|
||||
- const: al
|
||||
- const: tmo
|
||||
- const: wu
|
||||
- const: exit
|
||||
minItems: 16
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: APB bus clock
|
||||
- description: transfer clock
|
||||
- description: SFRs clock
|
||||
minItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pclk
|
||||
- const: tclk
|
||||
- const: pclkrw
|
||||
minItems: 2
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: Reset signal
|
||||
- description: APB interface reset signal/SCAN reset signal
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: presetn
|
||||
- const: tresetn
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clock-names
|
||||
- clocks
|
||||
- power-domains
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
allOf:
|
||||
- $ref: i3c.yaml#
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r9a08g045-i3c
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
interrupts:
|
||||
minItems: 17
|
||||
interrupt-names:
|
||||
minItems: 17
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,r9a09g047-i3c
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
clock-names:
|
||||
minItems: 3
|
||||
interrupts:
|
||||
maxItems: 16
|
||||
interrupt-names:
|
||||
maxItems: 16
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a08g045-cpg.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
i3c@1005b000 {
|
||||
compatible = "renesas,r9a08g045-i3c";
|
||||
reg = <0x1005b000 0x1000>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
|
||||
<&cpg CPG_MOD R9A08G045_I3C_TCLK>;
|
||||
clock-names = "pclk", "tclk";
|
||||
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ierr", "terr", "abort", "resp",
|
||||
"cmd", "ibi", "rx", "tx", "rcv",
|
||||
"st", "sp", "tend", "nack",
|
||||
"al", "tmo", "wu", "exit";
|
||||
resets = <&cpg R9A08G045_I3C_PRESETN>,
|
||||
<&cpg R9A08G045_I3C_TRESETN>;
|
||||
reset-names = "presetn", "tresetn";
|
||||
power-domains = <&cpg>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
...
|
||||
|
|
@ -68,13 +68,13 @@ examples:
|
|||
#include <dt-bindings/reset/sun8i-h3-ccu.h>
|
||||
|
||||
msgbox: mailbox@1c17000 {
|
||||
compatible = "allwinner,sun8i-h3-msgbox",
|
||||
"allwinner,sun6i-a31-msgbox";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MSGBOX>;
|
||||
resets = <&ccu RST_BUS_MSGBOX>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
compatible = "allwinner,sun8i-h3-msgbox",
|
||||
"allwinner,sun6i-a31-msgbox";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MSGBOX>;
|
||||
resets = <&ccu RST_BUS_MSGBOX>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
description:
|
||||
Contains the interrupt information corresponding to each of the 3 links
|
||||
of MHU.
|
||||
|
|
@ -46,8 +46,8 @@ additionalProperties: false
|
|||
examples:
|
||||
- |
|
||||
mailbox@c883c404 {
|
||||
compatible = "amlogic,meson-gxbb-mhu";
|
||||
reg = <0xc883c404 0x4c>;
|
||||
interrupts = <208>, <209>, <210>;
|
||||
#mbox-cells = <1>;
|
||||
compatible = "amlogic,meson-gxbb-mhu";
|
||||
reg = <0xc883c404 0x4c>;
|
||||
interrupts = <208>, <209>, <210>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -78,11 +78,11 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
mailbox@77408000 {
|
||||
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
|
||||
reg = <0x77408000 0x4000>;
|
||||
interrupts = <1 583 4>, <1 584 4>, <1 585 4>, <1 586 4>;
|
||||
interrupt-names = "send-empty", "send-not-empty",
|
||||
"recv-empty", "recv-not-empty";
|
||||
#mbox-cells = <0>;
|
||||
};
|
||||
mailbox@77408000 {
|
||||
compatible = "apple,t8103-asc-mailbox", "apple,asc-mailbox-v4";
|
||||
reg = <0x77408000 0x4000>;
|
||||
interrupts = <1 583 4>, <1 584 4>, <1 585 4>, <1 586 4>;
|
||||
interrupt-names = "send-empty", "send-not-empty",
|
||||
"recv-empty", "recv-not-empty";
|
||||
#mbox-cells = <0>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,68 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ASPEED AST2700 mailbox controller
|
||||
|
||||
maintainers:
|
||||
- Jammy Huang <jammy_huang@aspeedtech.com>
|
||||
|
||||
description: >
|
||||
ASPEED AST2700 has multiple processors that need to communicate with each
|
||||
other. The mailbox controller provides a way for these processors to send
|
||||
messages to each other. It is a hardware-based inter-processor communication
|
||||
mechanism that allows processors to send and receive messages through
|
||||
dedicated channels.
|
||||
|
||||
The mailbox's tx/rx are independent, meaning that one processor can send a
|
||||
message while another processor is receiving a message simultaneously.
|
||||
There are 4 channels available for both tx and rx operations. Each channel
|
||||
has a FIFO buffer that can hold messages of a fixed size (32 bytes in this
|
||||
case).
|
||||
|
||||
The mailbox controller also supports interrupt generation, allowing
|
||||
processors to notify each other when a message is available or when an event
|
||||
occurs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: aspeed,ast2700-mailbox
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: TX control register
|
||||
- description: RX control register
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#mbox-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- "#mbox-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mailbox@12c1c200 {
|
||||
compatible = "aspeed,ast2700-mailbox";
|
||||
reg = <0x12c1c200 0x100>, <0x12c1c300 0x100>;
|
||||
reg-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mailbox/brcm,bcm74110-mbox.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM74110 Mailbox
|
||||
|
||||
maintainers:
|
||||
- Justin Chen <justin.chen@broadcom.com>
|
||||
- Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
|
||||
description: Broadcom mailbox hardware first introduced with 74110
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm74110-mbox
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: RX doorbell and watermark interrupts
|
||||
- description: TX doorbell and watermark interrupts
|
||||
|
||||
"#mbox-cells":
|
||||
const: 2
|
||||
description:
|
||||
The first cell is channel type and second cell is shared memory slot
|
||||
|
||||
brcm,rx:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: RX Mailbox number
|
||||
|
||||
brcm,tx:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: TX Mailbox number
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- "#mbox-cells"
|
||||
- brcm,rx
|
||||
- brcm,tx
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
mailbox@a552000 {
|
||||
compatible = "brcm,bcm74110-mbox";
|
||||
reg = <0xa552000 0x1104>;
|
||||
interrupts = <GIC_SPI 0x67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 0x66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <0x2>;
|
||||
brcm,rx = <0x7>;
|
||||
brcm,tx = <0x6>;
|
||||
};
|
||||
|
|
@ -59,9 +59,6 @@ description: |
|
|||
<dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^hsp@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
|
|
@ -131,14 +128,10 @@ examples:
|
|||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||
|
||||
hsp_top0: hsp@3c00000 {
|
||||
mailbox@3c00000 {
|
||||
compatible = "nvidia,tegra186-hsp";
|
||||
reg = <0x03c00000 0xa0000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "doorbell";
|
||||
#mbox-cells = <2>;
|
||||
};
|
||||
|
||||
client {
|
||||
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_CCPLEX>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ examples:
|
|||
# Example apcs with msm8996
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
apcs_glb: mailbox@9820000 {
|
||||
mailbox@9820000 {
|
||||
compatible = "qcom,msm8996-apcs-hmss-global";
|
||||
reg = <0x9820000 0x1000>;
|
||||
|
||||
|
|
@ -259,13 +259,6 @@ examples:
|
|||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rpm-glink {
|
||||
compatible = "qcom,glink-rpm";
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,rpm-msg-ram = <&rpm_msg_ram>;
|
||||
mboxes = <&apcs_glb 0>;
|
||||
};
|
||||
|
||||
# Example apcs with qcs404
|
||||
- |
|
||||
#define GCC_APSS_AHB_CLK_SRC 1
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,milos-ipcc
|
||||
- qcom,qcs8300-ipcc
|
||||
- qcom,qdu1000-ipcc
|
||||
- qcom,sa8255p-ipcc
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ examples:
|
|||
- |
|
||||
/* OMAP4 */
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
mailbox: mailbox@4a0f4000 {
|
||||
mailbox@4a0f4000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x4a0f4000 0x200>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
@ -260,13 +260,9 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
dsp {
|
||||
mboxes = <&mailbox &mbox_dsp>;
|
||||
};
|
||||
|
||||
- |
|
||||
/* AM33xx */
|
||||
mailbox1: mailbox@480c8000 {
|
||||
mailbox@480c8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480c8000 0x200>;
|
||||
interrupts = <77>;
|
||||
|
|
@ -283,7 +279,7 @@ examples:
|
|||
|
||||
- |
|
||||
/* AM65x */
|
||||
mailbox0_cluster0: mailbox@31f80000 {
|
||||
mailbox@31f80000 {
|
||||
compatible = "ti,am654-mailbox";
|
||||
reg = <0x31f80000 0x200>;
|
||||
#mbox-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ properties:
|
|||
- const: scfg
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
|
||||
interrupt-names:
|
||||
minItems: 1
|
||||
|
|
@ -68,12 +68,12 @@ examples:
|
|||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
secure_proxy: mailbox@32c00000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x32c00000 0x100000>,
|
||||
<0x32400000 0x100000>,
|
||||
<0x32800000 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
#mbox-cells = <1>;
|
||||
reg-names = "target_data", "rt", "scfg";
|
||||
reg = <0x32c00000 0x100000>,
|
||||
<0x32400000 0x100000>,
|
||||
<0x32800000 0x100000>;
|
||||
interrupt-names = "rx_011";
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ which are described in the following files:
|
|||
- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml
|
||||
- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml
|
||||
- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
|
||||
- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
|
||||
- Documentation/devicetree/bindings/phy/motorola,cpcap-usb-phy.yaml
|
||||
- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
|
||||
- Documentation/devicetree/bindings/rtc/cpcap-rtc.txt
|
||||
- Documentation/devicetree/bindings/leds/leds-cpcap.txt
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Analog Devices ADIN1200/ADIN1300 PHY
|
||||
|
||||
maintainers:
|
||||
- Alexandru Tachici <alexandru.tachici@analog.com>
|
||||
- Marcelo Schmitt <marcelo.schmitt@analog.com>
|
||||
|
||||
description: |
|
||||
Bindings for Analog Devices Industrial Ethernet PHYs
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: ADI ADIN1110 MAC-PHY
|
||||
|
||||
maintainers:
|
||||
- Alexandru Tachici <alexandru.tachici@analog.com>
|
||||
- Marcelo Schmitt <marcelo.schmitt@analog.com>
|
||||
|
||||
description: |
|
||||
The ADIN1110 is a low power single port 10BASE-T1L MAC-
|
||||
|
|
|
|||
|
|
@ -62,11 +62,13 @@ properties:
|
|||
items:
|
||||
- description: GMAC main clock
|
||||
- description: Peripheral registers interface clock
|
||||
- description: APB glue registers interface clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: stmmaceth
|
||||
- const: pclk
|
||||
- const: apb
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
|
|
@ -88,8 +90,8 @@ examples:
|
|||
compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
|
||||
reg = <0xe7070000 0x2000>, <0xec003000 0x1000>;
|
||||
reg-names = "dwmac", "apb";
|
||||
clocks = <&clk 1>, <&clk 2>;
|
||||
clock-names = "stmmaceth", "pclk";
|
||||
clocks = <&clk 1>, <&clk 2>, <&clk 3>;
|
||||
clock-names = "stmmaceth", "pclk", "apb";
|
||||
interrupts = <66>;
|
||||
interrupt-names = "macirq";
|
||||
phy-mode = "rgmii-id";
|
||||
|
|
|
|||
|
|
@ -1,39 +0,0 @@
|
|||
* Freescale 83xx and 512x PCI bridges
|
||||
|
||||
Freescale 83xx and 512x SOCs include the same PCI bridge core.
|
||||
|
||||
83xx/512x specific notes:
|
||||
- reg: should contain two address length tuples
|
||||
The first is for the internal PCI bridge registers
|
||||
The second is for the PCI config space access registers
|
||||
|
||||
Example (MPC8313ERDB)
|
||||
pci0: pci@e0008500 {
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0E -mini PCI */
|
||||
0x7000 0x0 0x0 0x1 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x3 &ipic 18 0x8
|
||||
0x7000 0x0 0x0 0x4 &ipic 18 0x8
|
||||
|
||||
/* IDSEL 0x0F - PCI slot */
|
||||
0x7800 0x0 0x0 0x1 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x2 &ipic 18 0x8
|
||||
0x7800 0x0 0x0 0x3 &ipic 17 0x8
|
||||
0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <66 0x8>;
|
||||
bus-range = <0x0 0x0>;
|
||||
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
|
||||
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
|
||||
clock-frequency = <66666666>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0xe0008500 0x100 /* internal registers */
|
||||
0xe0008300 0x8>; /* config space access registers */
|
||||
compatible = "fsl,mpc8349-pci";
|
||||
device_type = "pci";
|
||||
};
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
Aardvark PCIe controller
|
||||
|
||||
This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
|
||||
|
||||
The Device Tree node describing an Aardvark PCIe controller must
|
||||
contain the following properties:
|
||||
|
||||
- compatible: Should be "marvell,armada-3700-pcie"
|
||||
- reg: range of registers for the PCIe controller
|
||||
- interrupts: the interrupt line of the PCIe controller
|
||||
- #address-cells: set to <3>
|
||||
- #size-cells: set to <2>
|
||||
- device_type: set to "pci"
|
||||
- ranges: ranges for the PCI memory and I/O regions
|
||||
- #interrupt-cells: set to <1>
|
||||
- msi-controller: indicates that the PCIe controller can itself
|
||||
handle MSI interrupts
|
||||
- msi-parent: pointer to the MSI controller to be used
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties to
|
||||
define the mapping of the PCIe interface to interrupt numbers.
|
||||
- bus-range: PCI bus numbers covered
|
||||
- phys: the PCIe PHY handle
|
||||
- max-link-speed: see pci.txt
|
||||
- reset-gpios: see pci.txt
|
||||
|
||||
In addition, the Device Tree describing an Aardvark PCIe controller
|
||||
must include a sub-node that describes the legacy interrupt controller
|
||||
built into the PCIe controller. This sub-node must have the following
|
||||
properties:
|
||||
|
||||
- interrupt-controller
|
||||
- #interrupt-cells: set to <1>
|
||||
|
||||
Example:
|
||||
|
||||
pcie0: pcie@d0070000 {
|
||||
compatible = "marvell,armada-3700-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0xd0070000 0 0x20000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
msi-controller;
|
||||
msi-parent = <&pcie0>;
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
|
||||
0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
phys = <&comphy1 0>;
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/amazon,al-alpine-v3-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amazon Annapurna Labs Alpine v3 PCIe Host Bridge
|
||||
|
||||
maintainers:
|
||||
- Jonathan Chocron <jonnyc@amazon.com>
|
||||
|
||||
description:
|
||||
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys
|
||||
DesignWare PCI controller.
|
||||
|
||||
allOf:
|
||||
- $ref: snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amazon,al-alpine-v2-pcie
|
||||
- amazon,al-alpine-v3-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PCIe ECAM space
|
||||
- description: AL proprietary registers
|
||||
- description: Designware PCIe registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: config
|
||||
- const: controller
|
||||
- const: dbi
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@fb600000 {
|
||||
compatible = "amazon,al-alpine-v3-pcie";
|
||||
reg = <0x0 0xfb600000 0x0 0x00100000
|
||||
0x0 0xfd800000 0x0 0x00010000
|
||||
0x0 0xfd810000 0x0 0x00001000>;
|
||||
reg-names = "config", "controller", "dbi";
|
||||
bus-range = <0 255>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0x00 0 0 7>;
|
||||
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
|
||||
ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
|
||||
};
|
||||
};
|
||||
84
Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml
Normal file
84
Documentation/devicetree/bindings/pci/apm,xgene-pcie.yaml
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/apm,xgene-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: AppliedMicro X-Gene PCIe interface
|
||||
|
||||
maintainers:
|
||||
- Toan Le <toan@os.amperecomputing.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: apm,xgene-storm-pcie
|
||||
- const: apm,xgene-pcie
|
||||
- items:
|
||||
- const: apm,xgene-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Controller configuration registers
|
||||
- description: PCI configuration space registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: csr
|
||||
- const: cfg
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pcie
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- '#interrupt-cells'
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@1f2b0000 {
|
||||
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = <0x00 0x1f2b0000 0x0 0x00010000>, /* Controller registers */
|
||||
<0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000>, /* io */
|
||||
<0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000>,
|
||||
<0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1>,
|
||||
<0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1>,
|
||||
<0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1>,
|
||||
<0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
* Axis ARTPEC-6 PCIe interface
|
||||
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
|
||||
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
|
||||
|
||||
Required properties:
|
||||
- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
|
||||
"axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
|
||||
"axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
|
||||
"axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
|
||||
- reg: base addresses and lengths of the PCIe controller (DBI),
|
||||
the PHY controller, and configuration address space.
|
||||
- reg-names: Must include the following entries:
|
||||
- "dbi"
|
||||
- "phy"
|
||||
- "config"
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: Must include the following entries:
|
||||
- "msi": The interrupt that is asserted when an MSI is received
|
||||
- axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
|
||||
used to enable and control the Synopsys IP.
|
||||
|
||||
Example:
|
||||
|
||||
pcie@f8050000 {
|
||||
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
|
||||
reg = <0xf8050000 0x2000
|
||||
0xf8040000 0x1000
|
||||
0xc0000000 0x2000>;
|
||||
reg-names = "dbi", "phy", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
/* downstream I/O */
|
||||
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
|
||||
/* non-prefetchable memory */
|
||||
0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
axis,syscon-pcie = <&syscon>;
|
||||
};
|
||||
118
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.yaml
Normal file
118
Documentation/devicetree/bindings/pci/axis,artpec6-pcie.yaml
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright 2025 Axis AB
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Axis ARTPEC-6 PCIe host controller
|
||||
|
||||
maintainers:
|
||||
- Jesper Nilsson <jesper.nilsson@axis.com>
|
||||
|
||||
description:
|
||||
This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- axis,artpec6-pcie
|
||||
- axis,artpec6-pcie-ep
|
||||
- axis,artpec7-pcie
|
||||
- axis,artpec7-pcie-ep
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- axis,artpec6-pcie
|
||||
- axis,artpec6-pcie-ep
|
||||
- axis,artpec7-pcie
|
||||
- axis,artpec7-pcie-ep
|
||||
- const: snps,dw-pcie
|
||||
|
||||
reg:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
reg-names:
|
||||
minItems: 3
|
||||
maxItems: 4
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi
|
||||
|
||||
axis,syscon-pcie:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
System controller phandle used to enable and control the Synopsys IP.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- axis,syscon-pcie
|
||||
|
||||
oneOf:
|
||||
- $ref: snps,dw-pcie.yaml#
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: phy
|
||||
- const: config
|
||||
|
||||
- $ref: snps,dw-pcie-ep.yaml#
|
||||
properties:
|
||||
reg:
|
||||
minItems: 4
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: dbi2
|
||||
- const: phy
|
||||
- const: addr_space
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pcie@f8050000 {
|
||||
compatible = "axis,artpec6-pcie", "snps,dw-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0xf8050000 0x2000
|
||||
0xf8040000 0x1000
|
||||
0xc0000000 0x2000>;
|
||||
reg-names = "dbi", "phy", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,
|
||||
<0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
||||
axis,syscon-pcie = <&syscon>;
|
||||
};
|
||||
|
|
@ -107,6 +107,10 @@ properties:
|
|||
- const: bridge
|
||||
- const: swinit
|
||||
|
||||
num-lanes:
|
||||
default: 1
|
||||
maximum: 4
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,99 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/marvell,armada-3700-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 3700 (Aardvark) PCIe Controller
|
||||
|
||||
maintainers:
|
||||
- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
||||
- Pali Rohár <pali@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,armada-3700-pcie
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
msi-controller: true
|
||||
|
||||
msi-parent:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: PCIe reset GPIO signals.
|
||||
|
||||
interrupt-controller:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#interrupt-cells'
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@d0070000 {
|
||||
compatible = "marvell,armada-3700-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0xd0070000 0 0x20000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-controller;
|
||||
msi-parent = <&pcie0>;
|
||||
ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000>,
|
||||
<0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
phys = <&comphy1 0>;
|
||||
max-link-speed = <2>;
|
||||
reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -51,7 +51,7 @@ properties:
|
|||
|
||||
max-link-speed:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
enum: [ 1, 2, 3, 4, 5, 6 ]
|
||||
|
||||
msi-map:
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -1,46 +0,0 @@
|
|||
* Amazon Annapurna Labs PCIe host bridge
|
||||
|
||||
Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
|
||||
PCI core. It inherits common properties defined in
|
||||
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
|
||||
|
||||
Properties of the host controller node that differ from it are:
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Value should contain
|
||||
- "amazon,al-alpine-v2-pcie" for alpine_v2
|
||||
- "amazon,al-alpine-v3-pcie" for alpine_v3
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: Register ranges as listed in the reg-names property
|
||||
|
||||
- reg-names:
|
||||
Usage: required
|
||||
Value type: <stringlist>
|
||||
Definition: Must include the following entries
|
||||
- "config" PCIe ECAM space
|
||||
- "controller" AL proprietary registers
|
||||
- "dbi" Designware PCIe registers
|
||||
|
||||
Example:
|
||||
|
||||
pcie-external0: pcie@fb600000 {
|
||||
compatible = "amazon,al-alpine-v3-pcie";
|
||||
reg = <0x0 0xfb600000 0x0 0x00100000
|
||||
0x0 0xfd800000 0x0 0x00010000
|
||||
0x0 0xfd810000 0x0 0x00001000>;
|
||||
reg-names = "config", "controller", "dbi";
|
||||
bus-range = <0 255>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-map-mask = <0x00 0 0 7>;
|
||||
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
|
||||
ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
|
||||
};
|
||||
|
|
@ -51,10 +51,18 @@ properties:
|
|||
|
||||
phys:
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
description:
|
||||
This property is deprecated, instead of referencing this property from
|
||||
the host bridge node, use the property from the PCIe root port node.
|
||||
|
||||
phy-names:
|
||||
items:
|
||||
- const: pciephy
|
||||
deprecated: true
|
||||
description:
|
||||
Phandle to the register map node. This property is deprecated, and not
|
||||
required to add in the root port also, as the root port has only one phy.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
|
@ -71,12 +79,18 @@ properties:
|
|||
maxItems: 12
|
||||
|
||||
perst-gpios:
|
||||
description: GPIO controlled connection to PERST# signal
|
||||
description: GPIO controlled connection to PERST# signal. This property is
|
||||
deprecated, instead of referencing this property from the host bridge node,
|
||||
use the reset-gpios property from the root port node.
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
|
||||
wake-gpios:
|
||||
description: GPIO controlled connection to WAKE# signal
|
||||
description: GPIO controlled connection to WAKE# signal. This property is
|
||||
deprecated, instead of referencing this property from the host bridge node,
|
||||
use the property from the PCIe root port node.
|
||||
maxItems: 1
|
||||
deprecated: true
|
||||
|
||||
vddpe-3v3-supply:
|
||||
description: PCIe endpoint power supply
|
||||
|
|
@ -85,6 +99,20 @@ properties:
|
|||
opp-table:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
"^pcie@":
|
||||
type: object
|
||||
$ref: /schemas/pci/pci-pci-bridge.yaml#
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- reg-names
|
||||
|
|
|
|||
122
Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
Normal file
122
Documentation/devicetree/bindings/pci/qcom,pcie-sa8255p.yaml
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
|
||||
DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sa8255p
|
||||
|
||||
reg:
|
||||
description:
|
||||
The base address and size of the ECAM area for accessing PCI
|
||||
Configuration Space, as accessed from the parent bus. The base
|
||||
address corresponds to the first bus in the "bus-range" property. If
|
||||
no "bus-range" is specified, this will be bus 0 (the default).
|
||||
maxItems: 1
|
||||
|
||||
ranges:
|
||||
description:
|
||||
As described in IEEE Std 1275-1994, but must provide at least a
|
||||
definition of non-prefetchable memory. One or both of prefetchable Memory
|
||||
may also be provided.
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
|
||||
interrupt-names:
|
||||
items:
|
||||
- const: msi0
|
||||
- const: msi1
|
||||
- const: msi2
|
||||
- const: msi3
|
||||
- const: msi4
|
||||
- const: msi5
|
||||
- const: msi6
|
||||
- const: msi7
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
iommu-map: true
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
- power-domains
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pci@1c00000 {
|
||||
compatible = "qcom,pcie-sa8255p";
|
||||
reg = <0x4 0x00000000 0 0x10000000>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
|
||||
<0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
|
||||
bus-range = <0x00 0xff>;
|
||||
dma-coherent;
|
||||
linux,pci-domain = <0>;
|
||||
power-domains = <&scmi5_pd 0>;
|
||||
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
|
||||
<0x100 &pcie_smmu 0x0001 0x1>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
||||
"msi4", "msi5", "msi6", "msi7";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -16,7 +16,12 @@ description:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sa8775p
|
||||
oneOf:
|
||||
- const: qcom,pcie-sa8775p
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-qcs8300
|
||||
- const: qcom,pcie-sa8775p
|
||||
|
||||
reg:
|
||||
minItems: 6
|
||||
|
|
@ -61,11 +66,14 @@ properties:
|
|||
- const: global
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: PCIe controller reset
|
||||
- description: PCIe link down reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pci
|
||||
- const: link_down
|
||||
|
||||
required:
|
||||
- interconnects
|
||||
|
|
@ -161,8 +169,10 @@ examples:
|
|||
|
||||
power-domains = <&gcc PCIE_0_GDSC>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>;
|
||||
reset-names = "pci";
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
|
||||
reset-names = "pci",
|
||||
"link_down";
|
||||
|
||||
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
|
||||
|
|
|
|||
|
|
@ -165,9 +165,6 @@ examples:
|
|||
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
|
||||
<0x100 &apps_smmu 0x1c81 0x1>;
|
||||
|
||||
phys = <&pcie1_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie1_clkreq_n>;
|
||||
|
||||
|
|
@ -176,7 +173,18 @@ examples:
|
|||
resets = <&gcc GCC_PCIE_1_BCR>;
|
||||
reset-names = "pci";
|
||||
|
||||
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
vddpe-3v3-supply = <&pp3300_ssd>;
|
||||
pcie1_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
phys = <&pcie1_phy>;
|
||||
|
||||
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -33,8 +33,8 @@ properties:
|
|||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
|
|
@ -44,8 +44,6 @@ properties:
|
|||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: ref # REFERENCE clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
|
|
@ -117,17 +115,13 @@ examples:
|
|||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_CLKREF_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"ref",
|
||||
"tbu";
|
||||
"slave_q2a";
|
||||
|
||||
dma-coherent;
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,12 @@ description:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pcie-sm8150
|
||||
oneOf:
|
||||
- const: qcom,pcie-sm8150
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,pcie-qcs615
|
||||
- const: qcom,pcie-sm8150
|
||||
|
||||
reg:
|
||||
minItems: 5
|
||||
|
|
@ -33,8 +38,8 @@ properties:
|
|||
- const: mhi # MHI registers
|
||||
|
||||
clocks:
|
||||
minItems: 8
|
||||
maxItems: 8
|
||||
minItems: 6
|
||||
maxItems: 6
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
|
|
@ -44,8 +49,6 @@ properties:
|
|||
- const: bus_master # Master AXI clock
|
||||
- const: bus_slave # Slave AXI clock
|
||||
- const: slave_q2a # Slave Q2A clock
|
||||
- const: tbu # PCIe TBU clock
|
||||
- const: ref # REFERENCE clock
|
||||
|
||||
interrupts:
|
||||
minItems: 8
|
||||
|
|
@ -111,17 +114,13 @@ examples:
|
|||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
||||
clock-names = "pipe",
|
||||
"aux",
|
||||
"cfg",
|
||||
"bus_master",
|
||||
"bus_slave",
|
||||
"slave_q2a",
|
||||
"tbu",
|
||||
"ref";
|
||||
"slave_q2a";
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ properties:
|
|||
- description: See native 'dbi' CSR region for details.
|
||||
enum: [ ctrl ]
|
||||
- description: See native 'elbi/app' CSR region for details.
|
||||
enum: [ apb, mgmt, link, ulreg, appl ]
|
||||
enum: [ apb, mgmt, link, ulreg, appl, controller ]
|
||||
- description: See native 'atu' CSR region for details.
|
||||
enum: [ atu_dma ]
|
||||
- description: Syscon-related CSR regions.
|
||||
|
|
|
|||
122
Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
Normal file
122
Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: DesignWare based PCIe Root Complex controller on Sophgo SoCs
|
||||
|
||||
maintainers:
|
||||
- Inochi Amaoto <inochiama@gmail.com>
|
||||
|
||||
description:
|
||||
SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
|
||||
PCIe IP and thus inherits all the common properties defined in
|
||||
snps,dw-pcie.yaml.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-host-bridge.yaml#
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: sophgo,sg2044-pcie
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Data Bus Interface (DBI) registers
|
||||
- description: iATU registers
|
||||
- description: Config registers
|
||||
- description: Sophgo designed configuration registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: dbi
|
||||
- const: atu
|
||||
- const: config
|
||||
- const: app
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: core clk
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
|
||||
interrupt-controller:
|
||||
description: Interrupt controller node for handling legacy PCI interrupts.
|
||||
type: object
|
||||
|
||||
properties:
|
||||
"#address-cells":
|
||||
const: 0
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: combined legacy interrupt
|
||||
|
||||
required:
|
||||
- "#address-cells"
|
||||
- "#interrupt-cells"
|
||||
- interrupt-controller
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
msi-parent: true
|
||||
|
||||
ranges:
|
||||
maxItems: 5
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie@6c00400000 {
|
||||
compatible = "sophgo,sg2044-pcie";
|
||||
reg = <0x6c 0x00400000 0x0 0x00001000>,
|
||||
<0x6c 0x00700000 0x0 0x00004000>,
|
||||
<0x40 0x00000000 0x0 0x00001000>,
|
||||
<0x6c 0x00780c00 0x0 0x00000400>;
|
||||
reg-names = "dbi", "atu", "config", "app";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
bus-range = <0x00 0xff>;
|
||||
clocks = <&clk 0>;
|
||||
clock-names = "core";
|
||||
device_type = "pci";
|
||||
linux,pci-domain = <0>;
|
||||
msi-parent = <&msi>;
|
||||
ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>,
|
||||
<0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>,
|
||||
<0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>,
|
||||
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
|
||||
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
|
||||
|
||||
interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
SPEAr13XX PCIe DT detail:
|
||||
================================
|
||||
|
||||
SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
|
||||
controller.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
|
||||
- phys : phandle to PHY node associated with PCIe controller
|
||||
- phy-names : must be "pcie-phy"
|
||||
- All other definitions as per generic PCI bindings
|
||||
|
||||
Optional properties:
|
||||
- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
|
||||
45
Documentation/devicetree/bindings/pci/st,spear1340-pcie.yaml
Normal file
45
Documentation/devicetree/bindings/pci/st,spear1340-pcie.yaml
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/st,spear1340-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ST SPEAr1340 PCIe controller
|
||||
|
||||
maintainers:
|
||||
- Pratyush Anand <pratyush.anand@gmail.com>
|
||||
|
||||
description:
|
||||
SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
|
||||
controller.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,spear1340-pcie
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: st,spear1340-pcie
|
||||
- const: snps,dw-pcie
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
st,pcie-is-gen1:
|
||||
type: boolean
|
||||
description: Indicates forced gen1 initialization is needed.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
allOf:
|
||||
- $ref: snps,dw-pcie.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
* AppliedMicro X-Gene PCIe interface
|
||||
|
||||
Required properties:
|
||||
- device_type: set to "pci"
|
||||
- compatible: should contain "apm,xgene-pcie" to identify the core.
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names
|
||||
property.
|
||||
- reg-names: Must include the following entries:
|
||||
"csr": controller configuration registers.
|
||||
"cfg": PCIe configuration space registers.
|
||||
- #address-cells: set to <3>
|
||||
- #size-cells: set to <2>
|
||||
- ranges: ranges for the outbound memory, I/O regions.
|
||||
- dma-ranges: ranges for the inbound memory regions.
|
||||
- #interrupt-cells: set to <1>
|
||||
- interrupt-map-mask and interrupt-map: standard PCI properties
|
||||
to define the mapping of the PCIe interface to interrupt
|
||||
numbers.
|
||||
- clocks: from common clock binding: handle to pci clock.
|
||||
|
||||
Optional properties:
|
||||
- status: Either "ok" or "disabled".
|
||||
- dma-coherent: Present if DMA operations are coherent
|
||||
|
||||
Example:
|
||||
|
||||
pcie0: pcie@1f2b0000 {
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
|
||||
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
|
||||
reg-names = "csr", "cfg";
|
||||
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
|
||||
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
|
||||
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
|
||||
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
|
||||
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||||
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
|
||||
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
|
||||
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
|
||||
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
|
||||
dma-coherent;
|
||||
clocks = <&pcie0clk 0>;
|
||||
};
|
||||
|
||||
169
Documentation/devicetree/bindings/phy/apm,xgene-phy.yaml
Normal file
169
Documentation/devicetree/bindings/phy/apm,xgene-phy.yaml
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/apm,xgene-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene 15Gbps Multi-purpose PHY
|
||||
|
||||
maintainers:
|
||||
- Khuong Dinh <khuong@os.amperecomputing.com>
|
||||
|
||||
description:
|
||||
PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
|
||||
PHY (pair of lanes) has its own node.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: apm,xgene-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#phy-cells':
|
||||
description:
|
||||
Possible values are 0 (SATA), 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
apm,tx-eye-tuning:
|
||||
description:
|
||||
Manual control to fine tune the capture of the serial bit lines from the
|
||||
automatic calibrated position. Two set of 3-tuple setting for each
|
||||
supported link speed on the host. Range from 0 to 127 in unit of one bit
|
||||
period.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 127
|
||||
default: 10
|
||||
|
||||
apm,tx-eye-direction:
|
||||
description:
|
||||
Eye tuning manual control direction. 0 means sample data earlier than the
|
||||
nominal sampling point. 1 means sample data later than the nominal
|
||||
sampling point. Two set of 3-tuple setting for each supported link speed
|
||||
on the host.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
enum: [0, 1]
|
||||
default: 0
|
||||
|
||||
apm,tx-boost-gain:
|
||||
description:
|
||||
Frequency boost AC (LSB 3-bit) and DC (2-bit) gain control. Two set of
|
||||
3-tuple setting for each supported link speed on the host. Range is
|
||||
between 0 to 31 in unit of dB. Default is 3.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
|
||||
apm,tx-amplitude:
|
||||
description:
|
||||
Amplitude control. Two set of 3-tuple setting for each supported link
|
||||
speed on the host. Range is between 0 to 199500 in unit of uV.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 199500
|
||||
default: 199500
|
||||
|
||||
apm,tx-pre-cursor1:
|
||||
description:
|
||||
1st pre-cursor emphasis taps control. Two set of 3-tuple setting for
|
||||
each supported link speed on the host. Range is 0 to 273000 in unit of
|
||||
uV.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 273000
|
||||
default: 0
|
||||
|
||||
apm,tx-pre-cursor2:
|
||||
description:
|
||||
2nd pre-cursor emphasis taps control. Two set of 3-tuple setting for
|
||||
each supported link speed on the host. Range is 0 to 127400 in unit uV.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 127400
|
||||
default: 0
|
||||
|
||||
apm,tx-post-cursor:
|
||||
description: |
|
||||
Post-cursor emphasis taps control. Two set of 3-tuple setting for Gen1,
|
||||
Gen2, and Gen3 link speeds. Range is between 0 to 31 in unit of 18.2mV.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
items:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 31
|
||||
default: 0xf
|
||||
|
||||
apm,tx-speed:
|
||||
description: >
|
||||
Tx operating speed. One set of 3-tuple for each supported link speed on
|
||||
the host:
|
||||
|
||||
0 = 1-2Gbps
|
||||
1 = 2-4Gbps (1st tuple default)
|
||||
2 = 4-8Gbps
|
||||
3 = 8-15Gbps (2nd tuple default)
|
||||
4 = 2.5-4Gbps
|
||||
5 = 4-5Gbps
|
||||
6 = 5-6Gbps
|
||||
7 = 6-16Gbps (3rd tuple default).
|
||||
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
items:
|
||||
maximum: 7
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@1f21a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x1f21a000 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
* APM X-Gene 15Gbps Multi-purpose PHY nodes
|
||||
|
||||
PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
|
||||
PHY (pair of lanes) has its own node.
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall be "apm,xgene-phy".
|
||||
- reg : PHY memory resource is the SDS PHY access resource.
|
||||
- #phy-cells : Shall be 1 as it expects one argument for setting
|
||||
the mode of the PHY. Possible values are 0 (SATA),
|
||||
1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
|
||||
|
||||
Optional properties:
|
||||
- status : Shall be "ok" if enabled or "disabled" if disabled.
|
||||
Default is "ok".
|
||||
- clocks : Reference to the clock entry.
|
||||
- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
|
||||
bit lines from the automatic calibrated position.
|
||||
Two set of 3-tuple setting for each (up to 3)
|
||||
supported link speed on the host. Range from 0 to
|
||||
127 in unit of one bit period. Default is 10.
|
||||
- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
|
||||
data earlier than the nominal sampling point. 1 means
|
||||
sample data later than the nominal sampling point.
|
||||
Two set of 3-tuple setting for each (up to 3)
|
||||
supported link speed on the host. Default is 0.
|
||||
- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
|
||||
gain control. Two set of 3-tuple setting for each
|
||||
(up to 3) supported link speed on the host. Range is
|
||||
between 0 to 31 in unit of dB. Default is 3.
|
||||
- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
|
||||
each (up to 3) supported link speed on the host.
|
||||
Range is between 0 to 199500 in unit of uV.
|
||||
Default is 199500 uV.
|
||||
- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
|
||||
3-tuple setting for each (up to 3) supported link
|
||||
speed on the host. Range is 0 to 273000 in unit of
|
||||
uV. Default is 0.
|
||||
- apm,tx-pre-cursor2 : 2nd pre-cursor emphasis taps control. Two set of
|
||||
3-tuple setting for each (up to 3) supported link
|
||||
speed on the host. Range is 0 to 127400 in unit uV.
|
||||
Default is 0x0.
|
||||
- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
|
||||
3-tuple setting for Gen1, Gen2, and Gen3. Range is
|
||||
between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
|
||||
- apm,tx-speed : Tx operating speed. One set of 3-tuple for each
|
||||
supported link speed on the host.
|
||||
0 = 1-2Gbps
|
||||
1 = 2-4Gbps (1st tuple default)
|
||||
2 = 4-8Gbps
|
||||
3 = 8-15Gbps (2nd tuple default)
|
||||
4 = 2.5-4Gbps
|
||||
5 = 4-5Gbps
|
||||
6 = 5-6Gbps
|
||||
7 = 6-16Gbps (3rd tuple default)
|
||||
|
||||
NOTE: PHY override parameters are board specific setting.
|
||||
|
||||
Example:
|
||||
phy1: phy@1f21a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f21a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
phy2: phy@1f22a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f22a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
phy3: phy@1f23a000 {
|
||||
compatible = "apm,xgene-phy";
|
||||
reg = <0x0 0x1f23a000 0x0 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
Berlin SATA PHY
|
||||
---------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
"marvell,berlin2-sata-phy"
|
||||
"marvell,berlin2q-sata-phy"
|
||||
- address-cells: should be 1
|
||||
- size-cells: should be 0
|
||||
- phy-cells: from the generic PHY bindings, must be 1
|
||||
- reg: address and length of the register
|
||||
- clocks: reference to the clock entry
|
||||
|
||||
Sub-nodes:
|
||||
Each PHY should be represented as a sub-node.
|
||||
|
||||
Sub-nodes required properties:
|
||||
- reg: the PHY number
|
||||
|
||||
Example:
|
||||
sata_phy: phy@f7e900a0 {
|
||||
compatible = "marvell,berlin2q-sata-phy";
|
||||
reg = <0xf7e900a0 0x200>;
|
||||
clocks = <&chip CLKID_SATA>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
sata-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
sata-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
* Marvell Berlin USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
|
||||
- reg: base address and length of the registers
|
||||
- #phys-cells: should be 0
|
||||
- resets: reference to the reset controller
|
||||
|
||||
Example:
|
||||
|
||||
usb-phy@f774000 {
|
||||
compatible = "marvell,berlin2-usb-phy";
|
||||
reg = <0xf774000 0x128>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&chip 0x104 14>;
|
||||
};
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
BROADCOM NORTHSTAR2 USB2 (DUAL ROLE DEVICE) PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: brcm,ns2-drd-phy
|
||||
- reg: offset and length of the NS2 PHY related registers.
|
||||
- reg-names
|
||||
The below registers must be provided.
|
||||
icfg - for DRD ICFG configurations
|
||||
rst-ctrl - for DRD IDM reset
|
||||
crmu-ctrl - for CRMU core vdd, PHY and PHY PLL reset
|
||||
usb2-strap - for port over current polarity reversal
|
||||
- #phy-cells: Must be 0. No args required.
|
||||
- vbus-gpios: vbus gpio binding
|
||||
- id-gpios: id gpio binding
|
||||
|
||||
Refer to phy/phy-bindings.txt for the generic PHY binding properties
|
||||
|
||||
Example:
|
||||
usbdrd_phy: phy@66000960 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "brcm,ns2-drd-phy";
|
||||
reg = <0x66000960 0x24>,
|
||||
<0x67012800 0x4>,
|
||||
<0x6501d148 0x4>,
|
||||
<0x664d0700 0x4>;
|
||||
reg-names = "icfg", "rst-ctrl",
|
||||
"crmu-ctrl", "usb2-strap";
|
||||
id-gpios = <&gpio_g 30 0>;
|
||||
vbus-gpios = <&gpio_g 31 0>;
|
||||
};
|
||||
62
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.yaml
Normal file
62
Documentation/devicetree/bindings/phy/brcm,ns2-drd-phy.yaml
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Northstar2 USB2 Dual Role Device PHY
|
||||
|
||||
maintainers:
|
||||
- Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
- Hauke Mehrtens <hauke@hauke-m.de>
|
||||
- Rafał Miłecki <zajec5@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,ns2-drd-phy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: DRD ICFG configurations
|
||||
- description: DRD IDM reset
|
||||
- description: CRMU core vdd, PHY and PHY PLL reset
|
||||
- description: Port over current polarity reversal
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: icfg
|
||||
- const: rst-ctrl
|
||||
- const: crmu-ctrl
|
||||
- const: usb2-strap
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
id-gpios:
|
||||
maxItems: 1
|
||||
description: ID GPIO line
|
||||
|
||||
vbus-gpios:
|
||||
maxItems: 1
|
||||
description: VBUS GPIO line
|
||||
|
||||
required:
|
||||
- '#phy-cells'
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- id-gpios
|
||||
- vbus-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@66000960 {
|
||||
#phy-cells = <0>;
|
||||
compatible = "brcm,ns2-drd-phy";
|
||||
reg = <0x66000960 0x24>, <0x67012800 0x4>, <0x6501d148 0x4>, <0x664d0700 0x4>;
|
||||
reg-names = "icfg", "rst-ctrl", "crmu-ctrl", "usb2-strap";
|
||||
id-gpios = <&gpio_g 30 0>;
|
||||
vbus-gpios = <&gpio_g 31 0>;
|
||||
};
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
Broadcom Stingray PCIe PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "brcm,sr-pcie-phy"
|
||||
- reg: base address and length of the PCIe SS register space
|
||||
- brcm,sr-cdru: phandle to the CDRU syscon node
|
||||
- brcm,sr-mhb: phandle to the MHB syscon node
|
||||
- #phy-cells: Must be 1, denotes the PHY index
|
||||
|
||||
For PAXB based root complex, one can have a configuration of up to 8 PHYs
|
||||
PHY index goes from 0 to 7
|
||||
|
||||
For the internal PAXC based root complex, PHY index is always 8
|
||||
|
||||
Example:
|
||||
mhb: syscon@60401000 {
|
||||
compatible = "brcm,sr-mhb", "syscon";
|
||||
reg = <0 0x60401000 0 0x38c>;
|
||||
};
|
||||
|
||||
cdru: syscon@6641d000 {
|
||||
compatible = "brcm,sr-cdru", "syscon";
|
||||
reg = <0 0x6641d000 0 0x400>;
|
||||
};
|
||||
|
||||
pcie_phy: phy@40000000 {
|
||||
compatible = "brcm,sr-pcie-phy";
|
||||
reg = <0 0x40000000 0 0x800>;
|
||||
brcm,sr-cdru = <&cdru>;
|
||||
brcm,sr-mhb = <&mhb>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
/* users of the PCIe PHY */
|
||||
|
||||
pcie0: pcie@48000000 {
|
||||
...
|
||||
...
|
||||
phys = <&pcie_phy 0>;
|
||||
phy-names = "pcie-phy";
|
||||
};
|
||||
46
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.yaml
Normal file
46
Documentation/devicetree/bindings/phy/brcm,sr-pcie-phy.yaml
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/brcm,sr-pcie-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Stingray PCIe PHY
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <ray.jui@broadcom.com>
|
||||
|
||||
description: >
|
||||
For PAXB based root complex, one can have a configuration of up to 8 PHYs.
|
||||
PHY index goes from 0 to 7.
|
||||
|
||||
For the internal PAXC based root complex, PHY index is always 8.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: brcm,sr-pcie-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#phy-cells':
|
||||
const: 1
|
||||
|
||||
brcm,sr-cdru:
|
||||
description: phandle to the CDRU syscon node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
brcm,sr-mhb:
|
||||
description: phandle to the MHB syscon node
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@40000000 {
|
||||
compatible = "brcm,sr-pcie-phy";
|
||||
reg = <0x40000000 0x800>;
|
||||
brcm,sr-cdru = <&cdru>;
|
||||
brcm,sr-mhb = <&mhb>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/brcm,sr-usb-combo-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom Stingray USB PHY
|
||||
|
||||
maintainers:
|
||||
- Ray Jui <rjui@broadcom.com>
|
||||
- Scott Branden <sbranden@broadcom.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,sr-usb-combo-phy
|
||||
- brcm,sr-usb-hs-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#phy-cells':
|
||||
description: PHY cell count indicating PHY type
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#phy-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,sr-usb-combo-phy
|
||||
then:
|
||||
properties:
|
||||
'#phy-cells':
|
||||
const: 1
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: brcm,sr-usb-hs-phy
|
||||
then:
|
||||
properties:
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usb-phy@0 {
|
||||
compatible = "brcm,sr-usb-combo-phy";
|
||||
reg = <0x00000000 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
- |
|
||||
usb-phy@20000 {
|
||||
compatible = "brcm,sr-usb-hs-phy";
|
||||
reg = <0x00020000 0x100>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
Broadcom Stingray USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of the listed compatibles
|
||||
- "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
|
||||
- "brcm,sr-usb-hs-phy" is a single HS PHY.
|
||||
- reg: offset and length of the PHY blocks registers
|
||||
- #phy-cells:
|
||||
- Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
|
||||
the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
|
||||
- Must be 0 for brcm,sr-usb-hs-phy.
|
||||
|
||||
Refer to phy/phy-bindings.txt for the generic PHY binding properties
|
||||
|
||||
Example:
|
||||
usbphy0: usb-phy@0 {
|
||||
compatible = "brcm,sr-usb-combo-phy";
|
||||
reg = <0x00000000 0x100>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
usbphy1: usb-phy@10000 {
|
||||
compatible = "brcm,sr-usb-combo-phy";
|
||||
reg = <0x00010000 0x100>,
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
usbphy2: usb-phy@20000 {
|
||||
compatible = "brcm,sr-usb-hs-phy";
|
||||
reg = <0x00020000 0x100>,
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
Device tree binding documentation for am816x USB PHY
|
||||
=========================
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "ti,dm816x-usb-phy"
|
||||
- reg : offset and length of the PHY register set.
|
||||
- reg-names : name for the phy registers
|
||||
- clocks : phandle to the clock
|
||||
- clock-names : name of the clock
|
||||
- syscon: phandle for the syscon node to access misc registers
|
||||
- #phy-cells : from the generic PHY bindings, must be 1
|
||||
- syscon: phandle for the syscon node to access misc registers
|
||||
|
||||
Example:
|
||||
|
||||
usb_phy0: usb-phy@20 {
|
||||
compatible = "ti,dm8168-usb-phy";
|
||||
reg = <0x20 0x8>;
|
||||
reg-names = "phy";
|
||||
clocks = <&main_fapll 6>;
|
||||
clock-names = "refclk";
|
||||
#phy-cells = <0>;
|
||||
syscon = <&scm_conf>;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/hisilicon,hi6220-usb-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Hisilicon hi6220 USB PHY
|
||||
|
||||
maintainers:
|
||||
- Zhangfei Gao <zhangfei.gao@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: hisilicon,hi6220-usb-phy
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
phy-supply:
|
||||
description: PHY power supply.
|
||||
|
||||
hisilicon,peripheral-syscon:
|
||||
description: Phandle to the system controller for PHY control.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usbphy {
|
||||
compatible = "hisilicon,hi6220-usb-phy";
|
||||
#phy-cells = <0>;
|
||||
phy-supply = <&fixed_5v_hub>;
|
||||
hisilicon,peripheral-syscon = <&sys_ctrl>;
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/hisilicon,hix5hd2-sata-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: HiSilicon hix5hd2 SATA PHY
|
||||
|
||||
maintainers:
|
||||
- Jiancheng Xue <xuejiancheng@huawei.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: hisilicon,hix5hd2-sata-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
hisilicon,peripheral-syscon:
|
||||
description: Phandle of syscon used to control peripheral
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
hisilicon,power-reg:
|
||||
description: Offset and bit number within peripheral-syscon register controlling SATA power supply
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
items:
|
||||
- description: Offset within peripheral-syscon register
|
||||
- description: Bit number controlling SATA power supply
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#phy-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@f9900000 {
|
||||
compatible = "hisilicon,hix5hd2-sata-phy";
|
||||
reg = <0xf9900000 0x10000>;
|
||||
#phy-cells = <0>;
|
||||
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
|
||||
hisilicon,power-reg = <0x8 10>;
|
||||
};
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/hisilicon,inno-usb2-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: HiSilicon INNO USB2 PHY
|
||||
|
||||
maintainers:
|
||||
- Pengcheng Li <lpc.li@hisilicon.com>
|
||||
|
||||
description:
|
||||
The INNO USB2 PHY device should be a child node of peripheral controller that
|
||||
contains the PHY configuration register, and each device supports up to 2 PHY
|
||||
ports which are represented as child nodes of INNO USB2 PHY device.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- hisilicon,hi3798cv200-usb2-phy
|
||||
- hisilicon,hi3798mv100-usb2-phy
|
||||
- hisilicon,inno-usb2-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^phy@[0-1]$":
|
||||
description: PHY port subnode
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maximum: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
- resets
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- resets
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/histb-clock.h>
|
||||
|
||||
usb2-phy@120 {
|
||||
compatible = "hisilicon,hi3798cv200-usb2-phy";
|
||||
reg = <0x120 0x4>;
|
||||
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
|
||||
resets = <&crg 0xbc 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&crg 0xbc 8>;
|
||||
};
|
||||
|
||||
phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&crg 0xbc 9>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
Hisilicon hix5hd2 SATA PHY
|
||||
-----------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "hisilicon,hix5hd2-sata-phy"
|
||||
- reg: offset and length of the PHY registers
|
||||
- #phy-cells: must be 0
|
||||
Refer to phy/phy-bindings.txt for the generic PHY binding properties
|
||||
|
||||
Optional Properties:
|
||||
- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
|
||||
- hisilicon,power-reg: offset and bit number within peripheral-syscon,
|
||||
register of controlling sata power supply.
|
||||
|
||||
Example:
|
||||
sata_phy: phy@f9900000 {
|
||||
compatible = "hisilicon,hix5hd2-sata-phy";
|
||||
reg = <0xf9900000 0x10000>;
|
||||
#phy-cells = <0>;
|
||||
hisilicon,peripheral-syscon = <&peripheral_ctrl>;
|
||||
hisilicon,power-reg = <0x8 10>;
|
||||
};
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/img,pistachio-usb-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Imagination Pistachio USB PHY
|
||||
|
||||
maintainers:
|
||||
- Andrew Bresticker <abrestic@chromium.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: img,pistachio-usb-phy
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: usb_phy
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
phy-supply:
|
||||
description: USB VBUS supply. Must supply 5.0V.
|
||||
|
||||
img,refclk:
|
||||
description:
|
||||
Reference clock source for the USB PHY. See
|
||||
<dt-bindings/phy/phy-pistachio-usb.h> for valid values.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
img,cr-top:
|
||||
description: CR_TOP syscon phandle.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#phy-cells'
|
||||
- img,refclk
|
||||
- img,cr-top
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/phy/phy-pistachio-usb.h>
|
||||
#include <dt-bindings/clock/pistachio-clk.h>
|
||||
|
||||
usb-phy {
|
||||
compatible = "img,pistachio-usb-phy";
|
||||
clocks = <&clk_core CLK_USB_PHY>;
|
||||
clock-names = "usb_phy";
|
||||
#phy-cells = <0>;
|
||||
phy-supply = <&usb_vbus>;
|
||||
img,refclk = <REFCLK_CLK_CORE>;
|
||||
img,cr-top = <&cr_top>;
|
||||
};
|
||||
|
|
@ -1,19 +0,0 @@
|
|||
TI Keystone USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ti,keystone-usbphy".
|
||||
- #address-cells, #size-cells : should be '1' if the device has sub-nodes
|
||||
with 'reg' property.
|
||||
- reg : Address and length of the usb phy control register set.
|
||||
|
||||
The main purpose of this PHY driver is to enable the USB PHY reference clock
|
||||
gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
|
||||
an NOP PHY driver. Hence this node is referenced as both the usb2 and usb3
|
||||
phy node in the USB Glue layer driver node.
|
||||
|
||||
usb_phy: usb_phy@2620738 {
|
||||
compatible = "ti,keystone-usbphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2620738 32>;
|
||||
};
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/lantiq,ase-usb2-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Lantiq XWAY SoC RCU USB 1.1/2.0 PHY
|
||||
|
||||
maintainers:
|
||||
- Hauke Mehrtens <hauke@hauke-m.de>
|
||||
|
||||
description:
|
||||
This node has to be a sub node of the Lantiq RCU block.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- lantiq,ase-usb2-phy
|
||||
- lantiq,danube-usb2-phy
|
||||
- lantiq,xrx100-usb2-phy
|
||||
- lantiq,xrx200-usb2-phy
|
||||
- lantiq,xrx300-usb2-phy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Offset of the USB PHY configuration register
|
||||
- description: Offset of the USB Analog configuration register
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: phy
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- enum: [ phy, ctrl ]
|
||||
- const: ctrl
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- '#phy-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usb2-phy@18 {
|
||||
compatible = "lantiq,xrx200-usb2-phy";
|
||||
reg = <0x18 4>, <0x38 4>;
|
||||
clocks = <&pmu 1>;
|
||||
clock-names = "phy";
|
||||
resets = <&reset1 4 4>, <&reset0 4 4>;
|
||||
reset-names = "phy", "ctrl";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,armada-375-usb-cluster.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Armada 375 USB Cluster
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
description:
|
||||
Control register for the Armada 375 USB cluster, managing USB2 and USB3 features.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,armada-375-usb-cluster
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#phy-cells':
|
||||
description: Number of PHY cells in specifier. 1 for USB2, 2 for USB3.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#phy-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usbcluster: usb-cluster@18400 {
|
||||
compatible = "marvell,armada-375-usb-cluster";
|
||||
reg = <0x18400 0x4>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,armada-380-comphy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Armada 38x COMPHY controller
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
description:
|
||||
This comphy controller can be found on Marvell Armada 38x. It provides a
|
||||
number of shared PHYs used by various interfaces (network, sata, usb,
|
||||
PCIe...).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: marvell,armada-380-comphy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: COMPHY register location and length
|
||||
- description: Configuration register location and length
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: comphy
|
||||
- const: conf
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
'^phy@[0-5]$':
|
||||
description: A COMPHY lane
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maximum: 1
|
||||
|
||||
'#phy-cells':
|
||||
description: Input port index for the PHY lane
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- '#phy-cells'
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
comphy: phy@18300 {
|
||||
compatible = "marvell,armada-380-comphy";
|
||||
reg = <0x18300 0x100>, <0x18460 4>;
|
||||
reg-names = "comphy", "conf";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpm_comphy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
cpm_comphy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,berlin2-sata-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Berlin SATA PHY
|
||||
|
||||
maintainers:
|
||||
- Antoine Tenart <atenart@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,berlin2-sata-phy
|
||||
- marvell,berlin2q-sata-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
'#phy-cells':
|
||||
const: 1
|
||||
|
||||
patternProperties:
|
||||
'^sata-phy@[0-1]$':
|
||||
description: A SATA PHY sub-node.
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
maximum: 1
|
||||
description: PHY index number.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
- '#phy-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/berlin2q.h>
|
||||
|
||||
phy@f7e900a0 {
|
||||
compatible = "marvell,berlin2q-sata-phy";
|
||||
reg = <0xf7e900a0 0x200>;
|
||||
clocks = <&chip CLKID_SATA>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
sata-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
sata-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,berlin2-usb-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell Berlin USB PHY
|
||||
|
||||
maintainers:
|
||||
- Antoine Tenart <atenart@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,berlin2-usb-phy
|
||||
- marvell,berlin2cd-usb-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usb-phy@f774000 {
|
||||
compatible = "marvell,berlin2-usb-phy";
|
||||
reg = <0xf774000 0x128>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&chip 0x104 14>;
|
||||
};
|
||||
154
Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
Normal file
154
Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml
Normal file
|
|
@ -0,0 +1,154 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MVEBU COMPHY Controller
|
||||
|
||||
maintainers:
|
||||
- Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
|
||||
description: >
|
||||
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
|
||||
|
||||
* Armada 7k/8k (on the CP110)
|
||||
* Armada 3700
|
||||
|
||||
It provides a number of shared PHYs used by various interfaces (network, SATA,
|
||||
USB, PCIe...).
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,comphy-cp110
|
||||
- marvell,comphy-a3700
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Generic COMPHY registers
|
||||
- description: Lane 1 (PCIe/GbE) registers (Armada 3700)
|
||||
- description: Lane 0 (USB3/GbE) registers (Armada 3700)
|
||||
- description: Lane 2 (SATA/USB3) registers (Armada 3700)
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: comphy
|
||||
- const: lane1_pcie_gbe
|
||||
- const: lane0_usb3_gbe
|
||||
- const: lane2_sata_usb3
|
||||
|
||||
'#address-cells':
|
||||
const: 1
|
||||
|
||||
'#size-cells':
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: mg_clk
|
||||
- const: mg_core_clk
|
||||
- const: axi_clk
|
||||
|
||||
marvell,system-controller:
|
||||
description: Phandle to the Marvell system controller (CP110 only)
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
patternProperties:
|
||||
'^phy@[0-2]$':
|
||||
description: A COMPHY lane child node
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: COMPHY lane number
|
||||
|
||||
'#phy-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
- '#phy-cells'
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,comphy-a3700
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks: false
|
||||
clock-names: false
|
||||
|
||||
required:
|
||||
- reg-names
|
||||
|
||||
else:
|
||||
required:
|
||||
- marvell,system-controller
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@120000 {
|
||||
compatible = "marvell,comphy-cp110";
|
||||
reg = <0x120000 0x6000>;
|
||||
clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>;
|
||||
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
marvell,system-controller = <&syscon0>;
|
||||
|
||||
phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
phy@18300 {
|
||||
compatible = "marvell,comphy-a3700";
|
||||
reg = <0x18300 0x300>,
|
||||
<0x1F000 0x400>,
|
||||
<0x5C000 0x400>,
|
||||
<0xe0178 0x8>;
|
||||
reg-names = "comphy",
|
||||
"lane1_pcie_gbe",
|
||||
"lane0_usb3_gbe",
|
||||
"lane2_sata_usb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
comphy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy2: phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,mmp2-usb-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MMP2/PXA USB PHY
|
||||
|
||||
maintainers:
|
||||
- Lubomir Rintel <lkundrak@v3.sk>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- marvell,mmp2-usb-phy
|
||||
- marvell,pxa910-usb-phy
|
||||
- marvell,pxa168-usb-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usbphy@d4207000 {
|
||||
compatible = "marvell,mmp2-usb-phy";
|
||||
reg = <0xd4207000 0x40>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/marvell,mvebu-sata-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Marvell MVEBU SATA PHY
|
||||
|
||||
maintainers:
|
||||
- Andrew Lunn <andrew@lunn.ch>
|
||||
- Gregory Clement <gregory.clement@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: marvell,mvebu-sata-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sata
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#phy-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sata-phy@84000 {
|
||||
compatible = "marvell,mvebu-sata-phy";
|
||||
reg = <0x84000 0x0334>;
|
||||
clocks = <&gate_clk 15>;
|
||||
clock-names = "sata";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -72,11 +72,6 @@ allOf:
|
|||
contains:
|
||||
const: fsl,imx8qxp-mipi-dphy
|
||||
then:
|
||||
properties:
|
||||
assigned-clocks: false
|
||||
assigned-clock-parents: false
|
||||
assigned-clock-rates: false
|
||||
|
||||
required:
|
||||
- fsl,syscon
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,107 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/motorola,cpcap-usb-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Motorola CPCAP PMIC USB PHY
|
||||
|
||||
maintainers:
|
||||
- Tony Lindgren <tony@atomide.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- motorola,cpcap-usb-phy
|
||||
- motorola,mapphone-cpcap-usb-phy
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
interrupts:
|
||||
description: CPCAP PMIC interrupts used by the USB PHY
|
||||
items:
|
||||
- description: id_ground interrupt
|
||||
- description: id_float interrupt
|
||||
- description: se0conn interrupt
|
||||
- description: vbusvld interrupt
|
||||
- description: sessvld interrupt
|
||||
- description: sessend interrupt
|
||||
- description: se1 interrupt
|
||||
- description: dm interrupt
|
||||
- description: dp interrupt
|
||||
|
||||
interrupt-names:
|
||||
description: Interrupt names
|
||||
items:
|
||||
- const: id_ground
|
||||
- const: id_float
|
||||
- const: se0conn
|
||||
- const: vbusvld
|
||||
- const: sessvld
|
||||
- const: sessend
|
||||
- const: se1
|
||||
- const: dm
|
||||
- const: dp
|
||||
|
||||
io-channels:
|
||||
description: IIO ADC channels used by the USB PHY
|
||||
items:
|
||||
- description: vbus channel
|
||||
- description: id channel
|
||||
|
||||
io-channel-names:
|
||||
items:
|
||||
- const: vbus
|
||||
- const: id
|
||||
|
||||
vusb-supply: true
|
||||
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: default
|
||||
- const: ulpi
|
||||
- const: utmi
|
||||
- const: uart
|
||||
|
||||
mode-gpios:
|
||||
description: Optional GPIOs for configuring alternate modes
|
||||
items:
|
||||
- description: "mode selection GPIO #0"
|
||||
- description: "mode selection GPIO #1"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#phy-cells'
|
||||
- interrupts-extended
|
||||
- interrupt-names
|
||||
- io-channels
|
||||
- io-channel-names
|
||||
- vusb-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
phy {
|
||||
compatible = "motorola,mapphone-cpcap-usb-phy";
|
||||
#phy-cells = <0>;
|
||||
interrupts-extended = <
|
||||
&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
|
||||
&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
|
||||
&cpcap 48 1
|
||||
>;
|
||||
interrupt-names = "id_ground", "id_float", "se0conn", "vbusvld",
|
||||
"sessvld", "sessend", "se1", "dm", "dp";
|
||||
io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
|
||||
io-channel-names = "vbus", "id";
|
||||
vusb-supply = <&vusb>;
|
||||
pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
|
||||
pinctrl-1 = <&usb_ulpi_pins>;
|
||||
pinctrl-2 = <&usb_utmi_pins>;
|
||||
pinctrl-3 = <&uart3_pins>;
|
||||
pinctrl-names = "default", "ulpi", "utmi", "uart";
|
||||
mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/motorola,mapphone-mdm6600.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Motorola Mapphone MDM6600 USB PHY
|
||||
|
||||
maintainers:
|
||||
- Tony Lindgren <tony@atomide.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: motorola,mapphone-mdm6600
|
||||
|
||||
enable-gpios:
|
||||
description: GPIO to enable the USB PHY
|
||||
maxItems: 1
|
||||
|
||||
power-gpios:
|
||||
description: GPIO to power on the device
|
||||
maxItems: 1
|
||||
|
||||
reset-gpios:
|
||||
description: GPIO to reset the device
|
||||
maxItems: 1
|
||||
|
||||
motorola,mode-gpios:
|
||||
description: Two GPIOs to configure MDM6600 USB start-up mode for normal mode versus USB flashing mode
|
||||
items:
|
||||
- description: normal mode select GPIO
|
||||
- description: USB flashing mode select GPIO
|
||||
|
||||
motorola,cmd-gpios:
|
||||
description: Three GPIOs to control the power state of the MDM6600
|
||||
items:
|
||||
- description: power state control GPIO 0
|
||||
- description: power state control GPIO 1
|
||||
- description: power state control GPIO 2
|
||||
|
||||
motorola,status-gpios:
|
||||
description: Three GPIOs to read the power state of the MDM6600
|
||||
items:
|
||||
- description: power state read GPIO 0
|
||||
- description: power state read GPIO 1
|
||||
- description: power state read GPIO 2
|
||||
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- enable-gpios
|
||||
- power-gpios
|
||||
- reset-gpios
|
||||
- motorola,mode-gpios
|
||||
- motorola,cmd-gpios
|
||||
- motorola,status-gpios
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
usb-phy {
|
||||
compatible = "motorola,mapphone-mdm6600";
|
||||
enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
|
||||
power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio5 21 GPIO_ACTIVE_HIGH>;
|
||||
motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio4 8 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio5 14 GPIO_ACTIVE_HIGH>;
|
||||
motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio2 21 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio2 23 GPIO_ACTIVE_HIGH>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
mvebu armada 38x comphy driver
|
||||
------------------------------
|
||||
|
||||
This comphy controller can be found on Marvell Armada 38x. It provides a
|
||||
number of shared PHYs used by various interfaces (network, sata, usb,
|
||||
PCIe...).
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be "marvell,armada-380-comphy"
|
||||
- reg: should contain the comphy register location and length.
|
||||
- #address-cells: should be 1.
|
||||
- #size-cells: should be 0.
|
||||
|
||||
Optional properties:
|
||||
|
||||
- reg-names: must be "comphy" as the first name, and "conf".
|
||||
- reg: must contain the comphy register location and length as the first
|
||||
pair, followed by an optional configuration register address and
|
||||
length pair.
|
||||
|
||||
A sub-node is required for each comphy lane provided by the comphy.
|
||||
|
||||
Required properties (child nodes):
|
||||
|
||||
- reg: comphy lane number.
|
||||
- #phy-cells : from the generic phy bindings, must be 1. Defines the
|
||||
input port to use for a given comphy lane.
|
||||
|
||||
Example:
|
||||
|
||||
comphy: phy@18300 {
|
||||
compatible = "marvell,armada-380-comphy";
|
||||
reg-names = "comphy", "conf";
|
||||
reg = <0x18300 0x100>, <0x18460 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpm_comphy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
cpm_comphy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
* Atheros AR71XX/9XXX USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: "qca,ar7100-usb-phy"
|
||||
- #phys-cells: should be 0
|
||||
- reset-names: "phy"[, "suspend-override"]
|
||||
- resets: references to the reset controllers
|
||||
|
||||
Example:
|
||||
|
||||
usb-phy {
|
||||
compatible = "qca,ar7100-usb-phy";
|
||||
|
||||
reset-names = "phy", "suspend-override";
|
||||
resets = <&rst 4>, <&rst 3>;
|
||||
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
Motorola CPCAP PMIC USB PHY binding
|
||||
|
||||
Required properties:
|
||||
compatible: Shall be either "motorola,cpcap-usb-phy" or
|
||||
"motorola,mapphone-cpcap-usb-phy"
|
||||
#phy-cells: Shall be 0
|
||||
interrupts: CPCAP PMIC interrupts used by the USB PHY
|
||||
interrupt-names: Interrupt names
|
||||
io-channels: IIO ADC channels used by the USB PHY
|
||||
io-channel-names: IIO ADC channel names
|
||||
vusb-supply: Regulator for the PHY
|
||||
|
||||
Optional properties:
|
||||
pinctrl: Optional alternate pin modes for the PHY
|
||||
pinctrl-names: Names for optional pin modes
|
||||
mode-gpios: Optional GPIOs for configuring alternate modes
|
||||
|
||||
Example:
|
||||
cpcap_usb2_phy: phy {
|
||||
compatible = "motorola,mapphone-cpcap-usb-phy";
|
||||
pinctrl-0 = <&usb_gpio_mux_sel1 &usb_gpio_mux_sel2>;
|
||||
pinctrl-1 = <&usb_ulpi_pins>;
|
||||
pinctrl-2 = <&usb_utmi_pins>;
|
||||
pinctrl-3 = <&uart3_pins>;
|
||||
pinctrl-names = "default", "ulpi", "utmi", "uart";
|
||||
#phy-cells = <0>;
|
||||
interrupts-extended = <
|
||||
&cpcap 15 0 &cpcap 14 0 &cpcap 28 0 &cpcap 19 0
|
||||
&cpcap 18 0 &cpcap 17 0 &cpcap 16 0 &cpcap 49 0
|
||||
&cpcap 48 1
|
||||
>;
|
||||
interrupt-names =
|
||||
"id_ground", "id_float", "se0conn", "vbusvld",
|
||||
"sessvld", "sessend", "se1", "dm", "dp";
|
||||
mode-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH
|
||||
&gpio1 0 GPIO_ACTIVE_HIGH>;
|
||||
io-channels = <&cpcap_adc 2>, <&cpcap_adc 7>;
|
||||
io-channel-names = "vbus", "id";
|
||||
vusb-supply = <&vusb>;
|
||||
};
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
TI DA8xx/OMAP-L1xx/AM18xx USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "ti,da830-usb-phy".
|
||||
- #phy-cells: must be 1.
|
||||
|
||||
This device controls the PHY for both the USB 1.1 OHCI and USB 2.0 OTG
|
||||
controllers on DA8xx SoCs. Consumers of this device should use index 0 for
|
||||
the USB 2.0 phy device and index 1 for the USB 1.1 phy device.
|
||||
|
||||
It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
|
||||
to access the CFGCHIP2 register.
|
||||
|
||||
Example:
|
||||
|
||||
cfgchip: cfgchip@1417c {
|
||||
compatible = "ti,da830-cfgchip", "syscon";
|
||||
reg = <0x1417c 0x14>;
|
||||
};
|
||||
|
||||
usb_phy: usb-phy {
|
||||
compatible = "ti,da830-usb-phy";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
usb20: usb@200000 {
|
||||
compatible = "ti,da830-musb";
|
||||
reg = <0x200000 0x1000>;
|
||||
interrupts = <58>;
|
||||
phys = <&usb_phy 0>;
|
||||
phy-names = "usb-phy";
|
||||
};
|
||||
|
||||
usb11: usb@225000 {
|
||||
compatible = "ti,da830-ohci";
|
||||
reg = <0x225000 0x1000>;
|
||||
interrupts = <59>;
|
||||
phys = <&usb_phy 1>;
|
||||
phy-names = "usb-phy";
|
||||
};
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
Hisilicon hi6220 usb PHY
|
||||
-----------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "hisilicon,hi6220-usb-phy"
|
||||
- #phy-cells: must be 0
|
||||
- hisilicon,peripheral-syscon: phandle of syscon used to control phy.
|
||||
Refer to phy/phy-bindings.txt for the generic PHY binding properties
|
||||
|
||||
Example:
|
||||
usb_phy: usbphy {
|
||||
compatible = "hisilicon,hi6220-usb-phy";
|
||||
#phy-cells = <0>;
|
||||
phy-supply = <&fixed_5v_hub>;
|
||||
hisilicon,peripheral-syscon = <&sys_ctrl>;
|
||||
};
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
Device tree bindings for HiSilicon INNO USB2 PHY
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following strings:
|
||||
"hisilicon,inno-usb2-phy",
|
||||
"hisilicon,hi3798cv200-usb2-phy".
|
||||
- reg: Should be the address space for PHY configuration register in peripheral
|
||||
controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
|
||||
- clocks: The phandle and clock specifier pair for INNO USB2 PHY device
|
||||
reference clock.
|
||||
- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
|
||||
signal.
|
||||
- #address-cells: Must be 1.
|
||||
- #size-cells: Must be 0.
|
||||
|
||||
The INNO USB2 PHY device should be a child node of peripheral controller that
|
||||
contains the PHY configuration register, and each device supports up to 2 PHY
|
||||
ports which are represented as child nodes of INNO USB2 PHY device.
|
||||
|
||||
Required properties for PHY port node:
|
||||
- reg: The PHY port instance number.
|
||||
- #phy-cells: Defined by generic PHY bindings. Must be 0.
|
||||
- resets: The phandle and reset specifier pair for PHY port reset signal.
|
||||
|
||||
Refer to phy/phy-bindings.txt for the generic PHY binding properties
|
||||
|
||||
Example:
|
||||
|
||||
perictrl: peripheral-controller@8a20000 {
|
||||
compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
|
||||
reg = <0x8a20000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x8a20000 0x1000>;
|
||||
|
||||
usb2_phy1: usb2-phy@120 {
|
||||
compatible = "hisilicon,hi3798cv200-usb2-phy";
|
||||
reg = <0x120 0x4>;
|
||||
clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
|
||||
resets = <&crg 0xbc 4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_phy1_port0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&crg 0xbc 8>;
|
||||
};
|
||||
|
||||
usb2_phy1_port1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&crg 0xbc 9>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2_phy2: usb2-phy@124 {
|
||||
compatible = "hisilicon,hi3798cv200-usb2-phy";
|
||||
reg = <0x124 0x4>;
|
||||
clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
|
||||
resets = <&crg 0xbc 6>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_phy2_port0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <0>;
|
||||
resets = <&crg 0xbc 10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
|
||||
===========================================
|
||||
|
||||
This binding describes the USB PHY hardware provided by the RCU module on the
|
||||
Lantiq XWAY SoCs.
|
||||
|
||||
This node has to be a sub node of the Lantiq RCU block.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
Required properties (controller (parent) node):
|
||||
- compatible : Should be one of
|
||||
"lantiq,ase-usb2-phy"
|
||||
"lantiq,danube-usb2-phy"
|
||||
"lantiq,xrx100-usb2-phy"
|
||||
"lantiq,xrx200-usb2-phy"
|
||||
"lantiq,xrx300-usb2-phy"
|
||||
- reg : Defines the following sets of registers in the parent
|
||||
syscon device
|
||||
- Offset of the USB PHY configuration register
|
||||
- Offset of the USB Analog configuration
|
||||
register (only for xrx200 and xrx200)
|
||||
- clocks : References to the (PMU) "phy" clk gate.
|
||||
- clock-names : Must be "phy"
|
||||
- resets : References to the RCU USB configuration reset bits.
|
||||
- reset-names : Must be one of the following:
|
||||
"phy" (optional)
|
||||
"ctrl" (shared)
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
Example for the USB PHYs on an xRX200 SoC:
|
||||
usb_phy0: usb2-phy@18 {
|
||||
compatible = "lantiq,xrx200-usb2-phy";
|
||||
reg = <0x18 4>, <0x38 4>;
|
||||
|
||||
clocks = <&pmu PMU_GATE_USB0_PHY>;
|
||||
clock-names = "phy";
|
||||
resets = <&reset1 4 4>, <&reset0 4 4>;
|
||||
reset-names = "phy", "ctrl";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
Device tree binding documentation for Motorola Mapphone MDM6600 USB PHY
|
||||
|
||||
Required properties:
|
||||
- compatible Must be "motorola,mapphone-mdm6600"
|
||||
- enable-gpios GPIO to enable the USB PHY
|
||||
- power-gpios GPIO to power on the device
|
||||
- reset-gpios GPIO to reset the device
|
||||
- motorola,mode-gpios Two GPIOs to configure MDM6600 USB start-up mode for
|
||||
normal mode versus USB flashing mode
|
||||
- motorola,cmd-gpios Three GPIOs to control the power state of the MDM6600
|
||||
- motorola,status-gpios Three GPIOs to read the power state of the MDM6600
|
||||
|
||||
Example:
|
||||
|
||||
usb-phy {
|
||||
compatible = "motorola,mapphone-mdm6600";
|
||||
enable-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
|
||||
power-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
motorola,mode-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio5 21 GPIO_ACTIVE_HIGH>;
|
||||
motorola,cmd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio4 8 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio5 14 GPIO_ACTIVE_HIGH>;
|
||||
motorola,status-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio2 21 GPIO_ACTIVE_HIGH>,
|
||||
<&gpio2 23 GPIO_ACTIVE_HIGH>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
|
@ -1,94 +0,0 @@
|
|||
MVEBU comphy drivers
|
||||
--------------------
|
||||
|
||||
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
|
||||
* Armada 7k/8k (on the CP110)
|
||||
* Armada 3700
|
||||
It provides a number of shared PHYs used by various interfaces (network, SATA,
|
||||
USB, PCIe...).
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of:
|
||||
* "marvell,comphy-cp110" for Armada 7k/8k
|
||||
* "marvell,comphy-a3700" for Armada 3700
|
||||
- reg: should contain the COMPHY register(s) location(s) and length(s).
|
||||
* 1 entry for Armada 7k/8k
|
||||
* 4 entries for Armada 3700 along with the corresponding reg-names
|
||||
properties, memory areas are:
|
||||
* Generic COMPHY registers
|
||||
* Lane 1 (PCIe/GbE)
|
||||
* Lane 0 (USB3/GbE)
|
||||
* Lane 2 (SATA/USB3)
|
||||
- marvell,system-controller: should contain a phandle to the system
|
||||
controller node (only for Armada 7k/8k)
|
||||
- #address-cells: should be 1.
|
||||
- #size-cells: should be 0.
|
||||
|
||||
Optional properlties:
|
||||
|
||||
- clocks: pointers to the reference clocks for this device (CP110 only),
|
||||
consequently: MG clock, MG Core clock, AXI clock.
|
||||
- clock-names: names of used clocks for CP110 only, must be :
|
||||
"mg_clk", "mg_core_clk" and "axi_clk".
|
||||
|
||||
A sub-node is required for each comphy lane provided by the comphy.
|
||||
|
||||
Required properties (child nodes):
|
||||
|
||||
- reg: COMPHY lane number.
|
||||
- #phy-cells : from the generic PHY bindings, must be 1. Defines the
|
||||
input port to use for a given comphy lane.
|
||||
|
||||
Examples:
|
||||
|
||||
CP11X_LABEL(comphy): phy@120000 {
|
||||
compatible = "marvell,comphy-cp110";
|
||||
reg = <0x120000 0x6000>;
|
||||
marvell,system-controller = <&CP11X_LABEL(syscon0)>;
|
||||
clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
|
||||
<&CP11X_LABEL(clk) 1 18>;
|
||||
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CP11X_LABEL(comphy0): phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
CP11X_LABEL(comphy1): phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
comphy: phy@18300 {
|
||||
compatible = "marvell,comphy-a3700";
|
||||
reg = <0x18300 0x300>,
|
||||
<0x1F000 0x400>,
|
||||
<0x5C000 0x400>,
|
||||
<0xe0178 0x8>;
|
||||
reg-names = "comphy",
|
||||
"lane1_pcie_gbe",
|
||||
"lane0_usb3_gbe",
|
||||
"lane2_sata_usb3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
comphy0: phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy1: phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
comphy2: phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user