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pinctrl: npcm8xx: use new generic GPIO chip API
Convert the driver to using the new generic GPIO chip interfaces from linux/gpio/generic.h. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/20250811-gpio-mmio-pinctrl-conv-v1-3-a84c5da2be20@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Bartosz Golaszewski
Linus Walleij
parent
658cd189d7
commit
d2e9afca3a
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@ -4,6 +4,7 @@
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/generic.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/syscon.h>
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@ -90,7 +91,7 @@ struct debounce_time {
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};
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struct npcm8xx_gpio {
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struct gpio_chip gc;
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struct gpio_generic_chip chip;
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void __iomem *base;
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struct debounce_time debounce;
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int irqbase;
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@ -115,24 +116,20 @@ struct npcm8xx_pinctrl {
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};
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/* GPIO handling in the pinctrl driver */
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static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,
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static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg,
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unsigned int pinmask)
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{
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unsigned long flags;
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guard(gpio_generic_lock_irqsave)(chip);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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iowrite32(ioread32(reg) | pinmask, reg);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,
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static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg,
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unsigned int pinmask)
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{
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unsigned long flags;
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guard(gpio_generic_lock_irqsave)(chip);
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raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
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iowrite32(ioread32(reg) & ~pinmask, reg);
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raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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@ -233,32 +230,32 @@ static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVBE, gpio);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_POL, gpio);
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break;
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default:
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return -EINVAL;
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}
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if (type & IRQ_TYPE_LEVEL_MASK) {
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
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irq_set_handler_locked(d, handle_level_irq);
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} else if (type & IRQ_TYPE_EDGE_BOTH) {
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_EVTYP, gpio);
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irq_set_handler_locked(d, handle_edge_irq);
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}
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@ -1842,7 +1839,7 @@ static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,
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static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank,
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struct regmap *gcr_regmap, unsigned int pin)
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{
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int gpio = pin % bank->gc.ngpio;
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int gpio = pin % bank->chip.gc.ngpio;
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unsigned long pinmask = BIT(gpio);
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u32 val;
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@ -1862,15 +1859,15 @@ static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank,
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int arg)
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{
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void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC;
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int gpio = BIT(pin % bank->gc.ngpio);
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int gpio = BIT(pin % bank->chip.gc.ngpio);
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if (pincfg[pin].flag & SLEW) {
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switch (arg) {
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case 0:
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npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio);
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npcm_gpio_clr(&bank->chip, OSRC_Offset, gpio);
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return 0;
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case 1:
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npcm_gpio_set(&bank->gc, OSRC_Offset, gpio);
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npcm_gpio_set(&bank->chip, OSRC_Offset, gpio);
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return 0;
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default:
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return -EINVAL;
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@ -1902,7 +1899,7 @@ static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
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struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
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struct npcm8xx_gpio *bank =
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&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
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int gpio = pin % bank->gc.ngpio;
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int gpio = pin % bank->chip.gc.ngpio;
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unsigned long pinmask = BIT(gpio);
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int flg, val;
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u32 ds = 0;
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@ -1913,7 +1910,7 @@ static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev,
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val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask;
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ds = val ? DSHI(flg) : DSLO(flg);
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dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
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dev_dbg(bank->chip.gc.parent, "pin %d strength %d = %d\n", pin, val, ds);
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return ds;
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}
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@ -1923,15 +1920,15 @@ static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm,
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{
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struct npcm8xx_gpio *bank =
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&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
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int gpio = BIT(pin % bank->gc.ngpio);
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int gpio = BIT(pin % bank->chip.gc.ngpio);
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int v;
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v = pincfg[pin].flag & DRIVE_STRENGTH_MASK;
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if (DSLO(v) == nval)
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);
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else if (DSHI(v) == nval)
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_ODSC, gpio);
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else
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return -ENOTSUPP;
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@ -2054,7 +2051,7 @@ static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
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struct npcm8xx_gpio *bank =
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&npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK];
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int gpio = BIT(offset % bank->gc.ngpio);
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int gpio = BIT(offset % bank->chip.gc.ngpio);
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if (input)
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iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
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@ -2085,7 +2082,7 @@ static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
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if (bank->debounce.set_val[i]) {
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if (bank->debounce.nanosec_val[i] == nanosecs) {
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debounce_select = i << gpio_debounce;
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npcm_gpio_set(&bank->gc, DBNCS_offset,
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npcm_gpio_set(&bank->chip, DBNCS_offset,
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debounce_select);
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break;
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}
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@ -2093,7 +2090,7 @@ static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio,
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bank->debounce.set_val[i] = true;
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bank->debounce.nanosec_val[i] = nanosecs;
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debounce_select = i << gpio_debounce;
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npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select);
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npcm_gpio_set(&bank->chip, DBNCS_offset, debounce_select);
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switch (nanosecs) {
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case 1 ... 1040:
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iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4));
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@ -2145,21 +2142,21 @@ static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin,
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{
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struct npcm8xx_gpio *bank =
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&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
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int gpio = BIT(pin % bank->gc.ngpio);
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int gpio = BIT(pin % bank->chip.gc.ngpio);
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int ret;
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if (nanosecs) {
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ret = debounce_timing_setting(bank, pin % bank->gc.ngpio,
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ret = debounce_timing_setting(bank, pin % bank->chip.gc.ngpio,
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nanosecs);
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if (ret)
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dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin);
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else
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC,
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC,
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gpio);
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return ret;
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}
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_DBNC, gpio);
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return 0;
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}
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@ -2172,7 +2169,7 @@ static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
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struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);
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struct npcm8xx_gpio *bank =
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&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
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int gpio = pin % bank->gc.ngpio;
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int gpio = pin % bank->chip.gc.ngpio;
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unsigned long pinmask = BIT(gpio);
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u32 ie, oe, pu, pd;
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int rc = 0;
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@ -2235,34 +2232,34 @@ static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm,
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struct npcm8xx_gpio *bank =
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&npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK];
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u32 arg = pinconf_to_config_argument(config);
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int gpio = BIT(pin % bank->gc.ngpio);
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int gpio = BIT(pin % bank->chip.gc.ngpio);
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio);
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_PD, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_PU, gpio);
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC);
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bank->direction_input(&bank->gc, pin % bank->gc.ngpio);
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bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio);
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break;
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case PIN_CONFIG_OUTPUT:
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bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg);
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bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg);
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iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES);
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break;
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case PIN_CONFIG_DRIVE_PUSH_PULL:
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npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
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npcm_gpio_clr(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);
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break;
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case PIN_CONFIG_DRIVE_OPEN_DRAIN:
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npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio);
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npcm_gpio_set(&bank->chip, bank->base + NPCM8XX_GP_N_OTYP, gpio);
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break;
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case PIN_CONFIG_INPUT_DEBOUNCE:
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return npcm_set_debounce(npcm, pin, arg * 1000);
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@ -2313,13 +2310,14 @@ static int npcmgpio_add_pin_ranges(struct gpio_chip *chip)
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{
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struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
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return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent),
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bank->pinctrl_id, bank->gc.base,
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bank->gc.ngpio);
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return gpiochip_add_pin_range(&bank->chip.gc, dev_name(chip->parent),
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bank->pinctrl_id, bank->chip.gc.base,
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bank->chip.gc.ngpio);
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}
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static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
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{
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struct gpio_generic_chip_config config;
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struct fwnode_reference_args args;
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struct device *dev = pctrl->dev;
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struct fwnode_handle *child;
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@ -2331,15 +2329,19 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
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if (!pctrl->gpio_bank[id].base)
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return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id);
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ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4,
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pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
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pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
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NULL,
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NULL,
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pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
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BGPIOF_READ_OUTPUT_REG_SET);
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config = (typeof(config)){
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.dev = dev,
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.sz = 4,
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.dat = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN,
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.set = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT,
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.dirin = pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM,
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.flags = BGPIOF_READ_OUTPUT_REG_SET,
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};
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ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config);
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if (ret)
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return dev_err_probe(dev, ret, "bgpio_init() failed\n");
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return dev_err_probe(dev, ret,
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"failed to initialize the generic GPIO chip\n");
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ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args);
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if (ret < 0)
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@ -2353,26 +2355,26 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
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pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip;
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pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK;
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pctrl->gpio_bank[id].pinctrl_id = args.args[0];
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pctrl->gpio_bank[id].gc.base = -1;
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pctrl->gpio_bank[id].gc.ngpio = args.args[2];
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pctrl->gpio_bank[id].gc.owner = THIS_MODULE;
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pctrl->gpio_bank[id].gc.parent = dev;
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pctrl->gpio_bank[id].gc.fwnode = child;
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pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
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if (pctrl->gpio_bank[id].gc.label == NULL)
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pctrl->gpio_bank[id].chip.gc.base = -1;
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pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2];
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pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE;
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pctrl->gpio_bank[id].chip.gc.parent = dev;
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pctrl->gpio_bank[id].chip.gc.fwnode = child;
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pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child);
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if (pctrl->gpio_bank[id].chip.gc.label == NULL)
|
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return -ENOMEM;
|
||||
|
||||
pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show;
|
||||
pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input;
|
||||
pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input;
|
||||
pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output;
|
||||
pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
|
||||
pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
|
||||
pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
|
||||
pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;
|
||||
pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show;
|
||||
pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input;
|
||||
pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input;
|
||||
pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output;
|
||||
pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output;
|
||||
pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request;
|
||||
pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request;
|
||||
pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free;
|
||||
for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
|
||||
pctrl->gpio_bank[id].debounce.set_val[i] = false;
|
||||
pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges;
|
||||
pctrl->gpio_bank[id].chip.gc.add_pin_ranges = npcmgpio_add_pin_ranges;
|
||||
id++;
|
||||
}
|
||||
|
||||
|
|
@ -2387,7 +2389,7 @@ static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
|
|||
for (id = 0 ; id < pctrl->bank_num ; id++) {
|
||||
struct gpio_irq_chip *girq;
|
||||
|
||||
girq = &pctrl->gpio_bank[id].gc.irq;
|
||||
girq = &pctrl->gpio_bank[id].chip.gc.irq;
|
||||
girq->chip = &pctrl->gpio_bank[id].irq_chip;
|
||||
girq->parent_handler = npcmgpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
|
|
@ -2401,7 +2403,7 @@ static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl)
|
|||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_level_irq;
|
||||
ret = devm_gpiochip_add_data(pctrl->dev,
|
||||
&pctrl->gpio_bank[id].gc,
|
||||
&pctrl->gpio_bank[id].chip.gc,
|
||||
&pctrl->gpio_bank[id]);
|
||||
if (ret)
|
||||
return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user