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drm/i915: Extract intel_{get,set}_m_n()

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Make the M/N setup/readout a bit less repitive by extracting
a few small helpers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127093303.17309-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2022-01-27 11:32:50 +02:00
parent 516b33460c
commit d29c993027
1 changed files with 47 additions and 62 deletions
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109
drivers/gpu/drm/i915/display/intel_display.c
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@ -3113,6 +3113,17 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
}
}
static void intel_set_m_n(struct drm_i915_private *i915,
const struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
{
intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->gmch_m);
intel_de_write(i915, data_n_reg, m_n->gmch_n);
intel_de_write(i915, link_m_reg, m_n->link_m);
intel_de_write(i915, link_n_reg, m_n->link_n);
}
static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n)
{
@ -3120,11 +3131,9 @@ static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe),
TU_SIZE(m_n->tu) | m_n->gmch_m);
intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m);
intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n);
intel_set_m_n(dev_priv, m_n,
PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
}
static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
@ -3150,35 +3159,23 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta
enum transcoder transcoder = crtc_state->cpu_transcoder;
if (DISPLAY_VER(dev_priv) >= 5) {
intel_de_write(dev_priv, PIPE_DATA_M1(transcoder),
TU_SIZE(m_n->tu) | m_n->gmch_m);
intel_de_write(dev_priv, PIPE_DATA_N1(transcoder),
m_n->gmch_n);
intel_de_write(dev_priv, PIPE_LINK_M1(transcoder),
m_n->link_m);
intel_de_write(dev_priv, PIPE_LINK_N1(transcoder),
m_n->link_n);
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
/*
* M2_N2 registers are set only if DRRS is supported
* (to make sure the registers are not unnecessarily accessed).
*/
if (m2_n2 && crtc_state->has_drrs &&
transcoder_has_m2_n2(dev_priv, transcoder)) {
intel_de_write(dev_priv, PIPE_DATA_M2(transcoder),
TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
intel_de_write(dev_priv, PIPE_DATA_N2(transcoder),
m2_n2->gmch_n);
intel_de_write(dev_priv, PIPE_LINK_M2(transcoder),
m2_n2->link_m);
intel_de_write(dev_priv, PIPE_LINK_N2(transcoder),
m2_n2->link_n);
intel_set_m_n(dev_priv, m2_n2,
PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
} else {
intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe),
TU_SIZE(m_n->tu) | m_n->gmch_m);
intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m);
intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n);
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
}
@ -3863,6 +3860,18 @@ int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
return DIV_ROUND_UP(bps, link_bw * 8);
}
static void intel_get_m_n(struct drm_i915_private *i915,
struct intel_link_m_n *m_n,
i915_reg_t data_m_reg, i915_reg_t data_n_reg,
i915_reg_t link_m_reg, i915_reg_t link_n_reg)
{
m_n->link_m = intel_de_read(i915, link_m_reg);
m_n->link_n = intel_de_read(i915, link_n_reg);
m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;
m_n->gmch_n = intel_de_read(i915, data_n_reg);
m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
}
static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
@ -3870,13 +3879,9 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe));
m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe));
m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
& ~TU_SIZE_MASK;
m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe));
m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe))
& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
intel_get_m_n(dev_priv, m_n,
PCH_TRANS_DATA_M1(pipe), PCH_TRANS_DATA_N1(pipe),
PCH_TRANS_LINK_M1(pipe), PCH_TRANS_LINK_N1(pipe));
}
static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
@ -3888,39 +3893,19 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
enum pipe pipe = crtc->pipe;
if (DISPLAY_VER(dev_priv) >= 5) {
m_n->link_m = intel_de_read(dev_priv,
PIPE_LINK_M1(transcoder));
m_n->link_n = intel_de_read(dev_priv,
PIPE_LINK_N1(transcoder));
m_n->gmch_m = intel_de_read(dev_priv,
PIPE_DATA_M1(transcoder))
& ~TU_SIZE_MASK;
m_n->gmch_n = intel_de_read(dev_priv,
PIPE_DATA_N1(transcoder));
m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder))
& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {
m2_n2->link_m = intel_de_read(dev_priv,
PIPE_LINK_M2(transcoder));
m2_n2->link_n = intel_de_read(dev_priv,
PIPE_LINK_N2(transcoder));
m2_n2->gmch_m = intel_de_read(dev_priv,
PIPE_DATA_M2(transcoder))
& ~TU_SIZE_MASK;
m2_n2->gmch_n = intel_de_read(dev_priv,
PIPE_DATA_N2(transcoder));
m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder))
& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
intel_get_m_n(dev_priv, m2_n2,
PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
} else {
m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe));
m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe));
m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
& ~TU_SIZE_MASK;
m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe));
m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe))
& TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
}