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dt-bindings: edac: Convert apm,xgene-edac to DT schema

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Convert the APM XGene EDAC binding to DT schema. Add the missing
"apm,xgene-edac-soc" compatible, and drop the unused
"apm,xgene-edac-pmd-v2" compatible.

Link: https://lore.kernel.org/r/20250828223023.2409337-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Rob Herring (Arm) 2025-08-28 17:30:21 -05:00
parent 047170ac08
commit d27ce63a31
3 changed files with 204 additions and 113 deletions
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203
Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml Normal file
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@ -0,0 +1,203 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/apm,xgene-edac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC EDAC
maintainers:
- Khuong Dinh <khuong@os.amperecomputing.com>
description: >
EDAC node is defined to describe on-chip error detection and correction.
The following error types are supported:
memory controller - Memory controller
PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
L3 - L3 cache controller
SoC - SoC IPs such as Ethernet, SATA, etc
properties:
compatible:
const: apm,xgene-edac
reg:
items:
- description: CPU bus (PCP) resource
'#address-cells':
const: 2
'#size-cells':
const: 2
ranges: true
interrupts:
description: Interrupt-specifier for MCU, PMD, L3, or SoC error IRQ(s).
items:
- description: MCU error IRQ
- description: PMD error IRQ
- description: L3 error IRQ
- description: SoC error IRQ
minItems: 1
regmap-csw:
description: Regmap of the CPU switch fabric (CSW) resource.
$ref: /schemas/types.yaml#/definitions/phandle
regmap-mcba:
description: Regmap of the MCB-A (memory bridge) resource.
$ref: /schemas/types.yaml#/definitions/phandle
regmap-mcbb:
description: Regmap of the MCB-B (memory bridge) resource.
$ref: /schemas/types.yaml#/definitions/phandle
regmap-efuse:
description: Regmap of the PMD efuse resource.
$ref: /schemas/types.yaml#/definitions/phandle
regmap-rb:
description: Regmap of the register bus resource (optional for compatibility).
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- regmap-csw
- regmap-mcba
- regmap-mcbb
- regmap-efuse
- reg
- interrupts
# Child-node bindings
patternProperties:
'^edacmc@':
description: Memory controller subnode
type: object
additionalProperties: false
properties:
compatible:
const: apm,xgene-edac-mc
reg:
maxItems: 1
memory-controller:
description: Instance number of the memory controller.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
required:
- compatible
- reg
- memory-controller
'^edacpmd@':
description: PMD subnode
type: object
additionalProperties: false
properties:
compatible:
const: apm,xgene-edac-pmd
reg:
maxItems: 1
pmd-controller:
description: Instance number of the PMD controller.
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 3
required:
- compatible
- reg
- pmd-controller
'^edacl3@':
description: L3 subnode
type: object
additionalProperties: false
properties:
compatible:
enum:
- apm,xgene-edac-l3
- apm,xgene-edac-l3-v2
reg:
maxItems: 1
required:
- compatible
- reg
'^edacsoc@':
description: SoC subnode
type: object
additionalProperties: false
properties:
compatible:
enum:
- apm,xgene-edac-soc
- apm,xgene-edac-soc-v1
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
edac@78800000 {
compatible = "apm,xgene-edac";
reg = <0x0 0x78800000 0x0 0x100>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, <0x0 0x27 0x4>;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
regmap-efuse = <&efuse>;
regmap-rb = <&rb>;
edacmc@7e800000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e800000 0x0 0x1000>;
memory-controller = <0>;
};
edacpmd@7c000000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c000000 0x0 0x200000>;
pmd-controller = <0>;
};
edacl3@7e600000 {
compatible = "apm,xgene-edac-l3";
reg = <0x0 0x7e600000 0x0 0x1000>;
};
edacsoc@7e930000 {
compatible = "apm,xgene-edac-soc-v1";
reg = <0x0 0x7e930000 0x0 0x1000>;
};
};
};

112
Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
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@ -1,112 +0,0 @@
* APM X-Gene SoC EDAC node
EDAC node is defined to describe on-chip error detection and correction.
The follow error types are supported:
memory controller - Memory controller
PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
L3 - L3 cache controller
SoC - SoC IP's such as Ethernet, SATA, and etc
The following section describes the EDAC DT node binding.
Required properties:
- compatible : Shall be "apm,xgene-edac".
- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
- regmap-efuse : Regmap of the PMD efuse resource.
- regmap-rb : Regmap of the register bus resource. This property
is optional only for compatibility. If the RB
error conditions are not cleared, it will
continuously generate interrupt.
- reg : First resource shall be the CPU bus (PCP) resource.
- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
IRQ(s).
Required properties for memory controller subnode:
- compatible : Shall be "apm,xgene-edac-mc".
- reg : First resource shall be the memory controller unit
(MCU) resource.
- memory-controller : Instance number of the memory controller.
Required properties for PMD subnode:
- compatible : Shall be "apm,xgene-edac-pmd" or
"apm,xgene-edac-pmd-v2".
- reg : First resource shall be the PMD resource.
- pmd-controller : Instance number of the PMD controller.
Required properties for L3 subnode:
- compatible : Shall be "apm,xgene-edac-l3" or
"apm,xgene-edac-l3-v2".
- reg : First resource shall be the L3 EDAC resource.
Required properties for SoC subnode:
- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or
"apm,xgene-edac-l3-soc" for general value reporting
only.
- reg : First resource shall be the SoC EDAC resource.
Example:
csw: csw@7e200000 {
compatible = "apm,xgene-csw", "syscon";
reg = <0x0 0x7e200000 0x0 0x1000>;
};
mcba: mcba@7e700000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e700000 0x0 0x1000>;
};
mcbb: mcbb@7e720000 {
compatible = "apm,xgene-mcb", "syscon";
reg = <0x0 0x7e720000 0x0 0x1000>;
};
efuse: efuse@1054a000 {
compatible = "apm,xgene-efuse", "syscon";
reg = <0x0 0x1054a000 0x0 0x20>;
};
rb: rb@7e000000 {
compatible = "apm,xgene-rb", "syscon";
reg = <0x0 0x7e000000 0x0 0x10>;
};
edac@78800000 {
compatible = "apm,xgene-edac";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
regmap-efuse = <&efuse>;
regmap-rb = <&rb>;
reg = <0x0 0x78800000 0x0 0x100>;
interrupts = <0x0 0x20 0x4>,
<0x0 0x21 0x4>,
<0x0 0x27 0x4>;
edacmc@7e800000 {
compatible = "apm,xgene-edac-mc";
reg = <0x0 0x7e800000 0x0 0x1000>;
memory-controller = <0>;
};
edacpmd@7c000000 {
compatible = "apm,xgene-edac-pmd";
reg = <0x0 0x7c000000 0x0 0x200000>;
pmd-controller = <0>;
};
edacl3@7e600000 {
compatible = "apm,xgene-edac-l3";
reg = <0x0 0x7e600000 0x0 0x1000>;
};
edacsoc@7e930000 {
compatible = "apm,xgene-edac-soc-v1";
reg = <0x0 0x7e930000 0x0 0x1000>;
};
};

2
MAINTAINERS
View File

@ -1872,7 +1872,7 @@ F: arch/arm64/boot/dts/apm/
APPLIED MICRO (APM) X-GENE SOC EDAC
M: Khuong Dinh <khuong@os.amperecomputing.com>
S: Supported
F: Documentation/devicetree/bindings/edac/apm-xgene-edac.txt
F: Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml
F: drivers/edac/xgene_edac.c
APPLIED MICRO (APM) X-GENE SOC ETHERNET (V2) DRIVER