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KVM: selftests: Add basic stress test for save+restore and #PF handling
Add a basic stress test for handling #PFs in a guest while the host is doing save+restore cycles. The guest periodically accesses non-present memory causing a #PF, and the #PF handler walks the page tables and updates the PTE to be present, like a proper #PF handler. After every access (and #PF), the guest triggers a sync and the test performs save+restore of the VM. This is not very meaningful as save+restore are performed after the access and #PF handling complete, but following changes will change that. Assisted-by: Gemini:gemini-3.1-pro Signed-off-by: Yosry Ahmed <yosry@kernel.org> Link: https://patch.msgid.link/20260728174232.2423257-11-yosry@kernel.org Signed-off-by: Sean Christopherson <seanjc@google.com>
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@ -106,6 +106,7 @@ TEST_GEN_PROGS_x86 += x86/pmu_counters_test
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TEST_GEN_PROGS_x86 += x86/pmu_event_filter_test
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TEST_GEN_PROGS_x86 += x86/private_mem_conversions_test
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TEST_GEN_PROGS_x86 += x86/private_mem_kvm_exits_test
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TEST_GEN_PROGS_x86 += x86/save_restore_pf_stress_test
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TEST_GEN_PROGS_x86 += x86/set_boot_cpu_id
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TEST_GEN_PROGS_x86 += x86/set_sregs_test
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TEST_GEN_PROGS_x86 += x86/smaller_maxphyaddr_emulation_test
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@ -612,6 +612,14 @@ static inline void set_cr0(u64 val)
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__asm__ __volatile__("mov %0, %%cr0" : : "r" (val) : "memory");
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}
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static inline u64 get_cr2(void)
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{
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u64 cr2;
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__asm__ __volatile__("mov %%cr2, %[cr2]" : [cr2]"=r"(cr2));
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return cr2;
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}
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static inline u64 get_cr3(void)
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{
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u64 cr3;
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@ -907,6 +915,11 @@ static inline void write_sse_reg(int reg, const sse128_t *data)
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}
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}
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static inline void invlpg(u64 addr)
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{
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__asm__ __volatile__("invlpg (%0)" : : "r"(addr) : "memory");
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}
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static inline void cpu_relax(void)
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{
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asm volatile("rep; nop" ::: "memory");
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160
tools/testing/selftests/kvm/x86/save_restore_pf_stress_test.c
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160
tools/testing/selftests/kvm/x86/save_restore_pf_stress_test.c
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@ -0,0 +1,160 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <errno.h>
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#include <sys/types.h>
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#include <time.h>
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#include <unistd.h>
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#include "test_util.h"
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#include "kvm_util.h"
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#include "processor.h"
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#define NR_ITERATIONS 500
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#define PTRS_PER_PTE 512
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#define PXD_INDEX(vaddr, level) (((vaddr) >> PG_LEVEL_SHIFT(level)) & (PTRS_PER_PTE - 1))
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#define TEST_MEM_BASE_GVA 0xc0000000ULL
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#define TEST_PGTABLE_GVA_OFFSET 0xd0000000ULL
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#define PATTERN 0xabcdefabcdefabcdULL
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static u64 expected_vaddr;
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static u64 guest_faults;
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static u64 *guest_get_pte(u64 vaddr)
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{
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u64 pgtable_pa, pte;
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u64 *pgtable;
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int level;
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level = (get_cr4() & X86_CR4_LA57) ? PG_LEVEL_256T : PG_LEVEL_512G;
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pgtable_pa = get_cr3() & PHYSICAL_PAGE_MASK;
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for (; level > PG_LEVEL_4K; level--) {
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pgtable = (u64 *)(pgtable_pa + TEST_PGTABLE_GVA_OFFSET);
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pte = pgtable[PXD_INDEX(vaddr, level)];
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GUEST_ASSERT(pte & PTE_PRESENT_MASK(&guest_mmu));
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GUEST_ASSERT(!(pte & PTE_HUGE_MASK(&guest_mmu)));
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pgtable_pa = PTE_GET_PA(pte);
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}
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pgtable = (u64 *)(pgtable_pa + TEST_PGTABLE_GVA_OFFSET);
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return &pgtable[PXD_INDEX(vaddr, PG_LEVEL_4K)];
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}
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static void guest_pf_handler(struct ex_regs *regs)
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{
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u64 fault_addr;
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u64 *ptep;
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fault_addr = get_cr2();
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GUEST_ASSERT_EQ(fault_addr, READ_ONCE(expected_vaddr));
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ptep = guest_get_pte(fault_addr);
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GUEST_ASSERT(ptep);
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GUEST_ASSERT(!(*ptep & PTE_PRESENT_MASK(&guest_mmu)));
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*ptep |= PTE_PRESENT_MASK(&guest_mmu);
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guest_faults++;
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}
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static void guest_access_memory(void *arg)
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{
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u64 vaddr, val;
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int i;
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for (i = 0; ; i++) {
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vaddr = TEST_MEM_BASE_GVA + (i % PTRS_PER_PTE) * PAGE_SIZE;
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WRITE_ONCE(expected_vaddr, vaddr);
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/* Read to trigger #PF */
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val = READ_ONCE(*(u64 *)vaddr);
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GUEST_ASSERT_EQ(val, PATTERN);
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/* Clear the present bit again so it faults next time */
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*guest_get_pte(vaddr) &= ~PTE_PRESENT_MASK(&guest_mmu);
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invlpg(vaddr);
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GUEST_SYNC(guest_faults);
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}
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}
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int main(int argc, char *argv[])
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{
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struct kvm_x86_state *state;
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int r, i, level;
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gpa_t gpa, pgtable_gpa;
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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struct ucall uc;
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u64 *pgtable;
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gva_t gva;
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u64 pte;
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vm = vm_create_with_one_vcpu(&vcpu, guest_access_memory);
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vm_install_exception_handler(vm, PF_VECTOR, guest_pf_handler);
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/* Allocate a page and write the pattern to it */
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gva = vm_alloc_page(vm);
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*(u64 *)addr_gva2hva(vm, gva) = PATTERN;
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gpa = addr_gva2gpa(vm, gva);
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/*
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* Map all virtual addresses to the pattern page and clear the present
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* bit such that guest accesses will cause a #PF.
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*/
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for (i = 0; i < PTRS_PER_PTE; i++) {
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gva = TEST_MEM_BASE_GVA + i * getpagesize();
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virt_pg_map(vm, gva, gpa);
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*vm_get_pte(vm, gva) &= ~PTE_PRESENT_MASK(&vm->mmu);
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}
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/*
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* Now create mappings for the page tables created above so that the
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* guest #PF handler can walk them. All PTEs for test virtual addresses
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* should lie on the same PTE page, so one page is mapped for each page
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* table level.
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*
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* Use an offset for the GVA instead of creating identity mappings to
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* avoid collision with existing mappings at low GVAs (e.g. ELF).
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*/
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pgtable_gpa = vm->mmu.pgd;
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for (level = vm->mmu.pgtable_levels; level >= PG_LEVEL_4K; level--) {
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virt_map(vm, pgtable_gpa + TEST_PGTABLE_GVA_OFFSET, pgtable_gpa, 1);
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pgtable = addr_gpa2hva(vm, pgtable_gpa);
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pte = pgtable[PXD_INDEX(TEST_MEM_BASE_GVA, level)];
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pgtable_gpa = PTE_GET_PA(pte);
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}
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for (i = 1; i <= NR_ITERATIONS; i++) {
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r = __vcpu_run(vcpu);
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TEST_ASSERT(!r, "vcpu_run failed");
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TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
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get_ucall(vcpu, &uc);
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if (uc.cmd == UCALL_ABORT) {
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REPORT_GUEST_ASSERT(uc);
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break;
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}
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TEST_ASSERT_EQ(uc.cmd, UCALL_SYNC);
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TEST_ASSERT_EQ(uc.args[1], i);
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state = vcpu_save_state(vcpu);
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kvm_vm_release(vm);
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vcpu = vm_recreate_with_one_vcpu(vm);
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vcpu_load_state(vcpu, state);
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kvm_x86_state_cleanup(state);
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pr_info("\rSave+restore iterations: %d", i);
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}
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pr_info("\n");
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sync_global_from_guest(vm, guest_faults);
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pr_info("Guest page faults: %lu\n", guest_faults);
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kvm_vm_free(vm);
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return 0;
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}
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