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PCI: dwc: Add debugfs based Error Injection support for DWC
Add support to provide Error Injection interface to userspace. This set of debug registers are part of the RAS DES feature present in DesignWare PCIe controllers. Signed-off-by: Shradha Todi <shradha.t@samsung.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Hrishikesh Deleep <hrishikesh.d@samsung.com> Link: https://lore.kernel.org/r/20250221131548.59616-5-shradha.t@samsung.com [kwilczynski: commit log, tidy up code comments, update documentation, change debugfs property name from "duplicate_dllp" to "duplicate_tlp"] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
This commit is contained in:
Shradha Todi
Krzysztof Wilczyński
parent
4fbfa17f9a
commit
d20ee8e2db
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@ -11,3 +11,77 @@ Contact: Shradha Todi <shradha.t@samsung.com>
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Description: (RW) Write the lane number to be checked as valid or invalid.
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Read will return the status of PIPE RXVALID signal of the
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selected lane. The default selected lane is Lane0.
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What: /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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Date: February 2025
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Contact: Shradha Todi <shradha.t@samsung.com>
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Description: The "rasdes_err_inj" is a directory which can be used to inject
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errors into the system. The possible errors that can be injected
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are:
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1) tx_lcrc - TLP LCRC error injection TX Path
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2) b16_crc_dllp - 16b CRC error injection of ACK/NAK DLLP
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3) b16_crc_upd_fc - 16b CRC error injection of Update-FC DLLP
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4) tx_ecrc - TLP ECRC error injection TX Path
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5) fcrc_tlp - TLP's FCRC error injection TX Path
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6) parity_tsos - Parity error of TSOS
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7) parity_skpos - Parity error on SKPOS
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8) rx_lcrc - LCRC error injection RX Path
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9) rx_ecrc - ECRC error injection RX Path
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10) tlp_err_seq - TLPs SEQ# error
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11) ack_nak_dllp_seq - DLLPS ACK/NAK SEQ# error
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12) ack_nak_dllp - ACK/NAK DLLPs transmission block
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13) upd_fc_dllp - UpdateFC DLLPs transmission block
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14) nak_dllp - Always transmission for NAK DLLP
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15) inv_sync_hdr_sym - Invert SYNC header
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16) com_pad_ts1 - COM/PAD TS1 order set
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17) com_pad_ts2 - COM/PAD TS2 order set
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18) com_fts - COM/FTS FTS order set
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19) com_idl - COM/IDL E-idle order set
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20) end_edb - END/EDB symbol
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21) stp_sdp - STP/SDP symbol
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22) com_skp - COM/SKP SKP order set
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23) posted_tlp_hdr - Posted TLP Header credit value control
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24) non_post_tlp_hdr - Non-Posted TLP Header credit value control
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25) cmpl_tlp_hdr - Completion TLP Header credit value control
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26) posted_tlp_data - Posted TLP Data credit value control
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27) non_post_tlp_data - Non-Posted TLP Data credit value control
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28) cmpl_tlp_data - Completion TLP Data credit value control
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29) duplicate_tlp - Generates duplicate TLPs
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30) nullified_tlp - Generates Nullified TLPs
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(WO) Write to the attribute will prepare controller to inject
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the respective error in the next transmission of data.
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Parameter required to write will change in the following ways:
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- Errors 9 and 10 are sequence errors. The write command:
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echo <count> <diff> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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<diff>
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The difference to add or subtract from natural
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sequence number to generate sequence error.
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Allowed range from -4095 to 4095
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- Errors 23 to 28 are credit value error insertions. The write
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command:
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echo <count> <diff> <vc> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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<diff>
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The difference to add or subtract from UpdateFC
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credit value. Allowed range from -4095 to 4095
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<vc>
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Target VC number
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- All other errors. The write command:
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echo <count> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
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<count>
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Number of errors to be injected
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@ -17,6 +17,20 @@
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#define PIPE_DETECT_LANE BIT(17)
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#define LANE_SELECT GENMASK(3, 0)
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#define ERR_INJ0_OFF 0x34
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#define EINJ_VAL_DIFF GENMASK(28, 16)
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#define EINJ_VC_NUM GENMASK(14, 12)
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#define EINJ_TYPE_SHIFT 8
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#define EINJ0_TYPE GENMASK(11, 8)
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#define EINJ1_TYPE BIT(8)
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#define EINJ2_TYPE GENMASK(9, 8)
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#define EINJ3_TYPE GENMASK(10, 8)
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#define EINJ4_TYPE GENMASK(10, 8)
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#define EINJ5_TYPE BIT(8)
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#define EINJ_COUNT GENMASK(7, 0)
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#define ERR_INJ_ENABLE_REG 0x30
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#define DWC_DEBUGFS_BUF_MAX 128
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/**
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@ -33,6 +47,74 @@ struct dwc_pcie_rasdes_info {
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struct mutex reg_event_lock;
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};
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/**
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* struct dwc_pcie_rasdes_priv - Stores file specific private data information
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* @pci: Reference to the dw_pcie structure
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* @idx: Index of specific file related information in array of structs
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*
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* All debugfs files will have this struct as its private data.
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*/
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struct dwc_pcie_rasdes_priv {
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struct dw_pcie *pci;
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int idx;
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};
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/**
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* struct dwc_pcie_err_inj - Store details about each error injection
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* supported by DWC RAS DES
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* @name: Name of the error that can be injected
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* @err_inj_group: Group number to which the error belongs. The value
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* can range from 0 to 5
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* @err_inj_type: Each group can have multiple types of error
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*/
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struct dwc_pcie_err_inj {
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const char *name;
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u32 err_inj_group;
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u32 err_inj_type;
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};
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static const struct dwc_pcie_err_inj err_inj_list[] = {
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{"tx_lcrc", 0x0, 0x0},
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{"b16_crc_dllp", 0x0, 0x1},
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{"b16_crc_upd_fc", 0x0, 0x2},
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{"tx_ecrc", 0x0, 0x3},
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{"fcrc_tlp", 0x0, 0x4},
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{"parity_tsos", 0x0, 0x5},
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{"parity_skpos", 0x0, 0x6},
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{"rx_lcrc", 0x0, 0x8},
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{"rx_ecrc", 0x0, 0xb},
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{"tlp_err_seq", 0x1, 0x0},
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{"ack_nak_dllp_seq", 0x1, 0x1},
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{"ack_nak_dllp", 0x2, 0x0},
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{"upd_fc_dllp", 0x2, 0x1},
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{"nak_dllp", 0x2, 0x2},
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{"inv_sync_hdr_sym", 0x3, 0x0},
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{"com_pad_ts1", 0x3, 0x1},
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{"com_pad_ts2", 0x3, 0x2},
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{"com_fts", 0x3, 0x3},
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{"com_idl", 0x3, 0x4},
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{"end_edb", 0x3, 0x5},
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{"stp_sdp", 0x3, 0x6},
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{"com_skp", 0x3, 0x7},
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{"posted_tlp_hdr", 0x4, 0x0},
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{"non_post_tlp_hdr", 0x4, 0x1},
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{"cmpl_tlp_hdr", 0x4, 0x2},
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{"posted_tlp_data", 0x4, 0x4},
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{"non_post_tlp_data", 0x4, 0x5},
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{"cmpl_tlp_data", 0x4, 0x6},
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{"duplicate_tlp", 0x5, 0x0},
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{"nullified_tlp", 0x5, 0x1},
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};
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static const u32 err_inj_type_mask[] = {
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EINJ0_TYPE,
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EINJ1_TYPE,
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EINJ2_TYPE,
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EINJ3_TYPE,
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EINJ4_TYPE,
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EINJ5_TYPE,
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};
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static ssize_t lane_detect_read(struct file *file, char __user *buf,
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size_t count, loff_t *ppos)
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{
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@ -96,6 +178,64 @@ static ssize_t rx_valid_write(struct file *file, const char __user *buf,
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return lane_detect_write(file, buf, count, ppos);
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}
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static ssize_t err_inj_write(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct dwc_pcie_rasdes_priv *pdata = file->private_data;
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struct dw_pcie *pci = pdata->pci;
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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u32 val, counter, vc_num, err_group, type_mask;
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int val_diff = 0;
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char *kern_buf;
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err_group = err_inj_list[pdata->idx].err_inj_group;
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type_mask = err_inj_type_mask[err_group];
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kern_buf = memdup_user_nul(buf, count);
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if (IS_ERR(kern_buf))
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return PTR_ERR(kern_buf);
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if (err_group == 4) {
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val = sscanf(kern_buf, "%u %d %u", &counter, &val_diff, &vc_num);
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if ((val != 3) || (val_diff < -4095 || val_diff > 4095)) {
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kfree(kern_buf);
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return -EINVAL;
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}
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} else if (err_group == 1) {
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val = sscanf(kern_buf, "%u %d", &counter, &val_diff);
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if ((val != 2) || (val_diff < -4095 || val_diff > 4095)) {
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kfree(kern_buf);
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return -EINVAL;
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}
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} else {
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val = kstrtou32(kern_buf, 0, &counter);
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if (val) {
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kfree(kern_buf);
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return val;
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}
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}
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val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group));
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val &= ~(type_mask | EINJ_COUNT);
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val |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask);
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val |= FIELD_PREP(EINJ_COUNT, counter);
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if (err_group == 1 || err_group == 4) {
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val &= ~(EINJ_VAL_DIFF);
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val |= FIELD_PREP(EINJ_VAL_DIFF, val_diff);
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}
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if (err_group == 4) {
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val &= ~(EINJ_VC_NUM);
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val |= FIELD_PREP(EINJ_VC_NUM, vc_num);
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}
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dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val);
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dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group));
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kfree(kern_buf);
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return count;
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}
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#define dwc_debugfs_create(name) \
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debugfs_create_file(#name, 0644, rasdes_debug, pci, \
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&dbg_ ## name ## _fops)
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@ -110,6 +250,11 @@ static const struct file_operations dbg_ ## name ## _fops = { \
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DWC_DEBUGFS_FOPS(lane_detect);
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DWC_DEBUGFS_FOPS(rx_valid);
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static const struct file_operations dwc_pcie_err_inj_ops = {
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.open = simple_open,
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.write = err_inj_write,
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};
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static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
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{
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struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
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@ -119,10 +264,11 @@ static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
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static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
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{
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struct dentry *rasdes_debug;
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struct dentry *rasdes_debug, *rasdes_err_inj;
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struct dwc_pcie_rasdes_info *rasdes_info;
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struct dwc_pcie_rasdes_priv *priv_tmp;
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struct device *dev = pci->dev;
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int ras_cap;
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int ras_cap, i, ret;
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/*
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* If a given SoC has no RAS DES capability, the following call is
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@ -141,6 +287,7 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
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/* Create subdirectories for Debug, Error Injection, Statistics. */
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rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
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rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir);
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mutex_init(&rasdes_info->reg_event_lock);
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rasdes_info->ras_cap_offset = ras_cap;
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@ -150,7 +297,24 @@ static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
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dwc_debugfs_create(lane_detect);
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dwc_debugfs_create(rx_valid);
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/* Create debugfs files for Error Injection subdirectory. */
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for (i = 0; i < ARRAY_SIZE(err_inj_list); i++) {
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priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
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if (!priv_tmp) {
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ret = -ENOMEM;
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goto err_deinit;
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}
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priv_tmp->idx = i;
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priv_tmp->pci = pci;
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debugfs_create_file(err_inj_list[i].name, 0200, rasdes_err_inj, priv_tmp,
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&dwc_pcie_err_inj_ops);
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}
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return 0;
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err_deinit:
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dwc_pcie_rasdes_debugfs_deinit(pci);
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return ret;
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}
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void dwc_pcie_debugfs_deinit(struct dw_pcie *pci)
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