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spi: airoha: reduce the number of modification of REG_SPI_NFI_CNFG and REG_SPI_NFI_SECCUS_SIZE registers
This just reduce the number of modification of REG_SPI_NFI_CNFG and REG_SPI_NFI_SECCUS_SIZE registers during dirmap operation. This patch is a necessary step to avoid reading flash page settings from SNFI registers during driver startup. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://patch.msgid.link/20251012121707.2296160-11-mikhail.kshevetskiy@iopsys.eu Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -668,7 +668,48 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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if (err < 0)
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return err;
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err = airoha_snand_nfi_config(as_ctrl);
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/* NFI reset */
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err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
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if (err)
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goto error_dma_mode_off;
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/* NFI configure:
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* - No AutoFDM (custom sector size (SECCUS) register will be used)
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* - No SoC's hardware ECC (flash internal ECC will be used)
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* - Use burst mode (faster, but requires 16 byte alignment for addresses)
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* - Setup for reading (SPI_NFI_READ_MODE)
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* - Setup reading command: FIELD_PREP(SPI_NFI_OPMODE, 6)
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* - Use DMA instead of PIO for data reading
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*/
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_DMA_MODE |
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SPI_NFI_READ_MODE |
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SPI_NFI_DMA_BURST_EN |
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SPI_NFI_HW_ECC_EN |
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SPI_NFI_AUTO_FDM_EN |
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SPI_NFI_OPMODE,
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SPI_NFI_DMA_MODE |
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SPI_NFI_READ_MODE |
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SPI_NFI_DMA_BURST_EN |
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FIELD_PREP(SPI_NFI_OPMODE, 6));
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if (err)
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goto error_dma_mode_off;
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/* Set number of sector will be read */
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val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_SEC_NUM, val);
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if (err)
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goto error_dma_mode_off;
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/* Set custom sector size */
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val = as_ctrl->nfi_cfg.sec_size;
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
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SPI_NFI_CUS_SEC_SIZE |
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SPI_NFI_CUS_SEC_SIZE_EN,
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FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
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SPI_NFI_CUS_SEC_SIZE_EN);
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if (err)
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goto error_dma_mode_off;
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@ -684,7 +725,14 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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if (err)
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goto error_dma_unmap;
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/* set cust sec size */
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/*
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* Setup transfer length
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* ---------------------
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* The following rule MUST be met:
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* transfer_length =
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* = NFI_SNF_MISC_CTL2.read_data_byte_number =
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* = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
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*/
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val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
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val = FIELD_PREP(SPI_NFI_READ_DATA_BYTE_NUM, val);
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err = regmap_update_bits(as_ctrl->regmap_nfi,
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@ -711,18 +759,6 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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if (err)
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goto error_dma_unmap;
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/* set nfi read */
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_OPMODE,
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FIELD_PREP(SPI_NFI_OPMODE, 6));
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if (err)
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goto error_dma_unmap;
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err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
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if (err)
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goto error_dma_unmap;
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err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
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if (err)
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goto error_dma_unmap;
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@ -815,7 +851,48 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
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if (err < 0)
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return err;
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err = airoha_snand_nfi_config(as_ctrl);
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/* NFI reset */
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err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_FIFO_FLUSH | SPI_NFI_RST);
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if (err)
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goto error_dma_mode_off;
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/*
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* NFI configure:
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* - No AutoFDM (custom sector size (SECCUS) register will be used)
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* - No SoC's hardware ECC (flash internal ECC will be used)
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* - Use burst mode (faster, but requires 16 byte alignment for addresses)
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* - Setup for writing (SPI_NFI_READ_MODE bit is cleared)
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* - Setup writing command: FIELD_PREP(SPI_NFI_OPMODE, 3)
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* - Use DMA instead of PIO for data writing
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*/
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_DMA_MODE |
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SPI_NFI_READ_MODE |
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SPI_NFI_DMA_BURST_EN |
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SPI_NFI_HW_ECC_EN |
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SPI_NFI_AUTO_FDM_EN |
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SPI_NFI_OPMODE,
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SPI_NFI_DMA_MODE |
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SPI_NFI_DMA_BURST_EN |
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FIELD_PREP(SPI_NFI_OPMODE, 3));
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if (err)
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goto error_dma_mode_off;
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/* Set number of sector will be written */
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val = FIELD_PREP(SPI_NFI_SEC_NUM, as_ctrl->nfi_cfg.sec_num);
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
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SPI_NFI_SEC_NUM, val);
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if (err)
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goto error_dma_mode_off;
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/* Set custom sector size */
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val = as_ctrl->nfi_cfg.sec_size;
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_SECCUS_SIZE,
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SPI_NFI_CUS_SEC_SIZE |
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SPI_NFI_CUS_SEC_SIZE_EN,
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FIELD_PREP(SPI_NFI_CUS_SEC_SIZE, val) |
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SPI_NFI_CUS_SEC_SIZE_EN);
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if (err)
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goto error_dma_mode_off;
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@ -831,8 +908,16 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
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if (err)
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goto error_dma_unmap;
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val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
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as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
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/*
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* Setup transfer length
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* ---------------------
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* The following rule MUST be met:
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* transfer_length =
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* = NFI_SNF_MISC_CTL2.write_data_byte_number =
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* = NFI_CON.sector_number * NFI_SECCUS.custom_sector_size
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*/
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val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
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val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM, val);
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err = regmap_update_bits(as_ctrl->regmap_nfi,
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REG_SPI_NFI_SNF_MISC_CTL2,
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SPI_NFI_PROG_LOAD_BYTE_NUM, val);
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@ -857,22 +942,6 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
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if (err)
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goto error_dma_unmap;
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err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_READ_MODE);
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if (err)
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goto error_dma_unmap;
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err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_OPMODE,
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FIELD_PREP(SPI_NFI_OPMODE, 3));
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if (err)
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goto error_dma_unmap;
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err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
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SPI_NFI_DMA_MODE);
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if (err)
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goto error_dma_unmap;
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err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
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if (err)
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goto error_dma_unmap;
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