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arm64: dts: qcom: sc7280: Add DT nodes for the TBUs

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Add the device-tree nodes for the TBUs (translation buffer units) that
are present on the sc7280 platforms. The TBUs can be used debug the
kernel and provide additional information when a context faults occur.

Describe all the registers, clocks, interconnects and power-domain
resources that are needed for each of the TBUs.

Signed-off-by: Georgi Djakov <quic_c_gdjako@quicinc.com>
Link: https://lore.kernel.org/r/20240417133731.2055383-8-quic_c_gdjako@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Georgi Djakov 2024-04-17 06:37:31 -07:00 committed by Bjorn Andersson
parent 7bb38c20f2
commit d1f2b41e96
1 changed files with 89 additions and 0 deletions
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89
arch/arm64/boot/dts/qcom/sc7280.dtsi
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@ -2990,6 +2990,18 @@ adreno_smmu: iommu@3da0000 {
dma-coherent;
};
gfx_0_tbu: tbu@3dd9000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x3dd9000 0x0 0x1000>;
qcom,stream-id-range = <&adreno_smmu 0x0 0x400>;
};
gfx_1_tbu: tbu@3ddd000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x3ddd000 0x0 0x1000>;
qcom,stream-id-range = <&adreno_smmu 0x400 0x400>;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sc7280-mpss-pas";
reg = <0 0x04080000 0 0x10000>;
@ -5862,6 +5874,83 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
};
anoc_1_tbu: tbu@151dd000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151dd000 0x0 0x1000>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
qcom,stream-id-range = <&apps_smmu 0x0 0x400>;
};
anoc_2_tbu: tbu@151e1000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151e1000 0x0 0x1000>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
qcom,stream-id-range = <&apps_smmu 0x400 0x400>;
};
mnoc_hf_0_tbu: tbu@151e5000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151e5000 0x0 0x1000>;
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
qcom,stream-id-range = <&apps_smmu 0x800 0x400>;
};
mnoc_hf_1_tbu: tbu@151e9000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151e9000 0x0 0x1000>;
interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
qcom,stream-id-range = <&apps_smmu 0xc00 0x400>;
};
compute_dsp_1_tbu: tbu@151ed000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151ed000 0x0 0x1000>;
interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
qcom,stream-id-range = <&apps_smmu 0x1000 0x400>;
};
compute_dsp_0_tbu: tbu@151f1000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151f1000 0x0 0x1000>;
interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
qcom,stream-id-range = <&apps_smmu 0x1400 0x400>;
};
adsp_tbu: tbu@151f5000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151f5000 0x0 0x1000>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
qcom,stream-id-range = <&apps_smmu 0x1800 0x400>;
};
anoc_1_pcie_tbu: tbu@151f9000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151f9000 0x0 0x1000>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
};
mnoc_sf_0_tbu: tbu@151fd000 {
compatible = "qcom,sc7280-tbu";
reg = <0x0 0x151fd000 0x0 0x1000>;
interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
qcom,stream-id-range = <&apps_smmu 0x2000 0x400>;
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0 0x17a00000 0 0x10000>, /* GICD */