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drm/i915/gvt: handle fence reg access during GPU reset
Lots of reduntant log info will be printed out during GPU reset, including accessing untracked mmio register and fence register, variable disable_warn_untrack is added previously to handle the situation, but the accessing of fence register is ignored in the previously patch, so add it back. Besides, set the variable disable_warn_untrack to the defalut value after GPU reset is finished. Signed-off-by: Zhao, Xinda <xinda.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -173,16 +173,19 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
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* pv_info first, we treat guest not supporting GVT,
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* and we will let vgpu enter failsafe mode.
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*/
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if (!vgpu->pv_notified) {
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if (!vgpu->pv_notified)
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enter_failsafe_mode(vgpu,
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GVT_FAILSAFE_UNSUPPORTED_GUEST);
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return -EINVAL;
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if (!vgpu->mmio.disable_warn_untrack) {
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gvt_err("vgpu%d: found oob fence register access\n",
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vgpu->id);
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gvt_err("vgpu%d: total fence %d, access fence %d\n",
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vgpu->id, vgpu_fence_sz(vgpu),
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fence_num);
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}
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gvt_err("vgpu%d: found oob fence register access\n",
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vgpu->id);
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gvt_err("vgpu%d: total fence num %d access fence num %d\n",
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vgpu->id, vgpu_fence_sz(vgpu), fence_num);
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memset(p_data, 0, bytes);
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return -EINVAL;
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}
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return 0;
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}
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@ -384,6 +384,8 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu)
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/* set the bit 0:2(Core C-State ) to C0 */
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vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
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vgpu->mmio.disable_warn_untrack = false;
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}
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/**
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