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drm/amdgpu: Remove is_idle (non trivial functions)

Browse Source 
The is_idle method on amd_ip_funcs is never called.
Remove the implementations that actually do something.
In most cases the same code has been duplicated in
the wait_for_idle method implementations that is still used.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dr. David Alan Gilbert 2026-08-15 19:00:32 +01:00 committed by Alex Deucher
parent ecaca20be8
commit d1b8ffe14a
28 changed files with 0 additions and 414 deletions
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12
drivers/gpu/drm/amd/amdgpu/cik_ih.c
View File

@ -357,17 +357,6 @@ static int cik_ih_resume(struct amdgpu_ip_block *ip_block)
return cik_ih_hw_init(ip_block);
}
static bool cik_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
return false;
return true;
}
static int cik_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -435,7 +424,6 @@ static const struct amd_ip_funcs cik_ih_ip_funcs = {
.hw_fini = cik_ih_hw_fini,
.suspend = cik_ih_suspend,
.resume = cik_ih_resume,
.is_idle = cik_ih_is_idle,
.wait_for_idle = cik_ih_wait_for_idle,
.soft_reset = cik_ih_soft_reset,
.set_clockgating_state = cik_ih_set_clockgating_state,

12
drivers/gpu/drm/amd/amdgpu/cz_ih.c
View File

@ -351,17 +351,6 @@ static int cz_ih_resume(struct amdgpu_ip_block *ip_block)
return cz_ih_hw_init(ip_block);
}
static bool cz_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
return false;
return true;
}
static int cz_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -431,7 +420,6 @@ static const struct amd_ip_funcs cz_ih_ip_funcs = {
.hw_fini = cz_ih_hw_fini,
.suspend = cz_ih_suspend,
.resume = cz_ih_resume,
.is_idle = cz_ih_is_idle,
.wait_for_idle = cz_ih_wait_for_idle,
.soft_reset = cz_ih_soft_reset,
.set_clockgating_state = cz_ih_set_clockgating_state,

12
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
View File

@ -7611,17 +7611,6 @@ static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v10_0_hw_init(ip_block);
}
static bool gfx_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
return false;
else
return true;
}
static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned int i;
@ -9821,7 +9810,6 @@ static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.hw_fini = gfx_v10_0_hw_fini,
.suspend = gfx_v10_0_suspend,
.resume = gfx_v10_0_resume,
.is_idle = gfx_v10_0_is_idle,
.wait_for_idle = gfx_v10_0_wait_for_idle,
.soft_reset = gfx_v10_0_soft_reset,
.set_clockgating_state = gfx_v10_0_set_clockgating_state,

12
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
View File

@ -5099,17 +5099,6 @@ static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v11_0_hw_init(ip_block);
}
static bool gfx_v11_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
return false;
else
return true;
}
static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -7057,7 +7046,6 @@ static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
.hw_fini = gfx_v11_0_hw_fini,
.suspend = gfx_v11_0_suspend,
.resume = gfx_v11_0_resume,
.is_idle = gfx_v11_0_is_idle,
.wait_for_idle = gfx_v11_0_wait_for_idle,
.soft_reset = gfx_v11_0_soft_reset,
.set_clockgating_state = gfx_v11_0_set_clockgating_state,

12
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
View File

@ -3929,17 +3929,6 @@ static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v12_0_hw_init(ip_block);
}
static bool gfx_v12_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
GRBM_STATUS, GUI_ACTIVE))
return false;
else
return true;
}
static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -5343,7 +5332,6 @@ static const struct amd_ip_funcs gfx_v12_0_ip_funcs = {
.hw_fini = gfx_v12_0_hw_fini,
.suspend = gfx_v12_0_suspend,
.resume = gfx_v12_0_resume,
.is_idle = gfx_v12_0_is_idle,
.wait_for_idle = gfx_v12_0_wait_for_idle,
.set_clockgating_state = gfx_v12_0_set_clockgating_state,
.set_powergating_state = gfx_v12_0_set_powergating_state,

11
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@ -4511,16 +4511,6 @@ static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block)
return gfx_v7_0_hw_init(ip_block);
}
static bool gfx_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
return false;
else
return true;
}
static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -4951,7 +4941,6 @@ static const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
.hw_fini = gfx_v7_0_hw_fini,
.suspend = gfx_v7_0_suspend,
.resume = gfx_v7_0_resume,
.is_idle = gfx_v7_0_is_idle,
.wait_for_idle = gfx_v7_0_wait_for_idle,
.soft_reset = gfx_v7_0_soft_reset,
.set_clockgating_state = gfx_v7_0_set_clockgating_state,

13
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
View File

@ -1221,18 +1221,6 @@ static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
return false;
return true;
}
static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned int i;
@ -1592,7 +1580,6 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
.hw_fini = gmc_v8_0_hw_fini,
.suspend = gmc_v8_0_suspend,
.resume = gmc_v8_0_resume,
.is_idle = gmc_v8_0_is_idle,
.wait_for_idle = gmc_v8_0_wait_for_idle,
.set_clockgating_state = gmc_v8_0_set_clockgating_state,
.set_powergating_state = gmc_v8_0_set_powergating_state,

12
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
View File

@ -345,17 +345,6 @@ static int iceland_ih_resume(struct amdgpu_ip_block *ip_block)
return iceland_ih_hw_init(ip_block);
}
static bool iceland_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
return false;
return true;
}
static int iceland_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -423,7 +412,6 @@ static const struct amd_ip_funcs iceland_ih_ip_funcs = {
.hw_fini = iceland_ih_hw_fini,
.suspend = iceland_ih_suspend,
.resume = iceland_ih_resume,
.is_idle = iceland_ih_is_idle,
.wait_for_idle = iceland_ih_wait_for_idle,
.soft_reset = iceland_ih_soft_reset,
.set_clockgating_state = iceland_ih_set_clockgating_state,

13
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
View File

@ -919,18 +919,6 @@ static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block)
return sdma_v2_4_hw_init(ip_block);
}
static bool sdma_v2_4_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
SRBM_STATUS2__SDMA1_BUSY_MASK))
return false;
return true;
}
static int sdma_v2_4_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -1112,7 +1100,6 @@ static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
.hw_fini = sdma_v2_4_hw_fini,
.suspend = sdma_v2_4_suspend,
.resume = sdma_v2_4_resume,
.is_idle = sdma_v2_4_is_idle,
.wait_for_idle = sdma_v2_4_wait_for_idle,
.soft_reset = sdma_v2_4_soft_reset,
.set_clockgating_state = sdma_v2_4_set_clockgating_state,

13
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
View File

@ -1209,18 +1209,6 @@ static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v3_0_hw_init(ip_block);
}
static bool sdma_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS2);
if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
SRBM_STATUS2__SDMA1_BUSY_MASK))
return false;
return true;
}
static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -1492,7 +1480,6 @@ static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
.hw_fini = sdma_v3_0_hw_fini,
.suspend = sdma_v3_0_suspend,
.resume = sdma_v3_0_resume,
.is_idle = sdma_v3_0_is_idle,
.wait_for_idle = sdma_v3_0_wait_for_idle,
.soft_reset = sdma_v3_0_soft_reset,
.set_clockgating_state = sdma_v3_0_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
View File

@ -2027,21 +2027,6 @@ static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v4_0_hw_init(ip_block);
}
static bool sdma_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG);
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i, j;
@ -2412,7 +2397,6 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
.hw_fini = sdma_v4_0_hw_fini,
.suspend = sdma_v4_0_suspend,
.resume = sdma_v4_0_resume,
.is_idle = sdma_v4_0_is_idle,
.wait_for_idle = sdma_v4_0_wait_for_idle,
.soft_reset = sdma_v4_0_soft_reset,
.set_clockgating_state = sdma_v4_0_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
View File

@ -1627,21 +1627,6 @@ static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block)
return sdma_v4_4_2_hw_init(ip_block);
}
static bool sdma_v4_4_2_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i, j;
@ -2118,7 +2103,6 @@ const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
.hw_fini = sdma_v4_4_2_hw_fini,
.suspend = sdma_v4_4_2_suspend,
.resume = sdma_v4_4_2_resume,
.is_idle = sdma_v4_4_2_is_idle,
.wait_for_idle = sdma_v4_4_2_wait_for_idle,
.soft_reset = sdma_v4_4_2_soft_reset,
.set_clockgating_state = sdma_v4_4_2_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
View File

@ -1501,21 +1501,6 @@ static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v5_0_hw_init(ip_block);
}
static bool sdma_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -1916,7 +1901,6 @@ static const struct amd_ip_funcs sdma_v5_0_ip_funcs = {
.hw_fini = sdma_v5_0_hw_fini,
.suspend = sdma_v5_0_suspend,
.resume = sdma_v5_0_resume,
.is_idle = sdma_v5_0_is_idle,
.wait_for_idle = sdma_v5_0_wait_for_idle,
.soft_reset = sdma_v5_0_soft_reset,
.set_clockgating_state = sdma_v5_0_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
View File

@ -1417,21 +1417,6 @@ static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block)
return sdma_v5_2_hw_init(ip_block);
}
static bool sdma_v5_2_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -1921,7 +1906,6 @@ static const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
.hw_fini = sdma_v5_2_hw_fini,
.suspend = sdma_v5_2_suspend,
.resume = sdma_v5_2_resume,
.is_idle = sdma_v5_2_is_idle,
.wait_for_idle = sdma_v5_2_wait_for_idle,
.soft_reset = sdma_v5_2_soft_reset,
.set_clockgating_state = sdma_v5_2_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
View File

@ -1489,21 +1489,6 @@ static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v6_0_hw_init(ip_block);
}
static bool sdma_v6_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -1727,7 +1712,6 @@ const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
.hw_fini = sdma_v6_0_hw_fini,
.suspend = sdma_v6_0_suspend,
.resume = sdma_v6_0_resume,
.is_idle = sdma_v6_0_is_idle,
.wait_for_idle = sdma_v6_0_wait_for_idle,
.soft_reset = sdma_v6_0_soft_reset,
.set_clockgating_state = sdma_v6_0_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
View File

@ -1443,21 +1443,6 @@ static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block)
return sdma_v7_0_hw_init(ip_block);
}
static bool sdma_v7_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32(sdma_v7_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -1659,7 +1644,6 @@ const struct amd_ip_funcs sdma_v7_0_ip_funcs = {
.hw_fini = sdma_v7_0_hw_fini,
.suspend = sdma_v7_0_suspend,
.resume = sdma_v7_0_resume,
.is_idle = sdma_v7_0_is_idle,
.wait_for_idle = sdma_v7_0_wait_for_idle,
.soft_reset = sdma_v7_0_soft_reset,
.set_clockgating_state = sdma_v7_0_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
View File

@ -1404,21 +1404,6 @@ static int sdma_v7_1_resume(struct amdgpu_ip_block *ip_block)
return sdma_v7_1_hw_init(ip_block);
}
static bool sdma_v7_1_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 i;
for (i = 0; i < adev->sdma.num_instances; i++) {
u32 tmp = RREG32(sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_STATUS_REG));
if (!(tmp & SDMA0_SDMA_STATUS_REG__IDLE_MASK))
return false;
}
return true;
}
static int sdma_v7_1_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i, j;
@ -1624,7 +1609,6 @@ const struct amd_ip_funcs sdma_v7_1_ip_funcs = {
.hw_fini = sdma_v7_1_hw_fini,
.suspend = sdma_v7_1_suspend,
.resume = sdma_v7_1_resume,
.is_idle = sdma_v7_1_is_idle,
.wait_for_idle = sdma_v7_1_wait_for_idle,
.soft_reset = sdma_v7_1_soft_reset,
.set_clockgating_state = sdma_v7_1_set_clockgating_state,

12
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
View File

@ -363,17 +363,6 @@ static int tonga_ih_resume(struct amdgpu_ip_block *ip_block)
return tonga_ih_hw_init(ip_block);
}
static bool tonga_ih_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
u32 tmp = RREG32(mmSRBM_STATUS);
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
return false;
return true;
}
static int tonga_ih_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -442,7 +431,6 @@ static const struct amd_ip_funcs tonga_ih_ip_funcs = {
.hw_fini = tonga_ih_hw_fini,
.suspend = tonga_ih_suspend,
.resume = tonga_ih_resume,
.is_idle = tonga_ih_is_idle,
.wait_for_idle = tonga_ih_wait_for_idle,
.soft_reset = tonga_ih_soft_reset,
.set_clockgating_state = tonga_ih_set_clockgating_state,

8
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
View File

@ -789,13 +789,6 @@ static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block)
return uvd_v3_1_hw_init(ip_block);
}
static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
static int uvd_v3_1_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -843,7 +836,6 @@ static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
.prepare_suspend = uvd_v3_1_prepare_suspend,
.suspend = uvd_v3_1_suspend,
.resume = uvd_v3_1_resume,
.is_idle = uvd_v3_1_is_idle,
.wait_for_idle = uvd_v3_1_wait_for_idle,
.soft_reset = uvd_v3_1_soft_reset,
.set_clockgating_state = uvd_v3_1_set_clockgating_state,

8
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
View File

@ -664,13 +664,6 @@ static void uvd_v4_2_set_dcm(struct amdgpu_device *adev,
WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
}
static bool uvd_v4_2_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
static int uvd_v4_2_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -768,7 +761,6 @@ static const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
.prepare_suspend = uvd_v4_2_prepare_suspend,
.suspend = uvd_v4_2_suspend,
.resume = uvd_v4_2_resume,
.is_idle = uvd_v4_2_is_idle,
.wait_for_idle = uvd_v4_2_wait_for_idle,
.soft_reset = uvd_v4_2_soft_reset,
.set_clockgating_state = uvd_v4_2_set_clockgating_state,

8
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
View File

@ -580,13 +580,6 @@ static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
}
}
static bool uvd_v5_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
}
static int uvd_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
unsigned i;
@ -869,7 +862,6 @@ static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
.prepare_suspend = uvd_v5_0_prepare_suspend,
.suspend = uvd_v5_0_suspend,
.resume = uvd_v5_0_resume,
.is_idle = uvd_v5_0_is_idle,
.wait_for_idle = uvd_v5_0_wait_for_idle,
.soft_reset = uvd_v5_0_soft_reset,
.set_clockgating_state = uvd_v5_0_set_clockgating_state,

16
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
View File

@ -2216,21 +2216,6 @@ static int vcn_v3_0_reset(struct amdgpu_vcn_inst *vinst)
return vcn_v3_0_start(vinst);
}
static bool vcn_v3_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE);
}
return ret;
}
static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
@ -2376,7 +2361,6 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = {
.hw_fini = vcn_v3_0_hw_fini,
.suspend = vcn_v3_0_suspend,
.resume = vcn_v3_0_resume,
.is_idle = vcn_v3_0_is_idle,
.wait_for_idle = vcn_v3_0_wait_for_idle,
.set_clockgating_state = vcn_v3_0_set_clockgating_state,
.set_powergating_state = vcn_set_powergating_state,

23
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
View File

@ -2091,28 +2091,6 @@ static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
}
}
/**
* vcn_v4_0_is_idle - check VCN block is idle
*
* @ip_block: Pointer to the amdgpu_ip_block structure
*
* Check whether VCN block is idle
*/
static bool vcn_v4_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
}
return ret;
}
/**
* vcn_v4_0_wait_for_idle - wait for VCN block idle
*
@ -2304,7 +2282,6 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
.hw_fini = vcn_v4_0_hw_fini,
.suspend = vcn_v4_0_suspend,
.resume = vcn_v4_0_resume,
.is_idle = vcn_v4_0_is_idle,
.wait_for_idle = vcn_v4_0_wait_for_idle,
.set_clockgating_state = vcn_v4_0_set_clockgating_state,
.set_powergating_state = vcn_set_powergating_state,

21
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
View File

@ -1840,26 +1840,6 @@ static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev)
}
}
/**
* vcn_v4_0_3_is_idle - check VCN block is idle
*
* @ip_block: Pointer to the amdgpu_ip_block structure
*
* Check whether VCN block is idle
*/
static bool vcn_v4_0_3_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) ==
UVD_STATUS__IDLE);
}
return ret;
}
/**
* vcn_v4_0_3_wait_for_idle - wait for VCN block idle
*
@ -2049,7 +2029,6 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
.hw_fini = vcn_v4_0_3_hw_fini,
.suspend = vcn_v4_0_3_suspend,
.resume = vcn_v4_0_3_resume,
.is_idle = vcn_v4_0_3_is_idle,
.wait_for_idle = vcn_v4_0_3_wait_for_idle,
.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
.set_powergating_state = vcn_set_powergating_state,

23
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
View File

@ -1531,28 +1531,6 @@ static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev)
}
}
/**
* vcn_v4_0_5_is_idle - check VCN block is idle
*
* @ip_block: Pointer to the amdgpu_ip_block structure
*
* Check whether VCN block is idle
*/
static bool vcn_v4_0_5_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
}
return ret;
}
/**
* vcn_v4_0_5_wait_for_idle - wait for VCN block idle
*
@ -1707,7 +1685,6 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
.hw_fini = vcn_v4_0_5_hw_fini,
.suspend = vcn_v4_0_5_suspend,
.resume = vcn_v4_0_5_resume,
.is_idle = vcn_v4_0_5_is_idle,
.wait_for_idle = vcn_v4_0_5_wait_for_idle,
.set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
.set_powergating_state = vcn_set_powergating_state,

23
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
View File

@ -1317,28 +1317,6 @@ static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev)
}
}
/**
* vcn_v5_0_0_is_idle - check VCN block is idle
*
* @ip_block: Pointer to the amdgpu_ip_block structure
*
* Check whether VCN block is idle
*/
static bool vcn_v5_0_0_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
}
return ret;
}
/**
* vcn_v5_0_0_wait_for_idle - wait for VCN block idle
*
@ -1493,7 +1471,6 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
.hw_fini = vcn_v5_0_0_hw_fini,
.suspend = vcn_v5_0_0_suspend,
.resume = vcn_v5_0_0_resume,
.is_idle = vcn_v5_0_0_is_idle,
.wait_for_idle = vcn_v5_0_0_wait_for_idle,
.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
.set_powergating_state = vcn_set_powergating_state,

19
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
View File

@ -1483,24 +1483,6 @@ static void vcn_v5_0_1_set_unified_ring_funcs(struct amdgpu_device *adev)
}
}
/**
* vcn_v5_0_1_is_idle - check VCN block is idle
*
* @ip_block: Pointer to the amdgpu_ip_block structure
*
* Check whether VCN block is idle
*/
static bool vcn_v5_0_1_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
/**
* vcn_v5_0_1_wait_for_idle - wait for VCN block idle
*
@ -1672,7 +1654,6 @@ static const struct amd_ip_funcs vcn_v5_0_1_ip_funcs = {
.hw_fini = vcn_v5_0_1_hw_fini,
.suspend = vcn_v5_0_1_suspend,
.resume = vcn_v5_0_1_resume,
.is_idle = vcn_v5_0_1_is_idle,
.wait_for_idle = vcn_v5_0_1_wait_for_idle,
.soft_reset = NULL,
.set_clockgating_state = vcn_v5_0_1_set_clockgating_state,

19
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c
View File

@ -1043,24 +1043,6 @@ static void vcn_v5_0_2_set_unified_ring_funcs(struct amdgpu_device *adev)
}
}
/**
* vcn_v5_0_2_is_idle - check VCN block is idle
*
* @ip_block: Pointer to the amdgpu_ip_block structure
*
* Check whether VCN block is idle
*/
static bool vcn_v5_0_2_is_idle(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, ret = 1;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE);
return ret;
}
/**
* vcn_v5_0_2_wait_for_idle - wait for VCN block idle
*
@ -1233,7 +1215,6 @@ static const struct amd_ip_funcs vcn_v5_0_2_ip_funcs = {
.hw_fini = vcn_v5_0_2_hw_fini,
.suspend = vcn_v5_0_2_suspend,
.resume = vcn_v5_0_2_resume,
.is_idle = vcn_v5_0_2_is_idle,
.wait_for_idle = vcn_v5_0_2_wait_for_idle,
.soft_reset = NULL,
.set_clockgating_state = vcn_v5_0_2_set_clockgating_state,