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camera: add support gc0329/s5k5ca/sp0838 sensor driver
This commit is contained in:
ddl
parent
34bcc3db74
commit
d19e195105
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@ -64,6 +64,10 @@
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#define RK29_CAM_SENSOR_HI253 hi253
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#define RK29_CAM_SENSOR_HI704 hi704
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#define RK29_CAM_SENSOR_NT99250 nt99250
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#define RK29_CAM_SENSOR_SP0838 sp0838
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#define RK29_CAM_SENSOR_GC0329 gc0329
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#define RK29_CAM_SENSOR_S5K5CA s5k5ca
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#define RK29_CAM_SENSOR_NAME_OV7675 "ov7675"
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#define RK29_CAM_SENSOR_NAME_OV9650 "ov9650"
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@ -90,6 +94,9 @@
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#define RK29_CAM_SENSOR_NAME_HI253 "hi253"
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#define RK29_CAM_SENSOR_NAME_HI704 "hi704"
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#define RK29_CAM_SENSOR_NAME_NT99250 "nt99250"
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#define RK29_CAM_SENSOR_NAME_SP0838 "sp0838"
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#define RK29_CAM_SENSOR_NAME_GC0329 "gc0329"
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#define RK29_CAM_SENSOR_NAME_S5K5CA "s5k5ca"
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#define ov7675_FULL_RESOLUTION 0x30000 // 0.3 megapixel
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#define ov9650_FULL_RESOLUTION 0x130000 // 1.3 megapixel
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@ -115,6 +122,9 @@
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#define hi253_FULL_RESOLUTION 0x200000 // 2 megapixel
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#define hi704_FULL_RESOLUTION 0x30000 // 0.3 megapixel
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#define nt99250_FULL_RESOLUTION 0x200000 // 2 megapixel
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#define sp0838_FULL_RESOLUTION 0x30000 // 0.3 megapixel
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#define gc0329_FULL_RESOLUTION 0x30000 // 0.3 megapixel
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#define s5k5ca_FULL_RESOLUTION 0x300000 // 3 megapixel
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/*---------------- Camera Sensor Must Define Macro End ------------------------*/
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@ -1217,6 +1217,40 @@ config NT99250_USER_DEFINED_SERIES
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bool "NT99250 user defined init series"
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default n
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config SOC_CAMERA_GC0329
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tristate "gc0329 camera support for rockchip"
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depends on SOC_CAMERA && I2C
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help
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This is a gc0329 camera driver for rockchip
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config GC0329_USER_DEFINED_SERIES
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depends on SOC_CAMERA_GC0329
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bool "GC0329 user defined init series"
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default n
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config SOC_CAMERA_S5K5CA
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tristate "s5k5ca camera support for rockchip"
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depends on SOC_CAMERA && I2C
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help
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This is a s5k5ca camera driver for rockchip
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config S5K5CA_USER_DEFINED_SERIES
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depends on SOC_CAMERA_S5K5CA
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bool "s5k5ca user defined init series"
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default n
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config SOC_CAMERA_SP0838
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tristate "sp0838 camera support for rockchip"
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depends on SOC_CAMERA && I2C
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help
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This is a sp0838 camera driver for rockchip
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config S5K5CA_USER_DEFINED_SERIES
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depends on SOC_CAMERA_SP0838
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bool "sp0838 user defined init series"
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default n
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config SOC_CAMERA_OV9640
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tristate "ov9640 camera support"
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depends on SOC_CAMERA && I2C
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@ -112,6 +112,9 @@ obj-$(CONFIG_SOC_CAMERA_SID130B) += sid130B.o
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obj-$(CONFIG_SOC_CAMERA_HI253) += hi253.o
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obj-$(CONFIG_SOC_CAMERA_HI704) += hi704.o
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obj-$(CONFIG_SOC_CAMERA_NT99250) += nt99250.o
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obj-$(CONFIG_SOC_CAMERA_GC0329) += gc0329.o
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obj-$(CONFIG_SOC_CAMERA_SP0838) += sp0838.o
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obj-$(CONFIG_SOC_CAMERA_S5K5CA) += s5k5ca.o
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# And now the v4l2 drivers:
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obj-$(CONFIG_VIDEO_BT848) += bt8xx/
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3046
drivers/media/video/gc0329.c
Executable file
3046
drivers/media/video/gc0329.c
Executable file
File diff suppressed because it is too large
Load Diff
6093
drivers/media/video/s5k5ca.c
Executable file
6093
drivers/media/video/s5k5ca.c
Executable file
File diff suppressed because it is too large
Load Diff
242
drivers/media/video/s5k5ca.h
Executable file
242
drivers/media/video/s5k5ca.h
Executable file
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@ -0,0 +1,242 @@
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#ifndef __S5K6AA_H__
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#define __S5K6AA_H__
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struct reginfo
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{
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u16 reg;
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u16 val;
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};
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/* General purpose section */
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#define REG_TC_GP_SpecialEffects 0x01EE
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#define REG_TC_GP_EnablePreview 0x01F0
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#define REG_TC_GP_EnablePreviewChanged 0x01F2
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#define REG_TC_GP_EnableCapture 0x01F4
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#define REG_TC_GP_EnableCaptureChanged 0x01F6
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#define REG_TC_GP_NewConfigSync 0x01F8
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#define REG_TC_GP_PrevReqInputWidth 0x01FA
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#define REG_TC_GP_PrevReqInputHeight 0x01FC
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#define REG_TC_GP_PrevInputWidthOfs 0x01FE
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#define REG_TC_GP_PrevInputHeightOfs 0x0200
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#define REG_TC_GP_CapReqInputWidth 0x0202
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#define REG_TC_GP_CapReqInputHeight 0x0204
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#define REG_TC_GP_CapInputWidthOfs 0x0206
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#define REG_TC_GP_CapInputHeightOfs 0x0208
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#define REG_TC_GP_PrevZoomReqInputWidth 0x020A
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#define REG_TC_GP_PrevZoomReqInputHeight 0x020C
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#define REG_TC_GP_PrevZoomReqInputWidthOfs 0x020E
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#define REG_TC_GP_PrevZoomReqInputHeightOfs 0x0210
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#define REG_TC_GP_CapZoomReqInputWidth 0x0212
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#define REG_TC_GP_CapZoomReqInputHeight 0x0214
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#define REG_TC_GP_CapZoomReqInputWidthOfs 0x0216
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#define REG_TC_GP_CapZoomReqInputHeightOfs 0x0218
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#define REG_TC_GP_InputsChangeRequest 0x021A
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#define REG_TC_GP_ActivePrevConfig 0x021C
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#define REG_TC_GP_PrevConfigChanged 0x021E
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#define REG_TC_GP_PrevOpenAfterChange 0x0220
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#define REG_TC_GP_ErrorPrevConfig 0x0222
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#define REG_TC_GP_ActiveCapConfig 0x0224
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#define REG_TC_GP_CapConfigChanged 0x0226
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#define REG_TC_GP_ErrorCapConfig 0x0228
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#define REG_TC_GP_PrevConfigBypassChanged 0x022A
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#define REG_TC_GP_CapConfigBypassChanged 0x022C
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#define REG_TC_GP_SleepMode 0x022E
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#define REG_TC_GP_SleepModeChanged 0x0230
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#define REG_TC_GP_SRA_AddLow 0x0232
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#define REG_TC_GP_SRA_AddHigh 0x0234
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#define REG_TC_GP_SRA_AccessType 0x0236
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#define REG_TC_GP_SRA_Changed 0x0238
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#define REG_TC_GP_PrevMinFrTimeMsecMult10 0x023A
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#define REG_TC_GP_PrevOutKHzRate 0x023C
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#define REG_TC_GP_CapMinFrTimeMsecMult10 0x023E
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#define REG_TC_GP_CapOutKHzRate 0x0240
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/* Image property control section */
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#define REG_TC_UserBrightness 0x01E4
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#define REG_TC_UserContrast 0x01E6
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#define REG_TC_UserSaturation 0x01E8
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#define REG_TC_UserSharpBlur 0x01EA
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#define REG_TC_UserGlamour 0x01EC
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/* Flash control section */
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#define REG_TC_FLS_Mode 0x03B6
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#define REG_TC_FLS_Threshold 0x03B8
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#define REG_TC_FLS_Polarity 0x03BA
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#define REG_TC_FLS_XenonMode 0x03BC
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#define REG_TC_FLS_XenonPreFlashCnt 0x03BE
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/* Extended image property control section */
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#define REG_SF_USER_LeiLow 0x03C0
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#define REG_SF_USER_LeiHigh 0x03C2
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#define REG_SF_USER_LeiChanged 0x03C4
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#define REG_SF_USER_Exposure 0x03C6
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#define REG_SF_USER_ExposureChanged 0x03CA
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#define REG_SF_USER_TotalGain 0x03CC
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#define REG_SF_USER_TotalGainChanged 0x03CE
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#define REG_SF_USER_Rgain 0x03D0
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#define REG_SF_USER_RgainChanged 0x03D2
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#define REG_SF_USER_Ggain 0x03D4
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#define REG_SF_USER_GgainChanged 0x03D6
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#define REG_SF_USER_Bgain 0x03D8
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#define REG_SF_USER_BgainChanged 0x03DA
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#define REG_SF_USER_FlickerQuant 0x03DC
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#define REG_SF_USER_FlickerQuantChanged 0x03DE
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#define REG_SF_USER_GASRAlphaVal 0x03E0
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#define REG_SF_USER_GASRAlphaChanged 0x03E2
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#define REG_SF_USER_GASGAlphaVal 0x03E4
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#define REG_SF_USER_GASGAlphaChanged 0x03E6
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#define REG_SF_USER_GASBAlphaVal 0x03E8
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#define REG_SF_USER_GASBAlphaChanged 0x03EA
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#define REG_SF_USER_DbgIdx 0x03EC
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#define REG_SF_USER_DbgVal 0x03EE
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#define REG_SF_USER_DbgChanged 0x03F0
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#define REG_SF_USER_aGain 0x03F2
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#define REG_SF_USER_aGainChanged 0x03F4
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#define REG_SF_USER_dGain 0x03F6
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#define REG_SF_USER_dGainChanged 0x03F8
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/* Output interface control section */
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#define REG_TC_OIF_EnMipiLanes 0x03FA
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#define REG_TC_OIF_EnPackets 0x03FC
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#define REG_TC_OIF_CfgChanged 0x03FE
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/* Debug control section */
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#define REG_TC_DBG_AutoAlgEnBits 0x0400
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#define REG_TC_DBG_IspBypass 0x0402
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#define REG_TC_DBG_ReInitCmd 0x0404
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/* Version information section */
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#define REG_FWdate 0x012C
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#define REG_FWapiVer 0x012E
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#define REG_FWrevision 0x0130
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#define REG_FWpid 0x0132
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#define REG_FWprjName 0x0134
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#define REG_FWcompDate 0x0140
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#define REG_FWSFC_VER 0x014C
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#define REG_FWTC_VER 0x014E
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#define REG_FWrealImageLine 0x0150
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#define REG_FWsenId 0x0152
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#define REG_FWusDevIdQaVersion 0x0154
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#define REG_FWusFwCompilationBits 0x0156
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#define REG_ulSVNrevision 0x0158
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#define REG_SVNpathRomAddress 0x015C
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#define REG_TRAP_N_PATCH_START_ADD 0x1B00
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#define setot_usForceClocksSettings 0x0AEA
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#define setot_usConfigClocksSettings 0x0AEC
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#define REG_0TC_CCFG_uCaptureMode 0x030C
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#define REG_0TC_CCFG_usWidth 0x030E
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#define REG_0TC_CCFG_usHeight 0x0310
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#define REG_0TC_CCFG_Format 0x0312
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#define REG_0TC_CCFG_usMaxOut4KHzRate 0x0314
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#define REG_0TC_CCFG_usMinOut4KHzRate 0x0316
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#define REG_0TC_CCFG_PVIMask 0x0318
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#define REG_0TC_CCFG_uClockInd 0x031A
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#define REG_0TC_CCFG_usFrTimeType 0x031C
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#define REG_0TC_CCFG_FrRateQualityType 0x031E
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#define REG_0TC_CCFG_usMaxFrTimeMsecMult10 0x0320
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#define REG_0TC_CCFG_usMinFrTimeMsecMult10 0x0322
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#define lt_uMaxAnGain2 0x049A
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#define REG_TC_GP_ActivePrevConfig 0x021C
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#define REG_TC_GP_PrevOpenAfterChange 0x0220
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#define REG_TC_GP_NewConfigSync 0x01F8
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#define REG_TC_GP_PrevConfigChanged 0x021E
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#define REG_TC_GP_ActiveCapConfig 0x0224
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#define REG_TC_GP_CapConfigChanged 0x0226
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#define REG_TC_GP_EnableCapture 0x01F4
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#define REG_TC_GP_EnableCaptureChanged 0x01F6
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#define lt_uMaxExp1 0x0488 // 0x9C40
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#define lt_uMaxExp2 0x048C // 0xE848
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#define lt_uCapMaxExp1 0x0490 // 0x9C40
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#define lt_uCapMaxExp2 0x0494 // 0xE848
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#define lt_uMaxDigGain 0x049C // 0x0200
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#define lt_uMaxAnGain1 0x0498 // 0x0200
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#define lt_uMaxAnGain2 0x049A // 0x0500
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#define REG_1TC_CCFG_uCaptureMode 0x032E // 0x0000
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#define REG_1TC_CCFG_Cfg 0x0330 // 0x0500
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#define REG_1TC_CCFG_usWidth 0x0330 // 0x0500
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#define REG_1TC_CCFG_usHeight 0x0332 // 0x03C0
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#define REG_1TC_CCFG_Format 0x0334 // 0x0009
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#define REG_1TC_CCFG_usMaxOut4KHzRate 0x0336 // 0x1770
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#define REG_1TC_CCFG_usMinOut4KHzRate 0x0338 // 0x05DC
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#define REG_1TC_CCFG_PVIMask 0x033A // 0x0042
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#define REG_1TC_CCFG_uClockInd 0x033C // 0x0000
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#define REG_1TC_CCFG_usFrTimeType 0x033E // 0x0000
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#define REG_1TC_CCFG_FrRateQualityType 0x0340 // 0x0002
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#define REG_1TC_CCFG_usMaxFrTimeMsecMult10 0x0342 // 0x1964
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#define REG_1TC_CCFG_usMinFrTimeMsecMult10 0x0344 // 0x0000
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#define REG_1TC_CCFG_sSaturation 0x0346 // 0x0000
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#define REG_1TC_CCFG_sSharpBlur 0x0348 // 0x0000
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#define REG_1TC_CCFG_sGlamour 0x034A // 0x0000
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#define REG_1TC_CCFG_sColorTemp 0x034C // 0x0000
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#define REG_1TC_CCFG_uDeviceGammaIndex 0x034E // 0x0000
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#define REG_CapConfigControls_2_ 0x0350 // 0x0000
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#define REG_1TC_PCFG_usWidth 0x0268
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#define REG_1TC_PCFG_usHeight 0x026A
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#define REG_1TC_PCFG_Format 0x026C
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#define REG_1TC_PCFG_usMaxOut4KHzRate 0x026E
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#define REG_1TC_PCFG_usMinOut4KHzRate 0x0270
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#define REG_1TC_PCFG_PVIMask 0x0272
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#define REG_1TC_PCFG_uClockInd 0x0274
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#define REG_1TC_PCFG_usFrTimeType 0x0276
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#define REG_1TC_PCFG_FrRateQualityType 0x0278
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#define REG_1TC_PCFG_usMaxFrTimeMsecMult10 0x027A
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#define REG_1TC_PCFG_usMinFrTimeMsecMult10 0x027C
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#define AFC_Default60Hz 0x0B2A
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#define REG_TC_DBG_AutoAlgEnBits 0x0400
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#define REG_SF_USER_FlickerQuant 0x03DC
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#define REG_SF_USER_FlickerQuantChanged 0x03DE
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#define REG_2TC_PCFG_usWidth 0x028E
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#define REG_2TC_PCFG_usHeight 0x0290
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#define REG_2TC_PCFG_Format 0x0292
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#define REG_2TC_PCFG_usMaxOut4KHzRate 0x0294
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#define REG_2TC_PCFG_usMinOut4KHzRate 0x0296
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#define REG_2TC_PCFG_PVIMask 0x0298
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#define REG_2TC_PCFG_uClockInd 0x029A
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#define REG_2TC_PCFG_usFrTimeType 0x029C
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#define REG_2TC_PCFG_FrRateQualityType 0x029E
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#define REG_2TC_PCFG_usMaxFrTimeMsecMult10 0x02A0
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#define REG_2TC_PCFG_usMinFrTimeMsecMult10 0x02A2
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#define REG_3TC_PCFG_usWidth 0x02B4
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#define REG_3TC_PCFG_usHeight 0x02B6
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#define REG_3TC_PCFG_Format 0x02B8
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#define REG_3TC_PCFG_usMaxOut4KHzRate 0x02BA
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#define REG_3TC_PCFG_usMinOut4KHzRate 0x02BC
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#define REG_3TC_PCFG_PVIMask 0x02BE
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#define REG_3TC_PCFG_uClockInd 0x02C0
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#define REG_3TC_PCFG_usFrTimeType 0x02C2
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#define REG_3TC_PCFG_FrRateQualityType 0x02C4
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#define REG_3TC_PCFG_usMaxFrTimeMsecMult10 0x02C6
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#define REG_3TC_PCFG_usMinFrTimeMsecMult10 0x02C8
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#define SEQUENCE_INIT 0x00
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#define SEQUENCE_NORMAL 0x01
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#define SEQUENCE_CAPTURE 0x02
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#define SEQUENCE_PREVIEW 0x03
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#define SEQUENCE_PROPERTY 0xFFF9
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#define SEQUENCE_WAIT_MS 0xFFFA
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#define SEQUENCE_WAIT_US 0xFFFB
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#define SEQUENCE_END (0xFFFF)
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#define SEQUENCE_FAST_SETMODE_START (0xFFFD)
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#define SEQUENCE_FAST_SETMODE_END (0xFFFC)
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/*configure register for flipe and mirror during initial*/
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#define CONFIG_SENSOR_FLIPE 0
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#define CONFIG_SENSOR_MIRROR 1
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#define CONFIG_SENSOR_MIRROR_AND_FLIPE 0
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#define CONFIG_SENSOR_NONE_FLIP_MIRROR 0
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/**configure to indicate android cts****/
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#define CONFIG_SENSOR_FOR_CTS 1
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#endif
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2884
drivers/media/video/sp0838.c
Executable file
2884
drivers/media/video/sp0838.c
Executable file
File diff suppressed because it is too large
Load Diff
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@ -90,6 +90,7 @@ enum {
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/* Samsung sensors: reserved range 310-319 */
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V4L2_IDENT_S5K66A = 310, /* ddl@rock-chips.com : s5k66a support */
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V4L2_IDENT_S5K5CA = 311, /* ddl@rock-chips.com : s5k5ca support */
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/* Conexant MPEG encoder/decoders: reserved range 400-420 */
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V4L2_IDENT_CX23418_843 = 403, /* Integrated A/V Decoder on the '418 */
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@ -349,6 +350,8 @@ enum {
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V4L2_IDENT_NT99250 = 64108, /* ddl@rock-chips.com : nt99250 support */
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V4L2_IDENT_SID130B = 64109, /* ddl@rock-chips.com : sid130B support */
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V4L2_IDENT_SP0838 = 64110, /* ddl@rock-chips.com : SP0838 support */
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V4L2_IDENT_GC0329 = 64111, /* ddl@rock-chips.com : GC0329 support */
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/* Don't just add new IDs at the end: KEEP THIS LIST ORDERED BY ID! */
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user