From f47553325ede35ecfb82311342452a8f0f27ad2e Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 7 Jan 2016 16:25:44 +0800 Subject: [PATCH 01/30] ARM: dts: rockchip: set the pinctrl default setting for rk3036 i2s Sometime will hang if you set the i2s pinctrl as the none setting. Let's set the pinctrl as the default setting to enable the gpio bias. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index b9567c1e0687..8f1bb0fbf768 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -579,12 +579,12 @@ i2c2_xfer: i2c2-xfer { i2s { i2s_bus: i2s-bus { - rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_none>, - <1 1 RK_FUNC_1 &pcfg_pull_none>, - <1 2 RK_FUNC_1 &pcfg_pull_none>, - <1 3 RK_FUNC_1 &pcfg_pull_none>, - <1 4 RK_FUNC_1 &pcfg_pull_none>, - <1 5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 0 RK_FUNC_1 &pcfg_pull_default>, + <1 1 RK_FUNC_1 &pcfg_pull_default>, + <1 2 RK_FUNC_1 &pcfg_pull_default>, + <1 3 RK_FUNC_1 &pcfg_pull_default>, + <1 4 RK_FUNC_1 &pcfg_pull_default>, + <1 5 RK_FUNC_1 &pcfg_pull_default>; }; }; From 3860aa1ccfe01adb6c3fd09e880d812ceb408e5c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 9 Jan 2016 03:18:51 +0100 Subject: [PATCH 02/30] ARM: dts: rockchip: swap i2s clock ordering on rk3036 For sound setups using the simple-card mechanism, the main clock (sysclk) is expected to be the first element. For the i2s-driver itself it doesn't matter, as it uses named clocks, so we can just swap them. Reported-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 8f1bb0fbf768..ee457a2e997e 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -241,8 +241,8 @@ i2s: i2s@10220000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S>, <&cru SCLK_I2S>; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>; dmas = <&pdma 0>, <&pdma 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; From 47bf3a5c9e2aadaa6bfdff151e139196f1334c06 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 7 Jan 2016 16:25:45 +0800 Subject: [PATCH 03/30] ARM: dts: rockchip: add the sound setup for rk3036-kylin board The rk3036-kylin board uses a rt5616 audio codec connected to the i2s and can use the simple card to tie everyting together. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 992f9cadbc04..b28762522da0 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,6 +46,30 @@ / { model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5616-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC1", "Microphone Jack", + "MIC2", "Microphone Jack", + "Microphone Jack", "micbias1", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + simple-audio-card,cpu { + sound-dai = <&i2s>; + }; + + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + vcc_sys: vsys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -257,6 +281,17 @@ regulator-state-mem { &i2c2 { status = "okay"; + + rt5616: rt5616@1b { + compatible = "rt5616"; + reg = <0x1b>; + #sound-dai-cells = <0>; + }; +}; + +&i2s { + #sound-dai-cells = <0>; + status = "okay"; }; &sdio { From b270a63de5b37a6e8d2e18cabbaf14d255a609ba Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Thu, 31 Dec 2015 10:13:52 +0100 Subject: [PATCH 04/30] ARM: dts: rockchip: Add LEDs via gpio-leds for Radxa Rock2 Square Describe the two user-controllable LEDs on Rock2 Square boards. All information have been retrieved from the schematics and the vendor devicetree. The default-triggers mimic the behaviour of the vendor-kernel to keep functionalities in sync. Signed-off-by: Romain Perier Reviewed-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-square.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index c5453a0b07fc..bcaf868a76bb 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -49,6 +49,22 @@ chosen { stdout-path = "serial2:115200n8"; }; + gpio-leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + label = "rock2:green:state1"; + linux,default-trigger = "heartbeat"; + }; + + mmc { + gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + label = "rock2:blue:state2"; + linux,default-trigger = "mmc0"; + }; + }; + ir: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; From 5d69fa0f27f5bdff449858a20b7f50f08b9f33d8 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 15 Jan 2016 21:49:51 +0800 Subject: [PATCH 05/30] ARM: dts: rockchip: enable the uart0 for kylin board This patch is enabling the uart0 for bluetooth module. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index b28762522da0..c748d2cbeed6 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -308,6 +308,10 @@ &sdio { pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; }; +&uart0 { + status = "okay"; +}; + &uart2 { status = "okay"; }; From 99dc9fdc3105116b46273577e9641d7304b3046e Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 15 Jan 2016 21:49:52 +0800 Subject: [PATCH 06/30] ARM: dts: rockchip: enable the high speed on sdio for kylin board We want to the higher speed for wifi module working. Bootup kernel log: ... mmc_host mmc0: Bus speed (slot 0) = 37125000Hz (slot req 37500000Hz, actual 37125000HZ div = 0) or run 'cat /sys/kernel/debug/clk/clk_summary |grep phase -C 1' to check Otherwise, the mmc0 will run 400khz defalult value to work. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index c748d2cbeed6..905e187da381 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -299,6 +299,7 @@ &sdio { broken-cd; bus-width = <4>; + cap-sd-highspeed; cap-sdio-irq; default-sample-phase = <90>; keep-power-in-suspend; @@ -306,6 +307,10 @@ &sdio { num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; }; &uart0 { From 4a9d0b033702566cde2f33ed19ff9c8a90b7fe8f Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 15 Jan 2016 21:49:53 +0800 Subject: [PATCH 07/30] ARM: dts: rockchip: add the sdio power sequence for kylin board This patch adds the sdio power sequence for kylin board. The WLAN attached to a SDIO interface, wifi/bluetooth have reset and power been needed to enable. AFAIK, the simple power sequence provider sets a value for multiple GPIOs. So the reset and power of WlAN chip can be handled in mmc power sequence. On the module itself this is one of these, that should can be handled by reset GPIOs in simple mmc power sequence. The Bluetooth host wake is high active from bootup, this patch is also set pinctrl bias as the default to enable the pull up in soc internal. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 905e187da381..6a32b234525a 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,6 +46,23 @@ / { model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - SDIO_RESET_L_WL_RST + * - SDIO_RESET_L_BT_EN + */ + reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio0 27 GPIO_ACTIVE_LOW>, /* WL_RST */ + <&gpio2 9 GPIO_ACTIVE_LOW>; /* BT_EN */ + }; + sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -303,6 +320,7 @@ &sdio { cap-sdio-irq; default-sample-phase = <90>; keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; non-removable; num-slots = <1>; pinctrl-names = "default"; @@ -336,6 +354,12 @@ pmic_int: pmic-int { }; }; + sdio { + bt_wake_h: bt-wake-h { + rockchip,pins = <2 8 RK_FUNC_GPIO &pcfg_pull_default>; + }; + }; + sleep { global_pwroff: global-pwroff { rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>; From 6cff705b2dd944a14768e6a63c0773831583488e Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 15 Jan 2016 21:49:54 +0800 Subject: [PATCH 08/30] ARM: dts: rockchip: add the sdmmc for kylin board Although We can add the sdmmc node, shouldn't enable it. Since the sdmmc is reusing the same pin with uart2. Unfortunately, the uart2 is used by the debug port, so that will cause the debug information can't display on console if enabling the sdmmc. As we have supported the sdmmc (sd card) on hardware for kylin board. So, maybe we can have the sdmmc node in kylin dts, not to enable it. Anyway, you only need add the okay status if someone want to enable the sdmmc. e.g. if you use the adb to debug with android os. You can add the status = "okay" to enable the sdmmc for sd card working. The default status is disabling it. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 6a32b234525a..190f22cc95ef 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -331,6 +331,17 @@ &sdio { sd-uhs-sdr104; }; +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; +}; + &uart0 { status = "okay"; }; @@ -360,6 +371,12 @@ bt_wake_h: bt-wake-h { }; }; + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <2 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sleep { global_pwroff: global-pwroff { rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>; From ac79e0ef419681206ddb5aec502d2486090575a9 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 15 Jan 2016 21:26:18 +0800 Subject: [PATCH 09/30] ARM: dts: rockchip: enable pwm3 as pwm regulator for rk3066a based boards Rayeager/Bqcurie2/Marsboard use pwm3 modulate the vdd_logic voltage, so enable it. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 16 ++++++++++++++++ arch/arm/boot/dts/rk3066a-marsboard.dts | 16 ++++++++++++++++ arch/arm/boot/dts/rk3066a-rayeager.dts | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 38c91a839795..8a58bb3d7b6b 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -53,6 +53,18 @@ memory { reg = <0x60000000 0x40000000>; }; + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 1000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + voltage-table = <1000000 100>, + <1200000 42>; + status = "okay"; + }; + vcc_sd0: fixed-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -203,6 +215,10 @@ &mmc1 { /* wifi */ disable-wp; }; +&pwm3 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts index 7cdc308bfac5..a2b763e949b4 100644 --- a/arch/arm/boot/dts/rk3066a-marsboard.dts +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -52,6 +52,18 @@ memory { reg = <0x60000000 0x40000000>; }; + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 1000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + voltage-table = <1000000 100>, + <1200000 42>; + status = "okay"; + }; + vcc_sd0: sdmmc-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -194,6 +206,10 @@ phy_int: phy-int { }; }; +&pwm3 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 341c1f87936a..84f44f5ee3de 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -74,6 +74,18 @@ button@0 { }; }; + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 1000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + voltage-table = <1000000 100>, + <1200000 42>; + status = "okay"; + }; + vsys: vsys-regulator { compatible = "regulator-fixed"; regulator-name = "vsys"; @@ -431,6 +443,10 @@ &pwm2 { status = "okay"; }; +&pwm3 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_25>; status = "okay"; From 3a4294927afabd1cb0acbf0ae4fa0f2d96f09c69 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 15 Jan 2016 21:25:21 +0800 Subject: [PATCH 10/30] ARM: dts: rockchip: increase vdd_arm voltage for rk3066a based boards The current vdd_arm voltage is too low, increase it will make the system more stable. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 58bac5053858..81cf60c42712 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -61,11 +61,13 @@ cpu0: cpu@0 { reg = <0x0>; operating-points = < /* kHz uV */ - 1008000 1075000 - 816000 1025000 - 600000 1025000 - 504000 1000000 - 312000 975000 + 1416000 1300000 + 1200000 1175000 + 1008000 1125000 + 816000 1125000 + 600000 1100000 + 504000 1100000 + 312000 1075000 >; clock-latency = <40000>; clocks = <&cru ARMCLK>; From cab6f070ab53df0fa8a17e95ca7518a8c8e42e69 Mon Sep 17 00:00:00 2001 From: Chris Zhong Date: Wed, 6 Jan 2016 12:03:56 +0800 Subject: [PATCH 11/30] ARM: dts: rockchip: add rk3288 mipi_dsi nodes Add a mipi_dsi node, and also add mipi_dsi endpoints to vopb and vopl output port nodes. Signed-off-by: Chris Zhong Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 8ac49f3efc17..f0a091949f42 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -815,6 +815,10 @@ vopb_out_hdmi: endpoint@0 { reg = <0>; remote-endpoint = <&hdmi_in_vopb>; }; + vopb_out_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_in_vopb>; + }; }; }; @@ -848,6 +852,10 @@ vopl_out_hdmi: endpoint@0 { reg = <0>; remote-endpoint = <&hdmi_in_vopl>; }; + vopl_out_mipi: endpoint@2 { + reg = <2>; + remote-endpoint = <&mipi_in_vopl>; + }; }; }; @@ -861,6 +869,37 @@ vopl_mmu: iommu@ff940300 { status = "disabled"; }; + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0xff960000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; + clock-names = "ref", "pclk"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; + mipi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi>; + }; + }; + }; + }; + hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; From 30c4cbcd48b010259597436017228430edcfe242 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Sat, 9 Jan 2016 13:54:17 +0100 Subject: [PATCH 12/30] ARM: dts: rockchip: Add the iodomains for the Rock2 SOM Add the IO domain configuration for the Rock2 SOM and model the fixed regulator used as the vqmmc for the EMMC device. Signed-off-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-som.dtsi | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi index 1ece66f3e162..e1ee9f949035 100644 --- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi +++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi @@ -61,6 +61,31 @@ ext_gmac: external-gmac-clock { clock-output-names = "ext_gmac"; }; + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + rockchip,grf = <&grf>; + + audio-supply = <&vcc_io>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vccio_pmu>; + gpio30-supply = <&vccio_pmu>; + gpio1830 = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <150>; + vin-supply = <&vcc_io>; + }; + vcc_sys: vsys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; @@ -85,6 +110,7 @@ &emmc { pinctrl-names = "default"; pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; status = "okay"; }; From dfa31117dbf01e0aac76674a87a103200347e220 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Sat, 9 Jan 2016 13:54:18 +0100 Subject: [PATCH 13/30] ARM: dts: rockchip: Add the SDIO wifi on Radxa Rock2 square Enable the sdio0 slot on the Rock2 square which has a broadcom wifi chip attached and add a power sequence to enable the wifi chip and turn on the required 32k clock. Signed-off-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-rock2-square.dts | 32 ++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-rock2-square.dts b/arch/arm/boot/dts/rk3288-rock2-square.dts index bcaf868a76bb..dd3ad2e93a6d 100644 --- a/arch/arm/boot/dts/rk3288-rock2-square.dts +++ b/arch/arm/boot/dts/rk3288-rock2-square.dts @@ -86,6 +86,15 @@ spdif_out: spdif-out { #sound-dai-cells = <0>; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + }; + vcc_usb_host: vcc-host-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -111,6 +120,21 @@ vcc_sd: sdmmc-regulator { }; }; +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk &sdio0_int>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_18>; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; @@ -135,7 +159,7 @@ &hdmi { }; &i2c0 { - hym8563@51 { + hym8563: hym8563@51 { compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; @@ -177,6 +201,12 @@ sdmmc_pwr: sdmmc-pwr { rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &spdif { From b662f6d03aeeb20c0f795f469341778f4577a6bf Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 21 Jan 2016 20:32:09 +0800 Subject: [PATCH 14/30] dt-bindings: rockchip-dw-mshc: add RK3368 dw-mshc description rk3368 dtsi file add dw-mshc compatible "rockchip,rk3368-dw-mshc" but didn't add it into rockchip-dw-mshc.txt. Signed-off-by: Shawn Lin Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index 3dc13b68fc3f..634e2490795e 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt @@ -13,6 +13,7 @@ Required Properties: - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, before RK3288 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 + - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 Optional Properties: * clocks: from common clock binding: if ciu_drive and ciu_sample are From 296759c91e60c7fc84708d926161ee928697b0eb Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 21 Jan 2016 13:57:13 +0100 Subject: [PATCH 15/30] ARM: dts: rockchip: Bump sd card pin drive strength up on firefly boards It seems some firefly boards need 12mA drive strength for sdmmc. Using 4mA/8mA drive strength will cause the kernel to fail to recognize the sd card correctly. Increased the sdmmc lines drive strength from 4mA to 12mA. Signed-off-by: Wadim Egorov Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 4e3fd9aefe34..49ec20d24082 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -408,6 +408,11 @@ pcfg_output_low: pcfg-output-low { output-low; }; + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + act8846 { pwr_hold: pwr-hold { rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; @@ -457,6 +462,25 @@ work_led: work-led { }; sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + sdmmc_pwr: sdmmc-pwr { rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; }; From 0082180c8dd22c3b813618882ec9629d94172214 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 14 Jan 2016 09:08:41 +0800 Subject: [PATCH 16/30] ARM: dts: rockchip: add soc-specific compatibles for rk3036 SoCs While drivers will bind to the generic compatible values, this enables the use of more specialized drivers in the future, if the need arises. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index ee457a2e997e..78974492cb11 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -161,7 +161,7 @@ gic: interrupt-controller@10139000 { }; usb_otg: usb@10180000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x10180000 0x40000>; interrupts = ; @@ -176,7 +176,7 @@ usb_otg: usb@10180000 { }; usb_host: usb@101c0000 { - compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb", "snps,dwc2"; reg = <0x101c0000 0x40000>; interrupts = ; @@ -211,7 +211,7 @@ sdio: dwmmc@10218000 { }; emmc: dwmmc@1021c000 { - compatible = "rockchip,rk3288-dw-mshc"; + compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; interrupts = ; broken-cd; @@ -327,7 +327,7 @@ pwm3: pwm@20050030 { }; i2c1: i2c@20056000 { - compatible = "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; reg = <0x20056000 0x1000>; interrupts = ; #address-cells = <1>; @@ -340,7 +340,7 @@ i2c1: i2c@20056000 { }; i2c2: i2c@2005a000 { - compatible = "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; reg = <0x2005a000 0x1000>; interrupts = ; #address-cells = <1>; @@ -395,7 +395,7 @@ uart2: serial@20068000 { }; i2c0: i2c@20072000 { - compatible = "rockchip,rk3288-i2c"; + compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c"; reg = <0x20072000 0x1000>; interrupts = ; #address-cells = <1>; From df5ea015984633526874619ca1288fc5f2cf47c0 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Mon, 25 Jan 2016 12:19:26 +0100 Subject: [PATCH 17/30] ARM: dts: rockchip: Assign RK3288 EDP_24M input centrally The EDP 24M clock can be fed either by an SoC internal fixed clock or from an external IC. Change the default parent to the internal clock in the main rk3288 dtsi, to ensure (by default) it gets setup with a non-orphaned clock (hardware defaults to the externa clock). This prevents potential issues when the clock framework get support for deferring on orphaned clocks, while specific boards can always change the parent clock if an external input is preferred. Signed-off-by: Sjoerd Simons Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-veyron.dtsi | 5 ----- arch/arm/boot/dts/rk3288.dtsi | 3 +++ 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 9fce91ffff6f..5e61f07724d4 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -340,11 +340,6 @@ &i2c5 { i2c-scl-rising-time-ns = <1000>; }; -&power { - assigned-clocks = <&cru SCLK_EDP_24M>; - assigned-clock-parents = <&xin24m>; -}; - &pwm1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index f0a091949f42..c5d7e61c2272 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -630,6 +630,9 @@ power: power-controller { #address-cells = <1>; #size-cells = <0>; + assigned-clocks = <&cru SCLK_EDP_24M>; + assigned-clock-parents = <&xin24m>; + /* * Note: Although SCLK_* are the working clocks * of device without including on the NOC, needed for From 0ace8217c242bb3b89263bb38d13ce52960d83d9 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 19 Nov 2015 22:22:27 +0100 Subject: [PATCH 18/30] ARM: dts: rockchip: add clock-cells for usb phy nodes Add the #clock-cells properties for the usbphy nodes as they provide the pll-clocks now. Signed-off-by: Heiko Stuebner Reviewed-by: Douglas Anderson Reviewed-by: Michael Turquette Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 2 ++ arch/arm/boot/dts/rk3188.dtsi | 2 ++ arch/arm/boot/dts/rk3288.dtsi | 3 +++ 3 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 81cf60c42712..56922730d285 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -202,6 +202,7 @@ usbphy0: usb-phy0 { reg = <0x17c>; clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; + #clock-cells = <0>; }; usbphy1: usb-phy1 { @@ -209,6 +210,7 @@ usbphy1: usb-phy1 { reg = <0x188>; clocks = <&cru SCLK_OTGPHY1>; clock-names = "phyclk"; + #clock-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 348d46b7ada5..9271833958f9 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -171,6 +171,7 @@ usbphy0: usb-phy0 { reg = <0x10c>; clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; + #clock-cells = <0>; }; usbphy1: usb-phy1 { @@ -178,6 +179,7 @@ usbphy1: usb-phy1 { reg = <0x11c>; clocks = <&cru SCLK_OTGPHY1>; clock-names = "phyclk"; + #clock-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index c5d7e61c2272..6abbab67ce99 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -968,6 +968,7 @@ usbphy0: usb-phy0 { reg = <0x320>; clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; + #clock-cells = <0>; }; usbphy1: usb-phy1 { @@ -975,6 +976,7 @@ usbphy1: usb-phy1 { reg = <0x334>; clocks = <&cru SCLK_OTGPHY1>; clock-names = "phyclk"; + #clock-cells = <0>; }; usbphy2: usb-phy2 { @@ -982,6 +984,7 @@ usbphy2: usb-phy2 { reg = <0x348>; clocks = <&cru SCLK_OTGPHY2>; clock-names = "phyclk"; + #clock-cells = <0>; }; }; From b682572fc55edd4efcba8b8f29ac057b27980963 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jarosz?= Date: Tue, 19 Jan 2016 13:09:19 +0100 Subject: [PATCH 19/30] clk: rockchip: Add new id for rk3066 tsadc clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds new id for the sclk supplying the tsadc on rk3066 socs. Signed-off-by: Paweł Jarosz Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3188-cru-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 8df77a7c030b..4f53e70f68ee 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -55,6 +55,7 @@ #define SCLK_TIMER6 90 #define SCLK_JTAG 91 #define SCLK_SMC 92 +#define SCLK_TSADC 93 #define DCLK_LCDC0 190 #define DCLK_LCDC1 191 From 00f8508bc994405f6debfbfcd51e37b22b461378 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jarosz?= Date: Tue, 19 Jan 2016 13:09:21 +0100 Subject: [PATCH 20/30] ARM: dts: rockchip: add tsadc node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the device node for the TSADC found on rk3066. Signed-off-by: Paweł Jarosz Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 56922730d285..cb0a552e0b18 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -190,6 +190,16 @@ timer@2003a000 { clock-names = "timer", "pclk"; }; + tsadc: tsadc@20060000 { + compatible = "rockchip,rk3066-tsadc"; + reg = <0x20060000 0x100>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = ; + #io-channel-cells = <1>; + status = "disabled"; + }; + usbphy: phy { compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy"; rockchip,grf = <&grf>; From fe253133728cce8793c4390c943b5b46d073d5e4 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Thu, 28 Jan 2016 16:43:30 +0800 Subject: [PATCH 21/30] ARM: dts: rockchip: add the leds control for rk3036-kylin board As the kylin schematic drawing, add the needed work led for kylin board. Run: echo 0 > /sys/class/leds/kylin:red:led/brightness echo 1 > /sys/class/leds/kylin:red:led/brightness The led can normal on/off on kylin board. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 190f22cc95ef..3332a7f785c5 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,6 +46,17 @@ / { model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + leds: gpio-leds { + compatible = "gpio-leds"; + + work { + gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + label = "kylin:red:led"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + }; + }; + sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -359,6 +370,12 @@ &usb_otg { }; &pinctrl { + leds { + led_ctl: led-ctl { + rockchip,pins = <2 30 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic-int { rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>; From 8f338ecf0cd47d94303d9b4d9b2f9a99944ef0e2 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 2 Feb 2016 11:40:52 +0800 Subject: [PATCH 22/30] ARM: dts: rockchip: add mclk for rt5616 on rk3036 kylin board The I2S block that provide the output clock as the mclk for rt5616, That will be the master clock input. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 3332a7f785c5..b754613b9a9a 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -313,6 +313,8 @@ &i2c2 { rt5616: rt5616@1b { compatible = "rt5616"; reg = <0x1b>; + clocks = <&cru SCLK_I2S_OUT>; + clock-names = "mclk"; #sound-dai-cells = <0>; }; }; From f629fcfab2cd8a2f1a571fbc83e76a81ee3470db Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Tue, 2 Feb 2016 11:40:53 +0800 Subject: [PATCH 23/30] ARM: dts: rockchip: support the spi for rk3036 This patch adds the needed spi node for rk3036 dts. We have to use the 4 bus emmc to work if someone want to support the spi devices, since the pins are re-used by emmc data[5-8] and spi. In some caseswe need to support the spi devices, that will waste the emmc performance. Moment, the kylin/evb hasn't the spi devices to work, so maybe we need wait the new required to enable in kylin/evb board. Anyway, the spi should be needed land in rk3036 dts. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 78974492cb11..28fa2f848df8 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -60,6 +60,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; + spi = &spi; }; memory { @@ -407,6 +408,21 @@ i2c0: i2c@20072000 { status = "disabled"; }; + spi: spi@20074000 { + compatible = "rockchip,rockchip-spi"; + reg = <0x20074000 0x1000>; + interrupts = ; + clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>; + clock-names = "apb-pclk","spi_pclk"; + dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3036-pinctrl"; rockchip,grf = <&grf>; @@ -618,5 +634,29 @@ uart2_xfer: uart2-xfer { }; /* no rts / cts for uart2 */ }; + + spi { + spi_txd:spi-txd { + rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>; + }; + + spi_rxd:spi-rxd { + rockchip,pins = <1 28 RK_FUNC_3 &pcfg_pull_default>; + }; + + spi_clk:spi-clk { + rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_default>; + }; + + spi_cs0:spi-cs0 { + rockchip,pins = <1 30 RK_FUNC_3 &pcfg_pull_default>; + + }; + + spi_cs1:spi-cs1 { + rockchip,pins = <1 31 RK_FUNC_3 &pcfg_pull_default>; + + }; + }; }; }; From f6bb9d5f30d6986c4fdce1ed5a36088a0c30c544 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Fri, 29 Jan 2016 16:49:21 +0800 Subject: [PATCH 24/30] ARM: dts: rockchip: increase the mclk_fs to 512 for kylin board If we playback the 8KHz FS audio with the 256 mclk_fs, we need the mclk = 256 * 8000 = 2.048MHz, the frac div is 594 / 2.048 = 290, the frac div value 0x00809015 set to the CRU_CLKSEL7_CON will cause to hang. We increase the mclk_fs to 512, will get the mclk = 512 * 8000 = 4.096MHz, use 0x01009015 instead of 0x00809015 to work around this issue. We will keep tracking it. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036-kylin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index b754613b9a9a..d5913fe128ee 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -78,7 +78,7 @@ sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,name = "rockchip,rt5616-codec"; - simple-audio-card,mclk-fs = <256>; + simple-audio-card,mclk-fs = <512>; simple-audio-card,widgets = "Microphone", "Microphone Jack", "Headphone", "Headphone Jack"; From cef687d05f9ff8a022a23ded6d5f6ac82d40ddf3 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 26 Jan 2016 10:34:14 +0800 Subject: [PATCH 25/30] dt-bindings: rockchip-dw-mshc: add RK3036 dw-mshc description rk3036 dtsi file add dw-mshc compatible "rockchip,rk3036-dw-mshc" but didn't add it into rockchip-dw-mshc.txt. Signed-off-by: Shawn Lin Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index 634e2490795e..ea5614b6f613 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt @@ -13,6 +13,7 @@ Required Properties: - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, before RK3288 - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 + - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036 - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368 Optional Properties: From e7d6c9b1163255d8d6594e613eac7a4a8b1806a0 Mon Sep 17 00:00:00 2001 From: Addy Ke Date: Fri, 22 Jan 2016 19:06:47 +0800 Subject: [PATCH 26/30] ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3288 platform Pl330 integrated in rk3288 platform doesn't support DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk for it. Signed-off-by: Addy Ke Signed-off-by: Shawn Lin Reviewed-by: Doug Anderson Reviewed-by: Sonny Rao Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 6abbab67ce99..0934b6abcaab 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -145,6 +145,7 @@ dmac_peri: dma-controller@ff250000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; @@ -155,6 +156,7 @@ dmac_bus_ns: dma-controller@ff600000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; status = "disabled"; @@ -166,6 +168,7 @@ dmac_bus_s: dma-controller@ffb20000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; }; From 9bed8b41d8da3acdb72d5fafa7ac5ec0016dd188 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 22 Jan 2016 19:06:48 +0800 Subject: [PATCH 27/30] ARM: dts: rockchip: Add arm, pl330-broken-no-flushp quirk for rk3xxx platform Pl330 integrated in rk3xxx platform doesn't support DMAFLUSHP function. So we add arm,pl330-broken-no-flushp quirk for it. Signed-off-by: Shawn Lin Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 99eeea70223b..f1581f9d050f 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -78,6 +78,7 @@ dmac1_s: dma-controller@20018000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMA1>; clock-names = "apb_pclk"; }; @@ -88,6 +89,7 @@ dmac1_ns: dma-controller@2001c000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMA1>; clock-names = "apb_pclk"; status = "disabled"; @@ -99,6 +101,7 @@ dmac2: dma-controller@20078000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMA2>; clock-names = "apb_pclk"; }; From 29f12bbab4c3997c5c8879ea19cfc47440dedbd8 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 22 Jan 2016 19:06:49 +0800 Subject: [PATCH 28/30] ARM: dts: rockchip: add arm,pl330-broken-no-flushp quirk for rk3036 SoCs Pl330 integrated in rk3036 platform that doesn't support DMAFLUSHP function. So we add 'arm,pl330-broken-no-flushp' quirk for rk3036. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 28fa2f848df8..3864fa142df0 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -106,6 +106,7 @@ pdma: pdma@20078000 { interrupts = , ; #dma-cells = <1>; + arm,pl330-broken-no-flushp; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; From 4f66f247f70bda47ec2410d007520004ba8761de Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 8 Feb 2016 21:55:12 +0000 Subject: [PATCH 29/30] ARM: dts: rockchip: replace gpio-key,wakeup with wakeup-source property Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup and in one instance a value "0" is assigned probably assuming it won't be enabled as a wakeup source. Since the presence of the boolean property indicates it is enabled, value of "0" have no value. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Signed-off-by: Sudeep Holla Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 3 +-- arch/arm/boot/dts/rk3066a-rayeager.dts | 2 +- arch/arm/boot/dts/rk3188-radxarock.dts | 2 +- arch/arm/boot/dts/rk3288-evb.dtsi | 2 +- arch/arm/boot/dts/rk3288-firefly.dtsi | 2 +- arch/arm/boot/dts/rk3288-popmetal.dts | 2 +- arch/arm/boot/dts/rk3288-r89.dts | 2 +- arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 2 +- arch/arm/boot/dts/rk3288-veyron.dtsi | 2 +- 9 files changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 8a58bb3d7b6b..6d2a5b3a84a8 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -86,7 +86,7 @@ button@0 { linux,code = <116>; label = "GPIO Key Power"; linux,input-type = <1>; - gpio-key,wakeup = <1>; + wakeup-source; debounce-interval = <100>; }; button@1 { @@ -94,7 +94,6 @@ button@1 { linux,code = <104>; label = "GPIO Key Vol-"; linux,input-type = <1>; - gpio-key,wakeup = <0>; debounce-interval = <100>; }; /* VOL+ comes somehow thru the ADC */ diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 84f44f5ee3de..05533005a809 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -65,7 +65,7 @@ keys: gpio-keys { #size-cells = <0>; button@0 { - gpio-key,wakeup = <1>; + wakeup-source; gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = <116>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 66fa87d1e2c2..0b6924c97b6b 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -63,7 +63,7 @@ button@0 { linux,code = <116>; label = "GPIO Key Power"; linux,input-type = <1>; - gpio-key,wakeup = <1>; + wakeup-source; debounce-interval = <100>; }; }; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 4faabdb65868..78d47f7d2938 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -110,7 +110,7 @@ button@0 { linux,code = <116>; label = "GPIO Key Power"; linux,input-type = <1>; - gpio-key,wakeup = <1>; + wakeup-source; debounce-interval = <100>; }; }; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 49ec20d24082..98c586a43c73 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -91,7 +91,7 @@ keys: gpio-keys { #size-cells = <0>; button@0 { - gpio-key,wakeup = <1>; + wakeup-source; gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; linux,code = <116>; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 65c475642d5a..2ff9689d2e1b 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -74,7 +74,7 @@ button@0 { linux,code = <116>; label = "GPIO Key Power"; linux,input-type = <1>; - gpio-key,wakeup = <1>; + wakeup-source; debounce-interval = <100>; }; }; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 17f13c73fe5e..510a1d0d7abb 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -73,7 +73,7 @@ button@0 { linux,code = <116>; label = "GPIO Key Power"; linux,input-type = <1>; - gpio-key,wakeup = <1>; + wakeup-source; debounce-interval = <100>; }; }; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 136d650dd05f..610769d99522 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -108,7 +108,7 @@ &gpio_keys { lid { label = "Lid"; gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; + wakeup-source; linux,code = <0>; /* SW_LID */ linux,input-type = <5>; /* EV_SW */ debounce-interval = <1>; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5e61f07724d4..0350f79f57da 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -64,7 +64,7 @@ power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <100>; - gpio-key,wakeup; + wakeup-source; }; }; From 741d3b0c1f6187dbf9b509b6776c77828d4c66d5 Mon Sep 17 00:00:00 2001 From: James Chao Date: Sat, 30 Jan 2016 10:38:24 +0800 Subject: [PATCH 30/30] ARM: dts: cros-ec-keyboard: Add LOCK key to keyboard matrix The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices that use the Chrome OS EC keyboard matrix. Signed-off-by: James Chao Signed-off-by: YH Huang Signed-off-by: Daniel Kurtz Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/cros-ec-keyboard.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi index 4e42f30cb318..c0451051777e 100644 --- a/arch/arm/boot/dts/cros-ec-keyboard.dtsi +++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi @@ -55,6 +55,7 @@ MATRIX_KEY(0x03, 0x03, KEY_5) MATRIX_KEY(0x03, 0x04, KEY_F5) MATRIX_KEY(0x03, 0x06, KEY_6) MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x09, KEY_F13) MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) MATRIX_KEY(0x03, 0x0c, KEY_MUHENKAN)