From 84d2ae7c09d93949fc9e9fe57bdb78a2f3fa24aa Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Wed, 19 Jul 2023 12:50:16 +0530 Subject: [PATCH 1/4] ARM: dts: qcom: sdx65: Add PCIe EP interconnect path Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna chaitanya chundru Link: https://lore.kernel.org/r/1689751218-24492-3-git-send-email-quic_krichai@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 3bc67bb8c1eb..e41ac11910ea 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -335,6 +335,10 @@ pcie_ep: pcie-ep@1c00000 { ; interrupt-names = "global", "doorbell"; + interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; From 7ec041bd2715df2da4ab19c403c27d58d173c7c0 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Wed, 19 Jul 2023 12:50:17 +0530 Subject: [PATCH 2/4] ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect path Add cpu-pcie interconnect path for PCIe EP to sdx55 platform. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1689751218-24492-4-git-send-email-quic_krichai@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index d0f6120b665d..12dca14712ce 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -427,8 +427,9 @@ pcie_ep: pcie-ep@1c00000 { interrupt-names = "global", "doorbell"; - interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>; - interconnect-names = "pcie-mem"; + interconnects = <&system_noc MASTER_PCIE &mc_virt SLAVE_EBI_CH0>, + <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_PCIE_0>; + interconnect-names = "pcie-mem", "cpu-pcie"; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; From 5c876b8609026770c63700c21055452fa5641e53 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 31 Dec 2024 13:39:31 +0530 Subject: [PATCH 3/4] ARM: dts: qcom: sdx65: Disable USB U1/U2 entry Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. 3. On targets like SDX75, intermittent disconnects were observed with certain cables due to impedence variations. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20241231080932.3149448-2-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index e41ac11910ea..6b23ee676c9e 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -530,6 +530,8 @@ usb_dwc3: usb@a600000 { iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; }; From e3bab40d5961453545ef39aeb5198d2e718c9693 Mon Sep 17 00:00:00 2001 From: Prashanth K Date: Tue, 31 Dec 2024 13:39:32 +0530 Subject: [PATCH 4/4] ARM: dts: qcom: sdx55: Disable USB U1/U2 entry Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. 3. On targets like SDX75, intermittent disconnects were observed with certain cables due to impedence variations. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20241231080932.3149448-3-quic_prashk@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 12dca14712ce..39530eb580ea 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -614,6 +614,8 @@ usb_dwc3: usb@a600000 { iommus = <&apps_smmu 0x1a0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; };