drm/xe/xe3p: Add xe3p EU stall data format

Starting with Xe3p, IP address in EU stall data increases to 61 bits.
While at it, re-order the if-else ladder so the officially supported
platforms come before PVC.

Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://lore.kernel.org/r/20251016-xe3p-v3-24-3dd173a3097a@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Harish Chegondi 2025-10-16 19:26:43 -07:00 committed by Lucas De Marchi
parent bf3035fe45
commit d104d7ea86

View File

@ -124,6 +124,27 @@ struct xe_eu_stall_data_xe2 {
__u64 unused[6];
} __packed;
/*
* EU stall data format for Xe3p arch GPUs.
*/
struct xe_eu_stall_data_xe3p {
__u64 ip_addr:61; /* Bits 0 to 60 */
__u64 tdr_count:8; /* Bits 61 to 68 */
__u64 other_count:8; /* Bits 69 to 76 */
__u64 control_count:8; /* Bits 77 to 84 */
__u64 pipestall_count:8; /* Bits 85 to 92 */
__u64 send_count:8; /* Bits 93 to 100 */
__u64 dist_acc_count:8; /* Bits 101 to 108 */
__u64 sbid_count:8; /* Bits 109 to 116 */
__u64 sync_count:8; /* Bits 117 to 124 */
__u64 inst_fetch_count:8; /* Bits 125 to 132 */
__u64 active_count:8; /* Bits 133 to 140 */
__u64 ex_id:3; /* Bits 141 to 143 */
__u64 end_flag:1; /* Bit 144 */
__u64 unused_bits:47;
__u64 unused[5];
} __packed;
const u64 eu_stall_sampling_rates[] = {251, 251 * 2, 251 * 3, 251 * 4, 251 * 5, 251 * 6, 251 * 7};
/**
@ -167,10 +188,13 @@ size_t xe_eu_stall_data_record_size(struct xe_device *xe)
{
size_t record_size = 0;
if (xe->info.platform == XE_PVC)
record_size = sizeof(struct xe_eu_stall_data_pvc);
if (GRAPHICS_VER(xe) >= 35)
record_size = sizeof(struct xe_eu_stall_data_xe3p);
else if (GRAPHICS_VER(xe) >= 20)
record_size = sizeof(struct xe_eu_stall_data_xe2);
else if (xe->info.platform == XE_PVC)
record_size = sizeof(struct xe_eu_stall_data_pvc);
xe_assert(xe, is_power_of_2(record_size));