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gpio fixes for v7.1-rc1
- fix a regression in gpio-rockchip introduced on older chips during the merge window when converting to dynamic GPIO base - fix AST2700 debounce selector bit definitions in gpio-aspeed -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEkeUTLeW1Rh17omX8BZ0uy/82hMMFAmnrImYACgkQBZ0uy/82 hMOT3xAAtHVWeC4QbvaG4yoG7tp1dF87a3gliDvoZs7ntKC773eSM3Iuckefn8bZ cWn3EfC7DJbYtLvUtmqHaawKr6pgKuY3adIkguZY+EvHjtuGl2lEhJgEIsAyh/KW C1InaEAFZT+t5NnIeNQQ1JAZfd+zu3haC0anIEnb4qhgueb5dDYompAL5AUNopPK cyZOqlcCFHUPKhoPA/XWp9OIodZsIr2U8t5Ou7OO0VBrnwa/Mrjj2Rfsh8B97IOs AZS6b2s5SGK8b5mk7HLCsJM4fGU9BnDBDtx5nCQkukCpeqhEkBjvSPRbJBaxlZ60 6C773FXohIKhAixGzbP2PtwzEYDc2mr6Vf9oZxELWJvLUvPS+3kZ0WtqGiRJXx51 VO66iGuaVF6b2mtmokNyZ9amDu9qKku1+0i0og7w3DtV20RWb3dnExqnLYcCaL0p rsU3R2UFQIIAfFCoC9T1Dcrt2whCcLpcAhAWaT7b3L8r34ndY2jjcwP4JnYHCjEt 7BIdkgUn0pEaQSNZ4i2XJiEDDdcCsUvmApwBv1SlxUvb+lj4kXcDo/rLdPH/LG33 SrNGzHgMVrltBulMMbc0e78Ye/80pQOaGlP+I/bPO39w/kNZNW5Pxf7tZzSvrXEL d4Wfm6hxcZaDTQfpShNYpASkR+gZ08xB6getEiH8bfbOqu58Snc= =H+NQ -----END PGP SIGNATURE----- Merge tag 'gpio-fixes-for-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio fixes from Bartosz Golaszewski: - fix a regression in gpio-rockchip introduced on older chips during the merge window when converting to dynamic GPIO base - fix AST2700 debounce selector bit definitions in gpio-aspeed * tag 'gpio-fixes-for-v7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: gpio: aspeed: fix AST2700 debounce selector bit definitions gpio: rockchip: Fix GPIO regression after conversion to dynamic base allocation
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commit
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@ -42,8 +42,8 @@
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#define GPIO_G7_CTRL_IRQ_TYPE1 BIT(4)
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#define GPIO_G7_CTRL_IRQ_TYPE2 BIT(5)
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#define GPIO_G7_CTRL_RST_TOLERANCE BIT(6)
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#define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(7)
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#define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(8)
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#define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(7)
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#define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(8)
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#define GPIO_G7_CTRL_INPUT_MASK BIT(9)
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#define GPIO_G7_CTRL_IRQ_STS BIT(12)
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#define GPIO_G7_CTRL_IN_DATA BIT(13)
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@ -617,7 +617,7 @@ static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
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return -ENODEV;
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ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
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gc->base, gc->ngpio);
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bank->pin_base, bank->nr_pins);
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if (ret) {
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dev_err(bank->dev, "Failed to add pin range\n");
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goto fail;
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