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clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP

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Add the LHS_ACEL gate clock to the HSI0 clock controller. This clock is
critical for USB functionality and mark it as critical to keep it enabled.

Update CLK_NR_TOP to include the new clock.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://lore.kernel.org/r/20250831-usb-v2-2-00b9c0559733@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Denzeel Oliva 2025-08-31 12:13:15 +00:00 committed by Krzysztof Kozlowski
parent eb9bc16277
commit d0563d320b
1 changed files with 5 additions and 1 deletions
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6
drivers/clk/samsung/clk-exynos990.c
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@ -18,7 +18,7 @@
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1)
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
#define CLKS_NR_HSI0 (CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK + 1)
#define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@ -1332,6 +1332,10 @@ static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
"gout_hsi0_xiu_d_hsi0_aclk", "mout_hsi0_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
21, CLK_IGNORE_UNUSED, 0),
GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK,
"gout_hsi0_lhs_acel_d_hsi0_clk", "mout_hsi0_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
21, CLK_IS_CRITICAL, 0),
};
static const struct samsung_cmu_info hsi0_cmu_info __initconst = {