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drm/panel: st7701: Add Winstar wf40eswaa6mnn0 panel support
The Winstar wf40eswaa6mnn0 panel is a square 4.0" TFT LCD with a resolution of 480x480 pixels. This panel is driven by the Sitronix ST7701 controller and uses a MIPI DSI interface. The settings are based on the panel's datasheet and the init sequence provided by Winstar. It was tested on a Verdin iMX8MP from Toradex with a Carrier Board providing a MIPI DSI interface. Signed-off-by: Stefan Eichenberger <eichest@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250606114644.105371-2-eichest@gmail.com
This commit is contained in:
Stefan Eichenberger
Neil Armstrong
parent
783334f366
commit
d04f6367d3
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@ -520,6 +520,28 @@ static void rg28xx_gip_sequence(struct st7701 *st7701)
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st7701_switch_cmd_bkx(st7701, false, 0);
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}
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static void wf40eswaa6mnn0_gip_sequence(struct st7701 *st7701)
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{
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ST7701_WRITE(st7701, 0xE0, 0x00, 0x28, 0x02);
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ST7701_WRITE(st7701, 0xE1, 0x08, 0xA0, 0x00, 0x00, 0x07, 0xA0, 0x00,
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0x00, 0x00, 0x44, 0x44);
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ST7701_WRITE(st7701, 0xE2, 0x11, 0x11, 0x44, 0x44, 0xED, 0xA0, 0x00,
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0x00, 0xEC, 0xA0, 0x00, 0x00);
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ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x11, 0x11);
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ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
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ST7701_WRITE(st7701, 0xE5, 0x0A, 0xE9, 0xD8, 0xA0, 0x0C, 0xEB, 0xD8,
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0xA0, 0x0E, 0xED, 0xD8, 0xA0, 0x10, 0xEF, 0xD8, 0xA0);
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ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x11, 0x11);
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ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
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ST7701_WRITE(st7701, 0xE8, 0x09, 0xE8, 0xD8, 0xA0, 0x0B, 0xEA, 0xD8,
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0xA0, 0x0D, 0xEC, 0xD8, 0xA0, 0x0F, 0xEE, 0xD8, 0xA0);
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ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x88, 0x00, 0x40);
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ST7701_WRITE(st7701, 0xEC, 0x3C, 0x00);
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ST7701_WRITE(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x02, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0x20, 0x45, 0x67, 0x98, 0xBA);
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ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0);
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}
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static int st7701_prepare(struct drm_panel *panel)
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{
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struct st7701 *st7701 = panel_to_st7701(panel);
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@ -1135,6 +1157,107 @@ static const struct st7701_panel_desc rg28xx_desc = {
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.gip_sequence = rg28xx_gip_sequence,
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};
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static const struct drm_display_mode wf40eswaa6mnn0_mode = {
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.clock = 18306,
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.hdisplay = 480,
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.hsync_start = 480 + 2,
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.hsync_end = 480 + 2 + 45,
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.htotal = 480 + 2 + 45 + 13,
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.vdisplay = 480,
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.vsync_start = 480 + 2,
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.vsync_end = 480 + 2 + 70,
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.vtotal = 480 + 2 + 70 + 13,
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.width_mm = 72,
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.height_mm = 70,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
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};
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static const struct st7701_panel_desc wf40eswaa6mnn0_desc = {
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.mode = &wf40eswaa6mnn0_mode,
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.lanes = 2,
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.format = MIPI_DSI_FMT_RGB888,
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.panel_sleep_delay = 0,
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.pv_gamma = {
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0x1),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x08),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x10),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0c),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x08),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x10),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0c),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x08),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x04),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x14),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0xb3),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3a),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
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},
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.nv_gamma = {
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x13),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x19),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1f),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0f),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x14),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x07),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x07),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x07),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x02),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0xf),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x0f),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0xa3),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
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CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x0d)
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},
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.nlinv = 3,
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.vop_uv = 4737500,
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.vcom_uv = 662500,
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.vgh_mv = 15000,
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.vgl_mv = -10170,
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.avdd_mv = 6600,
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.avcl_mv = -4600,
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.gamma_op_bias = OP_BIAS_MIDDLE,
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.input_op_bias = OP_BIAS_MIDDLE,
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.output_op_bias = OP_BIAS_MIN,
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.t2d_ns = 1600,
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.t3d_ns = 10400,
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.eot_en = true,
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.gip_sequence = wf40eswaa6mnn0_gip_sequence,
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};
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static void st7701_cleanup(void *data)
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{
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struct st7701 *st7701 = (struct st7701 *)data;
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@ -1265,6 +1388,7 @@ static const struct of_device_id st7701_dsi_of_match[] = {
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{ .compatible = "densitron,dmt028vghmcmi-1a", .data = &dmt028vghmcmi_1a_desc },
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{ .compatible = "elida,kd50t048a", .data = &kd50t048a_desc },
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{ .compatible = "techstar,ts8550b", .data = &ts8550b_desc },
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{ .compatible = "winstar,wf40eswaa6mnn0", .data = &wf40eswaa6mnn0_desc },
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{ }
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};
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MODULE_DEVICE_TABLE(of, st7701_dsi_of_match);
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