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serial: sh-sci: Fix a comment about SCIFA
The comment was correct when it was added, at that time RZ/T1 was the only SoC in the RZ/T line. Since then, further SoCs have been added with RZ/T names which do not use the same SCIFA register layout and so the comment is now misleading. So we update the comment to explicitly reference only RZ/T1 SoCs. Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Link: https://lore.kernel.org/r/20250403212919.1137670-8-thierry.bultel.yh@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -310,7 +310,7 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
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},
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/*
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* The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
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* The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1.
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* It looks like a normal SCIF with FIFO data, but with a
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* compressed address space. Also, the break out of interrupts
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* are different: ERI/BRI, RXI, TXI, TEI, DRI.
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