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x86/mce: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr(), wrmsr() and rdmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://patch.msgid.link/20260629060526.3638272-9-jgross@suse.com
This commit is contained in:
Juergen Gross
Ingo Molnar
parent
c69d7feb8d
commit
cff219368b
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@ -280,11 +280,11 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
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u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
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const struct smca_hwid *s_hwid;
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unsigned int i, hwid_mcatype;
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u32 high, low;
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struct msr val;
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u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
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/* Set appropriate bits in MCA_CONFIG */
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if (!rdmsr_safe(smca_config, &low, &high)) {
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if (!rdmsrq_safe(smca_config, &val.q)) {
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/*
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* OS is required to set the MCAX bit to acknowledge that it is
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* now using the new MSR ranges and new registers under each
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@ -294,7 +294,7 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
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*
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* MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
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*/
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high |= BIT(0);
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val.h |= BIT(0);
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/*
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* SMCA sets the Deferred Error Interrupt type per bank.
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@ -307,9 +307,9 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
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* APIC based interrupt. First, check that no interrupt has been
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* set.
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*/
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if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) {
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if ((val.l & BIT(5)) && !((val.h >> 5) & 0x3) && data->dfr_intr_en) {
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__set_bit(bank, data->dfr_intr_banks);
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high |= BIT(5);
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val.h |= BIT(5);
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}
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/*
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@ -324,33 +324,33 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
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* The OS should set this to inform the platform that the OS is ready
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* to handle the MCA Thresholding interrupt.
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*/
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if ((low & BIT(10)) && data->thr_intr_en) {
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if ((val.l & BIT(10)) && data->thr_intr_en) {
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__set_bit(bank, data->thr_intr_banks);
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high |= BIT(8);
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val.h |= BIT(8);
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}
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this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
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this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(val.l & BIT(8));
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if (low & MCI_CONFIG_PADDRV)
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if (val.l & MCI_CONFIG_PADDRV)
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this_cpu_ptr(smca_banks)[bank].paddrv = 1;
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wrmsr(smca_config, low, high);
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wrmsrq(smca_config, val.q);
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}
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if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
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if (rdmsrq_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &val.q)) {
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pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
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return;
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}
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hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
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(high & MCI_IPID_MCATYPE) >> 16);
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hwid_mcatype = HWID_MCATYPE(val.h & MCI_IPID_HWID,
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(val.h & MCI_IPID_MCATYPE) >> 16);
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for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
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s_hwid = &smca_hwid_mcatypes[i];
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if (hwid_mcatype == s_hwid->hwid_mcatype) {
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this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
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this_cpu_ptr(smca_banks)[bank].id = low;
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this_cpu_ptr(smca_banks)[bank].id = val.l;
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this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
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break;
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}
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@ -432,50 +432,50 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
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static void threshold_restart_block(void *_tr)
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{
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struct thresh_restart *tr = _tr;
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u32 hi, lo;
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struct msr val;
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/* sysfs write might race against an offline operation */
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if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
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return;
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rdmsr(tr->b->address, lo, hi);
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rdmsrq(tr->b->address, val.q);
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/*
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* Reset error count and overflow bit.
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* This is done during init or after handling an interrupt.
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*/
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if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) {
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hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
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hi |= THRESHOLD_MAX - tr->b->threshold_limit;
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if (val.h & MASK_OVERFLOW_HI || tr->set_lvt_off) {
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val.h &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
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val.h |= THRESHOLD_MAX - tr->b->threshold_limit;
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} else if (tr->old_limit) { /* change limit w/o reset */
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int new_count = (hi & THRESHOLD_MAX) +
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int new_count = (val.h & THRESHOLD_MAX) +
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(tr->old_limit - tr->b->threshold_limit);
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hi = (hi & ~MASK_ERR_COUNT_HI) |
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val.h = (val.h & ~MASK_ERR_COUNT_HI) |
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(new_count & THRESHOLD_MAX);
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}
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/* clear IntType */
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hi &= ~MASK_INT_TYPE_HI;
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val.h &= ~MASK_INT_TYPE_HI;
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if (!tr->b->interrupt_capable)
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goto done;
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if (tr->set_lvt_off) {
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if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
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if (lvt_off_valid(tr->b, tr->lvt_off, val.l, val.h)) {
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/* set new lvt offset */
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hi &= ~MASK_LVTOFF_HI;
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hi |= tr->lvt_off << 20;
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val.h &= ~MASK_LVTOFF_HI;
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val.h |= tr->lvt_off << 20;
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}
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}
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if (tr->b->interrupt_enable)
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hi |= INT_TYPE_APIC;
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val.h |= INT_TYPE_APIC;
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done:
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hi |= MASK_COUNT_EN_HI;
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wrmsr(tr->b->address, lo, hi);
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val.h |= MASK_COUNT_EN_HI;
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wrmsrq(tr->b->address, val.q);
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}
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static void threshold_restart_bank(unsigned int bank, bool intr_en)
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@ -726,7 +726,8 @@ static void smca_enable_interrupt_vectors(void)
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void mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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unsigned int bank, block, cpu = smp_processor_id();
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u32 low = 0, high = 0, address = 0;
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struct msr val = { .q = 0 };
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u32 address = 0;
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int offset = -1;
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amd_apply_cpu_quirks(c);
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@ -746,21 +747,21 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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disable_err_thresholding(c, bank);
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for (block = 0; block < NR_BLOCKS; ++block) {
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address = get_block_address(address, low, high, bank, block, cpu);
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address = get_block_address(address, val.l, val.h, bank, block, cpu);
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if (!address)
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break;
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if (rdmsr_safe(address, &low, &high))
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if (rdmsrq_safe(address, &val.q))
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break;
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if (!(high & MASK_VALID_HI))
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if (!(val.h & MASK_VALID_HI))
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continue;
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if (!(high & MASK_CNTP_HI) ||
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(high & MASK_LOCKED_HI))
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if (!(val.h & MASK_CNTP_HI) ||
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(val.h & MASK_LOCKED_HI))
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continue;
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offset = prepare_threshold_block(bank, block, address, offset, high);
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offset = prepare_threshold_block(bank, block, address, offset, val.h);
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}
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}
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}
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@ -1083,24 +1084,24 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
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u32 address)
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{
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struct threshold_block *b = NULL;
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u32 low, high;
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struct msr val;
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int err;
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if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
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return 0;
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if (rdmsr_safe(address, &low, &high))
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if (rdmsrq_safe(address, &val.q))
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return 0;
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if (!(high & MASK_VALID_HI)) {
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if (!(val.h & MASK_VALID_HI)) {
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if (block)
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goto recurse;
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else
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return 0;
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}
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if (!(high & MASK_CNTP_HI) ||
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(high & MASK_LOCKED_HI))
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if (!(val.h & MASK_CNTP_HI) ||
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(val.h & MASK_LOCKED_HI))
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goto recurse;
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b = kzalloc_obj(struct threshold_block);
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@ -1112,7 +1113,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
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b->cpu = cpu;
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b->address = address;
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b->interrupt_enable = 0;
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b->interrupt_capable = lvt_interrupt_supported(bank, high);
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b->interrupt_capable = lvt_interrupt_supported(bank, val.h);
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b->threshold_limit = get_thr_limit();
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if (b->interrupt_capable) {
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@ -1124,13 +1125,13 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
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list_add(&b->miscj, &tb->miscj);
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mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20);
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mce_threshold_block_init(b, (val.h & MASK_LVTOFF_HI) >> 20);
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err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
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if (err)
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goto out_free;
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recurse:
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address = get_block_address(address, low, high, bank, ++block, cpu);
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address = get_block_address(address, val.l, val.h, bank, ++block, cpu);
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if (!address)
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return 0;
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@ -1866,7 +1866,7 @@ static void __mcheck_cpu_init_generic(void)
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rdmsrq(MSR_IA32_MCG_CAP, cap);
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if (cap & MCG_CTL_P)
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wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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wrmsrq(MSR_IA32_MCG_CTL, ~0ULL);
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}
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static void __mcheck_cpu_init_prepare_banks(void)
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@ -23,16 +23,16 @@ int mce_p5_enabled __read_mostly;
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/* Machine check handler for Pentium class Intel CPUs: */
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noinstr void pentium_machine_check(struct pt_regs *regs)
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{
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u32 loaddr, hi, lotype;
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u64 addr, type;
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instrumentation_begin();
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rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
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rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
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rdmsrq(MSR_IA32_P5_MC_ADDR, addr);
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rdmsrq(MSR_IA32_P5_MC_TYPE, type);
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pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
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smp_processor_id(), loaddr, lotype);
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smp_processor_id(), (u32)addr, (u32)type);
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if (lotype & (1<<5)) {
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if (type & (1<<5)) {
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pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
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smp_processor_id());
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}
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@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs)
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/* Set up machine check reporting for processors with Intel style MCE: */
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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u64 q;
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/* Default P5 to off as its often misconnected: */
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if (!mce_p5_enabled)
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@ -55,8 +55,8 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
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return;
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/* Read registers before enabling: */
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rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
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rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
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rdmsrq(MSR_IA32_P5_MC_ADDR, q);
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rdmsrq(MSR_IA32_P5_MC_TYPE, q);
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pr_info("Intel old style machine check architecture supported.\n");
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/* Enable MCE: */
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@ -28,12 +28,12 @@ noinstr void winchip_machine_check(struct pt_regs *regs)
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/* Set up machine check reporting on the Winchip C6 series */
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void winchip_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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struct msr val;
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rdmsr(MSR_IDT_FCR1, lo, hi);
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lo |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
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lo &= ~(1<<4); /* Enable MCE */
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wrmsr(MSR_IDT_FCR1, lo, hi);
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rdmsrq(MSR_IDT_FCR1, val.q);
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val.l |= (1<<2); /* Enable EIERRINT (int 18 MCE) */
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val.l &= ~(1<<4); /* Enable MCE */
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wrmsrq(MSR_IDT_FCR1, val.q);
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cr4_set_bits(X86_CR4_MCE);
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