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mtd: rawnand: qcom: move common code to the 'qpic_common' module
The 'qpic_common' module provides some generic functions which are usable by both the 'qcom_nandc' and by the 'spi-qpic-snand' driver. Move more code from the 'qcom_nandc' driver to there in order to allow using those also from the 'spi-qpic-snand' driver. No functional changes. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
Gabor Juhos
Miquel Raynal
parent
555d48e520
commit
cfae2182fa
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@ -775,5 +775,136 @@ int qcom_nandc_alloc(struct qcom_nand_controller *nandc)
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}
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EXPORT_SYMBOL(qcom_nandc_alloc);
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/* reads back FLASH_STATUS register set by the controller */
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int qcom_nandc_check_flash_errors(struct qcom_nand_controller *nandc,
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int cw_cnt)
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{
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int i;
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qcom_nandc_dev_to_mem(nandc, true);
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for (i = 0; i < cw_cnt; i++) {
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u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
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if (flash & (FS_OP_ERR | FS_MPU_ERR))
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return -EIO;
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}
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return 0;
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}
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EXPORT_SYMBOL(qcom_nandc_check_flash_errors);
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/*
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* Helper to prepare DMA descriptors for configuring registers
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* before reading a NAND page.
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*/
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void qcom_nandc_config_page_read(struct qcom_nand_controller *nandc)
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{
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qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
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if (!nandc->props->qpic_version2)
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qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr,
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NAND_ERASED_CW_DETECT_CFG, 1, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set,
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NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
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}
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EXPORT_SYMBOL(qcom_nandc_config_page_read);
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/*
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* Helper to prepare DMA descriptors used to configure registers needed for
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* before writing a NAND page.
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*/
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void qcom_nandc_config_page_write(struct qcom_nand_controller *nandc)
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{
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qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
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if (!nandc->props->qpic_version2)
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qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1,
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NAND_BAM_NEXT_SGL);
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}
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EXPORT_SYMBOL(qcom_nandc_config_page_write);
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/*
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* Helper to prepare DMA descriptors for configuring registers
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* before writing each codeword in NAND page.
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*/
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void qcom_nandc_config_cw_write(struct qcom_nand_controller *nandc)
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{
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qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
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qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
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qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
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qcom_write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
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NAND_BAM_NEXT_SGL);
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}
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EXPORT_SYMBOL(qcom_nandc_config_cw_write);
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/**
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* qcom_nandc_set_read_loc_first() - to set read location first register
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* @nandc: NAND controller's private data
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* @reg_base: location register base
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* @cw_offset: code word offset
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* @read_size: code word read length
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* @is_last_read_loc: is this the last read location
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*
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* This function will set location register value
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*/
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void qcom_nandc_set_read_loc_first(struct qcom_nand_controller *nandc,
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int reg_base, u32 cw_offset,
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u32 read_size, u32 is_last_read_loc)
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{
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__le32 locreg_val;
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u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
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FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
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FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
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locreg_val = cpu_to_le32(val);
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if (reg_base == NAND_READ_LOCATION_0)
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nandc->regs->read_location0 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_1)
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nandc->regs->read_location1 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_2)
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nandc->regs->read_location2 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_3)
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nandc->regs->read_location3 = locreg_val;
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}
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EXPORT_SYMBOL(qcom_nandc_set_read_loc_first);
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/**
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* qcom_nandc_set_read_loc_last - to set read location last register
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* @nandc: NAND controller's private data
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* @reg_base: location register base
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* @cw_offset: code word offset
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* @read_size: code word read length
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* @is_last_read_loc: is this the last read location
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*
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* This function will set location last register value
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*/
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void qcom_nandc_set_read_loc_last(struct qcom_nand_controller *nandc,
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int reg_base, u32 cw_offset,
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u32 read_size, u32 is_last_read_loc)
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{
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__le32 locreg_val;
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u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
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FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
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FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
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locreg_val = cpu_to_le32(val);
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if (reg_base == NAND_READ_LOCATION_LAST_CW_0)
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nandc->regs->read_location_last0 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_LAST_CW_1)
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nandc->regs->read_location_last1 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_LAST_CW_2)
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nandc->regs->read_location_last2 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_LAST_CW_3)
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nandc->regs->read_location_last3 = locreg_val;
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}
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EXPORT_SYMBOL(qcom_nandc_set_read_loc_last);
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MODULE_DESCRIPTION("QPIC controller common api");
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MODULE_LICENSE("GPL");
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@ -149,68 +149,6 @@ static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw)
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return cw == (ecc->steps - 1);
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}
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/**
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* qcom_nandc_set_read_loc_first() - to set read location first register
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* @nandc: NAND controller's private data
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* @reg_base: location register base
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* @cw_offset: code word offset
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* @read_size: code word read length
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* @is_last_read_loc: is this the last read location
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*
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* This function will set location register value
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*/
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static void qcom_nandc_set_read_loc_first(struct qcom_nand_controller *nandc,
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int reg_base, u32 cw_offset,
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u32 read_size, u32 is_last_read_loc)
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{
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__le32 locreg_val;
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u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
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FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
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FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
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locreg_val = cpu_to_le32(val);
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if (reg_base == NAND_READ_LOCATION_0)
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nandc->regs->read_location0 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_1)
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nandc->regs->read_location1 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_2)
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nandc->regs->read_location2 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_3)
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nandc->regs->read_location3 = locreg_val;
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}
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/**
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* qcom_nandc_set_read_loc_last - to set read location last register
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* @nandc: NAND controller's private data
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* @reg_base: location register base
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* @cw_offset: code word offset
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* @read_size: code word read length
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* @is_last_read_loc: is this the last read location
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*
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* This function will set location last register value
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*/
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static void qcom_nandc_set_read_loc_last(struct qcom_nand_controller *nandc,
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int reg_base, u32 cw_offset,
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u32 read_size, u32 is_last_read_loc)
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{
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__le32 locreg_val;
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u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) |
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FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) |
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FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc);
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locreg_val = cpu_to_le32(val);
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if (reg_base == NAND_READ_LOCATION_LAST_CW_0)
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nandc->regs->read_location_last0 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_LAST_CW_1)
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nandc->regs->read_location_last1 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_LAST_CW_2)
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nandc->regs->read_location_last2 = locreg_val;
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else if (reg_base == NAND_READ_LOCATION_LAST_CW_3)
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nandc->regs->read_location_last3 = locreg_val;
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}
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/* helper to configure location register values */
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static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
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u32 cw_offset, u32 read_size, u32 is_last_read_loc)
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@ -301,22 +239,6 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, i
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host->cw_data : host->cw_size, 1);
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}
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/*
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* Helper to prepare DMA descriptors for configuring registers
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* before reading a NAND page.
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*/
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static void qcom_nandc_config_page_read(struct qcom_nand_controller *nandc)
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{
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qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
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if (!nandc->props->qpic_version2)
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qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_clr,
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NAND_ERASED_CW_DETECT_CFG, 1, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->erased_cw_detect_cfg_set,
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NAND_ERASED_CW_DETECT_CFG, 1, NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
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}
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/*
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* Helper to prepare DMA descriptors for configuring registers
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* before reading each codeword in NAND page.
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@ -361,35 +283,6 @@ config_nand_single_cw_page_read(struct nand_chip *chip,
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config_nand_cw_read(chip, use_ecc, cw);
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}
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/*
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* Helper to prepare DMA descriptors used to configure registers needed for
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* before writing a NAND page.
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*/
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static void qcom_nandc_config_page_write(struct qcom_nand_controller *nandc)
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{
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qcom_write_reg_dma(nandc, &nandc->regs->addr0, NAND_ADDR0, 2, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
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if (!nandc->props->qpic_version2)
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qcom_write_reg_dma(nandc, &nandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1,
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NAND_BAM_NEXT_SGL);
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}
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/*
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* Helper to prepare DMA descriptors for configuring registers
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* before writing each codeword in NAND page.
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*/
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static void qcom_nandc_config_cw_write(struct qcom_nand_controller *nandc)
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{
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qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
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qcom_write_reg_dma(nandc, &nandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
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qcom_read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
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qcom_write_reg_dma(nandc, &nandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
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qcom_write_reg_dma(nandc, &nandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
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NAND_BAM_NEXT_SGL);
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}
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/*
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* when using BCH ECC, the HW flags an error in NAND_FLASH_STATUS if it read
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* an erased CW, and reports an erased CW in NAND_ERASED_CW_DETECT_STATUS.
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@ -438,30 +331,6 @@ static bool erased_chunk_check_and_fixup(u8 *data_buf, int data_len)
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return true;
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}
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struct qcom_nandc_read_stats {
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__le32 flash;
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__le32 buffer;
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__le32 erased_cw;
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};
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/* reads back FLASH_STATUS register set by the controller */
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static int qcom_nandc_check_flash_errors(struct qcom_nand_controller *nandc,
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int cw_cnt)
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{
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int i;
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qcom_nandc_dev_to_mem(nandc, true);
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for (i = 0; i < cw_cnt; i++) {
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u32 flash = le32_to_cpu(nandc->reg_read_buf[i]);
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if (flash & (FS_OP_ERR | FS_MPU_ERR))
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return -EIO;
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}
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return 0;
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}
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/* performs raw read for one codeword */
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static int
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qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
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@ -457,6 +457,12 @@ struct qcom_nandc_props {
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bool use_codeword_fixup;
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};
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struct qcom_nandc_read_stats {
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__le32 flash;
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__le32 buffer;
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__le32 erased_cw;
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};
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void qcom_free_bam_transaction(struct qcom_nand_controller *nandc);
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struct bam_transaction *qcom_alloc_bam_transaction(struct qcom_nand_controller *nandc);
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void qcom_clear_bam_transaction(struct qcom_nand_controller *nandc);
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@ -482,5 +488,16 @@ int qcom_submit_descs(struct qcom_nand_controller *nandc);
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void qcom_clear_read_regs(struct qcom_nand_controller *nandc);
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void qcom_nandc_unalloc(struct qcom_nand_controller *nandc);
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int qcom_nandc_alloc(struct qcom_nand_controller *nandc);
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int qcom_nandc_check_flash_errors(struct qcom_nand_controller *nandc,
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int cw_cnt);
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void qcom_nandc_config_page_read(struct qcom_nand_controller *nandc);
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void qcom_nandc_config_page_write(struct qcom_nand_controller *nandc);
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void qcom_nandc_config_cw_write(struct qcom_nand_controller *nandc);
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void qcom_nandc_set_read_loc_first(struct qcom_nand_controller *nandc,
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int reg_base, u32 cw_offset,
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u32 read_size, u32 is_last_read_loc);
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void qcom_nandc_set_read_loc_last(struct qcom_nand_controller *nandc,
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int reg_base, u32 cw_offset,
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u32 read_size, u32 is_last_read_loc);
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#endif
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