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amd-drm-fixes-6.13-2025-01-15:
amdgpu: - SMU 13 fix - DP MST fixes - DCN 3.5 fix - PSR fixes - eDP fix - VRR fix - Enforce isolation fixes - GFX 12 fix - PSP 14.x fix -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQgO5Idg2tXNTSZAr293/aFa7yZ2AUCZ4fQTwAKCRC93/aFa7yZ 2DZ+AP4q+vj/IHhWNzZyZbmNVIzhuETll0xoGbRyKxKnGawrLQEAiFunHwFFV2Gs JDc4c9+rgRRhjdh8oq/8NdJhtRtMKww= =8WYx -----END PGP SIGNATURE----- Merge tag 'amd-drm-fixes-6.13-2025-01-15' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.13-2025-01-15: amdgpu: - SMU 13 fix - DP MST fixes - DCN 3.5 fix - PSR fixes - eDP fix - VRR fix - Enforce isolation fixes - GFX 12 fix - PSP 14.x fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250115151602.210704-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie
commit
cf8182d337
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@ -715,8 +715,9 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
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void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
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{
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enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE;
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if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
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((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) {
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if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
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((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) ||
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(IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) {
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pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
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amdgpu_gfx_off_ctrl(adev, idle);
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} else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &&
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@ -122,6 +122,10 @@ static int amdgpu_is_fw_attestation_supported(struct amdgpu_device *adev)
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if (adev->flags & AMD_IS_APU)
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return 0;
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if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 2) ||
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amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 3))
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return 0;
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if (adev->asic_type >= CHIP_SIENNA_CICHLID)
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return 1;
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@ -1989,6 +1989,7 @@ void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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u32 idx;
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bool sched_work = false;
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if (!adev->gfx.enable_cleaner_shader)
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return;
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@ -2007,15 +2008,19 @@ void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring)
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mutex_lock(&adev->enforce_isolation_mutex);
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if (adev->enforce_isolation[idx]) {
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if (adev->kfd.init_complete)
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amdgpu_gfx_kfd_sch_ctrl(adev, idx, false);
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sched_work = true;
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}
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mutex_unlock(&adev->enforce_isolation_mutex);
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if (sched_work)
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amdgpu_gfx_kfd_sch_ctrl(adev, idx, false);
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}
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void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring)
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{
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struct amdgpu_device *adev = ring->adev;
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u32 idx;
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bool sched_work = false;
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if (!adev->gfx.enable_cleaner_shader)
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return;
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@ -2031,9 +2036,12 @@ void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring)
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mutex_lock(&adev->enforce_isolation_mutex);
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if (adev->enforce_isolation[idx]) {
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if (adev->kfd.init_complete)
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amdgpu_gfx_kfd_sch_ctrl(adev, idx, true);
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sched_work = true;
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}
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mutex_unlock(&adev->enforce_isolation_mutex);
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if (sched_work)
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amdgpu_gfx_kfd_sch_ctrl(adev, idx, true);
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}
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/*
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@ -193,8 +193,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
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need_ctx_switch = ring->current_ctx != fence_ctx;
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if (ring->funcs->emit_pipeline_sync && job &&
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((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) ||
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(amdgpu_sriov_vf(adev) && need_ctx_switch) ||
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amdgpu_vm_need_pipeline_sync(ring, job))) {
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need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {
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need_pipe_sync = true;
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if (tmp)
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@ -8896,6 +8896,7 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
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struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
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struct amdgpu_dm_connector *aconn =
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(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
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bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
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if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
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if (pr->config.replay_supported && !pr->replay_feature_enabled)
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@ -8922,14 +8923,15 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
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* adequate number of fast atomic commits to notify KMD
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* of update events. See `vblank_control_worker()`.
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*/
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if (acrtc_attach->dm_irq_params.allow_sr_entry &&
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if (!vrr_active &&
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acrtc_attach->dm_irq_params.allow_sr_entry &&
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#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
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!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
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#endif
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(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
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if (pr->replay_feature_enabled && !pr->replay_allow_active)
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amdgpu_dm_replay_enable(acrtc_state->stream, true);
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if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
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if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
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!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
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amdgpu_dm_psr_enable(acrtc_state->stream);
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}
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@ -9100,7 +9102,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
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timestamp_ns;
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if (acrtc_state->stream->link->psr_settings.psr_allow_active)
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amdgpu_dm_psr_disable(acrtc_state->stream);
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amdgpu_dm_psr_disable(acrtc_state->stream, true);
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mutex_unlock(&dm->dc_lock);
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}
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}
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@ -9266,11 +9268,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
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bundle->stream_update.abm_level = &acrtc_state->abm_level;
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mutex_lock(&dm->dc_lock);
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if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
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if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) {
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if (acrtc_state->stream->link->replay_settings.replay_allow_active)
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amdgpu_dm_replay_disable(acrtc_state->stream);
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if (acrtc_state->stream->link->psr_settings.psr_allow_active)
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amdgpu_dm_psr_disable(acrtc_state->stream);
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amdgpu_dm_psr_disable(acrtc_state->stream, true);
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}
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mutex_unlock(&dm->dc_lock);
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@ -11379,6 +11381,25 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
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return 0;
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}
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static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,
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struct drm_atomic_state *state,
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struct drm_crtc_state *crtc_state)
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{
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struct drm_plane *plane;
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struct drm_plane_state *new_plane_state, *old_plane_state;
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drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
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new_plane_state = drm_atomic_get_plane_state(state, plane);
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old_plane_state = drm_atomic_get_plane_state(state, plane);
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if (old_plane_state->fb && new_plane_state->fb &&
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get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb))
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return true;
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}
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return false;
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}
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/**
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* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
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*
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@ -11576,10 +11597,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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/* Remove exiting planes if they are modified */
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for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
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if (old_plane_state->fb && new_plane_state->fb &&
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get_mem_type(old_plane_state->fb) !=
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get_mem_type(new_plane_state->fb))
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lock_and_validation_needed = true;
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ret = dm_update_plane_state(dc, state, plane,
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old_plane_state,
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@ -11874,9 +11891,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
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/*
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* Only allow async flips for fast updates that don't change
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* the FB pitch, the DCC state, rotation, etc.
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* the FB pitch, the DCC state, rotation, mem_type, etc.
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*/
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if (new_crtc_state->async_flip && lock_and_validation_needed) {
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if (new_crtc_state->async_flip &&
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(lock_and_validation_needed ||
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amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) {
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drm_dbg_atomic(crtc->dev,
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"[CRTC:%d:%s] async flips are only supported for fast updates\n",
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crtc->base.id, crtc->name);
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@ -697,6 +697,8 @@ struct amdgpu_dm_connector {
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struct drm_dp_mst_port *mst_output_port;
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struct amdgpu_dm_connector *mst_root;
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struct drm_dp_aux *dsc_aux;
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uint32_t mst_local_bw;
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uint16_t vc_full_pbn;
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struct mutex handle_mst_msg_ready;
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/* TODO see if we can merge with ddc_bus or make a dm_connector */
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@ -30,6 +30,7 @@
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#include "amdgpu_dm.h"
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#include "dc.h"
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#include "amdgpu_securedisplay.h"
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#include "amdgpu_dm_psr.h"
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static const char *const pipe_crc_sources[] = {
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"none",
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@ -224,6 +225,10 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
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mutex_lock(&adev->dm.dc_lock);
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/* For PSR1, check that the panel has exited PSR */
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if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
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amdgpu_dm_psr_wait_disable(stream_state);
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/* Enable or disable CRTC CRC generation */
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if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
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if (!dc_stream_configure_crc(stream_state->ctx->dc,
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@ -357,6 +362,17 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
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}
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/*
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* Reading the CRC requires the vblank interrupt handler to be
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* enabled. Keep a reference until CRC capture stops.
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*/
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enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
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if (!enabled && enable) {
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ret = drm_crtc_vblank_get(crtc);
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if (ret)
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goto cleanup;
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}
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#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
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/* Reset secure_display when we change crc source from debugfs */
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amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
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@ -367,16 +383,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
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goto cleanup;
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}
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/*
|
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* Reading the CRC requires the vblank interrupt handler to be
|
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* enabled. Keep a reference until CRC capture stops.
|
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*/
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enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
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if (!enabled && enable) {
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ret = drm_crtc_vblank_get(crtc);
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if (ret)
|
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goto cleanup;
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|
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if (dm_is_crc_source_dprx(source)) {
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if (drm_dp_start_crc(aux, crtc)) {
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DRM_DEBUG_DRIVER("dp start crc failed\n");
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|
|
|
|||
|
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@ -93,7 +93,7 @@ int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
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return rc;
|
||||
}
|
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|
||||
bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
|
||||
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
|
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{
|
||||
return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
|
||||
dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
|
||||
|
|
@ -142,7 +142,7 @@ static void amdgpu_dm_crtc_set_panel_sr_feature(
|
|||
amdgpu_dm_replay_enable(vblank_work->stream, true);
|
||||
} else if (vblank_enabled) {
|
||||
if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
|
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amdgpu_dm_psr_disable(vblank_work->stream);
|
||||
amdgpu_dm_psr_disable(vblank_work->stream, false);
|
||||
} else if (link->psr_settings.psr_feature_enabled &&
|
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allow_sr_entry && !is_sr_active && !is_crc_window_active) {
|
||||
|
||||
|
|
|
|||
|
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@ -37,7 +37,7 @@ int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable);
|
|||
|
||||
bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc);
|
||||
|
||||
bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state);
|
||||
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state);
|
||||
|
||||
int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc);
|
||||
|
||||
|
|
|
|||
|
|
@ -3606,7 +3606,7 @@ static int crc_win_update_set(void *data, u64 val)
|
|||
/* PSR may write to OTG CRC window control register,
|
||||
* so close it before starting secure_display.
|
||||
*/
|
||||
amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
|
||||
amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);
|
||||
|
||||
spin_lock_irq(&adev_to_drm(adev)->event_lock);
|
||||
|
||||
|
|
|
|||
|
|
@ -155,6 +155,17 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector)
|
||||
{
|
||||
aconnector->drm_edid = NULL;
|
||||
aconnector->dsc_aux = NULL;
|
||||
aconnector->mst_output_port->passthrough_aux = NULL;
|
||||
aconnector->mst_local_bw = 0;
|
||||
aconnector->vc_full_pbn = 0;
|
||||
}
|
||||
|
||||
static void
|
||||
amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
|
||||
{
|
||||
|
|
@ -182,9 +193,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
|
|||
|
||||
dc_sink_release(dc_sink);
|
||||
aconnector->dc_sink = NULL;
|
||||
aconnector->drm_edid = NULL;
|
||||
aconnector->dsc_aux = NULL;
|
||||
port->passthrough_aux = NULL;
|
||||
amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
|
||||
}
|
||||
|
||||
aconnector->mst_status = MST_STATUS_DEFAULT;
|
||||
|
|
@ -504,9 +513,7 @@ dm_dp_mst_detect(struct drm_connector *connector,
|
|||
|
||||
dc_sink_release(aconnector->dc_sink);
|
||||
aconnector->dc_sink = NULL;
|
||||
aconnector->drm_edid = NULL;
|
||||
aconnector->dsc_aux = NULL;
|
||||
port->passthrough_aux = NULL;
|
||||
amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
|
||||
|
||||
amdgpu_dm_set_mst_status(&aconnector->mst_status,
|
||||
MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
|
||||
|
|
@ -1819,9 +1826,18 @@ enum dc_status dm_dp_mst_is_port_support_mode(
|
|||
struct drm_dp_mst_port *immediate_upstream_port = NULL;
|
||||
uint32_t end_link_bw = 0;
|
||||
|
||||
/*Get last DP link BW capability*/
|
||||
if (dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw)) {
|
||||
if (stream_kbps > end_link_bw) {
|
||||
/*Get last DP link BW capability. Mode shall be supported by Legacy peer*/
|
||||
if (aconnector->mst_output_port->pdt != DP_PEER_DEVICE_DP_LEGACY_CONV &&
|
||||
aconnector->mst_output_port->pdt != DP_PEER_DEVICE_NONE) {
|
||||
if (aconnector->vc_full_pbn != aconnector->mst_output_port->full_pbn) {
|
||||
dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw);
|
||||
aconnector->vc_full_pbn = aconnector->mst_output_port->full_pbn;
|
||||
aconnector->mst_local_bw = end_link_bw;
|
||||
} else {
|
||||
end_link_bw = aconnector->mst_local_bw;
|
||||
}
|
||||
|
||||
if (end_link_bw > 0 && stream_kbps > end_link_bw) {
|
||||
DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
|
||||
"Mode required bw can't fit into last link\n");
|
||||
return DC_FAIL_BANDWIDTH_VALIDATE;
|
||||
|
|
@ -1835,11 +1851,15 @@ enum dc_status dm_dp_mst_is_port_support_mode(
|
|||
if (immediate_upstream_port) {
|
||||
virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn);
|
||||
virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
|
||||
if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
|
||||
DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
|
||||
"Max dsc compression can't fit into MST available bw\n");
|
||||
return DC_FAIL_BANDWIDTH_VALIDATE;
|
||||
}
|
||||
} else {
|
||||
/* For topology LCT 1 case - only one mstb*/
|
||||
virtual_channel_bw_in_kbps = root_link_bw_in_kbps;
|
||||
}
|
||||
|
||||
if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
|
||||
DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
|
||||
"Max dsc compression can't fit into MST available bw\n");
|
||||
return DC_FAIL_BANDWIDTH_VALIDATE;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -201,14 +201,13 @@ void amdgpu_dm_psr_enable(struct dc_stream_state *stream)
|
|||
*
|
||||
* Return: true if success
|
||||
*/
|
||||
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
|
||||
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait)
|
||||
{
|
||||
unsigned int power_opt = 0;
|
||||
bool psr_enable = false;
|
||||
|
||||
DRM_DEBUG_DRIVER("Disabling psr...\n");
|
||||
|
||||
return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
|
||||
return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -251,3 +250,33 @@ bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)
|
|||
|
||||
return allow_active;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR
|
||||
* @stream: stream state attached to the eDP link
|
||||
*
|
||||
* Waits for a max of 500ms for the eDP panel to exit PSR.
|
||||
*
|
||||
* Return: true if panel exited PSR, false otherwise.
|
||||
*/
|
||||
bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream)
|
||||
{
|
||||
enum dc_psr_state psr_state = PSR_STATE0;
|
||||
struct dc_link *link = stream->link;
|
||||
int retry_count;
|
||||
|
||||
if (link == NULL)
|
||||
return false;
|
||||
|
||||
for (retry_count = 0; retry_count <= 1000; retry_count++) {
|
||||
dc_link_get_psr_state(link, &psr_state);
|
||||
if (psr_state == PSR_STATE0)
|
||||
break;
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
if (retry_count == 1000)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,8 +34,9 @@
|
|||
void amdgpu_dm_set_psr_caps(struct dc_link *link);
|
||||
void amdgpu_dm_psr_enable(struct dc_stream_state *stream);
|
||||
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
|
||||
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
|
||||
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait);
|
||||
bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
|
||||
bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm);
|
||||
bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream);
|
||||
|
||||
#endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */
|
||||
|
|
|
|||
|
|
@ -63,7 +63,8 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,
|
|||
|
||||
bool should_use_dmub_lock(struct dc_link *link)
|
||||
{
|
||||
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
|
||||
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
|
||||
link->psr_settings.psr_version == DC_PSR_VERSION_1)
|
||||
return true;
|
||||
|
||||
if (link->replay_settings.replay_feature_enabled)
|
||||
|
|
|
|||
|
|
@ -195,9 +195,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
|
|||
.dcn_downspread_percent = 0.5,
|
||||
.gpuvm_min_page_size_bytes = 4096,
|
||||
.hostvm_min_page_size_bytes = 4096,
|
||||
.do_urgent_latency_adjustment = 1,
|
||||
.do_urgent_latency_adjustment = 0,
|
||||
.urgent_latency_adjustment_fabric_clock_component_us = 0,
|
||||
.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
|
||||
.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
|
||||
};
|
||||
|
||||
void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
|
||||
|
|
|
|||
|
|
@ -579,8 +579,8 @@ static void CalculateBytePerPixelAndBlockSizes(
|
|||
{
|
||||
*BytePerPixelDETY = 0;
|
||||
*BytePerPixelDETC = 0;
|
||||
*BytePerPixelY = 0;
|
||||
*BytePerPixelC = 0;
|
||||
*BytePerPixelY = 1;
|
||||
*BytePerPixelC = 1;
|
||||
|
||||
if (SourcePixelFormat == dml2_444_64) {
|
||||
*BytePerPixelDETY = 8;
|
||||
|
|
|
|||
|
|
@ -1398,12 +1398,12 @@ void dcn32_disable_link_output(struct dc_link *link,
|
|||
|
||||
link_hwss->disable_link_output(link, link_res, signal);
|
||||
link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
|
||||
|
||||
if (signal == SIGNAL_TYPE_EDP &&
|
||||
link->dc->hwss.edp_power_control &&
|
||||
!link->skip_implict_edp_power_control)
|
||||
link->dc->hwss.edp_power_control(link, false);
|
||||
else if (dmcu != NULL && dmcu->funcs->unlock_phy)
|
||||
/*
|
||||
* Add the logic to extract BOTH power up and power down sequences
|
||||
* from enable/disable link output and only call edp panel control
|
||||
* in enable_link_dp and disable_link_dp once.
|
||||
*/
|
||||
if (dmcu != NULL && dmcu->funcs->unlock_phy)
|
||||
dmcu->funcs->unlock_phy(dmcu);
|
||||
|
||||
dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
|
||||
|
|
|
|||
|
|
@ -2643,11 +2643,12 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
|
|||
&backend_workload_mask);
|
||||
|
||||
/* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
|
||||
if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
|
||||
((smu->adev->pm.fw_version == 0x004e6601) ||
|
||||
(smu->adev->pm.fw_version >= 0x004e7300))) ||
|
||||
(amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
|
||||
smu->adev->pm.fw_version >= 0x00504500)) {
|
||||
if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) &&
|
||||
((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
|
||||
((smu->adev->pm.fw_version == 0x004e6601) ||
|
||||
(smu->adev->pm.fw_version >= 0x004e7300))) ||
|
||||
(amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
|
||||
smu->adev->pm.fw_version >= 0x00504500))) {
|
||||
workload_type = smu_cmn_to_asic_specific_index(smu,
|
||||
CMN2ASIC_MAPPING_WORKLOAD,
|
||||
PP_SMC_POWER_PROFILE_POWERSAVING);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user