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drm/amd/display: bandwidth update fix
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
Alex Deucher
parent
45209ef719
commit
cf43759306
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@ -795,159 +795,6 @@ static bool streams_changed(
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return false;
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}
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static void fill_display_configs(
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const struct validate_context *context,
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struct dm_pp_display_configuration *pp_display_cfg)
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{
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int j;
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int num_cfgs = 0;
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for (j = 0; j < context->stream_count; j++) {
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int k;
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const struct core_stream *stream = context->streams[j];
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struct dm_pp_single_disp_config *cfg =
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&pp_display_cfg->disp_configs[num_cfgs];
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const struct pipe_ctx *pipe_ctx = NULL;
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for (k = 0; k < MAX_PIPES; k++)
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if (stream == context->res_ctx.pipe_ctx[k].stream) {
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pipe_ctx = &context->res_ctx.pipe_ctx[k];
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break;
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}
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ASSERT(pipe_ctx != NULL);
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num_cfgs++;
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cfg->signal = pipe_ctx->stream->signal;
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cfg->pipe_idx = pipe_ctx->pipe_idx;
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cfg->src_height = stream->public.src.height;
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cfg->src_width = stream->public.src.width;
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cfg->ddi_channel_mapping =
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stream->sink->link->ddi_channel_mapping.raw;
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cfg->transmitter =
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stream->sink->link->link_enc->transmitter;
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cfg->link_settings.lane_count =
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stream->sink->link->public.cur_link_settings.lane_count;
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cfg->link_settings.link_rate =
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stream->sink->link->public.cur_link_settings.link_rate;
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cfg->link_settings.link_spread =
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stream->sink->link->public.cur_link_settings.link_spread;
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cfg->sym_clock = stream->phy_pix_clk;
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/* Round v_refresh*/
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cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
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cfg->v_refresh /= stream->public.timing.h_total;
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cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
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/ stream->public.timing.v_total;
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}
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pp_display_cfg->display_count = num_cfgs;
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}
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static uint32_t get_min_vblank_time_us(const struct validate_context *context)
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{
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uint8_t j;
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uint32_t min_vertical_blank_time = -1;
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for (j = 0; j < context->stream_count; j++) {
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const struct dc_stream *stream = &context->streams[j]->public;
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uint32_t vertical_blank_in_pixels = 0;
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uint32_t vertical_blank_time = 0;
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vertical_blank_in_pixels = stream->timing.h_total *
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(stream->timing.v_total
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- stream->timing.v_addressable);
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vertical_blank_time = vertical_blank_in_pixels
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* 1000 / stream->timing.pix_clk_khz;
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if (min_vertical_blank_time > vertical_blank_time)
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min_vertical_blank_time = vertical_blank_time;
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}
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return min_vertical_blank_time;
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}
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static int determine_sclk_from_bounding_box(
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const struct core_dc *dc,
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int required_sclk)
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{
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int i;
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/*
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* Some asics do not give us sclk levels, so we just report the actual
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* required sclk
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*/
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if (dc->sclk_lvls.num_levels == 0)
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return required_sclk;
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for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
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if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
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return dc->sclk_lvls.clocks_in_khz[i];
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}
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/*
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* even maximum level could not satisfy requirement, this
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* is unexpected at this stage, should have been caught at
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* validation time
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*/
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ASSERT(0);
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return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
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}
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void pplib_apply_display_requirements(
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struct core_dc *dc,
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const struct validate_context *context,
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struct dm_pp_display_configuration *pp_display_cfg)
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{
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pp_display_cfg->all_displays_in_sync =
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context->bw_results.all_displays_in_sync;
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pp_display_cfg->nb_pstate_switch_disable =
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context->bw_results.nbp_state_change_enable == false;
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pp_display_cfg->cpu_cc6_disable =
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context->bw_results.cpuc_state_change_enable == false;
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pp_display_cfg->cpu_pstate_disable =
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context->bw_results.cpup_state_change_enable == false;
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pp_display_cfg->cpu_pstate_separation_time =
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context->bw_results.blackout_recovery_time_us;
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pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
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/ MEMORY_TYPE_MULTIPLIER;
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pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
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dc,
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context->bw_results.required_sclk);
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pp_display_cfg->min_engine_clock_deep_sleep_khz
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= context->bw_results.required_sclk_deep_sleep;
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pp_display_cfg->avail_mclk_switch_time_us =
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get_min_vblank_time_us(context);
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/* TODO: dce11.2*/
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pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
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pp_display_cfg->disp_clk_khz = context->dispclk_khz;
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fill_display_configs(context, pp_display_cfg);
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/* TODO: is this still applicable?*/
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if (pp_display_cfg->display_count == 1) {
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const struct dc_crtc_timing *timing =
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&context->streams[0]->public.timing;
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pp_display_cfg->crtc_index =
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pp_display_cfg->disp_configs[0].pipe_idx;
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pp_display_cfg->line_time_in_us = timing->h_total * 1000
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/ timing->pix_clk_khz;
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}
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if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
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struct dm_pp_display_configuration)) != 0)
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dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
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dc->prev_display_config = *pp_display_cfg;
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}
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bool dc_commit_streams(
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struct dc *dc,
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const struct dc_stream *streams[],
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@ -1036,9 +883,6 @@ bool dc_commit_streams(
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context->streams[i]->public.timing.pix_clk_khz);
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}
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pplib_apply_display_requirements(core_dc,
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context, &context->pp_display_cfg);
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resource_validate_ctx_destruct(core_dc->current_context);
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if (core_dc->temp_flip_context != core_dc->current_context) {
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@ -1065,7 +909,6 @@ bool dc_pre_update_surfaces_to_stream(
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{
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int i, j;
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struct core_dc *core_dc = DC_TO_CORE(dc);
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int prev_disp_clk = core_dc->current_context->dispclk_khz;
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struct dc_stream_status *stream_status = NULL;
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struct validate_context *context;
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bool ret = true;
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@ -1150,16 +993,7 @@ bool dc_pre_update_surfaces_to_stream(
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goto unexpected_fail;
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}
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if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)
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&& prev_disp_clk < context->dispclk_khz) {
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pplib_apply_display_requirements(core_dc, context,
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&context->pp_display_cfg);
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context->res_ctx.pool->display_clock->funcs->set_clock(
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context->res_ctx.pool->display_clock,
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context->dispclk_khz * 115 / 100);
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core_dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
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core_dc->current_context->dispclk_khz = context->dispclk_khz;
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}
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core_dc->hwss.set_bandwidth(core_dc, context, false);
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for (i = 0; i < new_surface_count; i++)
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for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
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@ -1206,10 +1040,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
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return false;
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}
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core_dc->hwss.set_bandwidth(core_dc);
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/*TODO: dce specific*/
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pplib_apply_display_requirements(core_dc, context, &context->pp_display_cfg);
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core_dc->hwss.set_bandwidth(core_dc, context, true);
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resource_validate_ctx_destruct(core_dc->current_context);
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core_dc->current_context = context;
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@ -104,22 +104,18 @@ static bool dce100_enable_display_power_gating(
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return false;
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}
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static void set_display_mark_for_pipe_if_needed(struct core_dc *dc,
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struct pipe_ctx *pipe_ctx,
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struct validate_context *context)
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{
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/* Do nothing until we have proper bandwitdth calcs */
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}
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static void set_displaymarks(
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const struct core_dc *dc, struct validate_context *context)
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{
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/* Do nothing until we have proper bandwitdth calcs */
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}
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static void set_bandwidth(struct core_dc *dc)
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static void set_bandwidth(
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struct core_dc *dc,
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struct validate_context *context,
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bool decrease_allowed)
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{
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/* Do nothing until we have proper bandwitdth calcs */
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dc->hwss.set_displaymarks(dc, context);
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}
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@ -132,7 +128,6 @@ bool dce100_hw_sequencer_construct(struct core_dc *dc)
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/* TODO: dce80 is empty implementation at the moment*/
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dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
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dc->hwss.set_displaymarks = set_displaymarks;
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dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
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dc->hwss.set_bandwidth = set_bandwidth;
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return true;
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@ -1209,93 +1209,6 @@ static uint32_t compute_pstate_blackout_duration(
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return total_dest_line_time_ns;
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}
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/* get the index of the pipe_ctx if there were no gaps in the pipe_ctx array*/
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int get_bw_result_idx(
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struct resource_context *res_ctx,
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int pipe_idx)
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{
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int i, collapsed_idx;
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if (res_ctx->pipe_ctx[pipe_idx].top_pipe)
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return 3;
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collapsed_idx = 0;
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for (i = 0; i < pipe_idx; i++) {
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if (res_ctx->pipe_ctx[i].stream)
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collapsed_idx++;
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}
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return collapsed_idx;
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}
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static bool is_watermark_set_a_greater(
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const struct bw_watermarks *set_a,
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const struct bw_watermarks *set_b)
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{
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if (set_a->a_mark > set_b->a_mark
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|| set_a->b_mark > set_b->b_mark
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|| set_a->c_mark > set_b->c_mark
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|| set_a->d_mark > set_b->d_mark)
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return true;
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return false;
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}
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static bool did_watermarks_increase(
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struct pipe_ctx *pipe_ctx,
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struct validate_context *context,
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struct validate_context *old_context)
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{
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int collapsed_pipe_idx = get_bw_result_idx(&context->res_ctx,
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pipe_ctx->pipe_idx);
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int old_collapsed_pipe_idx = get_bw_result_idx(&old_context->res_ctx,
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pipe_ctx->pipe_idx);
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struct pipe_ctx *old_pipe_ctx = &old_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
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if (!old_pipe_ctx->stream)
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return true;
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if (is_watermark_set_a_greater(
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&context->bw_results.nbp_state_change_wm_ns[collapsed_pipe_idx],
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&old_context->bw_results.nbp_state_change_wm_ns[old_collapsed_pipe_idx]))
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return true;
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if (is_watermark_set_a_greater(
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&context->bw_results.stutter_exit_wm_ns[collapsed_pipe_idx],
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&old_context->bw_results.stutter_exit_wm_ns[old_collapsed_pipe_idx]))
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return true;
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if (is_watermark_set_a_greater(
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&context->bw_results.urgent_wm_ns[collapsed_pipe_idx],
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&old_context->bw_results.urgent_wm_ns[old_collapsed_pipe_idx]))
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return true;
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return false;
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}
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static void program_wm_for_pipe(struct core_dc *dc,
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struct pipe_ctx *pipe_ctx,
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struct validate_context *context)
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{
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int total_dest_line_time_ns = compute_pstate_blackout_duration(
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dc->bw_vbios.blackout_duration,
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pipe_ctx->stream);
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int bw_result_idx = get_bw_result_idx(&context->res_ctx,
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pipe_ctx->pipe_idx);
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pipe_ctx->mi->funcs->mem_input_program_display_marks(
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pipe_ctx->mi,
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context->bw_results.nbp_state_change_wm_ns[bw_result_idx],
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context->bw_results.stutter_exit_wm_ns[bw_result_idx],
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context->bw_results.urgent_wm_ns[bw_result_idx],
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total_dest_line_time_ns);
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if (pipe_ctx->top_pipe)
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pipe_ctx->mi->funcs->mem_input_program_chroma_display_marks(
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pipe_ctx->mi,
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context->bw_results.nbp_state_change_wm_ns[bw_result_idx + 1],
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context->bw_results.stutter_exit_wm_ns[bw_result_idx + 1],
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context->bw_results.urgent_wm_ns[bw_result_idx + 1],
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total_dest_line_time_ns);
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}
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void dce110_set_displaymarks(
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const struct core_dc *dc,
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struct validate_context *context)
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@ -1589,7 +1502,7 @@ static void reset_hw_ctx_wrap(
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}
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}
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/*TODO: const validate_context*/
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enum dc_status dce110_apply_ctx_to_hw(
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struct core_dc *dc,
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struct validate_context *context)
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@ -1768,7 +1681,7 @@ enum dc_status dce110_apply_ctx_to_hw(
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return status;
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}
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dc->hwss.set_displaymarks(dc, context);
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dc->hwss.set_bandwidth(dc, context, true);
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/* to save power */
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apply_min_clocks(dc, context, &clocks_state, false);
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@ -1777,6 +1690,7 @@ enum dc_status dce110_apply_ctx_to_hw(
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switch_dp_clock_sources(dc, &context->res_ctx);
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return DC_OK;
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}
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@ -2135,7 +2049,6 @@ static void init_hw(struct core_dc *dc)
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}
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}
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/* TODO: move this to apply_ctx_tohw some how?*/
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static void dce110_power_on_pipe_if_needed(
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struct core_dc *dc,
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struct pipe_ctx *pipe_ctx,
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@ -2180,31 +2093,175 @@ static void dce110_power_on_pipe_if_needed(
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}
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}
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static void dce110_increase_watermarks_for_pipe(
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struct core_dc *dc,
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struct pipe_ctx *pipe_ctx,
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struct validate_context *context)
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static void fill_display_configs(
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const struct validate_context *context,
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struct dm_pp_display_configuration *pp_display_cfg)
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{
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if (did_watermarks_increase(pipe_ctx, context, dc->current_context))
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program_wm_for_pipe(dc, pipe_ctx, context);
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int j;
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int num_cfgs = 0;
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for (j = 0; j < context->stream_count; j++) {
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int k;
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const struct core_stream *stream = context->streams[j];
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struct dm_pp_single_disp_config *cfg =
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&pp_display_cfg->disp_configs[num_cfgs];
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const struct pipe_ctx *pipe_ctx = NULL;
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for (k = 0; k < MAX_PIPES; k++)
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if (stream == context->res_ctx.pipe_ctx[k].stream) {
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pipe_ctx = &context->res_ctx.pipe_ctx[k];
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break;
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}
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ASSERT(pipe_ctx != NULL);
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num_cfgs++;
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cfg->signal = pipe_ctx->stream->signal;
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cfg->pipe_idx = pipe_ctx->pipe_idx;
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cfg->src_height = stream->public.src.height;
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cfg->src_width = stream->public.src.width;
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cfg->ddi_channel_mapping =
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stream->sink->link->ddi_channel_mapping.raw;
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cfg->transmitter =
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stream->sink->link->link_enc->transmitter;
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cfg->link_settings.lane_count =
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stream->sink->link->public.cur_link_settings.lane_count;
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cfg->link_settings.link_rate =
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stream->sink->link->public.cur_link_settings.link_rate;
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cfg->link_settings.link_spread =
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stream->sink->link->public.cur_link_settings.link_spread;
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cfg->sym_clock = stream->phy_pix_clk;
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/* Round v_refresh*/
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cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000;
|
||||
cfg->v_refresh /= stream->public.timing.h_total;
|
||||
cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2)
|
||||
/ stream->public.timing.v_total;
|
||||
}
|
||||
|
||||
pp_display_cfg->display_count = num_cfgs;
|
||||
}
|
||||
|
||||
static void dce110_set_bandwidth(struct core_dc *dc)
|
||||
static uint32_t get_min_vblank_time_us(const struct validate_context *context)
|
||||
{
|
||||
uint8_t j;
|
||||
uint32_t min_vertical_blank_time = -1;
|
||||
|
||||
for (j = 0; j < context->stream_count; j++) {
|
||||
const struct dc_stream *stream = &context->streams[j]->public;
|
||||
uint32_t vertical_blank_in_pixels = 0;
|
||||
uint32_t vertical_blank_time = 0;
|
||||
|
||||
vertical_blank_in_pixels = stream->timing.h_total *
|
||||
(stream->timing.v_total
|
||||
- stream->timing.v_addressable);
|
||||
|
||||
vertical_blank_time = vertical_blank_in_pixels
|
||||
* 1000 / stream->timing.pix_clk_khz;
|
||||
|
||||
if (min_vertical_blank_time > vertical_blank_time)
|
||||
min_vertical_blank_time = vertical_blank_time;
|
||||
}
|
||||
|
||||
return min_vertical_blank_time;
|
||||
}
|
||||
|
||||
static int determine_sclk_from_bounding_box(
|
||||
const struct core_dc *dc,
|
||||
int required_sclk)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < dc->current_context->res_ctx.pool->pipe_count; i++) {
|
||||
struct pipe_ctx *pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
|
||||
/*
|
||||
* Some asics do not give us sclk levels, so we just report the actual
|
||||
* required sclk
|
||||
*/
|
||||
if (dc->sclk_lvls.num_levels == 0)
|
||||
return required_sclk;
|
||||
|
||||
if (!pipe_ctx->stream)
|
||||
continue;
|
||||
for (i = 0; i < dc->sclk_lvls.num_levels; i++) {
|
||||
if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk)
|
||||
return dc->sclk_lvls.clocks_in_khz[i];
|
||||
}
|
||||
/*
|
||||
* even maximum level could not satisfy requirement, this
|
||||
* is unexpected at this stage, should have been caught at
|
||||
* validation time
|
||||
*/
|
||||
ASSERT(0);
|
||||
return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
|
||||
}
|
||||
|
||||
program_wm_for_pipe(dc, pipe_ctx, dc->current_context);
|
||||
static void pplib_apply_display_requirements(
|
||||
struct core_dc *dc,
|
||||
struct validate_context *context)
|
||||
{
|
||||
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
|
||||
|
||||
pp_display_cfg->all_displays_in_sync =
|
||||
context->bw_results.all_displays_in_sync;
|
||||
pp_display_cfg->nb_pstate_switch_disable =
|
||||
context->bw_results.nbp_state_change_enable == false;
|
||||
pp_display_cfg->cpu_cc6_disable =
|
||||
context->bw_results.cpuc_state_change_enable == false;
|
||||
pp_display_cfg->cpu_pstate_disable =
|
||||
context->bw_results.cpup_state_change_enable == false;
|
||||
pp_display_cfg->cpu_pstate_separation_time =
|
||||
context->bw_results.blackout_recovery_time_us;
|
||||
|
||||
pp_display_cfg->min_memory_clock_khz = context->bw_results.required_yclk
|
||||
/ MEMORY_TYPE_MULTIPLIER;
|
||||
|
||||
pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
|
||||
dc,
|
||||
context->bw_results.required_sclk);
|
||||
|
||||
pp_display_cfg->min_engine_clock_deep_sleep_khz
|
||||
= context->bw_results.required_sclk_deep_sleep;
|
||||
|
||||
pp_display_cfg->avail_mclk_switch_time_us =
|
||||
get_min_vblank_time_us(context);
|
||||
/* TODO: dce11.2*/
|
||||
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
|
||||
|
||||
pp_display_cfg->disp_clk_khz = context->dispclk_khz;
|
||||
|
||||
fill_display_configs(context, pp_display_cfg);
|
||||
|
||||
/* TODO: is this still applicable?*/
|
||||
if (pp_display_cfg->display_count == 1) {
|
||||
const struct dc_crtc_timing *timing =
|
||||
&context->streams[0]->public.timing;
|
||||
|
||||
pp_display_cfg->crtc_index =
|
||||
pp_display_cfg->disp_configs[0].pipe_idx;
|
||||
pp_display_cfg->line_time_in_us = timing->h_total * 1000
|
||||
/ timing->pix_clk_khz;
|
||||
}
|
||||
|
||||
dc->current_context->res_ctx.pool->display_clock->funcs->set_clock(
|
||||
dc->current_context->res_ctx.pool->display_clock,
|
||||
dc->current_context->dispclk_khz * 115 / 100);
|
||||
if (memcmp(&dc->prev_display_config, pp_display_cfg, sizeof(
|
||||
struct dm_pp_display_configuration)) != 0)
|
||||
dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
|
||||
|
||||
dc->prev_display_config = *pp_display_cfg;
|
||||
}
|
||||
|
||||
static void dce110_set_bandwidth(
|
||||
struct core_dc *dc,
|
||||
struct validate_context *context,
|
||||
bool decrease_allowed)
|
||||
{
|
||||
dc->hwss.set_displaymarks(dc, context);
|
||||
|
||||
if (decrease_allowed || context->dispclk_khz > dc->current_context->dispclk_khz) {
|
||||
context->res_ctx.pool->display_clock->funcs->set_clock(
|
||||
context->res_ctx.pool->display_clock,
|
||||
context->dispclk_khz * 115 / 100);
|
||||
dc->current_context->bw_results.dispclk_khz = context->dispclk_khz;
|
||||
dc->current_context->dispclk_khz = context->dispclk_khz;
|
||||
}
|
||||
|
||||
pplib_apply_display_requirements(dc, context);
|
||||
}
|
||||
|
||||
static void dce110_program_front_end_for_pipe(
|
||||
|
|
@ -2335,15 +2392,6 @@ static void dce110_program_front_end_for_pipe(
|
|||
pipe_ctx->scl_data.recout.y);
|
||||
}
|
||||
|
||||
static void dce110_prepare_pipe_for_context(
|
||||
struct core_dc *dc,
|
||||
struct pipe_ctx *pipe_ctx,
|
||||
struct validate_context *context)
|
||||
{
|
||||
dce110_power_on_pipe_if_needed(dc, pipe_ctx, context);
|
||||
dc->hwss.increase_watermarks_for_pipe(dc, pipe_ctx, context);
|
||||
}
|
||||
|
||||
static void dce110_apply_ctx_for_surface(
|
||||
struct core_dc *dc,
|
||||
struct core_surface *surface,
|
||||
|
|
@ -2388,7 +2436,7 @@ static void dce110_power_down_fe(struct core_dc *dc, struct pipe_ctx *pipe)
|
|||
static const struct hw_sequencer_funcs dce110_funcs = {
|
||||
.init_hw = init_hw,
|
||||
.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
|
||||
.prepare_pipe_for_context = dce110_prepare_pipe_for_context,
|
||||
.prepare_pipe_for_context = dce110_power_on_pipe_if_needed,
|
||||
.apply_ctx_for_surface = dce110_apply_ctx_for_surface,
|
||||
.set_plane_config = set_plane_config,
|
||||
.update_plane_addr = update_plane_addr,
|
||||
|
|
@ -2407,7 +2455,6 @@ static const struct hw_sequencer_funcs dce110_funcs = {
|
|||
.power_down_front_end = dce110_power_down_fe,
|
||||
.pipe_control_lock = dce_pipe_control_lock,
|
||||
.set_displaymarks = dce110_set_displaymarks,
|
||||
.increase_watermarks_for_pipe = dce110_increase_watermarks_for_pipe,
|
||||
.set_bandwidth = dce110_set_bandwidth,
|
||||
.set_drr = set_drr,
|
||||
.set_static_screen_control = set_static_screen_control,
|
||||
|
|
|
|||
|
|
@ -106,23 +106,18 @@ static bool dce80_enable_display_power_gating(
|
|||
return false;
|
||||
}
|
||||
|
||||
|
||||
static void set_display_mark_for_pipe_if_needed(struct core_dc *dc,
|
||||
struct pipe_ctx *pipe_ctx,
|
||||
struct validate_context *context)
|
||||
{
|
||||
/* Do nothing until we have proper bandwitdth calcs */
|
||||
}
|
||||
|
||||
static void set_displaymarks(
|
||||
const struct core_dc *dc, struct validate_context *context)
|
||||
{
|
||||
/* Do nothing until we have proper bandwitdth calcs */
|
||||
}
|
||||
|
||||
static void set_bandwidth(struct core_dc *dc)
|
||||
static void set_bandwidth(
|
||||
struct core_dc *dc,
|
||||
struct validate_context *context,
|
||||
bool decrease_allowed)
|
||||
{
|
||||
/* Do nothing until we have proper bandwitdth calcs */
|
||||
dc->hwss.set_displaymarks(dc, context);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -133,7 +128,6 @@ bool dce80_hw_sequencer_construct(struct core_dc *dc)
|
|||
dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
|
||||
dc->hwss.pipe_control_lock = dce_pipe_control_lock;
|
||||
dc->hwss.set_displaymarks = set_displaymarks;
|
||||
dc->hwss.increase_watermarks_for_pipe = set_display_mark_for_pipe_if_needed;
|
||||
dc->hwss.set_bandwidth = set_bandwidth;
|
||||
|
||||
return true;
|
||||
|
|
|
|||
|
|
@ -124,11 +124,10 @@ struct hw_sequencer_funcs {
|
|||
const struct core_dc *dc,
|
||||
struct validate_context *context);
|
||||
|
||||
void (*increase_watermarks_for_pipe)(struct core_dc *dc,
|
||||
struct pipe_ctx *pipe_ctx,
|
||||
struct validate_context *context);
|
||||
|
||||
void (*set_bandwidth)(struct core_dc *dc);
|
||||
void (*set_bandwidth)(
|
||||
struct core_dc *dc,
|
||||
struct validate_context *context,
|
||||
bool decrease_allowed);
|
||||
|
||||
void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,
|
||||
int vmin, int vmax);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user