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spi: spi-qpic-snand: Fix ECC_CFG_ECC_DISABLE shift in qcom_spi_read_last_cw()
The ECC_CFG_ECC_DISABLE define is BIT(0). It's supposed to be used
directly instead of used as a shifter.
Fixes: 7304d19090 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://patch.msgid.link/2f4b0a0b-2c03-41c0-8a4a-3d789a83832d@stanley.mountain
Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -514,7 +514,7 @@ static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
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cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
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0 << CW_PER_PAGE;
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cfg1 = ecc_cfg->cfg1_raw;
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ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
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ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
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snandc->regs->cmd = snandc->qspi->cmd;
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snandc->regs->cfg0 = cpu_to_le32(cfg0);
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