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mlxsw: reg: Add SGCR.lag_lookup_pgt_base

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Add SGCR.lag_lookup_pgt_base, which is used for configuring the base
address of the LAG table within the PGT table for cases when the driver
is responsible for the table placement.

Signed-off-by: Petr Machata <petrm@nvidia.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Petr Machata 2023-10-19 12:27:11 +02:00 committed by David S. Miller
parent 66eaaa8541
commit cf0a86e8ce
1 changed files with 10 additions and 1 deletions
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11
drivers/net/ethernet/mellanox/mlxsw/reg.h
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@ -38,9 +38,18 @@ static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
static inline void mlxsw_reg_sgcr_pack(char *payload)
/* reg_sgcr_lag_lookup_pgt_base
* Base address used for lookup in PGT table
* Supported when CONFIG_PROFILE.lag_mode = 1
* Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries.
* Access: RW
*/
MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);
static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base)
{
MLXSW_REG_ZERO(sgcr, payload);
mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base);
}
/* SPAD - Switch Physical Address Register