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drm/i915/lt_phy: Create macro for LT PHY PLL state

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Create a macro for PLL state for LT PHY similar as
for cx0 case.

v2:
- Move addition of LT_PHY_PLL_DP/HDMI_PARAMS() to this patch.
- Fix end of table checking while looking up a table.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260119093757.2850233-8-mika.kahola@intel.com
This commit is contained in:
Mika Kahola 2026-01-19 09:37:48 +00:00
parent 52801b2eb5
commit cf0635d40a
1 changed files with 50 additions and 33 deletions
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83
drivers/gpu/drm/i915/display/intel_lt_phy.c
View File

@ -437,15 +437,32 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = {
},
};
static const struct intel_lt_phy_pll_state * const xe3plpd_lt_dp_tables[] = {
&xe3plpd_lt_dp_rbr,
&xe3plpd_lt_dp_hbr1,
&xe3plpd_lt_dp_hbr2,
&xe3plpd_lt_dp_hbr3,
&xe3plpd_lt_dp_uhbr10,
&xe3plpd_lt_dp_uhbr13_5,
&xe3plpd_lt_dp_uhbr20,
NULL,
struct intel_lt_phy_pll_params {
const char *name;
bool is_hdmi;
int clock_rate;
const struct intel_lt_phy_pll_state *state;
};
#define __LT_PHY_PLL_PARAMS(__is_hdmi, __clock_rate, __state) { \
.name = __stringify(__state), \
.is_hdmi = __is_hdmi, \
.clock_rate = __clock_rate, \
.state = &__state, \
}
#define LT_PHY_PLL_HDMI_PARAMS(__clock_rate, __state) __LT_PHY_PLL_PARAMS(true, __clock_rate, __state)
#define LT_PHY_PLL_DP_PARAMS(__clock_rate, __state) __LT_PHY_PLL_PARAMS(false, __clock_rate, __state)
static const struct intel_lt_phy_pll_params xe3plpd_lt_dp_tables[] = {
LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr),
LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1),
LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2),
LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3),
LT_PHY_PLL_DP_PARAMS(1000000, xe3plpd_lt_dp_uhbr10),
LT_PHY_PLL_DP_PARAMS(1350000, xe3plpd_lt_dp_uhbr13_5),
LT_PHY_PLL_DP_PARAMS(2000000, xe3plpd_lt_dp_uhbr20),
{}
};
static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = {
@ -718,17 +735,17 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = {
},
};
static const struct intel_lt_phy_pll_state * const xe3plpd_lt_edp_tables[] = {
&xe3plpd_lt_dp_rbr,
&xe3plpd_lt_edp_2_16,
&xe3plpd_lt_edp_2_43,
&xe3plpd_lt_dp_hbr1,
&xe3plpd_lt_edp_3_24,
&xe3plpd_lt_edp_4_32,
&xe3plpd_lt_dp_hbr2,
&xe3plpd_lt_edp_6_75,
&xe3plpd_lt_dp_hbr3,
NULL,
static const struct intel_lt_phy_pll_params xe3plpd_lt_edp_tables[] = {
LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr),
LT_PHY_PLL_DP_PARAMS(216000, xe3plpd_lt_edp_2_16),
LT_PHY_PLL_DP_PARAMS(243000, xe3plpd_lt_edp_2_43),
LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1),
LT_PHY_PLL_DP_PARAMS(324000, xe3plpd_lt_edp_3_24),
LT_PHY_PLL_DP_PARAMS(432000, xe3plpd_lt_edp_4_32),
LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2),
LT_PHY_PLL_DP_PARAMS(675000, xe3plpd_lt_edp_6_75),
LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3),
{}
};
static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = {
@ -1001,13 +1018,13 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
},
};
static const struct intel_lt_phy_pll_state * const xe3plpd_lt_hdmi_tables[] = {
&xe3plpd_lt_hdmi_252,
&xe3plpd_lt_hdmi_272,
&xe3plpd_lt_hdmi_742p5,
&xe3plpd_lt_hdmi_1p485,
&xe3plpd_lt_hdmi_5p94,
NULL,
static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
LT_PHY_PLL_HDMI_PARAMS(27200, xe3plpd_lt_hdmi_272),
LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
{}
};
static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder)
@ -1346,7 +1363,7 @@ static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, struct r
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
}
static const struct intel_lt_phy_pll_state * const *
static const struct intel_lt_phy_pll_params *
intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@ -1735,7 +1752,7 @@ intel_lt_phy_calc_hdmi_port_clock(struct intel_display *display,
if (d8 == 0) {
drm_WARN_ON(display->drm,
"Invalid port clock using lowest HDMI portclock\n");
return xe3plpd_lt_hdmi_252.clock;
return xe3plpd_lt_hdmi_tables[0].clock_rate;
}
m2div_int = (pll_reg_3 & REG_GENMASK(14, 5)) >> 5;
temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32;
@ -1779,16 +1796,16 @@ int
intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
const struct intel_lt_phy_pll_state * const *tables;
const struct intel_lt_phy_pll_params *tables;
int i;
tables = intel_lt_phy_pll_tables_get(crtc_state, encoder);
if (!tables)
return -EINVAL;
for (i = 0; tables[i]; i++) {
if (crtc_state->port_clock == tables[i]->clock) {
crtc_state->dpll_hw_state.ltpll = *tables[i];
for (i = 0; tables[i].name; i++) {
if (crtc_state->port_clock == tables[i].clock_rate) {
crtc_state->dpll_hw_state.ltpll = *tables[i].state;
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
crtc_state->dpll_hw_state.ltpll.config[2] = 1;