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RISC-V: KVM: Introduce common kvm_riscv_isa_check_host()

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Rename kvm_riscv_vcpu_isa_check_host() to kvm_riscv_isa_check_host()
and use it as common function with KVM RISC-V to check isa extensions
supported by host.

Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com>
Reviewed-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260120080013.2153519-5-anup.patel@oss.qualcomm.com
Signed-off-by: Anup Patel <anup@brainfault.org>
This commit is contained in:
Anup Patel 2026-01-20 13:29:50 +05:30 committed by Anup Patel
parent 1ec8bea903
commit cf05b059d5
7 changed files with 33 additions and 27 deletions
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4
arch/riscv/include/asm/kvm_host.h
View File

@ -311,6 +311,10 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch); void __kvm_riscv_switch_to(struct kvm_vcpu_arch *vcpu_arch);
int __kvm_riscv_isa_check_host(unsigned long kvm_ext, unsigned long *guest_ext);
#define kvm_riscv_isa_check_host(ext) \
__kvm_riscv_isa_check_host(KVM_RISCV_ISA_EXT_##ext, NULL)
void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu);
unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu); unsigned long kvm_riscv_vcpu_num_regs(struct kvm_vcpu *vcpu);
int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu, int kvm_riscv_vcpu_copy_reg_indices(struct kvm_vcpu *vcpu,

2
arch/riscv/kvm/aia_device.c
View File

@ -23,7 +23,7 @@ static int aia_create(struct kvm_device *dev, u32 type)
if (irqchip_in_kernel(kvm)) if (irqchip_in_kernel(kvm))
return -EEXIST; return -EEXIST;
if (!riscv_isa_extension_available(NULL, SSAIA)) if (kvm_riscv_isa_check_host(SSAIA))
return -ENODEV; return -ENODEV;
ret = -EBUSY; ret = -EBUSY;

8
arch/riscv/kvm/vcpu_fp.c
View File

@ -60,17 +60,17 @@ void kvm_riscv_vcpu_guest_fp_restore(struct kvm_cpu_context *cntx,
void kvm_riscv_vcpu_host_fp_save(struct kvm_cpu_context *cntx) void kvm_riscv_vcpu_host_fp_save(struct kvm_cpu_context *cntx)
{ {
/* No need to check host sstatus as it can be modified outside */ /* No need to check host sstatus as it can be modified outside */
if (riscv_isa_extension_available(NULL, d)) if (!kvm_riscv_isa_check_host(D))
__kvm_riscv_fp_d_save(cntx); __kvm_riscv_fp_d_save(cntx);
else if (riscv_isa_extension_available(NULL, f)) else if (!kvm_riscv_isa_check_host(F))
__kvm_riscv_fp_f_save(cntx); __kvm_riscv_fp_f_save(cntx);
} }
void kvm_riscv_vcpu_host_fp_restore(struct kvm_cpu_context *cntx) void kvm_riscv_vcpu_host_fp_restore(struct kvm_cpu_context *cntx)
{ {
if (riscv_isa_extension_available(NULL, d)) if (!kvm_riscv_isa_check_host(D))
__kvm_riscv_fp_d_restore(cntx); __kvm_riscv_fp_d_restore(cntx);
else if (riscv_isa_extension_available(NULL, f)) else if (!kvm_riscv_isa_check_host(F))
__kvm_riscv_fp_f_restore(cntx); __kvm_riscv_fp_f_restore(cntx);
} }
#endif #endif

38
arch/riscv/kvm/vcpu_onereg.c
View File

@ -120,7 +120,7 @@ static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
return KVM_RISCV_ISA_EXT_MAX; return KVM_RISCV_ISA_EXT_MAX;
} }
static int kvm_riscv_vcpu_isa_check_host(unsigned long kvm_ext, unsigned long *guest_ext) int __kvm_riscv_isa_check_host(unsigned long kvm_ext, unsigned long *base_ext)
{ {
unsigned long host_ext; unsigned long host_ext;
@ -129,8 +129,7 @@ static int kvm_riscv_vcpu_isa_check_host(unsigned long kvm_ext, unsigned long *g
return -ENOENT; return -ENOENT;
kvm_ext = array_index_nospec(kvm_ext, ARRAY_SIZE(kvm_isa_ext_arr)); kvm_ext = array_index_nospec(kvm_ext, ARRAY_SIZE(kvm_isa_ext_arr));
*guest_ext = kvm_isa_ext_arr[kvm_ext]; switch (kvm_isa_ext_arr[kvm_ext]) {
switch (*guest_ext) {
case RISCV_ISA_EXT_SMNPM: case RISCV_ISA_EXT_SMNPM:
/* /*
* Pointer masking effective in (H)S-mode is provided by the * Pointer masking effective in (H)S-mode is provided by the
@ -141,13 +140,16 @@ static int kvm_riscv_vcpu_isa_check_host(unsigned long kvm_ext, unsigned long *g
host_ext = RISCV_ISA_EXT_SSNPM; host_ext = RISCV_ISA_EXT_SSNPM;
break; break;
default: default:
host_ext = *guest_ext; host_ext = kvm_isa_ext_arr[kvm_ext];
break; break;
} }
if (!__riscv_isa_extension_available(NULL, host_ext)) if (!__riscv_isa_extension_available(NULL, host_ext))
return -ENOENT; return -ENOENT;
if (base_ext)
*base_ext = kvm_isa_ext_arr[kvm_ext];
return 0; return 0;
} }
@ -158,7 +160,7 @@ static bool kvm_riscv_vcpu_isa_enable_allowed(unsigned long ext)
return false; return false;
case KVM_RISCV_ISA_EXT_SSCOFPMF: case KVM_RISCV_ISA_EXT_SSCOFPMF:
/* Sscofpmf depends on interrupt filtering defined in ssaia */ /* Sscofpmf depends on interrupt filtering defined in ssaia */
return __riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SSAIA); return !kvm_riscv_isa_check_host(SSAIA);
case KVM_RISCV_ISA_EXT_SVADU: case KVM_RISCV_ISA_EXT_SVADU:
/* /*
* The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero.
@ -265,7 +267,7 @@ void kvm_riscv_vcpu_setup_isa(struct kvm_vcpu *vcpu)
unsigned long guest_ext, i; unsigned long guest_ext, i;
for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) { for (i = 0; i < ARRAY_SIZE(kvm_isa_ext_arr); i++) {
if (kvm_riscv_vcpu_isa_check_host(i, &guest_ext)) if (__kvm_riscv_isa_check_host(i, &guest_ext))
continue; continue;
if (kvm_riscv_vcpu_isa_enable_allowed(i)) if (kvm_riscv_vcpu_isa_enable_allowed(i))
set_bit(guest_ext, vcpu->arch.isa); set_bit(guest_ext, vcpu->arch.isa);
@ -290,17 +292,17 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK;
break; break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
if (!riscv_isa_extension_available(NULL, ZICBOM)) if (kvm_riscv_isa_check_host(ZICBOM))
return -ENOENT; return -ENOENT;
reg_val = riscv_cbom_block_size; reg_val = riscv_cbom_block_size;
break; break;
case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
if (!riscv_isa_extension_available(NULL, ZICBOZ)) if (kvm_riscv_isa_check_host(ZICBOZ))
return -ENOENT; return -ENOENT;
reg_val = riscv_cboz_block_size; reg_val = riscv_cboz_block_size;
break; break;
case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size): case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
if (!riscv_isa_extension_available(NULL, ZICBOP)) if (kvm_riscv_isa_check_host(ZICBOP))
return -ENOENT; return -ENOENT;
reg_val = riscv_cbop_block_size; reg_val = riscv_cbop_block_size;
break; break;
@ -384,19 +386,19 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
} }
break; break;
case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
if (!riscv_isa_extension_available(NULL, ZICBOM)) if (kvm_riscv_isa_check_host(ZICBOM))
return -ENOENT; return -ENOENT;
if (reg_val != riscv_cbom_block_size) if (reg_val != riscv_cbom_block_size)
return -EINVAL; return -EINVAL;
break; break;
case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
if (!riscv_isa_extension_available(NULL, ZICBOZ)) if (kvm_riscv_isa_check_host(ZICBOZ))
return -ENOENT; return -ENOENT;
if (reg_val != riscv_cboz_block_size) if (reg_val != riscv_cboz_block_size)
return -EINVAL; return -EINVAL;
break; break;
case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size): case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
if (!riscv_isa_extension_available(NULL, ZICBOP)) if (kvm_riscv_isa_check_host(ZICBOP))
return -ENOENT; return -ENOENT;
if (reg_val != riscv_cbop_block_size) if (reg_val != riscv_cbop_block_size)
return -EINVAL; return -EINVAL;
@ -682,7 +684,7 @@ static int riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu,
unsigned long guest_ext; unsigned long guest_ext;
int ret; int ret;
ret = kvm_riscv_vcpu_isa_check_host(reg_num, &guest_ext); ret = __kvm_riscv_isa_check_host(reg_num, &guest_ext);
if (ret) if (ret)
return ret; return ret;
@ -700,7 +702,7 @@ static int riscv_vcpu_set_isa_ext_single(struct kvm_vcpu *vcpu,
unsigned long guest_ext; unsigned long guest_ext;
int ret; int ret;
ret = kvm_riscv_vcpu_isa_check_host(reg_num, &guest_ext); ret = __kvm_riscv_isa_check_host(reg_num, &guest_ext);
if (ret) if (ret)
return ret; return ret;
@ -859,13 +861,13 @@ static int copy_config_reg_indices(const struct kvm_vcpu *vcpu,
* was not available. * was not available.
*/ */
if (i == KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) && if (i == KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) &&
!riscv_isa_extension_available(NULL, ZICBOM)) kvm_riscv_isa_check_host(ZICBOM))
continue; continue;
else if (i == KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) && else if (i == KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) &&
!riscv_isa_extension_available(NULL, ZICBOZ)) kvm_riscv_isa_check_host(ZICBOZ))
continue; continue;
else if (i == KVM_REG_RISCV_CONFIG_REG(zicbop_block_size) && else if (i == KVM_REG_RISCV_CONFIG_REG(zicbop_block_size) &&
!riscv_isa_extension_available(NULL, ZICBOP)) kvm_riscv_isa_check_host(ZICBOP))
continue; continue;
size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; size = IS_ENABLED(CONFIG_32BIT) ? KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
@ -1086,7 +1088,7 @@ static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu,
KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64;
u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i; u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i;
if (kvm_riscv_vcpu_isa_check_host(i, &guest_ext)) if (__kvm_riscv_isa_check_host(i, &guest_ext))
continue; continue;
if (uindices) { if (uindices) {

2
arch/riscv/kvm/vcpu_pmu.c
View File

@ -845,7 +845,7 @@ void kvm_riscv_vcpu_pmu_init(struct kvm_vcpu *vcpu)
* filtering is available in the host. Otherwise, guest will always count * filtering is available in the host. Otherwise, guest will always count
* events while the execution is in hypervisor mode. * events while the execution is in hypervisor mode.
*/ */
if (!riscv_isa_extension_available(NULL, SSCOFPMF)) if (kvm_riscv_isa_check_host(SSCOFPMF))
return; return;
ret = riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs); ret = riscv_pmu_get_hpm_info(&hpm_width, &num_hw_ctrs);

2
arch/riscv/kvm/vcpu_timer.c
View File

@ -253,7 +253,7 @@ int kvm_riscv_vcpu_timer_init(struct kvm_vcpu *vcpu)
t->next_set = false; t->next_set = false;
/* Enable sstc for every vcpu if available in hardware */ /* Enable sstc for every vcpu if available in hardware */
if (riscv_isa_extension_available(NULL, SSTC)) { if (!kvm_riscv_isa_check_host(SSTC)) {
t->sstc_enabled = true; t->sstc_enabled = true;
hrtimer_setup(&t->hrt, kvm_riscv_vcpu_vstimer_expired, CLOCK_MONOTONIC, hrtimer_setup(&t->hrt, kvm_riscv_vcpu_vstimer_expired, CLOCK_MONOTONIC,
HRTIMER_MODE_REL); HRTIMER_MODE_REL);

4
arch/riscv/kvm/vcpu_vector.c
View File

@ -63,13 +63,13 @@ void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx,
void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx) void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx)
{ {
/* No need to check host sstatus as it can be modified outside */ /* No need to check host sstatus as it can be modified outside */
if (riscv_isa_extension_available(NULL, v)) if (!kvm_riscv_isa_check_host(V))
__kvm_riscv_vector_save(cntx); __kvm_riscv_vector_save(cntx);
} }
void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx) void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx)
{ {
if (riscv_isa_extension_available(NULL, v)) if (!kvm_riscv_isa_check_host(V))
__kvm_riscv_vector_restore(cntx); __kvm_riscv_vector_restore(cntx);
} }