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PCI: dwc: Support 16-lane operation

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Some hosts support 16 lanes of PCIe. Make num-lanes accept that number.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250926-topic-pcie_16ln-v1-1-c249acc18790@oss.qualcomm.com
This commit is contained in:
Konrad Dybcio 2025-09-26 14:22:45 +02:00 committed by Bjorn Helgaas
parent 8f5ae30d69
commit cef730075c
2 changed files with 4 additions and 0 deletions
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3
drivers/pci/controller/dwc/pcie-designware.c
View File

@ -841,6 +841,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
case 8:
plc |= PORT_LINK_MODE_8_LANES;
break;
case 16:
plc |= PORT_LINK_MODE_16_LANES;
break;
default:
dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
return;

1
drivers/pci/controller/dwc/pcie-designware.h
View File

@ -90,6 +90,7 @@
#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
#define PORT_LINK_MODE_16_LANES PORT_LINK_MODE(0x1f)
#define PCIE_PORT_LANE_SKEW 0x714
#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)