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Allwinner clock changes for 4.19
Our usual bunch of clock patches, this time to enable the A64 display engine clocks controller mostly. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAltXJ4QACgkQ0rTAlCFN r3Rv+g//ftUY11izKMlgE0rlQKJIx4MMEsndBQbXpNtkRVdsfvzYoPi36ax/B23R IC1GPRUNZdBTrrnh7bkcF1rXnCr7VQxT5rUwExKMmIV6+vjO1hfEldaF+Q8Ee2cu S8qBRorQn9Uk9dpDJwnfxZkqTW2a0652dHeT3Z76zAHtbsJ0FZCvR58qldoCxdff vCnjYMuPWyAolbkjcqHk/nNJKXerJf+0ILUwhc8SfBb321eQoqiA7bwm93lGlovG MTspY+156Fjhfi06dWSF7zxOKMW8MzopUUetawDpXzbSfbqYswg3xEMrAyGDWuUV +0E58qUvQoxSjWX4v7ZmUnA3Q6bKu+q1GX4GF+MTZTK2KSqlZs3fFdyf80lbrBDl KsQYn+68R5VpYA5aDcS4A2Su5SqSnfwBEjX9UnI+j2aIjD2zN7rShUHcV1t+n65w GWxdrcePT7/abC4Ke/td5DbZtnWxZ04muX7i56kT8zA6KJM+bta20ngA/hrTerQt FIP3hOVo5miWFDBodXqAXsdjAZS+ejoJ6HTDOlzwYoY8SaUaVE6uxCDqhvrj9jlo 0FxiYlYU4U19IV58OIcb8ddOKoipoFozKO4wK/igtAI+OWWiuNUDVHIibzzgWVdK zdF6Mqa04esXvZ5Q+1iVPa/xaOuxdZu+qDNqpY/GNhewioP2QQc= =RWXZ -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clock changes for 4.19 from Maxime Ripard: Our usual bunch of clock patches, this time to enable the A64 display engine clocks controller mostly. * tag 'sunxi-clk-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs
This commit is contained in:
Stephen Boyd
commit
cec5dfa4e4
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@ -6,6 +6,7 @@ Required properties :
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- "allwinner,sun8i-a83t-de2-clk"
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- "allwinner,sun8i-h3-de2-clk"
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- "allwinner,sun8i-v3s-de2-clk"
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- "allwinner,sun50i-a64-de2-clk"
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- "allwinner,sun50i-h5-de2-clk"
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- reg: Must contain the registers base address and length
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@ -288,17 +288,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
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.compatible = "allwinner,sun8i-v3s-de2-clk",
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.data = &sun8i_v3s_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun50i-a64-de2-clk",
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.data = &sun50i_a64_de2_clk_desc,
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},
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{
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.compatible = "allwinner,sun50i-h5-de2-clk",
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.data = &sun50i_a64_de2_clk_desc,
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},
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/*
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* The Allwinner A64 SoC needs some bit to be poke in syscon to make
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* DE2 really working.
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* So there's currently no A64 compatible here.
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* H5 shares the same reset line with A64, so here H5 is using the
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* clock description of A64.
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*/
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{ }
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};
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@ -66,17 +66,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
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CLK_SET_RATE_UNGATE);
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/* TODO: The result of N/M is required to be in [8, 25] range. */
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
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"osc24M", 0x0010,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
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"osc24M", 0x0010,
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192000000, /* Minimum rate */
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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/* TODO: The result of N/M is required to be in [8, 25] range. */
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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@ -152,17 +153,18 @@ static struct ccu_nk pll_periph1_clk = {
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};
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/* TODO: The result of N/M is required to be in [8, 25] range. */
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
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"osc24M", 0x030,
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
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"osc24M", 0x030,
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192000000, /* Minimum rate */
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8, 7, /* N */
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0, 4, /* M */
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BIT(24), /* frac enable */
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BIT(25), /* frac select */
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270000000, /* frac rate 0 */
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297000000, /* frac rate 1 */
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BIT(31), /* gate */
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BIT(28), /* lock */
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CLK_SET_RATE_UNGATE);
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static struct ccu_nkm pll_sata_clk = {
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.enable = BIT(31),
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@ -654,7 +656,8 @@ static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
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static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
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static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
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0x104, 0, 4, 24, 3, BIT(31), 0);
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0x104, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
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0x108, 0, 4, 24, 3, BIT(31), 0);
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@ -666,9 +669,11 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
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static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
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0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
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0x118, 0, 4, 24, 3, BIT(31), 0);
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0x118, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
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0x11c, 0, 4, 24, 3, BIT(31), 0);
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0x11c, 0, 4, 24, 3, BIT(31),
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CLK_SET_RATE_PARENT);
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static const char * const deinterlace_parents[] = { "pll-periph0",
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"pll-periph1" };
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@ -698,7 +703,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
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static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
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0x150, 0, 4, 24, 2, BIT(31), 0);
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0x150, 0, 4, 24, 2, BIT(31),
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CLK_SET_RATE_PARENT);
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static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
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0x154, BIT(31), 0);
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@ -25,7 +25,9 @@
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#define CLK_PLL_AUDIO_2X 4
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#define CLK_PLL_AUDIO_4X 5
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#define CLK_PLL_AUDIO_8X 6
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#define CLK_PLL_VIDEO0 7
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/* PLL_VIDEO0 is exported */
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#define CLK_PLL_VIDEO0_2X 8
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#define CLK_PLL_VE 9
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#define CLK_PLL_DDR0 10
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@ -34,7 +36,9 @@
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#define CLK_PLL_PERIPH0_2X 13
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#define CLK_PLL_PERIPH1 14
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#define CLK_PLL_PERIPH1_2X 15
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#define CLK_PLL_VIDEO1 16
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/* PLL_VIDEO1 is exported */
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#define CLK_PLL_VIDEO1_2X 17
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#define CLK_PLL_SATA 18
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#define CLK_PLL_SATA_OUT 19
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@ -43,6 +43,10 @@
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#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
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#define _DT_BINDINGS_CLK_SUN8I_R40_H_
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#define CLK_PLL_VIDEO0 7
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#define CLK_PLL_VIDEO1 16
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#define CLK_CPU 24
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#define CLK_BUS_MIPI_DSI 29
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