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drm/amd/pm: retire smu_13_0_6 mca dump support
retire smu_13_0_6 mca dump support Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Ce Sun <cesun102@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ce Sun
Alex Deucher
parent
75b10b24fd
commit
ceac787584
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@ -44,7 +44,6 @@
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#include "amdgpu_xgmi.h"
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#include <linux/pci.h>
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#include "amdgpu_ras.h"
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#include "amdgpu_mca.h"
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#include "smu_cmn.h"
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#include "mp/mp_13_0_6_offset.h"
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#include "mp/mp_13_0_6_sh_mask.h"
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@ -98,25 +97,6 @@ static const struct smu_feature_bits smu_v13_0_6_dpm_features = {
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
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#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
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#define LINK_SPEED_MAX 4
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#define MCA_BANK_IPID(_ip, _hwid, _type) \
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[AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
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struct mca_bank_ipid {
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enum amdgpu_mca_ip ip;
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uint16_t hwid;
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uint16_t mcatype;
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};
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struct mca_ras_info {
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enum amdgpu_ras_block blkid;
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enum amdgpu_mca_ip ip;
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int *err_code_array;
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int err_code_count;
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int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
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bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
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};
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#define P2S_TABLE_ID_A 0x50325341
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#define P2S_TABLE_ID_X 0x50325358
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@ -1942,17 +1922,6 @@ static int smu_v13_0_6_notify_unload(struct smu_context *smu)
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return 0;
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}
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static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
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{
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/* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
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if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
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return 0;
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return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
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enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
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NULL);
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}
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static int smu_v13_0_6_system_features_control(struct smu_context *smu,
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bool enable)
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{
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@ -3298,471 +3267,6 @@ static int smu_v13_0_6_post_init(struct smu_context *smu)
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return 0;
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}
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static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
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{
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struct smu_context *smu = adev->powerplay.pp_handle;
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return smu_v13_0_6_mca_set_debug_mode(smu, enable);
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}
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static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
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{
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uint32_t msg;
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int ret;
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if (!count)
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return -EINVAL;
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switch (type) {
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case AMDGPU_MCA_ERROR_TYPE_UE:
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msg = SMU_MSG_QueryValidMcaCount;
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break;
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case AMDGPU_MCA_ERROR_TYPE_CE:
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msg = SMU_MSG_QueryValidMcaCeCount;
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break;
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default:
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return -EINVAL;
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}
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ret = smu_cmn_send_smc_msg(smu, msg, count);
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if (ret) {
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*count = 0;
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return ret;
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}
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return 0;
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}
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static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
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int idx, int offset, uint32_t *val)
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{
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uint32_t msg, param;
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switch (type) {
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case AMDGPU_MCA_ERROR_TYPE_UE:
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msg = SMU_MSG_McaBankDumpDW;
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break;
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case AMDGPU_MCA_ERROR_TYPE_CE:
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msg = SMU_MSG_McaBankCeDumpDW;
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break;
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default:
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return -EINVAL;
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}
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param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
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return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
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}
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static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
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int idx, int offset, uint32_t *val, int count)
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{
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int ret, i;
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if (!val)
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return -EINVAL;
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for (i = 0; i < count; i++) {
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ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
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MCA_BANK_IPID(UMC, 0x96, 0x0),
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MCA_BANK_IPID(SMU, 0x01, 0x1),
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MCA_BANK_IPID(MP5, 0x01, 0x2),
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MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
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};
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static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
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{
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u64 ipid = entry->regs[MCA_REG_IDX_IPID];
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u32 instidhi, instid;
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/* NOTE: All MCA IPID register share the same format,
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* so the driver can share the MCMP1 register header file.
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* */
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info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
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info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
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/*
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* Unfied DieID Format: SAASS. A:AID, S:Socket.
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* Unfied DieID[4] = InstanceId[0]
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* Unfied DieID[0:3] = InstanceIdHi[0:3]
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*/
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instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
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instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
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info->aid = ((instidhi >> 2) & 0x03);
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info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
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}
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static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
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int idx, int reg_idx, uint64_t *val)
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{
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struct smu_context *smu = adev->powerplay.pp_handle;
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uint32_t data[2] = {0, 0};
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int ret;
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if (!val || reg_idx >= MCA_REG_IDX_COUNT)
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return -EINVAL;
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ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
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if (ret)
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return ret;
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*val = (uint64_t)data[1] << 32 | data[0];
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dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
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type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
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return 0;
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}
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static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
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int idx, struct mca_bank_entry *entry)
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{
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int i, ret;
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/* NOTE: populated all mca register by default */
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for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
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ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
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if (ret)
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return ret;
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}
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entry->idx = idx;
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entry->type = type;
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mca_bank_entry_info_decode(entry, &entry->info);
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return 0;
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}
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static int mca_decode_ipid_to_hwip(uint64_t val)
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{
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const struct mca_bank_ipid *ipid;
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uint16_t hwid, mcatype;
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int i;
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hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
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mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
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for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
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ipid = &smu_v13_0_6_mca_ipid_table[i];
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if (!ipid->hwid)
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continue;
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if (ipid->hwid == hwid && ipid->mcatype == mcatype)
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return i;
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}
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return AMDGPU_MCA_IP_UNKNOW;
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}
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static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
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{
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uint64_t status0;
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uint32_t ext_error_code;
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uint32_t odecc_err_cnt;
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status0 = entry->regs[MCA_REG_IDX_STATUS];
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ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
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odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
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if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
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*count = 0;
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return 0;
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}
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if (umc_v12_0_is_deferred_error(adev, status0) ||
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umc_v12_0_is_uncorrectable_error(adev, status0) ||
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umc_v12_0_is_correctable_error(adev, status0))
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*count = (ext_error_code == 0) ? odecc_err_cnt : 1;
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amdgpu_umc_update_ecc_status(adev,
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entry->regs[MCA_REG_IDX_STATUS],
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entry->regs[MCA_REG_IDX_IPID],
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entry->regs[MCA_REG_IDX_ADDR]);
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return 0;
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}
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static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
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uint32_t *count)
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{
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u32 ext_error_code;
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u32 err_cnt;
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ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
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err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
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if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
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(ext_error_code == 0 || ext_error_code == 9))
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*count = err_cnt;
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else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
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*count = err_cnt;
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return 0;
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}
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static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
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uint32_t errcode)
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{
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int i;
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if (!mca_ras->err_code_count || !mca_ras->err_code_array)
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return true;
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for (i = 0; i < mca_ras->err_code_count; i++) {
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if (errcode == mca_ras->err_code_array[i])
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return true;
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}
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return false;
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}
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static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
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{
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uint64_t status0, misc0;
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status0 = entry->regs[MCA_REG_IDX_STATUS];
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if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
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*count = 0;
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return 0;
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}
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if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
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REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
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REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
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*count = 1;
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return 0;
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} else {
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misc0 = entry->regs[MCA_REG_IDX_MISC0];
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*count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
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}
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return 0;
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}
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static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
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{
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uint64_t status0, misc0;
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status0 = entry->regs[MCA_REG_IDX_STATUS];
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if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
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*count = 0;
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return 0;
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}
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if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
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REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
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REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
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if (count)
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*count = 1;
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return 0;
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}
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misc0 = entry->regs[MCA_REG_IDX_MISC0];
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*count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
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return 0;
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}
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static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
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{
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uint32_t instlo;
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instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
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instlo &= GENMASK(31, 1);
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switch (instlo) {
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case 0x36430400: /* SMNAID XCD 0 */
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case 0x38430400: /* SMNAID XCD 1 */
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case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
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return true;
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default:
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return false;
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}
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return false;
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};
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static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
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enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
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{
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struct smu_context *smu = adev->powerplay.pp_handle;
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uint32_t errcode, instlo;
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instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
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instlo &= GENMASK(31, 1);
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if (instlo != 0x03b30400)
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return false;
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if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
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errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
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errcode &= 0xff;
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} else {
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errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
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}
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return mca_smu_check_error_code(adev, mca_ras, errcode);
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}
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static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
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static int mmhub_err_codes[] = {
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CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
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CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
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CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
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};
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static int vcn_err_codes[] = {
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CODE_VIDD, CODE_VIDV,
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};
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static int jpeg_err_codes[] = {
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CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
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CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
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CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
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CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
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};
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static const struct mca_ras_info mca_ras_table[] = {
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{
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.blkid = AMDGPU_RAS_BLOCK__UMC,
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.ip = AMDGPU_MCA_IP_UMC,
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.get_err_count = mca_umc_mca_get_err_count,
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}, {
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.blkid = AMDGPU_RAS_BLOCK__GFX,
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.ip = AMDGPU_MCA_IP_SMU,
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.get_err_count = mca_gfx_mca_get_err_count,
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.bank_is_valid = mca_gfx_smu_bank_is_valid,
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}, {
|
||||
.blkid = AMDGPU_RAS_BLOCK__SDMA,
|
||||
.ip = AMDGPU_MCA_IP_SMU,
|
||||
.err_code_array = sdma_err_codes,
|
||||
.err_code_count = ARRAY_SIZE(sdma_err_codes),
|
||||
.get_err_count = mca_smu_mca_get_err_count,
|
||||
.bank_is_valid = mca_smu_bank_is_valid,
|
||||
}, {
|
||||
.blkid = AMDGPU_RAS_BLOCK__MMHUB,
|
||||
.ip = AMDGPU_MCA_IP_SMU,
|
||||
.err_code_array = mmhub_err_codes,
|
||||
.err_code_count = ARRAY_SIZE(mmhub_err_codes),
|
||||
.get_err_count = mca_smu_mca_get_err_count,
|
||||
.bank_is_valid = mca_smu_bank_is_valid,
|
||||
}, {
|
||||
.blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
|
||||
.ip = AMDGPU_MCA_IP_PCS_XGMI,
|
||||
.get_err_count = mca_pcs_xgmi_mca_get_err_count,
|
||||
}, {
|
||||
.blkid = AMDGPU_RAS_BLOCK__VCN,
|
||||
.ip = AMDGPU_MCA_IP_SMU,
|
||||
.err_code_array = vcn_err_codes,
|
||||
.err_code_count = ARRAY_SIZE(vcn_err_codes),
|
||||
.get_err_count = mca_smu_mca_get_err_count,
|
||||
.bank_is_valid = mca_smu_bank_is_valid,
|
||||
}, {
|
||||
.blkid = AMDGPU_RAS_BLOCK__JPEG,
|
||||
.ip = AMDGPU_MCA_IP_SMU,
|
||||
.err_code_array = jpeg_err_codes,
|
||||
.err_code_count = ARRAY_SIZE(jpeg_err_codes),
|
||||
.get_err_count = mca_smu_mca_get_err_count,
|
||||
.bank_is_valid = mca_smu_bank_is_valid,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
|
||||
if (mca_ras_table[i].blkid == blkid)
|
||||
return &mca_ras_table[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
|
||||
{
|
||||
struct smu_context *smu = adev->powerplay.pp_handle;
|
||||
int ret;
|
||||
|
||||
switch (type) {
|
||||
case AMDGPU_MCA_ERROR_TYPE_UE:
|
||||
case AMDGPU_MCA_ERROR_TYPE_CE:
|
||||
ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
|
||||
enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
|
||||
{
|
||||
if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
|
||||
return false;
|
||||
|
||||
if (mca_ras->bank_is_valid)
|
||||
return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
|
||||
struct mca_bank_entry *entry, uint32_t *count)
|
||||
{
|
||||
const struct mca_ras_info *mca_ras;
|
||||
|
||||
if (!entry || !count)
|
||||
return -EINVAL;
|
||||
|
||||
mca_ras = mca_get_mca_ras_info(adev, blk);
|
||||
if (!mca_ras)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
|
||||
*count = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
|
||||
}
|
||||
|
||||
static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
|
||||
enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
|
||||
{
|
||||
return mca_get_mca_entry(adev, type, idx, entry);
|
||||
}
|
||||
|
||||
static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
|
||||
enum amdgpu_mca_error_type type, uint32_t *count)
|
||||
{
|
||||
return mca_get_valid_mca_count(adev, type, count);
|
||||
}
|
||||
|
||||
static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
|
||||
.max_ue_count = 12,
|
||||
.max_ce_count = 12,
|
||||
.mca_set_debug_mode = mca_smu_set_debug_mode,
|
||||
.mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
|
||||
.mca_get_mca_entry = mca_smu_get_mca_entry,
|
||||
.mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
|
||||
};
|
||||
|
||||
static void smu_v13_0_6_set_temp_funcs(struct smu_context *smu)
|
||||
{
|
||||
smu->smu_temp.temp_funcs = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)
|
||||
|
|
@ -3868,6 +3372,5 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
|
|||
smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
|
||||
smu_v13_0_init_msg_ctl(smu, message_map);
|
||||
smu_v13_0_6_set_temp_funcs(smu);
|
||||
amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user