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KVM: arm64: pkvm: Use a single function to expose all id-regs

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Rather than exposing a whole set of helper functions to retrieve
individual ID registers, use the existing decoding tree and expose
a single helper instead.

This allow a number of functions to be made static, and we now
have a single entry point to maintain.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Fuad Tabba <tabba@google.com>
Tested-by: Fuad Tabba <tabba@google.com>
Link: https://lore.kernel.org/r/20211013120346.2926621-3-maz@kernel.org
This commit is contained in:
Marc Zyngier 2021-10-13 13:03:37 +01:00
parent 8a049862c3
commit ce75916749
3 changed files with 26 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm64/kvm/hyp/include/nvhe/sys_regs.h
View File

@ -9,19 +9,7 @@
#include <asm/kvm_host.h>
u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu);
u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu);
u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id);
bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code);
int kvm_check_pvm_sysreg_table(void);
void inject_undef64(struct kvm_vcpu *vcpu);

10
arch/arm64/kvm/hyp/nvhe/pkvm.c
View File

@ -15,7 +15,7 @@
*/
static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = get_pvm_id_aa64pfr0(vcpu);
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR0_EL1);
u64 hcr_set = HCR_RW;
u64 hcr_clear = 0;
u64 cptr_set = 0;
@ -62,7 +62,7 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu)
*/
static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = get_pvm_id_aa64pfr1(vcpu);
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64PFR1_EL1);
u64 hcr_set = 0;
u64 hcr_clear = 0;
@ -81,7 +81,7 @@ static void pvm_init_traps_aa64pfr1(struct kvm_vcpu *vcpu)
*/
static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = get_pvm_id_aa64dfr0(vcpu);
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64DFR0_EL1);
u64 mdcr_set = 0;
u64 mdcr_clear = 0;
u64 cptr_set = 0;
@ -125,7 +125,7 @@ static void pvm_init_traps_aa64dfr0(struct kvm_vcpu *vcpu)
*/
static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = get_pvm_id_aa64mmfr0(vcpu);
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64MMFR0_EL1);
u64 mdcr_set = 0;
/* Trap Debug Communications Channel registers */
@ -140,7 +140,7 @@ static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu)
*/
static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
{
const u64 feature_ids = get_pvm_id_aa64mmfr1(vcpu);
const u64 feature_ids = pvm_read_id_reg(vcpu, SYS_ID_AA64MMFR1_EL1);
u64 hcr_set = 0;
/* Trap LOR */

37
arch/arm64/kvm/hyp/nvhe/sys_regs.c
View File

@ -82,7 +82,7 @@ static u64 get_restricted_features_unsigned(u64 sys_reg_val,
* based on allowed features, system features, and KVM support.
*/
u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
{
const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm);
u64 set_mask = 0;
@ -103,7 +103,7 @@ u64 get_pvm_id_aa64pfr0(const struct kvm_vcpu *vcpu)
return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask;
}
u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu)
{
const struct kvm *kvm = (const struct kvm *)kern_hyp_va(vcpu->kvm);
u64 allow_mask = PVM_ID_AA64PFR1_ALLOW;
@ -114,7 +114,7 @@ u64 get_pvm_id_aa64pfr1(const struct kvm_vcpu *vcpu)
return id_aa64pfr1_el1_sys_val & allow_mask;
}
u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu)
{
/*
* No support for Scalable Vectors, therefore, hyp has no sanitized
@ -124,7 +124,7 @@ u64 get_pvm_id_aa64zfr0(const struct kvm_vcpu *vcpu)
return 0;
}
u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu)
{
/*
* No support for debug, including breakpoints, and watchpoints,
@ -134,7 +134,7 @@ u64 get_pvm_id_aa64dfr0(const struct kvm_vcpu *vcpu)
return 0;
}
u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu)
{
/*
* No support for debug, therefore, hyp has no sanitized copy of the
@ -144,7 +144,7 @@ u64 get_pvm_id_aa64dfr1(const struct kvm_vcpu *vcpu)
return 0;
}
u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu)
{
/*
* No support for implementation defined features, therefore, hyp has no
@ -154,7 +154,7 @@ u64 get_pvm_id_aa64afr0(const struct kvm_vcpu *vcpu)
return 0;
}
u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu)
{
/*
* No support for implementation defined features, therefore, hyp has no
@ -164,12 +164,12 @@ u64 get_pvm_id_aa64afr1(const struct kvm_vcpu *vcpu)
return 0;
}
u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64isar0(const struct kvm_vcpu *vcpu)
{
return id_aa64isar0_el1_sys_val & PVM_ID_AA64ISAR0_ALLOW;
}
u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
{
u64 allow_mask = PVM_ID_AA64ISAR1_ALLOW;
@ -182,7 +182,7 @@ u64 get_pvm_id_aa64isar1(const struct kvm_vcpu *vcpu)
return id_aa64isar1_el1_sys_val & allow_mask;
}
u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu)
{
u64 set_mask;
@ -192,22 +192,19 @@ u64 get_pvm_id_aa64mmfr0(const struct kvm_vcpu *vcpu)
return (id_aa64mmfr0_el1_sys_val & PVM_ID_AA64MMFR0_ALLOW) | set_mask;
}
u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64mmfr1(const struct kvm_vcpu *vcpu)
{
return id_aa64mmfr1_el1_sys_val & PVM_ID_AA64MMFR1_ALLOW;
}
u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu)
static u64 get_pvm_id_aa64mmfr2(const struct kvm_vcpu *vcpu)
{
return id_aa64mmfr2_el1_sys_val & PVM_ID_AA64MMFR2_ALLOW;
}
/* Read a sanitized cpufeature ID register by its sys_reg_desc. */
static u64 read_id_reg(const struct kvm_vcpu *vcpu,
struct sys_reg_desc const *r)
/* Read a sanitized cpufeature ID register by its encoding */
u64 pvm_read_id_reg(const struct kvm_vcpu *vcpu, u32 id)
{
u32 id = reg_to_encoding(r);
switch (id) {
case SYS_ID_AA64PFR0_EL1:
return get_pvm_id_aa64pfr0(vcpu);
@ -245,6 +242,12 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
return 0;
}
static u64 read_id_reg(const struct kvm_vcpu *vcpu,
struct sys_reg_desc const *r)
{
return pvm_read_id_reg(vcpu, reg_to_encoding(r));
}
/*
* Accessor for AArch32 feature id registers.
*