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drm/amd/display: Fix DC definition of PMFW Pstate table for DCN316
[Why] During DC init, we read power management tables from PMFW. This info is exchanged in the form of a binary blob inside gpu memory. In order to parse the binary blob, the correct struct needs to be used. [How] Fix dcn316's definition of the DfPstateTable_t struct to align with PMFW Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -530,7 +530,16 @@ static void dcn316_clk_mgr_helper_populate_bw_params(
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bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
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bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
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bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
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bw_params->clk_table.entries[i].wck_ratio = 1;
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switch (clock_table->DfPstateTable[j].WckRatio) {
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case WCK_RATIO_1_2:
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bw_params->clk_table.entries[i].wck_ratio = 2;
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break;
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case WCK_RATIO_1_4:
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bw_params->clk_table.entries[i].wck_ratio = 4;
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break;
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default:
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bw_params->clk_table.entries[i].wck_ratio = 1;
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}
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temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
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if (temp)
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bw_params->clk_table.entries[i].dcfclk_mhz = temp;
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@ -57,10 +57,19 @@ typedef enum {
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WM_COUNT,
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} WM_CLOCK_e;
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typedef enum{
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WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1;
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WCK_RATIO_1_2,
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WCK_RATIO_1_4,
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WCK_RATIO_MAX
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} WCK_RATIO_e;
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typedef struct {
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uint32_t FClk;
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uint32_t MemClk;
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uint32_t Voltage;
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uint8_t WckRatio;
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uint8_t Spare[3];
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} DfPstateTable_t;
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//Freq in MHz
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