From cdf9781025b3ed18f15f6c061c070b8bdcc1716f Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 24 Apr 2026 13:48:13 -0700 Subject: [PATCH] drm/xe: Stop programming BLIT_CCTL on Xe2 and later platforms Xe1 platforms used the BLIT_CCTL register to specify the MOCS value that would be used for BCS engine instructions that did not have a way of specifying a MOCS index directly. From Xe2 onward, all BCS instructions now have explicit instruction fields for specifying a MOCS index and the BLIT_CCTL register is now a dummy register with no valid fields. Although continuing to write to it today has no effect, the register could repurposed in future platforms, so restrict the BLIT_CCTL RTP entry to only apply to Xe1 platforms. Bspec: 60280 Reviewed-by: Shuicheng Lin Link: https://patch.msgid.link/20260424-engine-setup-v2-3-59cc620a25f1@intel.com Signed-off-by: Matt Roper --- drivers/gpu/drm/xe/xe_hw_engine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index c7d211178300..0419cd045090 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -384,7 +384,7 @@ xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe) * BLIT_CCTL registers are needed to be programmed to un-cached. */ { XE_RTP_NAME("BLIT_CCTL_default_MOCS"), - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274), ENGINE_CLASS(COPY)), XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0), BLIT_CCTL_DST_MOCS_MASK |