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drm/amd/display: Always update divider settings for DP tunnel

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[Why]
When transitioning from 640x480 at RBRx1 to HBR3x1,
both output pixel mode and pixel rate divider should update.
The needs_divider_update flag was only for 8b10b and 128b132b transition.

[How]
For DP tunneling, always update divider settings.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Cruise Hung 2025-12-17 18:11:43 +08:00 committed by Alex Deucher
parent 1758cf3cfd
commit cdd9b2d7e4
2 changed files with 13 additions and 5 deletions
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7
drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
View File

@ -70,6 +70,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
struct dc_state *state = link->dc->current_state;
struct dc_stream_update stream_update = { 0 };
bool dpms_off = false;
bool needs_divider_update = false;
bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state);
bool is_hpo_acquired;
uint8_t count;
@ -79,6 +80,10 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
int num_streams_on_link = 0;
struct dc *dc = (struct dc *)link->dc;
needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) !=
link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings))
|| link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA;
udelay(100);
link_get_master_pipes_with_dpms_on(link, state, &count, pipes);
@ -95,7 +100,7 @@ static void dp_retrain_link_dp_test(struct dc_link *link,
pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg);
}
if (link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {
if (needs_divider_update && link->dc->res_pool->funcs->update_dc_state_for_encoder_switch) {
link->dc->res_pool->funcs->update_dc_state_for_encoder_switch(link,
link_setting, count,
*pipes, &audio_output[0]);

11
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
View File

@ -2250,12 +2250,15 @@ enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link,
int i;
#if defined(CONFIG_DRM_AMD_DC_FP)
for (i = 0; i < state->stream_count; i++)
if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)
link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);
if (link->dc->hwss.calculate_pix_rate_divider) {
for (i = 0; i < state->stream_count; i++)
if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link)
link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]);
}
for (i = 0; i < pipe_count; i++) {
link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);
if (link->dc->res_pool->funcs->build_pipe_pix_clk_params)
link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]);
// Setup audio
if (pipes[i].stream_res.audio != NULL)