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i.MX ARM device tree changes for 6.15:

Browse Source 
- New boards support: Variscite VAR-SOM-MX6UL SoM/Concerto, i.MX6
   apalis/colibri v1.2, i.MX28 based btt3
 - A bunch of TQMa6/7 cleanups from Alexander Stein and Markus Niebel,
   ordering DT properties, correcting 3.3V supply, adding partitions
   child node to spi-nor, etc.
 - A bunch of changes from Fabio Estevam to fix dt-schema warnings on
   various boards
 - Other small and random changes
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Merge tag 'imx-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX ARM device tree changes for 6.15:

- New boards support: Variscite VAR-SOM-MX6UL SoM/Concerto, i.MX6
  apalis/colibri v1.2, i.MX28 based btt3
- A bunch of TQMa6/7 cleanups from Alexander Stein and Markus Niebel,
  ordering DT properties, correcting 3.3V supply, adding partitions
  child node to spi-nor, etc.
- A bunch of changes from Fabio Estevam to fix dt-schema warnings on
  various boards
- Other small and random changes

* tag 'imx-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (32 commits)
  ARM: dts: apalis/colibri-imx6: Add support for v1.2
  ARM: dts: apalis/colibri-imx6: Enable STMPE811 TS
  ARM: dts: imx6ul: Add Variscite Concerto board support
  ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support
  ARM: dts: vf610-colibri: Remove compatible from SoM dtsi
  ARM: dts: imx6qdl-apalis/colibri: Remove compatible from SoM dtsi
  ARM: dts: imx6ul-tqma6ul1: Change include order to disable fec2 node
  ARM: dts: imx53-mba53: Fix the PCA9554 compatible
  ARM: dts: imx31: Use nand-controller as node name
  ARM: dts: vfxxx: Fix the order of the DMA entries
  ARM: dts: tqma7: Add partitions subnode to spi-nor
  ARM: dts: imx7-tqma7: Add vcc-supply for spi-nor
  ARM: dts: tqma6ul: Add partitions subnode to spi-nor
  ARM: dts: imx6ul-tqma6ul: Add vcc-supply for spi-nor
  ARM: dts: imx6ul-tqma6ul: Order DT properties
  ARM: dts: imx6qdl-tqma6: Add partitions subnode to spi-nor
  ARM: dts: imx6qdl-tqma6: use sw4_reg as 3.3V supply
  ARM: dts: imx6qdl-tqma6: limit PMIC SW4 to 3.3V
  ARM: dts: imx6qdl-tqma6: Order DT properties
  ARM: dts: imx7d-sdb: Complete WM8960 power supplies
  ...

Link: https://lore.kernel.org/r/20250312074005.663165-4-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-03-14 23:27:30 +01:00
commit cdd4a27027
45 changed files with 1301 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/nxp/imx/Makefile
View File

@ -69,6 +69,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-colibri-eval-v3.dtb \
imx6dl-colibri-iris.dtb \
imx6dl-colibri-iris-v2.dtb \
imx6dl-colibri-v1.2-aster.dtb \
imx6dl-colibri-v1.2-eval-v3.dtb \
imx6dl-colibri-v1.2-iris.dtb \
imx6dl-colibri-v1.2-iris-v2.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
@ -158,6 +162,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-apalis-ixora.dtb \
imx6q-apalis-ixora-v1.1.dtb \
imx6q-apalis-ixora-v1.2.dtb \
imx6q-apalis-v1.2-eval.dtb \
imx6q-apalis-v1.2-eval-v1.2.dtb \
imx6q-apalis-v1.2-ixora.dtb \
imx6q-apalis-v1.2-ixora-v1.1.dtb \
imx6q-apalis-v1.2-ixora-v1.2.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-b450v3.dtb \
@ -329,6 +338,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ul-var-som-concerto.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-aster.dtb \
imx6ull-colibri-emmc-aster.dtb \

2
arch/arm/boot/dts/nxp/imx/imx31.dtsi
View File

@ -340,7 +340,7 @@ emi@b8000000 { /* External Memory Interface */
#address-cells = <1>;
#size-cells = <1>;
nfc: nand@b8000000 {
nfc: nand-controller@b8000000 {
compatible = "fsl,imx31-nand", "fsl,imx27-nand";
reg = <0xb8000000 0x1000>;
interrupts = <33>;

2
arch/arm/boot/dts/nxp/imx/imx50.dtsi
View File

@ -338,7 +338,7 @@ src: reset-controller@53fd0000 {
clks: ccm@53fd4000 {
compatible = "fsl,imx50-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
interrupts = <71>, <72>;
#clock-cells = <1>;
};

2
arch/arm/boot/dts/nxp/imx/imx51.dtsi
View File

@ -458,7 +458,7 @@ src: reset-controller@73fd0000 {
clks: ccm@73fd4000 {
compatible = "fsl,imx51-ccm";
reg = <0x73fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
interrupts = <71>, <72>;
#clock-cells = <1>;
};
};

2
arch/arm/boot/dts/nxp/imx/imx53-mba53.dts
View File

@ -162,7 +162,7 @@ codec: sgtl5000@a {
};
expander: pca9554@20 {
compatible = "pca9554";
compatible = "nxp,pca9554";
reg = <0x20>;
interrupts = <109>;
#gpio-cells = <2>;

2
arch/arm/boot/dts/nxp/imx/imx53-ppd.dts
View File

@ -593,7 +593,7 @@ &i2c2 {
touchscreen@4b {
compatible = "atmel,maxtouch";
reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>;
reg = <0x4b>;
interrupt-parent = <&gpio5>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;

2
arch/arm/boot/dts/nxp/imx/imx53.dtsi
View File

@ -598,7 +598,7 @@ src: reset-controller@53fd0000 {
clks: ccm@53fd4000 {
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;
interrupts = <0 71 0x04 0 72 0x04>;
interrupts = <71>, <72>;
#clock-cells = <1>;
};

11
arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-aster.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6dl-colibri-aster.dts"
#include "imx6qdl-colibri-v1.2.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Aster Board";
};

11
arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6dl-colibri-eval-v3.dts"
#include "imx6qdl-colibri-v1.2.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Evaluation Board V3";
};

11
arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6dl-colibri-iris-v2.dts"
#include "imx6qdl-colibri-v1.2.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris V2 Board";
};

11
arch/arm/boot/dts/nxp/imx/imx6dl-colibri-v1.2-iris.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6dl-colibri-iris.dts"
#include "imx6qdl-colibri-v1.2.dtsi"
/ {
model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris Board";
};

11
arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6q-apalis-eval-v1.2.dts"
#include "imx6qdl-apalis-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board v1.2";
};

11
arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-eval.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6q-apalis-eval.dts"
#include "imx6qdl-apalis-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board";
};

11
arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6q-apalis-ixora-v1.1.dts"
#include "imx6qdl-apalis-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.1";
};

11
arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6q-apalis-ixora-v1.2.dts"
#include "imx6qdl-apalis-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.2";
};

11
arch/arm/boot/dts/nxp/imx/imx6q-apalis-v1.2-ixora.dts Normal file
View File

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
/dts-v1/;
#include "imx6q-apalis-ixora.dts"
#include "imx6qdl-apalis-v1.2.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board";
};

57
arch/arm/boot/dts/nxp/imx/imx6qdl-apalis-v1.2.dtsi Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
&i2c2 {
/delete-node/ stmpe811@41;
ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch_int>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio4>;
touchscreen-max-pressure = <4096>;
adi,resistance-plate-x = <120>;
adi,first-conversion-delay = /bits/ 8 <3>;
adi,acquisition-time = /bits/ 8 <1>;
adi,median-filter-size = /bits/ 8 <2>;
adi,averaging = /bits/ 8 <1>;
adi,conversion-interval = /bits/ 8 <255>;
};
tla2024_adc: adc@49 {
compatible = "ti,tla2024";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
/* Apalis AN1_ADC0 */
channel@4 {
reg = <4>;
ti,datarate = <4>;
ti,gain = <1>;
};
/* Apalis AN1_ADC1 */
channel@5 {
reg = <5>;
ti,datarate = <4>;
ti,gain = <1>;
};
/* Apalis AN1_ADC2 */
channel@6 {
reg = <6>;
ti,datarate = <4>;
ti,gain = <1>;
};
/* Apalis AN1_TSWIP_ADC3 */
channel@7 {
reg = <7>;
ti,datarate = <4>;
ti,gain = <1>;
};
};
};

2
arch/arm/boot/dts/nxp/imx/imx6qdl-apalis.dtsi
View File

@ -10,7 +10,6 @@
/ {
model = "Toradex Apalis iMX6Q/D Module";
compatible = "toradex,apalis_imx6q", "fsl,imx6q";
aliases {
mmc0 = &usdhc3; /* eMMC */
@ -664,7 +663,6 @@ stmpe_ts: stmpe_touchscreen {
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
status = "disabled";
};
stmpe_adc: stmpe_adc {

57
arch/arm/boot/dts/nxp/imx/imx6qdl-colibri-v1.2.dtsi Normal file
View File

@ -0,0 +1,57 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2025 Toradex */
&i2c2 {
/delete-node/ stmpe811@41;
ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch_int>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio6>;
touchscreen-max-pressure = <4096>;
adi,resistance-plate-x = <120>;
adi,first-conversion-delay = /bits/ 8 <3>;
adi,acquisition-time = /bits/ 8 <1>;
adi,median-filter-size = /bits/ 8 <2>;
adi,averaging = /bits/ 8 <1>;
adi,conversion-interval = /bits/ 8 <255>;
};
tla2024_adc: adc@49 {
compatible = "ti,tla2024";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
/* Colibri AIN0 */
channel@4 {
reg = <4>;
ti,datarate = <4>;
ti,gain = <1>;
};
/* Colibri AIN1 */
channel@5 {
reg = <5>;
ti,datarate = <4>;
ti,gain = <1>;
};
/* Colibri AIN2 */
channel@6 {
reg = <6>;
ti,datarate = <4>;
ti,gain = <1>;
};
/* Colibri AIN3 */
channel@7 {
reg = <7>;
ti,datarate = <4>;
ti,gain = <1>;
};
};
};

2
arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi
View File

@ -10,7 +10,6 @@
/ {
model = "Toradex Colibri iMX6DL/S Module";
compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
aliases {
mmc0 = &usdhc3; /* eMMC */
@ -588,7 +587,6 @@ stmpe_ts: stmpe_touchscreen {
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
status = "disabled";
};
stmpe_adc: stmpe_adc {

2
arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi
View File

@ -124,7 +124,7 @@ sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
model = "imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
ssi-controller = <&ssi1>;
audio-codec = <&tlv320aic32x4>;
audio-asrc = <&asrc>;

25
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6.dtsi
View File

@ -7,16 +7,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "supply-3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
@ -25,11 +15,16 @@ &ecspi1 {
m25p80: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
vcc-supply = <&sw4_reg>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
@ -119,7 +114,7 @@ reg_ddr_1v5b: sw3b {
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
@ -183,7 +178,7 @@ reg_vgen6_3v3: vgen6 {
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
vmmc-supply = <&sw4_reg>;
non-removable;
disable-wp;
no-sd;

4
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi
View File

@ -30,14 +30,14 @@ pmic: pmic@8 {
temperature-sensor@48 {
compatible = "national,lm75a";
reg = <0x48>;
vs-supply = <&reg_3p3v>;
vs-supply = <&sw4_reg>;
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&reg_3p3v>;
vcc-supply = <&sw4_reg>;
};
};

4
arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi
View File

@ -23,14 +23,14 @@ pmic: pmic@8 {
temperature-sensor@48 {
compatible = "national,lm75a";
reg = <0x48>;
vs-supply = <&reg_3p3v>;
vs-supply = <&sw4_reg>;
};
eeprom@50 {
compatible = "st,24c64", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&reg_3p3v>;
vcc-supply = <&sw4_reg>;
};
};

32
arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
View File

@ -62,6 +62,33 @@ reg_can_3v3: regulator-can-3v3 {
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
};
reg_audio_5v: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_audio_3v3: regulator-audio-3v3 {
compatible = "regulator-fixed";
regulator-name = "audio-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
reg_audio_1v8: regulator-audio-1v8 {
compatible = "regulator-fixed";
regulator-name = "audio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
@ -139,6 +166,11 @@ codec: wm8960@1a {
wlf,gpio-cfg = <1 3>;
clocks = <&clks IMX6UL_CLK_SAI2>;
clock-names = "mclk";
AVDD-supply = <&reg_audio_3v3>;
DBVDD-supply = <&reg_audio_1v8>;
DCVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
};
camera@3c {

11
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi
View File

@ -162,13 +162,18 @@ &qspi {
status = "okay";
flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <33000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
vcc-supply = <&reg_vldo4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};

3
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts
View File

@ -6,8 +6,9 @@
/dts-v1/;
#include "imx6ul-tqma6ul1.dtsi"
#include "imx6ul-tqma6ul2.dtsi"
#include "mba6ulx.dtsi"
#include "imx6ul-tqma6ul1.dtsi"
/ {
model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board";

2
arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul1.dtsi
View File

@ -4,8 +4,6 @@
* Author: Markus Niebel <Markus.Niebel@tq-group.com>
*/
#include "imx6ul-tqma6ul2.dtsi"
/ {
model = "TQ-Systems TQMa6UL1 SoM";
compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul";

320
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts Normal file
View File

@ -0,0 +1,320 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
* Variscite SoM mounted on it
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
#include "imx6ul-var-som.dtsi"
#include <dt-bindings/leds/common.h>
/ {
model = "Variscite VAR-SOM-MX6UL Concerto Board";
compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
key-back {
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-wakeup {
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "gpled2";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&fec1 {
status = "disabled";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <0>;
micrel,rmii-reference-clock-select-25-mhz = <1>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@68 {
/*
* To actually use this interrupt
* connect pins J14.8 & J14.10 on the Concerto-Board.
*/
compatible = "dallas,ds1337";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
};
};
&iomuxc {
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_enet2_gpio: enet2-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
>;
};
pinctrl_enet2_mdio: enet2-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_gpio_key_back: gpio-key-backgrp {
fsl,pins = <
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059
>;
};
pinctrl_gpio_leds: gpio-ledsgrp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
>;
};
pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0
>;
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&snvs_rtc {
status = "disabled";
};
&tsc {
/*
* Conflics with wdog1 ext-reset-output & SD CD pins,
* so we keep it disabled by default.
*/
status = "disabled";
};
/* Console UART */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* ttymxc4 UART */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
/*
* To actually use ext-reset-output
* connect pins J17.3 & J17.8 on the Concerto-Board
*/
fsl,ext-reset-output;
};

233
arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi Normal file
View File

@ -0,0 +1,233 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite VAR-SOM-MX6UL Module
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Variscite VAR-SOM-MX6UL module";
compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reg_gpio_dvfs: reg-gpio-dvfs {
compatible = "regulator-gpio";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1400000>;
regulator-name = "gpio_dvfs";
regulator-type = "voltage";
gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
states = <1300000 0x1
1400000 0x0>;
};
rmii_ref_clk: rmii-ref-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "rmii-ref";
};
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&cpu0 {
dc-supply = <&reg_gpio_dvfs>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz = <1>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet1_gpio: enet1-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
>;
};
pinctrl_enet1_mdio: enet1-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};
&pxp {
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

2
arch/arm/boot/dts/nxp/imx/imx7-mba7.dtsi
View File

@ -170,7 +170,7 @@ reg_audio_3v3: regulator-audio-3v3 {
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
ssi-controller = <&sai1>;
audio-codec = <&tlv320aic32x4>;
audio-routing =

7
arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi
View File

@ -265,6 +265,13 @@ flash0: flash@0 {
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
vcc-supply = <&vgen4_reg>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};

32
arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
View File

@ -143,6 +143,33 @@ reg_fec2_3v3: regulator-fec2-3v3 {
gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
};
reg_audio_5v: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_audio_3v3: regulator-audio-3v3 {
compatible = "regulator-fixed";
regulator-name = "audio-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
reg_audio_1v8: regulator-audio-1v8 {
compatible = "regulator-fixed";
regulator-name = "audio-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000 0>;
@ -406,6 +433,11 @@ codec: wm8960@1a {
<&clks IMX7D_AUDIO_MCLK_ROOT_DIV>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <884736000>, <12288000>;
AVDD-supply = <&reg_audio_3v3>;
DBVDD-supply = <&reg_audio_1v8>;
DCVDD-supply = <&reg_audio_1v8>;
SPKVDD1-supply = <&reg_audio_5v>;
SPKVDD2-supply = <&reg_audio_5v>;
};
};

56
arch/arm/boot/dts/nxp/imx/imx7s.dtsi
View File

@ -176,6 +176,34 @@ timer {
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
video_mux: csi-mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
csi_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_csi_mux>;
};
};
port@2 {
reg = <2>;
csi_mux_to_csi: endpoint {
remote-endpoint = <&csi_from_csi_mux>;
};
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@ -529,34 +557,6 @@ mux: mux-controller {
#mux-control-cells = <1>;
mux-reg-masks = <0x14 0x00000010>;
};
video_mux: csi-mux {
compatible = "video-mux";
mux-controls = <&mux 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
csi_mux_from_mipi_vc0: endpoint {
remote-endpoint = <&mipi_vc0_to_csi_mux>;
};
};
port@2 {
reg = <2>;
csi_mux_to_csi: endpoint {
remote-endpoint = <&csi_from_csi_mux>;
};
};
};
};
ocotp: efuse@30350000 {

2
arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi
View File

@ -142,7 +142,7 @@ linux,cma {
sound {
compatible = "fsl,imx-audio-tlv320aic32x4";
model = "imx-audio-tlv320aic32x4";
model = "tqm-tlv320aic32";
ssi-controller = <&sai1>;
audio-codec = <&tlv320aic32x4>;
audio-asrc = <&asrc>;

3
arch/arm/boot/dts/nxp/mxs/Makefile
View File

@ -8,6 +8,9 @@ dtb-$(CONFIG_ARCH_MXS) += \
imx28-apf28.dtb \
imx28-apf28dev.dtb \
imx28-apx4devkit.dtb \
imx28-btt3-0.dtb \
imx28-btt3-1.dtb \
imx28-btt3-2.dtb \
imx28-cfa10036.dtb \
imx28-cfa10037.dtb \
imx28-cfa10049.dtb \

12
arch/arm/boot/dts/nxp/mxs/imx28-btt3-0.dts Normal file
View File

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
/dts-v1/;
#include "imx28-btt3.dtsi"
&hog_pins_rev {
fsl,pull-up = <MXS_PULL_ENABLE>;
};

8
arch/arm/boot/dts/nxp/mxs/imx28-btt3-1.dts Normal file
View File

@ -0,0 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
/dts-v1/;
#include "imx28-btt3.dtsi"

39
arch/arm/boot/dts/nxp/mxs/imx28-btt3-2.dts Normal file
View File

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
/dts-v1/;
#include "imx28-btt3.dtsi"
/ {
panel {
compatible = "powertip,st7272", "panel-dpi";
power-supply = <&reg_3v3>;
width-mm = <70>;
height-mm = <52>;
panel-timing {
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
hfront-porch = <20>;
hback-porch = <68>;
hsync-len = <30>;
vfront-porch = <4>;
vback-porch = <14>;
vsync-len = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};

313
arch/arm/boot/dts/nxp/mxs/imx28-btt3.dtsi Normal file
View File

@ -0,0 +1,313 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*/
/dts-v1/;
#include "imx28-lwe.dtsi"
/ {
model = "BTT3";
compatible = "lwn,imx28-btt3", "fsl,imx28";
chosen {
bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1 quiet";
};
memory@40000000 {
reg = <0x40000000 0x10000000>;
device_type = "memory";
};
panel {
compatible = "powertip,hx8238a", "panel-dpi";
power-supply = <&reg_3v3>;
width-mm = <70>;
height-mm = <52>;
panel-timing {
clock-frequency = <6500000>;
hactive = <320>;
vactive = <240>;
hfront-porch = <20>;
hback-porch = <38>;
hsync-len = <30>;
vfront-porch = <4>;
vback-porch = <14>;
vsync-len = <4>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "BTTC Audio";
simple-audio-card,widgets = "Speaker", "BTTC Speaker";
simple-audio-card,routing = "BTTC Speaker", "SPKOUTN", "BTTC Speaker", "SPKOUTP";
simple-audio-card,dai-link@0 {
format = "left_j";
bitclock-master = <&dai0_master>;
frame-master = <&dai0_master>;
mclk-fs = <256>;
dai0_master: cpu {
sound-dai = <&saif0>;
};
codec {
sound-dai = <&wm89xx>;
clocks = <&saif0>;
};
};
};
wifi_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_en_pin_bttc>;
reset-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
/* W1-163 needs 60us for WL_EN to be low and */
/* 150ms after high before downloading FW is possible */
post-power-on-delay-ms = <200>;
power-off-delay-us = <100>;
};
};
&auart0 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_2pins_a>;
status = "okay";
};
&auart3 {
pinctrl-names = "default";
pinctrl-0 = <&auart3_pins_a>;
uart-has-rtscts;
status = "okay";
};
&i2c0 {
wm89xx: audio-codec@1a {
compatible = "wlf,wm8940";
reg = <0x1a>;
#sound-dai-cells = <0>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>, <&lcdif_sync_pins_bttc>,
<&lcdif_reset_pins_bttc>;
status = "okay";
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&mac0 {
clocks = <&clks 57>, <&clks 57>, <&clks 64>;
clock-names = "ipg", "ahb", "enet_out";
phy-handle = <&mac0_phy>;
phy-mode = "rmii";
phy-supply = <&reg_3v3>;
/*
* This MAC address is adjusted during production.
* Value specified below is used as a fallback during recovery.
*/
local-mac-address = [ 00 11 B8 00 BF 8A ];
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
mac0_phy: ethernet-phy@0 {
/* LAN8720Ai - PHY ID */
compatible = "ethernet-phy-id0007.c0f0","ethernet-phy-ieee802.3-c22";
reg = <0>;
smsc,disable-energy-detect;
max-speed = <100>;
reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
};
};
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&hog_pins_a>, <&hog_pins_rev>;
hog_pins_a: hog@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_RDY2__GPIO_0_22
MX28_PAD_GPMI_RDY3__GPIO_0_23
MX28_PAD_GPMI_RDN__GPIO_0_24
MX28_PAD_LCD_VSYNC__GPIO_1_28
MX28_PAD_SSP2_SS1__GPIO_2_20
MX28_PAD_SSP2_SS2__GPIO_2_21
MX28_PAD_AUART2_CTS__GPIO_3_10
MX28_PAD_AUART2_RTS__GPIO_3_11
MX28_PAD_GPMI_WRN__GPIO_0_25
MX28_PAD_ENET0_RXD2__GPIO_4_9
MX28_PAD_ENET0_TXD2__GPIO_4_11
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
hog_pins_rev: hog@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_ENET0_RXD3__GPIO_4_10
MX28_PAD_ENET0_TX_CLK__GPIO_4_5
MX28_PAD_ENET0_COL__GPIO_4_14
MX28_PAD_ENET0_CRS__GPIO_4_15
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
keypad_pins_bttc: keypad-bttc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_D00__GPIO_0_0
MX28_PAD_AUART0_CTS__GPIO_3_2
MX28_PAD_AUART0_RTS__GPIO_3_3
MX28_PAD_GPMI_D03__GPIO_0_3
MX28_PAD_GPMI_D04__GPIO_0_4
MX28_PAD_GPMI_D05__GPIO_0_5
MX28_PAD_GPMI_D06__GPIO_0_6
MX28_PAD_GPMI_D07__GPIO_0_7
MX28_PAD_GPMI_CE1N__GPIO_0_17
MX28_PAD_GPMI_CE2N__GPIO_0_18
MX28_PAD_GPMI_CE3N__GPIO_0_19
MX28_PAD_GPMI_RDY0__GPIO_0_20
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_sync_pins_bttc: lcdif-bttc@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_LCD_DOTCLK__LCD_DOTCLK
MX28_PAD_LCD_ENABLE__LCD_ENABLE
MX28_PAD_LCD_HSYNC__LCD_HSYNC
MX28_PAD_LCD_RD_E__LCD_VSYNC
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_DISABLE>;
};
lcdif_reset_pins_bttc: lcdif-bttc@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_LCD_RESET__GPIO_3_30
>;
fsl,drive-strength = <MXS_DRIVE_4mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
ssp1_sdio_pins_a: ssp1-sdio@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_SSP1_DATA0__SSP1_D0
MX28_PAD_GPMI_D01__SSP1_D1
MX28_PAD_GPMI_D02__SSP1_D2
MX28_PAD_SSP1_DATA3__SSP1_D3
MX28_PAD_SSP1_CMD__SSP1_CMD
MX28_PAD_SSP1_SCK__SSP1_SCK
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
wifi_en_pin_bttc: wifi-en-pin@0 {
reg = <0>;
fsl,pinmux-ids = <
MX28_PAD_GPMI_CLE__GPIO_0_27
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pins_a>;
status = "okay";
};
&reg_usb_5v {
gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
};
&saif0 {
pinctrl-names = "default";
pinctrl-0 = <&saif0_pins_a>;
#sound-dai-cells = <0>;
assigned-clocks = <&clks 53>;
assigned-clock-rates = <12000000>;
status = "okay";
};
&saif1 {
pinctrl-names = "default";
pinctrl-0 = <&saif1_pins_a>;
#sound-dai-cells = <0>;
fsl,saif-master = <&saif0>;
status = "okay";
};
&ssp1 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&ssp1_sdio_pins_a>;
bus-width = <4>;
no-1-8-v; /* force 3.3V VIO */
non-removable;
vmmc-supply = <&reg_3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
keep-power-in-suspend;
status = "okay";
wlan@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&ssp2 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
status = "okay";
};

13
arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts
View File

@ -24,30 +24,25 @@ reg_usb0_vbus: regulator-0 {
};
leds {
#address-cells = <1>;
#size-cells = <0>;
compatible = "gpio-leds";
status = "okay";
led@1 {
led-1 {
label = "sps1-1:yellow:user";
gpios = <&gpio0 6 0>;
linux,default-trigger = "heartbeat";
reg = <0>;
};
led@2 {
led-2 {
label = "sps1-2:red:user";
gpios = <&gpio0 3 0>;
linux,default-trigger = "heartbeat";
reg = <1>;
};
led@3 {
led-3 {
label = "sps1-3:red:user";
gpios = <&gpio0 0 0>;
default-trigger = "heartbeat";
reg = <2>;
linux,default-trigger = "heartbeat";
};
};

4
arch/arm/boot/dts/nxp/vf/vf610-bk4.dts
View File

@ -119,7 +119,7 @@ &dspi0 {
status = "okay";
spidev0@0 {
compatible = "lwn,bk4";
compatible = "lwn,bk4-spi";
spi-max-frequency = <30000000>;
reg = <0>;
fsl,spi-cs-sck-delay = <200>;
@ -136,7 +136,7 @@ &dspi3 {
#address-cells = <0>;
slave {
compatible = "lwn,bk4";
compatible = "lwn,bk4-spi";
spi-max-frequency = <30000000>;
};
};

1
arch/arm/boot/dts/nxp/vf/vf610-colibri.dtsi
View File

@ -8,7 +8,6 @@
/ {
model = "Toradex Colibri VF61 COM";
compatible = "toradex,vf610-colibri_vf61", "fsl,vf610";
memory@80000000 {
device_type = "memory";

4
arch/arm/boot/dts/nxp/vf/vf610-zii-dev-rev-c.dts
View File

@ -392,7 +392,7 @@ &uart3 {
};
&gpio0 {
eth0_intrp {
eth0-intrp-hog {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
input;
@ -401,7 +401,7 @@ eth0_intrp {
};
&gpio3 {
eth0_intrp {
eth0-intrp-hog {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
input;

21
arch/arm/boot/dts/nxp/vf/vfxxx.dtsi
View File

@ -158,8 +158,8 @@ dspi0: spi@4002c000 {
clocks = <&clks VF610_CLK_DSPI0>;
clock-names = "dspi";
spi-num-chipselects = <6>;
dmas = <&edma1 1 12>, <&edma1 1 13>;
dma-names = "rx", "tx";
dmas = <&edma1 1 13>, <&edma1 1 12>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -172,8 +172,8 @@ dspi1: spi@4002d000 {
clocks = <&clks VF610_CLK_DSPI1>;
clock-names = "dspi";
spi-num-chipselects = <4>;
dmas = <&edma1 1 14>, <&edma1 1 15>;
dma-names = "rx", "tx";
dmas = <&edma1 1 15>, <&edma1 1 14>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -529,9 +529,8 @@ dspi2: spi@400ac000 {
clocks = <&clks VF610_CLK_DSPI2>;
clock-names = "dspi";
spi-num-chipselects = <2>;
dmas = <&edma1 0 10>,
<&edma1 0 11>;
dma-names = "rx", "tx";
dmas = <&edma1 0 11>, <&edma1 0 10>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -544,8 +543,8 @@ dspi3: spi@400ad000 {
clocks = <&clks VF610_CLK_DSPI3>;
clock-names = "dspi";
spi-num-chipselects = <2>;
dmas = <&edma1 0 12>, <&edma1 0 13>;
dma-names = "rx", "tx";
dmas = <&edma1 0 13>, <&edma1 0 12>;
dma-names = "tx", "rx";
status = "disabled";
};
@ -725,13 +724,13 @@ crypto: crypto@400f0000 {
clocks = <&clks VF610_CLK_CAAM>;
clock-names = "ipg";
sec_jr0: jr0@1000 {
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <102 IRQ_TYPE_LEVEL_HIGH>;