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KVM x86/pmu changes for 6.11
- Don't advertise IA32_PERF_GLOBAL_OVF_CTRL as an MSR-to-be-saved, as it reads
'0' and writes from userspace are ignored.
- Update to the newfangled Intel CPU FMS infrastructure.
- Use macros instead of open-coded literals to clean up KVM's manipulation of
FIXED_CTR_CTRL MSRs.
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Merge tag 'kvm-x86-pmu-6.11' of https://github.com/kvm-x86/linux into HEAD
KVM x86/pmu changes for 6.11
- Don't advertise IA32_PERF_GLOBAL_OVF_CTRL as an MSR-to-be-saved, as it reads
'0' and writes from userspace are ignored.
- Update to the newfangled Intel CPU FMS infrastructure.
- Use macros instead of open-coded literals to clean up KVM's manipulation of
FIXED_CTR_CTRL MSRs.
This commit is contained in:
Paolo Bonzini
commit
cda231cd42
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@ -533,12 +533,16 @@ struct kvm_pmc {
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};
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/* More counters may conflict with other existing Architectural MSRs */
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#define KVM_INTEL_PMC_MAX_GENERIC 8
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#define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
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#define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1)
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#define KVM_PMC_MAX_FIXED 3
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#define MSR_ARCH_PERFMON_FIXED_CTR_MAX (MSR_ARCH_PERFMON_FIXED_CTR0 + KVM_PMC_MAX_FIXED - 1)
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#define KVM_AMD_PMC_MAX_GENERIC 6
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#define KVM_MAX(a, b) ((a) >= (b) ? (a) : (b))
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#define KVM_MAX_NR_INTEL_GP_COUNTERS 8
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#define KVM_MAX_NR_AMD_GP_COUNTERS 6
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#define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \
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KVM_MAX_NR_AMD_GP_COUNTERS)
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#define KVM_MAX_NR_INTEL_FIXED_COUTNERS 3
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#define KVM_MAX_NR_AMD_FIXED_COUTNERS 0
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#define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUTNERS, \
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KVM_MAX_NR_AMD_FIXED_COUTNERS)
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struct kvm_pmu {
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u8 version;
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@ -546,16 +550,16 @@ struct kvm_pmu {
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unsigned nr_arch_fixed_counters;
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unsigned available_event_types;
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u64 fixed_ctr_ctrl;
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u64 fixed_ctr_ctrl_mask;
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u64 fixed_ctr_ctrl_rsvd;
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u64 global_ctrl;
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u64 global_status;
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u64 counter_bitmask[2];
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u64 global_ctrl_mask;
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u64 global_status_mask;
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u64 global_ctrl_rsvd;
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u64 global_status_rsvd;
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u64 reserved_bits;
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u64 raw_event_mask;
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struct kvm_pmc gp_counters[KVM_INTEL_PMC_MAX_GENERIC];
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struct kvm_pmc fixed_counters[KVM_PMC_MAX_FIXED];
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struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS];
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struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS];
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/*
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* Overlay the bitmap with a 64-bit atomic so that all bits can be
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@ -571,9 +575,9 @@ struct kvm_pmu {
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u64 ds_area;
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u64 pebs_enable;
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u64 pebs_enable_mask;
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u64 pebs_enable_rsvd;
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u64 pebs_data_cfg;
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u64 pebs_data_cfg_mask;
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u64 pebs_data_cfg_rsvd;
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/*
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* If a guest counter is cross-mapped to host counter with different
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@ -34,16 +34,16 @@ EXPORT_SYMBOL_GPL(kvm_pmu_eventsel);
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/* Precise Distribution of Instructions Retired (PDIR) */
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static const struct x86_cpu_id vmx_pebs_pdir_cpu[] = {
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL),
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL),
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X86_MATCH_VFM(INTEL_ICELAKE_D, NULL),
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X86_MATCH_VFM(INTEL_ICELAKE_X, NULL),
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/* Instruction-Accurate PDIR (PDIR++) */
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL),
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X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, NULL),
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{}
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};
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/* Precise Distribution (PDist) */
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static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = {
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X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL),
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X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, NULL),
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{}
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};
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@ -69,7 +69,7 @@ static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = {
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* code. Each pmc, stored in kvm_pmc.idx field, is unique across
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* all perf counters (both gp and fixed). The mapping relationship
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* between pmc and perf counters is as the following:
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* * Intel: [0 .. KVM_INTEL_PMC_MAX_GENERIC-1] <=> gp counters
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* * Intel: [0 .. KVM_MAX_NR_INTEL_GP_COUNTERS-1] <=> gp counters
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* [KVM_FIXED_PMC_BASE_IDX .. KVM_FIXED_PMC_BASE_IDX + 2] <=> fixed
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* * AMD: [0 .. AMD64_NUM_COUNTERS-1] and, for families 15H
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* and later, [0 .. AMD64_NUM_COUNTERS_CORE-1] <=> gp counters
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@ -469,11 +469,11 @@ static int reprogram_counter(struct kvm_pmc *pmc)
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if (pmc_is_fixed(pmc)) {
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fixed_ctr_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl,
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pmc->idx - KVM_FIXED_PMC_BASE_IDX);
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if (fixed_ctr_ctrl & 0x1)
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if (fixed_ctr_ctrl & INTEL_FIXED_0_KERNEL)
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eventsel |= ARCH_PERFMON_EVENTSEL_OS;
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if (fixed_ctr_ctrl & 0x2)
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if (fixed_ctr_ctrl & INTEL_FIXED_0_USER)
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eventsel |= ARCH_PERFMON_EVENTSEL_USR;
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if (fixed_ctr_ctrl & 0x8)
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if (fixed_ctr_ctrl & INTEL_FIXED_0_ENABLE_PMI)
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eventsel |= ARCH_PERFMON_EVENTSEL_INT;
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new_config = (u64)fixed_ctr_ctrl;
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}
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@ -681,13 +681,13 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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if (!msr_info->host_initiated)
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break;
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if (data & pmu->global_status_mask)
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if (data & pmu->global_status_rsvd)
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return 1;
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pmu->global_status = data;
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break;
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case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
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data &= ~pmu->global_ctrl_mask;
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data &= ~pmu->global_ctrl_rsvd;
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fallthrough;
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case MSR_CORE_PERF_GLOBAL_CTRL:
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if (!kvm_valid_perf_global_ctrl(pmu, data))
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@ -704,7 +704,7 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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* GLOBAL_OVF_CTRL, a.k.a. GLOBAL STATUS_RESET, clears bits in
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* GLOBAL_STATUS, and so the set of reserved bits is the same.
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*/
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if (data & pmu->global_status_mask)
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if (data & pmu->global_status_rsvd)
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return 1;
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fallthrough;
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case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
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@ -768,11 +768,11 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
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pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
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pmu->reserved_bits = 0xffffffff00200000ull;
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pmu->raw_event_mask = X86_RAW_EVENT_MASK;
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pmu->global_ctrl_mask = ~0ull;
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pmu->global_status_mask = ~0ull;
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pmu->fixed_ctr_ctrl_mask = ~0ull;
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pmu->pebs_enable_mask = ~0ull;
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pmu->pebs_data_cfg_mask = ~0ull;
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pmu->global_ctrl_rsvd = ~0ull;
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pmu->global_status_rsvd = ~0ull;
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pmu->fixed_ctr_ctrl_rsvd = ~0ull;
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pmu->pebs_enable_rsvd = ~0ull;
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pmu->pebs_data_cfg_rsvd = ~0ull;
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bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX);
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if (!vcpu->kvm->arch.enable_pmu)
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@ -846,8 +846,8 @@ static inline bool cpl_is_matched(struct kvm_pmc *pmc)
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} else {
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config = fixed_ctrl_field(pmc_to_pmu(pmc)->fixed_ctr_ctrl,
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pmc->idx - KVM_FIXED_PMC_BASE_IDX);
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select_os = config & 0x1;
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select_user = config & 0x2;
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select_os = config & INTEL_FIXED_0_KERNEL;
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select_user = config & INTEL_FIXED_0_USER;
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}
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/*
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@ -14,7 +14,8 @@
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MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
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/* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
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#define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
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#define fixed_ctrl_field(ctrl_reg, idx) \
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(((ctrl_reg) >> ((idx) * INTEL_FIXED_BITS_STRIDE)) & INTEL_FIXED_BITS_MASK)
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#define VMWARE_BACKDOOR_PMC_HOST_TSC 0x10000
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#define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001
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@ -129,7 +130,7 @@ static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
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static inline bool kvm_valid_perf_global_ctrl(struct kvm_pmu *pmu,
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u64 data)
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{
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return !(pmu->global_ctrl_mask & data);
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return !(pmu->global_ctrl_rsvd & data);
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}
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/* returns general purpose PMC with the specified MSR. Note that it can be
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@ -170,7 +171,8 @@ static inline bool pmc_speculative_in_use(struct kvm_pmc *pmc)
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if (pmc_is_fixed(pmc))
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return fixed_ctrl_field(pmu->fixed_ctr_ctrl,
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pmc->idx - KVM_FIXED_PMC_BASE_IDX) & 0x3;
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pmc->idx - KVM_FIXED_PMC_BASE_IDX) &
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(INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER);
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return pmc->eventsel & ARCH_PERFMON_EVENTSEL_ENABLE;
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}
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@ -217,7 +219,7 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops)
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kvm_pmu_cap.num_counters_gp = min(kvm_pmu_cap.num_counters_gp,
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pmu_ops->MAX_NR_GP_COUNTERS);
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kvm_pmu_cap.num_counters_fixed = min(kvm_pmu_cap.num_counters_fixed,
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KVM_PMC_MAX_FIXED);
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KVM_MAX_NR_FIXED_COUNTERS);
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kvm_pmu_eventsel.INSTRUCTIONS_RETIRED =
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perf_get_hw_event_config(PERF_COUNT_HW_INSTRUCTIONS);
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@ -199,8 +199,8 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu)
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kvm_pmu_cap.num_counters_gp);
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if (pmu->version > 1) {
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pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1);
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pmu->global_status_mask = pmu->global_ctrl_mask;
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pmu->global_ctrl_rsvd = ~((1ull << pmu->nr_arch_gp_counters) - 1);
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pmu->global_status_rsvd = pmu->global_ctrl_rsvd;
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}
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pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;
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@ -217,10 +217,9 @@ static void amd_pmu_init(struct kvm_vcpu *vcpu)
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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int i;
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BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > AMD64_NUM_COUNTERS_CORE);
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BUILD_BUG_ON(KVM_AMD_PMC_MAX_GENERIC > INTEL_PMC_MAX_GENERIC);
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BUILD_BUG_ON(KVM_MAX_NR_AMD_GP_COUNTERS > AMD64_NUM_COUNTERS_CORE);
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for (i = 0; i < KVM_AMD_PMC_MAX_GENERIC ; i++) {
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for (i = 0; i < KVM_MAX_NR_AMD_GP_COUNTERS; i++) {
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pmu->gp_counters[i].type = KVM_PMC_GP;
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pmu->gp_counters[i].vcpu = vcpu;
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pmu->gp_counters[i].idx = i;
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@ -238,6 +237,6 @@ struct kvm_pmu_ops amd_pmu_ops __initdata = {
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.refresh = amd_pmu_refresh,
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.init = amd_pmu_init,
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.EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT,
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.MAX_NR_GP_COUNTERS = KVM_AMD_PMC_MAX_GENERIC,
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.MAX_NR_GP_COUNTERS = KVM_MAX_NR_AMD_GP_COUNTERS,
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.MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS,
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};
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@ -348,14 +348,14 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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switch (msr) {
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case MSR_CORE_PERF_FIXED_CTR_CTRL:
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if (data & pmu->fixed_ctr_ctrl_mask)
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if (data & pmu->fixed_ctr_ctrl_rsvd)
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return 1;
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if (pmu->fixed_ctr_ctrl != data)
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reprogram_fixed_counters(pmu, data);
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break;
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case MSR_IA32_PEBS_ENABLE:
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if (data & pmu->pebs_enable_mask)
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if (data & pmu->pebs_enable_rsvd)
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return 1;
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if (pmu->pebs_enable != data) {
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@ -371,7 +371,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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pmu->ds_area = data;
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break;
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case MSR_PEBS_DATA_CFG:
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if (data & pmu->pebs_data_cfg_mask)
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if (data & pmu->pebs_data_cfg_rsvd)
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return 1;
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pmu->pebs_data_cfg = data;
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@ -436,8 +436,8 @@ static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index)
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};
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u64 eventsel;
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BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) != KVM_PMC_MAX_FIXED);
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BUILD_BUG_ON(index >= KVM_PMC_MAX_FIXED);
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BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) != KVM_MAX_NR_INTEL_FIXED_COUTNERS);
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BUILD_BUG_ON(index >= KVM_MAX_NR_INTEL_FIXED_COUTNERS);
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/*
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* Yell if perf reports support for a fixed counter but perf doesn't
|
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|
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@ -448,6 +448,14 @@ static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index)
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return eventsel;
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}
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static void intel_pmu_enable_fixed_counter_bits(struct kvm_pmu *pmu, u64 bits)
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{
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int i;
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for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
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pmu->fixed_ctr_ctrl_rsvd &= ~intel_fixed_bits_by_idx(i, bits);
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}
|
||||
|
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static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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|
|
@ -456,8 +464,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
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union cpuid10_eax eax;
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union cpuid10_edx edx;
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u64 perf_capabilities;
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u64 counter_mask;
|
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int i;
|
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u64 counter_rsvd;
|
||||
|
||||
memset(&lbr_desc->records, 0, sizeof(lbr_desc->records));
|
||||
|
||||
|
|
@ -501,22 +508,24 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
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((u64)1 << edx.split.bit_width_fixed) - 1;
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||||
}
|
||||
|
||||
for (i = 0; i < pmu->nr_arch_fixed_counters; i++)
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pmu->fixed_ctr_ctrl_mask &= ~(0xbull << (i * 4));
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counter_mask = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
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intel_pmu_enable_fixed_counter_bits(pmu, INTEL_FIXED_0_KERNEL |
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INTEL_FIXED_0_USER |
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INTEL_FIXED_0_ENABLE_PMI);
|
||||
|
||||
counter_rsvd = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |
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(((1ull << pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX));
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pmu->global_ctrl_mask = counter_mask;
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pmu->global_ctrl_rsvd = counter_rsvd;
|
||||
|
||||
/*
|
||||
* GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET)
|
||||
* share reserved bit definitions. The kernel just happens to use
|
||||
* OVF_CTRL for the names.
|
||||
*/
|
||||
pmu->global_status_mask = pmu->global_ctrl_mask
|
||||
pmu->global_status_rsvd = pmu->global_ctrl_rsvd
|
||||
& ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
|
||||
MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
|
||||
if (vmx_pt_mode_is_host_guest())
|
||||
pmu->global_status_mask &=
|
||||
pmu->global_status_rsvd &=
|
||||
~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
|
||||
|
||||
entry = kvm_find_cpuid_entry_index(vcpu, 7, 0);
|
||||
|
|
@ -544,15 +553,12 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
|
|||
|
||||
if (perf_capabilities & PERF_CAP_PEBS_FORMAT) {
|
||||
if (perf_capabilities & PERF_CAP_PEBS_BASELINE) {
|
||||
pmu->pebs_enable_mask = counter_mask;
|
||||
pmu->pebs_enable_rsvd = counter_rsvd;
|
||||
pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
|
||||
for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
|
||||
pmu->fixed_ctr_ctrl_mask &=
|
||||
~(1ULL << (KVM_FIXED_PMC_BASE_IDX + i * 4));
|
||||
}
|
||||
pmu->pebs_data_cfg_mask = ~0xff00000full;
|
||||
pmu->pebs_data_cfg_rsvd = ~0xff00000full;
|
||||
intel_pmu_enable_fixed_counter_bits(pmu, ICL_FIXED_0_ADAPTIVE);
|
||||
} else {
|
||||
pmu->pebs_enable_mask =
|
||||
pmu->pebs_enable_rsvd =
|
||||
~((1ull << pmu->nr_arch_gp_counters) - 1);
|
||||
}
|
||||
}
|
||||
|
|
@ -564,14 +570,14 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu)
|
|||
struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
|
||||
struct lbr_desc *lbr_desc = vcpu_to_lbr_desc(vcpu);
|
||||
|
||||
for (i = 0; i < KVM_INTEL_PMC_MAX_GENERIC; i++) {
|
||||
for (i = 0; i < KVM_MAX_NR_INTEL_GP_COUNTERS; i++) {
|
||||
pmu->gp_counters[i].type = KVM_PMC_GP;
|
||||
pmu->gp_counters[i].vcpu = vcpu;
|
||||
pmu->gp_counters[i].idx = i;
|
||||
pmu->gp_counters[i].current_config = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < KVM_PMC_MAX_FIXED; i++) {
|
||||
for (i = 0; i < KVM_MAX_NR_INTEL_FIXED_COUTNERS; i++) {
|
||||
pmu->fixed_counters[i].type = KVM_PMC_FIXED;
|
||||
pmu->fixed_counters[i].vcpu = vcpu;
|
||||
pmu->fixed_counters[i].idx = i + KVM_FIXED_PMC_BASE_IDX;
|
||||
|
|
@ -731,6 +737,6 @@ struct kvm_pmu_ops intel_pmu_ops __initdata = {
|
|||
.deliver_pmi = intel_pmu_deliver_pmi,
|
||||
.cleanup = intel_pmu_cleanup,
|
||||
.EVENTSEL_EVENT = ARCH_PERFMON_EVENTSEL_EVENT,
|
||||
.MAX_NR_GP_COUNTERS = KVM_INTEL_PMC_MAX_GENERIC,
|
||||
.MAX_NR_GP_COUNTERS = KVM_MAX_NR_INTEL_GP_COUNTERS,
|
||||
.MIN_NR_GP_COUNTERS = 1,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2561,17 +2561,15 @@ static bool cpu_has_sgx(void)
|
|||
*/
|
||||
static bool cpu_has_perf_global_ctrl_bug(void)
|
||||
{
|
||||
if (boot_cpu_data.x86 == 0x6) {
|
||||
switch (boot_cpu_data.x86_model) {
|
||||
case INTEL_FAM6_NEHALEM_EP: /* AAK155 */
|
||||
case INTEL_FAM6_NEHALEM: /* AAP115 */
|
||||
case INTEL_FAM6_WESTMERE: /* AAT100 */
|
||||
case INTEL_FAM6_WESTMERE_EP: /* BC86,AAY89,BD102 */
|
||||
case INTEL_FAM6_NEHALEM_EX: /* BA97 */
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (boot_cpu_data.x86_vfm) {
|
||||
case INTEL_NEHALEM_EP: /* AAK155 */
|
||||
case INTEL_NEHALEM: /* AAP115 */
|
||||
case INTEL_WESTMERE: /* AAT100 */
|
||||
case INTEL_WESTMERE_EP: /* BC86,AAY89,BD102 */
|
||||
case INTEL_NEHALEM_EX: /* BA97 */
|
||||
return true;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return false;
|
||||
|
|
|
|||
|
|
@ -1448,10 +1448,10 @@ static const u32 msrs_to_save_pmu[] = {
|
|||
MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
|
||||
MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
|
||||
MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
|
||||
MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
|
||||
MSR_CORE_PERF_GLOBAL_CTRL,
|
||||
MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
|
||||
|
||||
/* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
|
||||
/* This part of MSRs should match KVM_MAX_NR_INTEL_GP_COUNTERS. */
|
||||
MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
|
||||
|
|
@ -1464,7 +1464,7 @@ static const u32 msrs_to_save_pmu[] = {
|
|||
MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
|
||||
MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
|
||||
|
||||
/* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
|
||||
/* This part of MSRs should match KVM_MAX_NR_AMD_GP_COUNTERS. */
|
||||
MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
|
||||
MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
|
||||
MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
|
||||
|
|
@ -7439,17 +7439,20 @@ static void kvm_probe_msr_to_save(u32 msr_index)
|
|||
intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
|
||||
return;
|
||||
break;
|
||||
case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
|
||||
case MSR_ARCH_PERFMON_PERFCTR0 ...
|
||||
MSR_ARCH_PERFMON_PERFCTR0 + KVM_MAX_NR_GP_COUNTERS - 1:
|
||||
if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
|
||||
kvm_pmu_cap.num_counters_gp)
|
||||
return;
|
||||
break;
|
||||
case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
|
||||
case MSR_ARCH_PERFMON_EVENTSEL0 ...
|
||||
MSR_ARCH_PERFMON_EVENTSEL0 + KVM_MAX_NR_GP_COUNTERS - 1:
|
||||
if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
|
||||
kvm_pmu_cap.num_counters_gp)
|
||||
return;
|
||||
break;
|
||||
case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
|
||||
case MSR_ARCH_PERFMON_FIXED_CTR0 ...
|
||||
MSR_ARCH_PERFMON_FIXED_CTR0 + KVM_MAX_NR_FIXED_COUNTERS - 1:
|
||||
if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
|
||||
kvm_pmu_cap.num_counters_fixed)
|
||||
return;
|
||||
|
|
@ -7480,7 +7483,7 @@ static void kvm_init_msr_lists(void)
|
|||
{
|
||||
unsigned i;
|
||||
|
||||
BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
|
||||
BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS != 3,
|
||||
"Please update the fixed PMCs in msrs_to_save_pmu[]");
|
||||
|
||||
num_msrs_to_save = 0;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user