From cd0361df27509401f729f834468855b8412feb87 Mon Sep 17 00:00:00 2001 From: Chun-Tse Shao Date: Tue, 9 Jun 2026 14:50:43 -0700 Subject: [PATCH] perf vendor events intel: Update lunarlake events from 1.22 to 1.25 The updated events were published in: https://github.com/intel/perfmon/commit/5535a3e8cc14ae8ef58013cf3d8e9480018b911a Signed-off-by: Chun-Tse Shao Reviewed-by: Dapeng Mi Reviewed-by: Ian Rogers Signed-off-by: Namhyung Kim --- .../pmu-events/arch/x86/lunarlake/cache.json | 2 +- .../arch/x86/lunarlake/pipeline.json | 27 ++- .../arch/x86/lunarlake/uncore-memory.json | 208 +++++++++++++++++- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 228 insertions(+), 11 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json index 92a3667b4520..5b350233a5e1 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json @@ -1,6 +1,6 @@ [ { - "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.", + "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json index d66eafccebbb..a7467b2f291d 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json @@ -190,7 +190,6 @@ "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", "PublicDescription": "Counts taken forward conditional branch instructions retired. Available PDIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x102", "Unit": "cpu_core" }, { @@ -324,6 +323,15 @@ "UMask": "0xdf", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of taken branch instructions retired", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN", + "SampleAfterValue": "200003", + "UMask": "0x80", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", "Counter": "0,1,2,3,4,5,6,7", @@ -446,7 +454,7 @@ "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", "PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x8001", + "UMask": "0x41", "Unit": "cpu_core" }, { @@ -475,7 +483,7 @@ "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", "PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x8002", + "UMask": "0x140", "Unit": "cpu_core" }, { @@ -575,11 +583,11 @@ "Unit": "cpu_core" }, { - "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0,1", + "PublicDescription": "This event counts the number of mispredicted ret instructions retired. Available PDIST counters: 0,1", "SampleAfterValue": "100007", "UMask": "0x8", "Unit": "cpu_core" @@ -1373,6 +1381,15 @@ "UMask": "0x88", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP", + "SampleAfterValue": "20003", + "UMask": "0x40", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of nukes due to memory renaming", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json index 63c4aa2791e4..a1e79f06645a 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json @@ -1,6 +1,30 @@ [ { - "BriefDescription": "Read CAS command sent to DRAM", + "BriefDescription": "ACT command for a read request sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x24", + "EventName": "UNC_M_ACT_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x26", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a write request sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x25", + "EventName": "UNC_M_ACT_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS command sent to DRAM.", "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", @@ -8,7 +32,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Write CAS command sent to DRAM", + "BriefDescription": "Write CAS command sent to DRAM.", "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", @@ -16,7 +40,94 @@ "Unit": "iMC" }, { - "BriefDescription": "Any Rank at Hot state", + "BriefDescription": "Counting the number of clocks.", + "Counter": "0,1,2,3,4", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE in DRAM is low.", + "Counter": "0,1,2,3,4", + "EventCode": "0x29", + "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Empty.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1D", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Empty", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Empty.", + "Counter": "0,1,2,3,4", + "EventCode": "0x20", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page Empty", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Hit.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1C", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Hit", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Hit.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1F", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page Hit", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Miss.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1E", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Miss", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Miss.", + "Counter": "0,1,2,3,4", + "EventCode": "0x21", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page Miss", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM in Self-refresh (all channels).", + "Counter": "0,1,2,3,4", + "EventCode": "0x12", + "EventName": "UNC_M_DRAM_SELF_REFRESH", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Hot state.", "Counter": "0,1,2,3,4", "EventCode": "0x19", "EventName": "UNC_M_DRAM_THERMAL_HOT", @@ -25,7 +136,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Any Rank at Warm state", + "BriefDescription": "Any Rank at Warm state.", "Counter": "0,1,2,3,4", "EventCode": "0x1A", "EventName": "UNC_M_DRAM_THERMAL_WARM", @@ -33,6 +144,42 @@ "PerPkg": "1", "Unit": "iMC" }, + { + "BriefDescription": "PRE command sent to DRAM for a read/write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x27", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", + "EventCode": "0x3A", + "EventName": "UNC_M_RD_DATA", + "PerPkg": "1", + "PublicDescription": "This counter counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch).", + "Counter": "0,1,2,3,4", + "EventCode": "0x13", + "EventName": "UNC_M_RD_OCCUPANCY_CH0", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch)", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch).", + "Counter": "0,1,2,3,4", + "EventCode": "0x14", + "EventName": "UNC_M_RD_OCCUPANCY_CH1", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, { "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending or receiving 32B chunk data.", "Counter": "0,1,2,3,4", @@ -40,5 +187,58 @@ "EventName": "UNC_M_TOTAL_DATA", "PerPkg": "1", "Unit": "iMC" + }, + { + "BriefDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs.", + "Counter": "0,1,2,3,4", + "EventCode": "0x39", + "EventName": "UNC_M_TOTAL_REQUESTS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 read request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x02", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x03", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 read request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x04", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x05", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.", + "Counter": "0,1,2,3,4", + "EventCode": "0x3B", + "EventName": "UNC_M_WR_DATA", + "PerPkg": "1", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index b8ea72b99c52..7d19f8fa335a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core GenuineIntel-6-(57|85),v16,knightslanding,core -GenuineIntel-6-BD,v1.22,lunarlake,core +GenuineIntel-6-BD,v1.25,lunarlake,core GenuineIntel-6-(AA|AC|B5),v1.21,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core