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cxgb4: add error handlers to LE intr_handler

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cxgb4 does not look for HASHTBLMEMCRCERR and CMDTIDERR
bits in LE_DB_INT_CAUSE register, but these are enabled
in LE_DB_INT_ENABLE. So, add error handlers to LE
interrupt handler to emit a warning or alert message
for hash table mem crc and cmd tid errors

Signed-off-by: Raju Rangoju <rajur@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Raju Rangoju 2020-08-25 09:25:46 +05:30 committed by David S. Miller
parent 4718a471f1
commit cca852831c
2 changed files with 10 additions and 0 deletions
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2
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View File

@ -4745,9 +4745,11 @@ static void le_intr_handler(struct adapter *adap)
static struct intr_info t6_le_intr_info[] = {
{ T6_LIPMISS_F, "LE LIP miss", -1, 0 },
{ T6_LIP0_F, "LE 0 LIP error", -1, 0 },
{ CMDTIDERR_F, "LE cmd tid error", -1, 1 },
{ TCAMINTPERR_F, "LE parity error", -1, 1 },
{ T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
{ SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
{ HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
{ 0 }
};

8
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -3017,6 +3017,14 @@
#define REV_V(x) ((x) << REV_S)
#define REV_G(x) (((x) >> REV_S) & REV_M)
#define HASHTBLMEMCRCERR_S 27
#define HASHTBLMEMCRCERR_V(x) ((x) << HASHTBLMEMCRCERR_S)
#define HASHTBLMEMCRCERR_F HASHTBLMEMCRCERR_V(1U)
#define CMDTIDERR_S 22
#define CMDTIDERR_V(x) ((x) << CMDTIDERR_S)
#define CMDTIDERR_F CMDTIDERR_V(1U)
#define T6_UNKNOWNCMD_S 3
#define T6_UNKNOWNCMD_V(x) ((x) << T6_UNKNOWNCMD_S)
#define T6_UNKNOWNCMD_F T6_UNKNOWNCMD_V(1U)