mirror of
https://github.com/torvalds/linux.git
synced 2026-07-29 02:31:27 +02:00
net: phy: dp83867: remove check of delay strap configuration
The check that intended to handle "rgmii" PHY mode differently to the RGMII modes with internal delay never worked as intended: - added in commit2a10154abc("net: phy: dp83867: Add TI dp83867 phy"): logic error caused the condition to always evaluate to true - changed in commita46fa260f6("net: phy: dp83867: Fix warning check for setting the internal delay"): now the condition incorrectly evaluates to false for rgmii-txid - removed in commit2b89264925("net: phy: dp83867: Set up RGMII TX delay") Around the time of the removal, commitc11669a275("net: phy: dp83867: Rework delay rgmii delay handling") started clearing the delay enable flags in RGMIICTL. The change attempted to preserve the historical behavior of not disabling internal delays with "rgmii" PHY mode and also documented this in a comment, but due to a conflict between "Set up RGMII TX delay" and "Rework delay rgmii delay handling", the behavior dp83867_verify_rgmii_cfg() warned about (and that was also described in a comment in dp83867_config_init()) disappeared in the following merge of net into net-next in commitb4b12b0d2f("Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net"). While is doesn't appear that this breaking change was intentional, it has been like this since 2019, and the new behavior to disable the delays with "rgmii" PHY mode is generally desirable - in particular with MAC drivers that have to fix up the delay mode, resulting in the PHY driver not even seeing the same mode that was specified in the Device Tree. Remove the obsolete check and comment. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Link: https://patch.msgid.link/8a286207cd11b460bb0dbd27931de3626b9d7575.1746612711.git.matthias.schiffer@ew.tq-group.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
parent
6b466efc63
commit
cc7734e03e
|
|
@ -92,11 +92,6 @@
|
|||
#define DP83867_STRAP_STS1_RESERVED BIT(11)
|
||||
|
||||
/* STRAP_STS2 bits */
|
||||
#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
|
||||
#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
|
||||
#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
|
||||
#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
|
||||
#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
|
||||
#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)
|
||||
|
||||
/* PHY CTRL bits */
|
||||
|
|
@ -510,25 +505,6 @@ static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
|
|||
{
|
||||
struct dp83867_private *dp83867 = phydev->priv;
|
||||
|
||||
/* Existing behavior was to use default pin strapping delay in rgmii
|
||||
* mode, but rgmii should have meant no delay. Warn existing users.
|
||||
*/
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
|
||||
const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
|
||||
DP83867_STRAP_STS2);
|
||||
const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
|
||||
DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
|
||||
const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
|
||||
DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
|
||||
|
||||
if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
|
||||
rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
|
||||
phydev_warn(phydev,
|
||||
"PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
|
||||
"Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
|
||||
txskew, rxskew);
|
||||
}
|
||||
|
||||
/* RX delay *must* be specified if internal delay of RX is used. */
|
||||
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
|
||||
|
|
@ -836,13 +812,7 @@ static int dp83867_config_init(struct phy_device *phydev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* If rgmii mode with no internal delay is selected, we do NOT use
|
||||
* aligned mode as one might expect. Instead we use the PHY's default
|
||||
* based on pin strapping. And the "mode 0" default is to *use*
|
||||
* internal delay with a value of 7 (2.00 ns).
|
||||
*
|
||||
* Set up RGMII delays
|
||||
*/
|
||||
/* Set up RGMII delays */
|
||||
val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
|
||||
|
||||
val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user