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drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0

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DPU version 13.0.0 introduces structural changes including
register additions, removals, and relocations.

Refactor SSPP-related code to be compatible with DPU 13.0.0
modifications.

Co-developed-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/698710/
Link: https://lore.kernel.org/r/20260115092749.533-10-yuanjie.yang@oss.qualcomm.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Yuanjie Yang 2026-01-15 17:27:46 +08:00 committed by Dmitry Baryshkov
parent b78956dc9e
commit cc4b81f178
2 changed files with 111 additions and 41 deletions
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100
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
View File

@ -147,11 +147,18 @@
static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
u32 mode_mask;
if (!ctx)
return;
dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE);
}
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
struct dpu_hw_sspp *ctx, u32 op_mode_off)
{
u32 mode_mask;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO) {
/**
* if rect index is RECT_SOLO, we cannot expect a
@ -160,7 +167,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
*/
mode_mask = 0;
} else {
mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE);
mode_mask = DPU_REG_READ(&ctx->hw, op_mode_off);
mode_mask |= pipe->multirect_index;
if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_TIME_MX)
mode_mask |= BIT(2);
@ -168,10 +175,10 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe)
mode_mask &= ~BIT(2);
}
DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask);
DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask);
}
static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
@ -191,7 +198,7 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx,
DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode);
}
static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en)
{
const struct dpu_sspp_sub_blks *sblk = ctx->cap->sblk;
@ -213,10 +220,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode = 0;
u32 fast_clear = 0;
u32 op_mode_off, unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_error_off;
if (!ctx || !fmt)
@ -244,6 +247,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
}
}
dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off,
unpack_pat_off, format_off,
ubwc_ctrl_off, ubwc_error_off);
}
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off,
u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off,
u32 ubwc_error_off)
{
struct dpu_hw_blk_reg_map *c;
u32 chroma_samp, unpack, src_format;
u32 opmode;
u32 fast_clear;
c = &ctx->hw;
opmode = DPU_REG_READ(c, op_mode_off);
opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
@ -331,10 +349,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
_sspp_setup_csc10_opmode(ctx,
dpu_hw_sspp_setup_csc10_opmode(ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
MSM_FORMAT_IS_YUV(fmt));
@ -403,7 +421,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
tot_req_pixels[3]);
}
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
const struct msm_format *format)
{
@ -423,15 +441,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *cfg)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy;
u32 src_size_off, src_xy_off, out_size_off, out_xy_off;
if (!ctx || !cfg)
return;
c = &ctx->hw;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
pipe->multirect_index == DPU_SSPP_RECT_0) {
src_size_off = SSPP_SRC_SIZE;
@ -445,20 +459,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe *pipe,
out_xy_off = SSPP_OUT_XY_REC1;
}
/* src and dest rect programming */
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
drm_rect_width(&cfg->src_rect);
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
drm_rect_width(&cfg->dst_rect);
/* rectangle register programming */
DPU_REG_WRITE(c, src_size_off, src_size);
DPU_REG_WRITE(c, src_xy_off, src_xy);
DPU_REG_WRITE(c, out_size_off, dst_size);
DPU_REG_WRITE(c, out_xy_off, dst_xy);
dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off,
src_xy_off, out_size_off, out_xy_off);
}
static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
@ -515,7 +517,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe,
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1);
}
static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
const struct dpu_csc_cfg *data)
{
u32 offset;
@ -537,21 +539,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_fmt_layout cfg;
u32 const_clr_off;
if (!ctx)
return;
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
pipe->multirect_index == DPU_SSPP_RECT_0)
const_clr_off = SSPP_SRC_CONSTANT_COLOR;
else
const_clr_off = SSPP_SRC_CONSTANT_COLOR_REC1;
dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off);
}
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
u32 color, struct dpu_hw_sspp *ctx,
u32 const_clr_off)
{
struct dpu_hw_fmt_layout cfg;
/* cleanup source addresses */
memset(&cfg, 0, sizeof(cfg));
ctx->ops.setup_sourceaddress(pipe, &cfg);
if (pipe->multirect_index == DPU_SSPP_RECT_SOLO ||
pipe->multirect_index == DPU_SSPP_RECT_0)
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color);
else
DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1,
color);
DPU_REG_WRITE(&ctx->hw, const_clr_off, color);
}
static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
@ -565,14 +577,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx,
cfg);
}
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
bool danger_safe_en, u32 ctrl_off)
{
DPU_REG_WRITE(&ctx->hw, ctrl_off,
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
}
static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
bool danger_safe_en)
{
if (!ctx)
return;
DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL,
danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0);
dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL);
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
@ -627,7 +645,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c,
c->ops.setup_multirect = dpu_hw_sspp_setup_multirect;
if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features))
c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3;
c->ops.setup_scaler = dpu_hw_sspp_setup_scaler3;
if (test_bit(DPU_SSPP_CDP, &features))
c->ops.setup_cdp = dpu_hw_sspp_setup_cdp;

52
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
View File

@ -332,5 +332,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device *dev,
int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms,
struct dentry *entry);
void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en);
void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
u32 mask, u8 en);
void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
const struct msm_format *format);
void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx,
const struct dpu_csc_cfg *data);
void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe,
struct dpu_hw_sspp *ctx,
u32 op_mode_off);
void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_format *fmt,
u32 flags, struct dpu_hw_sspp *ctx,
u32 op_mode_off, u32 unpack_pat_off, u32 format_off,
u32 ubwc_ctrl_off, u32 ubwc_err_off);
static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *cfg,
struct dpu_hw_sspp *ctx, u32 src_size_off,
u32 src_xy_off, u32 out_size_off, u32 out_xy_off)
{
struct dpu_hw_blk_reg_map *c;
u32 src_size, src_xy, dst_size, dst_xy;
c = &ctx->hw;
/* src and dest rect programming */
src_xy = (cfg->src_rect.y1 << 16) | cfg->src_rect.x1;
src_size = (drm_rect_height(&cfg->src_rect) << 16) |
drm_rect_width(&cfg->src_rect);
dst_xy = (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1;
dst_size = (drm_rect_height(&cfg->dst_rect) << 16) |
drm_rect_width(&cfg->dst_rect);
/* rectangle register programming */
DPU_REG_WRITE(c, src_size_off, src_size);
DPU_REG_WRITE(c, src_xy_off, src_xy);
DPU_REG_WRITE(c, out_size_off, dst_size);
DPU_REG_WRITE(c, out_xy_off, dst_xy);
}
void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe,
u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off);
void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx,
bool danger_safe_en, u32 ctrl_off);
#endif /*_DPU_HW_SSPP_H */