From 6e3e43605b0ddd813bcc27c809bd80d5fb37fbf3 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:31 +0800 Subject: [PATCH 001/864] dt-bindings: add Canaan K230 boards compatible strings Since K230 was released, K210 is no longer the only SoC in the Kendryte series, so remove the K210 string from the description. Also, add two boards based on k230 to compatible strings to allow them to be used in the dt. Signed-off-by: Yangyu Chen Acked-by: Krzysztof Kozlowski Reviewed-by: Damien Le Moal Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/canaan.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml index 41fd11f70a49..f9854ff43ac6 100644 --- a/Documentation/devicetree/bindings/riscv/canaan.yaml +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -10,7 +10,7 @@ maintainers: - Damien Le Moal description: - Canaan Kendryte K210 SoC-based boards + Canaan Kendryte SoC-based boards properties: $nodename: @@ -42,6 +42,12 @@ properties: - items: - const: canaan,kendryte-k210 + - items: + - enum: + - canaan,canmv-k230 + - canaan,k230-usip-lp3-evb + - const: canaan,kendryte-k230 + additionalProperties: true ... From e43a725a4d58e8cfb9bdc28fef12e3809caceee8 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:32 +0800 Subject: [PATCH 002/864] dt-bindings: timer: Add Canaan K230 CLINT Add compatible string for Canaan K230 CLINT. Signed-off-by: Yangyu Chen Acked-by: Rob Herring Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3c16b260db04..7936aebe1765 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -49,6 +49,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - canaan,k230-clint - sophgo,cv1800b-clint - sophgo,cv1812h-clint - sophgo,sg2002-clint From 85dca15595e58d06ac3e305b1464d2cc9520b184 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:33 +0800 Subject: [PATCH 003/864] dt-bindings: interrupt-controller: Add Canaan K230 PLIC Add compatible string for Canaan K230 PLIC. Signed-off-by: Yangyu Chen Acked-by: Rob Herring Reviewed-by: Guo Ren Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index e0267223887e..639bbeb1f6bd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -71,6 +71,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - canaan,k230-plic - sophgo,cv1800b-plic - sophgo,cv1812h-plic - sophgo,sg2002-plic From 980512a5ca6f4ada16824a139b063c2c877cd319 Mon Sep 17 00:00:00 2001 From: Yangyu Chen Date: Mon, 8 Apr 2024 00:28:34 +0800 Subject: [PATCH 004/864] riscv: dts: add initial canmv-k230 and k230-evb dts Add initial dts for CanMV-K230 and K230-EVB powered by Canaan Kendryte K230 SoC [1]. Some key consideration: - Only place BigCore which is 1.6GHz RV64GCBV The existence of cache coherence between the two cores remains unknown since they have dedicated L2 caches. And the factory SDK uses it for other OS by default. I don't know whether the two CPUs on K230 SoC can be used in one system. So only place BigCore here. Meanwhile, although docs from Canaan said 1.6GHz Core with Vector is CPU1, the CSR.MHARTID of this core is 0. - Support for "zba" "zbb" "zbc" "zbs" are tested by hand The user manual of C908 from T-Head does not document it specifically. It just said it supports B extension V1.0. [2] I have tested it by using this [3] which attempts to execute "add.uw", "andn", "clmulr", "bclr" and they doesn't traps on K230. But on JH7110, "clmulr" and "bclr" will trap. - Support for "zicbom" is tested by hand Have tested with some out-of-tree drivers from [4] that need DMA and they do not come to the dts currently. - Support for "zicboz" is tested by hand Have tested with my own bare mental M-Mode program [5] which tries to use zicboz to clear a 64B aligned block and got output[6] shows it supports zicboz. - Cache parameters are inferred from T-Head docs [2] and Canaan docs [1] L1i: 32KB, VIPT 4-Way set-associative, 64B Cacheline L1d: 32KB, VIPT 4-Way set-associative, 64B Cacheline L2: 256KB, PIPT 16-way set-associative, 64B Cacheline The numbers of cache sets are calculated from these parameters. - MMU only supports Sv39 The T-Head docs [2] say the C908 core can be configured to support Sv48 and Sv39 or only Sv39. On K230, I tried to write "riscv,sv48" on mmu-type in dts and boot the mainline kernel. However, it failed during the kernel probe and fell back to Sv39. I also tested it on M-Mode software, writing Sv48 to satp.mode will not trap but will leave the CSR unchanged. While writing Sv39, it will take effect. It shows that this CPU does not support Sv48. - Svpbmt and T-Head MAEE both supported T-Head C908 does support both Svpbmt and T-Head MAEE for page-based memory attributes and is controlled by BIT(21) on CSR.MXSTATUS. The Svpbmt is used here for mainline kernel support for K230. If the kernel wants to use Svpbmt, the M-Mode software should unset BIT(21) of CSR.MXSTATUS before entering the S-Mode kernel. Otherwise, the kernel will not boot, as 0 on T-Head MAEE is NonCachable Memory. Once the kernel switches from bare metal to Sv39, It will lose dirty cache line modifications that haven't been written back to the memory. [1] https://developer.canaan-creative.com/k230/dev/zh/00_hardware/K230_datasheet.html#chapter-1-introduction [2] https://occ-intl-prod.oss-ap-southeast-1.aliyuncs.com/resource//1699268369347/XuanTie-C908-UserManual.pdf [3] https://github.com/cyyself/rvb_test [4] https://github.com/cyyself/linux/tree/k230-mainline [5] https://github.com/cyyself/simple-sw-workbench/commit/32657d807d64217323a80cb04ce114671e51ed60 [6] https://gist.github.com/cyyself/aa98b07b8c77bb1d53b5a4c5e67a37cf Signed-off-by: Yangyu Chen Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/Makefile | 2 + arch/riscv/boot/dts/canaan/k230-canmv.dts | 24 ++++ arch/riscv/boot/dts/canaan/k230-evb.dts | 24 ++++ arch/riscv/boot/dts/canaan/k230.dtsi | 143 ++++++++++++++++++++++ 4 files changed, 193 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile index 987d1f0c41f0..7d54ea5c6f3d 100644 --- a/arch/riscv/boot/dts/canaan/Makefile +++ b/arch/riscv/boot/dts/canaan/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb +dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb +dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts new file mode 100644 index 000000000000..9565915cead6 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include "k230.dtsi" + +/ { + model = "Canaan CanMV-K230"; + compatible = "canaan,canmv-k230", "canaan,kendryte-k230"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ddr: memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts new file mode 100644 index 000000000000..f898b8e62368 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include "k230.dtsi" + +/ { + model = "Kendryte K230 EVB"; + compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + ddr: memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x20000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi new file mode 100644 index 000000000000..104e08ef5869 --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + */ + +#include + +/dts-v1/; +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "canaan,kendryte-k230"; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <27000000>; + + cpu@0 { + compatible = "thead,c908", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", + "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh", + "svpbmt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <128>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + next-level-cache = <&l2_cache>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <262144>; + cache-sets = <256>; + cache-unified; + }; + }; + + apb_clk: apb-clk-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "apb_clk"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + plic: interrupt-controller@f00000000 { + compatible = "canaan,k230-plic" ,"thead,c900-plic"; + reg = <0xf 0x00000000 0x0 0x04000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <208>; + }; + + clint: timer@f04000000 { + compatible = "canaan,k230-clint", "thead,c900-clint"; + reg = <0xf 0x04000000 0x0 0x00010000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + + uart0: serial@91400000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91400000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@91401000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91401000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@91402000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91402000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@91403000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91403000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@91404000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x91404000 0x0 0x1000>; + clocks = <&apb_clk>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; +}; From f7e74a96da5ce89fa4b6d77f0407fe011fe8cd2f Mon Sep 17 00:00:00 2001 From: Jiayu Du Date: Sat, 27 Dec 2025 17:23:54 +0800 Subject: [PATCH 005/864] riscv: dts: canaan: Correct the formatting issues about k230 dts Correct the errors in the spacing format, and move the aliases from the SoC's dtsi to the board's dts, since it's more standard. Signed-off-by: Jiayu Du Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230-canmv.dts | 4 ++++ arch/riscv/boot/dts/canaan/k230-evb.dts | 4 ++++ arch/riscv/boot/dts/canaan/k230.dtsi | 6 +----- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts index 9565915cead6..593ca38e6824 100644 --- a/arch/riscv/boot/dts/canaan/k230-canmv.dts +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -9,6 +9,10 @@ / { model = "Canaan CanMV-K230"; compatible = "canaan,canmv-k230", "canaan,kendryte-k230"; + aliases { + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts index f898b8e62368..bfa53f2e2403 100644 --- a/arch/riscv/boot/dts/canaan/k230-evb.dts +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts @@ -9,6 +9,10 @@ / { model = "Kendryte K230 EVB"; compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230"; + aliases { + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:115200n8"; }; diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 104e08ef5869..1aeb77160216 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -11,10 +11,6 @@ / { #size-cells = <2>; compatible = "canaan,kendryte-k230"; - aliases { - serial0 = &uart0; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -75,7 +71,7 @@ soc { ranges; plic: interrupt-controller@f00000000 { - compatible = "canaan,k230-plic" ,"thead,c900-plic"; + compatible = "canaan,k230-plic", "thead,c900-plic"; reg = <0xf 0x00000000 0x0 0x04000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; interrupt-controller; From 8205ceec006616adb4d8a86f1e53d8252fd3eddc Mon Sep 17 00:00:00 2001 From: Ze Huang <18771902331@163.com> Date: Thu, 26 Sep 2024 23:57:45 +0800 Subject: [PATCH 006/864] riscv: dts: canaan: Add k230's pinctrl node Add pinctrl device, containing default config for uart, pwm, iis, iic and mmc. Signed-off-by: Ze Huang <18771902331@163.com> Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230-canmv.dts | 304 ++++++++++++++++++++++ arch/riscv/boot/dts/canaan/k230-pinctrl.h | 18 ++ arch/riscv/boot/dts/canaan/k230.dtsi | 6 + 3 files changed, 328 insertions(+) create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts index 593ca38e6824..32ba53d17c00 100644 --- a/arch/riscv/boot/dts/canaan/k230-canmv.dts +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -26,3 +26,307 @@ ddr: memory@0 { &uart0 { status = "okay"; }; + +&pinctrl { + jtag_pins: jtag-pins { + jtag-tck-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-pull-down; + input-schmitt-enable; + }; + + jtag-tdi-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-disable; + }; + + jtag-tdo-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + jtag-tms-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + uart2-pins-cfg { + pinmux = , /* uart2 txd */ + ; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + output-enable; + bias-disable; + }; + }; + + pwm2_pins: pwm2-pins { + pwm2-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm3_pins: pwm3-pins { + pwm3-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + pwm4_pins: pwm4-pins { + pwm4-pin-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iis_pins: iis-pins { + iis-clk-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + iis-ws-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + + iis-din0-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + input-enable; + bias-disable; + }; + + iis-dout0-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <4>; + power-source = ; + output-enable; + bias-disable; + }; + }; + + uart4_pins: uart4-pins { + uart4-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart4-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + uart0_pins: uart0-pins { + uart0-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart0-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + iic1_pins: iic1-pins { + iic1-pins-cfg { + pinmux = , /* iic1 scl */ + ; /* iic1 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic3_pins: iic3-pins { + iic3-pins-cfg { + pinmux = , /* iic3 scl */ + ; /* iic3 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic4_pins: iic4-pins { + iic4-pins-cfg { + pinmux = , /* iic4 scl */ + ; /* iic4 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + iic0_pins: iic0-pins { + iic0-pins-cfg { + pinmux = , /* iic0 scl */ + ; /* iic0 sda */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; + + uart3_pins: uart3-pins { + uart3-txd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + uart3-rxd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + key_pins: key-pins { + key-pins-cfg { + pinmux = , /* key0 */ + ; /* key1 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-disable; + input-schmitt-enable; + }; + }; + + mmc1_pins: mmc1-pins { + mmc1-cmd-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + + mmc1-clk-cfg { + pinmux = ; + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + output-enable; + bias-disable; + input-schmitt-enable; + }; + + mmc1-data-cfg { + pinmux = , /* mmc1 data0 */ + , /* mmc1 data1 */ + , /* mmc1 data2 */ + ; /* mmc1 data3 */ + slew-rate = <0>; + drive-strength = <7>; + power-source = ; + input-enable; + output-enable; + bias-pull-up; + input-schmitt-enable; + }; + }; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.h b/arch/riscv/boot/dts/canaan/k230-pinctrl.h new file mode 100644 index 000000000000..63dd999ca55b --- /dev/null +++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Canaan Bright Sight Co. Ltd + * Copyright (C) 2024 Ze Huang <18771902331@163.com> + */ + +#ifndef _K230_PINCTRL_H +#define _K230_PINCTRL_H + +#define K230_MSC_3V3 0 +#define K230_MSC_1V8 1 + +#define BANK_VOLTAGE_DEFAULT K230_MSC_1V8 +#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3 + +#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode)) + +#endif /* _K230_PINCTRL_H */ diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 1aeb77160216..5a1bf8a15abe 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -4,6 +4,7 @@ */ #include +#include "k230-pinctrl.h" /dts-v1/; / { @@ -86,6 +87,11 @@ clint: timer@f04000000 { interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; + pinctrl: pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x0 0x91105000 0x0 0x100>; + }; + uart0: serial@91400000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91400000 0x0 0x1000>; From 7071ae1d8a7623e4a83ada61f7e68761f6bef0e0 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sun, 18 Jan 2026 22:25:07 +0800 Subject: [PATCH 007/864] riscv: dts: canaan: k230: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k230.dtsi to conform to this rule. Also synchronize "riscv,isa" with "riscv,isa-extensions". Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 5a1bf8a15abe..041c9947a8fa 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -21,9 +21,9 @@ cpu@0 { compatible = "thead,c908", "riscv"; device_type = "cpu"; reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihpm_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicsr", "zifencei", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh", "svpbmt"; From 714e4cb7784ad798c1e19134d0125d5751a70131 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sat, 17 Jan 2026 18:06:23 +0800 Subject: [PATCH 008/864] riscv: dts: canaan: add reset controller for K230 Add the reset controller node for the K230 SoC. Also add the reset properties for all UART nodes. Signed-off-by: Junhui Liu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index 041c9947a8fa..a73b1926ab93 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include "k230-pinctrl.h" /dts-v1/; @@ -87,6 +88,12 @@ clint: timer@f04000000 { interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; }; + rst: reset-controller@91101000 { + compatible = "canaan,k230-rst"; + reg = <0x0 0x91101000 0x0 0x1000>; + #reset-cells = <1>; + }; + pinctrl: pinctrl@91105000 { compatible = "canaan,k230-pinctrl"; reg = <0x0 0x91105000 0x0 0x100>; @@ -99,6 +106,7 @@ uart0: serial@91400000 { interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART0>; status = "disabled"; }; @@ -109,6 +117,7 @@ uart1: serial@91401000 { interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART1>; status = "disabled"; }; @@ -119,6 +128,7 @@ uart2: serial@91402000 { interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART2>; status = "disabled"; }; @@ -129,6 +139,7 @@ uart3: serial@91403000 { interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART3>; status = "disabled"; }; @@ -139,6 +150,7 @@ uart4: serial@91404000 { interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; + resets = <&rst RST_UART4>; status = "disabled"; }; }; From 8f0a393b7d91ca66756123ac5f09b89c1696ff11 Mon Sep 17 00:00:00 2001 From: Xukai Wang Date: Sat, 25 Apr 2026 17:29:33 +0800 Subject: [PATCH 009/864] riscv: dts: canaan: Add clock definition for K230 This patch describes the clock controller integrated in K230 SoC and replace dummy clocks with the real ones for UARTs. For k230-canmv and k230-evb, they provide an additional external pulse input through a pin to serve as clock source. Co-developed-by: Troy Mitchell Signed-off-by: Troy Mitchell Signed-off-by: Xukai Wang Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/canaan/k230-canmv.dts | 11 ++++++++++ arch/riscv/boot/dts/canaan/k230-evb.dts | 11 ++++++++++ arch/riscv/boot/dts/canaan/k230.dtsi | 26 ++++++++++++++++------- 3 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts index 32ba53d17c00..2ba555f6de13 100644 --- a/arch/riscv/boot/dts/canaan/k230-canmv.dts +++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts @@ -21,6 +21,12 @@ ddr: memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x20000000>; }; + + timerx_pulse_in: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; }; &uart0 { @@ -330,3 +336,8 @@ mmc1-data-cfg { }; }; }; + +&sysclk { + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts index bfa53f2e2403..4246e4bba6cc 100644 --- a/arch/riscv/boot/dts/canaan/k230-evb.dts +++ b/arch/riscv/boot/dts/canaan/k230-evb.dts @@ -21,8 +21,19 @@ ddr: memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x20000000>; }; + + timerx_pulse_in: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; }; &uart0 { status = "okay"; }; + +&sysclk { + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; +}; diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi index a73b1926ab93..6dcb628a960b 100644 --- a/arch/riscv/boot/dts/canaan/k230.dtsi +++ b/arch/riscv/boot/dts/canaan/k230.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2024 Yangyu Chen */ +#include #include #include #include "k230-pinctrl.h" @@ -57,11 +58,11 @@ l2_cache: l2-cache { }; }; - apb_clk: apb-clk-clock { + osc24m: clock-24000000 { compatible = "fixed-clock"; - clock-frequency = <50000000>; - clock-output-names = "apb_clk"; #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc24m"; }; soc { @@ -99,10 +100,19 @@ pinctrl: pinctrl@91105000 { reg = <0x0 0x91105000 0x0 0x100>; }; + sysclk: clock-controller@91102000 { + compatible = "canaan,k230-clk"; + reg = <0x0 0x91102000 0x0 0x40>, + <0x0 0x91100000 0x0 0x108>; + clocks = <&osc24m>; + clock-names = "osc24m"; + #clock-cells = <1>; + }; + uart0: serial@91400000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91400000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART0_RATE>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -113,7 +123,7 @@ uart0: serial@91400000 { uart1: serial@91401000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91401000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART1_RATE>; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -124,7 +134,7 @@ uart1: serial@91401000 { uart2: serial@91402000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91402000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART2_RATE>; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -135,7 +145,7 @@ uart2: serial@91402000 { uart3: serial@91403000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91403000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART3_RATE>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; @@ -146,7 +156,7 @@ uart3: serial@91403000 { uart4: serial@91404000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x91404000 0x0 0x1000>; - clocks = <&apb_clk>; + clocks = <&sysclk K230_LS_UART4_RATE>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; reg-shift = <2>; From 85babf47515e2adf266dcc3be9804e31f752083e Mon Sep 17 00:00:00 2001 From: Jakob Unterwurzacher Date: Tue, 9 Jun 2026 10:17:25 +0200 Subject: [PATCH 010/864] arm64: dts: rockchip: fix emmc reset polarity on px30-cobra Technically, the reset signal is active low - it's called RST_n after all. But it is ignored completely unless RST_n_FUNCTION=1 (byte 162 in extcsd) is set in the emmc. It is 0 per default. For emmcs that have RST_n_FUNCTION=1 we failed like this: [ 3.074480] mmc1: Failed to initialize a non-removable card With this change they work normally. Cc: stable@vger.kernel.org Fixes: bb510ddc9d3e ("arm64: dts: rockchip: add px30-cobra base dtsi and board variants") Signed-off-by: Jakob Unterwurzacher Tested-by: Quentin Schulz Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260609081728.30616-2-jakobunt@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-cobra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi index add917af5de7..f14f9eca7d34 100644 --- a/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-cobra.dtsi @@ -35,7 +35,7 @@ emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; pinctrl-0 = <&emmc_reset>; pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; }; gpio-leds { From 2a08921edcab6a462fa6ddb02c91b90b5ac92429 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 12 Jun 2026 18:47:34 +0200 Subject: [PATCH 011/864] arm64: dts: rockchip: fix eMMC reset polarity on PP-1516 According to the Jedec 5.1 specification, the device is held in reset when RST_n is low, therefore the polarity of the line must be that, as specified in the Device Tree binding (mmc/mmc-pwrseq-emmc.yaml). Due to the wrong polarity, eMMC devices with RST_n_FUNCTION[162] bitfield [1:0] set to 0x1 (the default is 0x0) will be held in reset forever. Cc: stable@vger.kernel.org Fixes: 56198acdbf0d ("arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants") Signed-off-by: Quentin Schulz Link: https://patch.msgid.link/20260612-pp1516-emmc-polarity-v1-1-4816c1c909f7@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi index 192791993f05..02200de695d3 100644 --- a/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-pp1516.dtsi @@ -33,7 +33,7 @@ emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; pinctrl-0 = <&emmc_reset>; pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; }; gpio-leds { From 13f9cdcf462f98199d6a2bd408c39fac947633dc Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 10 Jun 2026 15:18:20 +0300 Subject: [PATCH 012/864] arm: dts: nuvoton: npcm7xx: Drop bogus FIU memory reg-names The NPCM7xx FIU controller nodes only describe the control register block, but they still advertise a second "memory" entry in reg-names. Drop the bogus name so the DTS matches the resources actually present in each node. Signed-off-by: Tomer Maimon Reviewed-by: Krzysztof Kozlowski Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index ab3c3c5713ae..a16450abea0e 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -191,7 +191,7 @@ fiu0: spi@fb000000 { #address-cells = <1>; #size-cells = <0>; reg = <0xfb000000 0x1000>; - reg-names = "control", "memory"; + reg-names = "control"; clocks = <&clk NPCM7XX_CLK_SPI0>; clock-names = "clk_spi0"; status = "disabled"; @@ -202,7 +202,7 @@ fiu3: spi@c0000000 { #address-cells = <1>; #size-cells = <0>; reg = <0xc0000000 0x1000>; - reg-names = "control", "memory"; + reg-names = "control"; clocks = <&clk NPCM7XX_CLK_SPI3>; clock-names = "clk_spi3"; pinctrl-names = "default"; @@ -215,7 +215,7 @@ fiux: spi@fb001000 { #address-cells = <1>; #size-cells = <0>; reg = <0xfb001000 0x1000>; - reg-names = "control", "memory"; + reg-names = "control"; clocks = <&clk NPCM7XX_CLK_SPIX>; clock-names = "clk_spix"; status = "disabled"; From d7cb66fad58d8fe3cb8c43f5e48dd51a8c15358c Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 10 Jun 2026 15:18:21 +0300 Subject: [PATCH 013/864] arm: dts: nuvoton: npcm7xx: Drop redundant FIU clock-names The NPCM7xx FIU controller nodes reference a single clock, but their clock-names properties are not described by the FIU binding. Drop the undocumented names so the DTS matches the binding. Signed-off-by: Tomer Maimon Reviewed-by: Krzysztof Kozlowski Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index a16450abea0e..83cd10b47273 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -193,7 +193,6 @@ fiu0: spi@fb000000 { reg = <0xfb000000 0x1000>; reg-names = "control"; clocks = <&clk NPCM7XX_CLK_SPI0>; - clock-names = "clk_spi0"; status = "disabled"; }; @@ -204,7 +203,6 @@ fiu3: spi@c0000000 { reg = <0xc0000000 0x1000>; reg-names = "control"; clocks = <&clk NPCM7XX_CLK_SPI3>; - clock-names = "clk_spi3"; pinctrl-names = "default"; pinctrl-0 = <&spi3_pins>; status = "disabled"; @@ -217,7 +215,6 @@ fiux: spi@fb001000 { reg = <0xfb001000 0x1000>; reg-names = "control"; clocks = <&clk NPCM7XX_CLK_SPIX>; - clock-names = "clk_spix"; status = "disabled"; }; From b90a899027ae9def17cff2c566f50e406bb95307 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 22 May 2026 15:41:59 +0530 Subject: [PATCH 014/864] arm64: dts: qcom: glymur: Add GPU smmu node Add the nodes to describe the GPU SMMU node. Signed-off-by: Rajendra Nayak Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20260522-glymur-gpu-dt-v5-3-562c406b210c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 20b49af7298e..2303b71e0a69 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3779,6 +3779,44 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; + clock-names = "hlos"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + ipcc: mailbox@3e04000 { compatible = "qcom,glymur-ipcc", "qcom,ipcc"; reg = <0x0 0x03e04000 0x0 0x1000>; From b6ff8cec8aaac2128a4fe82ccfba263cf645cc68 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Fri, 22 May 2026 15:42:00 +0530 Subject: [PATCH 015/864] arm64: dts: qcom: Add GPU support for Glymur The Adreno X2 series GPU present in Glymur SoC belongs to the A8x family. It is a new HW IP with architectural improvements as well as different set of hw configs like GMEM, num SPs, Caches sizes etc. Add the GPU and GMU nodes to describe this hardware. Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20260522-glymur-gpu-dt-v5-4-562c406b210c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 183 +++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 2303b71e0a69..bbc14a8d8714 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3751,6 +3751,129 @@ hsc_noc: interconnect@2000000 { #interconnect-cells = <2>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-44070001", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x6c000>, + <0x0 0x03d9e000 0x0 0x2000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + + interrupts = ; + + iommus = <&adreno_smmu 0 0x0>, + <&adreno_smmu 1 0x0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + #cooling-cells = <2>; + + interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2-adreno", + "operating-points-v2"; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + opp-level = ; + opp-peak-kBps = <2136719>; + opp-supported-hw = <0xf>; + /* ACD is disabled */ + }; + + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-level = ; + opp-peak-kBps = <6074219>; + opp-supported-hw = <0xf>; + /* ACD is disabled */ + }; + + opp-572000000 { + opp-hz = /bits/ 64 <572000000>; + opp-level = ; + opp-peak-kBps = <12449219>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0xe02d5ffd>; + }; + + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-level = ; + opp-peak-kBps = <12449219>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0xc0285ffd>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0xa82e5ffd>; + }; + + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882d5ffd>; + }; + + opp-1070000000 { + opp-hz = /bits/ 64 <1070000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882b5ffd>; + }; + + opp-1185000000 { + opp-hz = /bits/ 64 <1185000000>; + opp-level = ; + opp-peak-kBps = <16500000>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0xf>; + qcom,opp-acd-level = <0x882a5ffd>; + }; + + opp-1550000000 { + opp-hz = /bits/ 64 <1550000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0xa8295ffd>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0x7>; + qcom,opp-acd-level = <0x88295ffd>; + }; + + opp-1850000000 { + opp-hz = /bits/ 64 <1850000000>; + opp-level = ; + opp-peak-kBps = <18597657>; + opp-supported-hw = <0x3>; + qcom,opp-acd-level = <0x88285ffd>; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible = "qcom,glymur-gxclkctl"; reg = <0x0 0x03d64000 0x0 0x6000>; @@ -3762,6 +3885,66 @@ gxclkctl: clock-controller@3d64000 { #power-domain-cells = <1>; }; + gmu: gmu@3d6c000 { + compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; + + reg = <0x0 0x03d6c000 0x0 0x32000>; + reg-names = "gmu"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_GPU_GEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_RSCC_HUB_AON_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "memnoc", + "hub", + "rscc"; + + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5 0x0>; + + qcom,qmp = <&aoss_qmp>; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + opp-level = ; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + }; + + opp-725000000 { + opp-hz = /bits/ 64 <725000000>; + opp-level = ; + }; + + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,glymur-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; From 7d260e77d88fa026a1e181cecee545687fa80f92 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Fri, 22 May 2026 15:42:01 +0530 Subject: [PATCH 016/864] arm64: dts: qcom: glymur: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when it reaches 95°C. Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Akhil P Oommen Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260522-glymur-gpu-dt-v5-5-562c406b210c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 240 ++++++++++++++++++++------- 1 file changed, 184 insertions(+), 56 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index bbc14a8d8714..e753d948fec1 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -22,6 +22,7 @@ #include #include #include +#include #include "glymur-ipcc.h" @@ -8528,13 +8529,22 @@ aoss-7-critical { }; thermal_gpu_0_0: gpu-0-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 1>; + cooling-maps { + map0 { + trip = <&gpu00_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu00_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-0-0-critical { @@ -8543,16 +8553,26 @@ gpu-0-0-critical { type = "critical"; }; }; + }; thermal_gpu_0_1: gpu-0-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 2>; + cooling-maps { + map0 { + trip = <&gpu01_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu01_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-0-1-critical { @@ -8564,13 +8584,22 @@ gpu-0-1-critical { }; thermal_gpu_0_2: gpu-0-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 3>; + cooling-maps { + map0 { + trip = <&gpu02_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu02_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-0-2-critical { @@ -8582,13 +8611,22 @@ gpu-0-2-critical { }; thermal_gpu_1_0: gpu-1-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 4>; + cooling-maps { + map0 { + trip = <&gpu10_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu10_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-1-0-critical { @@ -8600,13 +8638,22 @@ gpu-1-0-critical { }; thermal_gpu_1_1: gpu-1-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 5>; + cooling-maps { + map0 { + trip = <&gpu11_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu11_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-1-1-critical { @@ -8618,13 +8665,22 @@ gpu-1-1-critical { }; thermal_gpu_1_2: gpu-1-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 6>; + cooling-maps { + map0 { + trip = <&gpu12_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu12_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-1-2-critical { @@ -8636,13 +8692,22 @@ gpu-1-2-critical { }; thermal_gpu_2_0: gpu-2-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 7>; + cooling-maps { + map0 { + trip = <&gpu20_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu20_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-2-0-critical { @@ -8654,13 +8719,22 @@ gpu-2-0-critical { }; thermal_gpu_2_1: gpu-2-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 8>; + cooling-maps { + map0 { + trip = <&gpu21_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu21_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-2-1-critical { @@ -8672,13 +8746,22 @@ gpu-2-1-critical { }; thermal_gpu_2_2: gpu-2-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 9>; + cooling-maps { + map0 { + trip = <&gpu22_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu22_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-2-2-critical { @@ -8690,13 +8773,22 @@ gpu-2-2-critical { }; thermal_gpu_3_0: gpu-3-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 10>; + cooling-maps { + map0 { + trip = <&gpu30_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu30_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-3-0-critical { @@ -8708,13 +8800,22 @@ gpu-3-0-critical { }; thermal_gpu_3_1: gpu-3-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 11>; + cooling-maps { + map0 { + trip = <&gpu31_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu31_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-3-1-critical { @@ -8726,13 +8827,22 @@ gpu-3-1-critical { }; thermal_gpu_3_2: gpu-3-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 12>; + cooling-maps { + map0 { + trip = <&gpu32_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpu32_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpu-3-2-critical { @@ -8744,13 +8854,22 @@ gpu-3-2-critical { }; thermal_gpuss_0: gpuss-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 13>; + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpuss0_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpuss-0-critical { @@ -8762,13 +8881,22 @@ gpuss-0-critical { }; thermal_gpuss_1: gpuss-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&tsens7 14>; + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { - temperature = <90000>; - hysteresis = <5000>; - type = "hot"; + gpuss1_alert0: trip-point0 { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; }; gpuss-1-critical { From 9d6a63012fcc3ff9152d802aeaea7d3a5a839e02 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 1 May 2026 11:18:33 +0200 Subject: [PATCH 017/864] arm64: dts: qcom: milos: Add interconnects to camcc The CAMSS_TOP_GDSC inside camcc requires an interconnect path to be enabled, otherwise the GDSC will be stuck on 'off' and can't be enabled. Add the interconnect path so that this requirement can be satisfied by the kernel. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260501-milos-camcc-icc-v2-5-bb83c1256cc3@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 8c9232988953..e97c9ca8320e 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1971,6 +1971,9 @@ camcc: clock-controller@adb0000 { <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; + #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; From ea2f58d9ebb0598611085a54528188d2322ae6fb Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 25 Jun 2026 16:02:02 +0530 Subject: [PATCH 018/864] dt-bindings: arm: qcom: sort compatibles alphabetically by base SoC The compatible entries in qcom.yaml were not in alphabetical order by their base SoC compatible string (the last const: qcom,* in each block), making the file harder to audit and maintain. Sort the entries for better maintenance. No functional change; reordering only. Assisted-by: Claude:claude-sonnet-4-6 Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260625-reorg_qcom_binding-v1-1-f2c6501f7401@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/arm/qcom.yaml | 494 +++++++++--------- 1 file changed, 247 insertions(+), 247 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 50cc18a6ec5e..dfbc82377fcf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -49,18 +49,31 @@ properties: - qcom,apq8074-dragonboard - const: qcom,apq8074 - - items: - - enum: - - qcom,apq8060-dragonboard - - qcom,msm8660-surf - - const: qcom,msm8660 - - items: - enum: - qcom,apq8084-mtp - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - sony,karin_windy + - const: qcom,apq8094 + + - items: + - enum: + - arrow,apq8096-db820c + - inforce,ifc6640 + - const: qcom,apq8096-sbc + - const: qcom,apq8096 + + - items: + - const: arrow,apq8096sg-db820c + - const: arrow,apq8096-db820c + - const: qcom,apq8096-sbc + - const: qcom,apq8096sg + - const: qcom,apq8096 + - items: - enum: - qcom,eliza-mtp @@ -71,11 +84,97 @@ properties: - qcom,glymur-crd - const: qcom,glymur + - items: + - enum: + - 8dev,jalapeno + - alfa-network,ap120c-ac + - const: qcom,ipq4018 + + - items: + - enum: + - qcom,ipq4019-ap-dk01.1-c1 + - qcom,ipq4019-ap-dk04.1-c3 + - qcom,ipq4019-ap-dk07.1-c1 + - qcom,ipq4019-ap-dk07.1-c2 + - qcom,ipq4019-dk04.1-c1 + - const: qcom,ipq4019 + + - items: + - enum: + - qcom,ipq5018-rdp432-c2 + - tplink,archer-ax55-v1 + - const: qcom,ipq5018 + + - items: + - enum: + - qcom,ipq5210-rdp504 + - const: qcom,ipq5210 + + - items: + - enum: + - qcom,ipq5332-ap-mi01.2 + - qcom,ipq5332-ap-mi01.3 + - qcom,ipq5332-ap-mi01.6 + - qcom,ipq5332-ap-mi01.9 + - const: qcom,ipq5332 + + - items: + - enum: + - qcom,ipq5424-rdp466 + - const: qcom,ipq5424 + + - items: + - enum: + - qcom,ipq6018-cp01 + - qcom,ipq6018-cp01-c1 + - const: qcom,ipq6018 + + - items: + - enum: + - mikrotik,rb3011 + - qcom,ipq8064-ap148 + - const: qcom,ipq8064 + + - items: + - enum: + - qcom,ipq8074-hk01 + - qcom,ipq8074-hk10-c1 + - qcom,ipq8074-hk10-c2 + - const: qcom,ipq8074 + + - items: + - enum: + - qcom,ipq9574-ap-al02-c2 + - qcom,ipq9574-ap-al02-c2-emmc + - qcom,ipq9574-ap-al02-c6 + - qcom,ipq9574-ap-al02-c7 + - qcom,ipq9574-ap-al02-c7-emmc + - qcom,ipq9574-ap-al02-c8 + - qcom,ipq9574-ap-al02-c9 + - const: qcom,ipq9574 + + - items: + - enum: + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 + + - items: + - enum: + - qcom,kaanapali-mtp + - qcom,kaanapali-qrd + - const: qcom,kaanapali + - items: - enum: - qcom,mahua-crd - const: qcom,mahua + - description: Sierra Wireless MangOH Green with WP8548 Module + items: + - const: swir,mangoh-green-wp8548 + - const: swir,wp8548 + - const: qcom,mdm9615 + - items: - enum: - fairphone,fp6 @@ -102,11 +201,69 @@ properties: - const: qcom,msm8926 - const: qcom,msm8226 + - items: + - enum: + - qcom,apq8060-dragonboard + - qcom,msm8660-surf + - const: qcom,msm8660 + + - items: + - enum: + - acer,a1-724 + - alcatel,idol347 + - asus,z00l + - gplus,fl8005a + - huawei,g7 + - lg,c50 + - lg,m216 + - longcheer,l8910 + - longcheer,l8150 + - motorola,harpia + - motorola,osprey + - motorola,surnia + - qcom,msm8916-mtp + - samsung,a3u-eur + - samsung,a5u-eur + - samsung,coreprimeltevzw + - samsung,e5 + - samsung,e7 + - samsung,fortuna3g + - samsung,gprimeltecan + - samsung,grandmax + - samsung,grandprimelte + - samsung,gt510 + - samsung,gt58 + - samsung,j3ltetw + - samsung,j5 + - samsung,j5x + - samsung,rossa + - samsung,serranove + - thwc,uf896 + - thwc,ufi001c + - wiko,chuppito + - wingtech,wt86518 + - wingtech,wt86528 + - wingtech,wt88047 + - yiming,uz801-v3 + - const: qcom,msm8916 + + - items: + - enum: + - xiaomi,riva + - xiaomi,rolex + - xiaomi,tiare + - const: qcom,msm8917 + - items: - enum: - wingtech,wt82918hd - const: qcom,msm8929 + - items: + - enum: + - xiaomi,land + - const: qcom,msm8937 + - items: - enum: - asus,z00t @@ -119,6 +276,16 @@ properties: - wingtech,wt82918hdhw39 - const: qcom,msm8939 + - items: + - enum: + - flipkart,rimob + - motorola,potter + - xiaomi,daisy + - xiaomi,mido + - xiaomi,tissot + - xiaomi,vince + - const: qcom,msm8953 + - items: - enum: - sony,kugo-row @@ -170,68 +337,6 @@ properties: - longcheer,l9360 - const: qcom,msm8976 - - items: - - enum: - - acer,a1-724 - - alcatel,idol347 - - asus,z00l - - gplus,fl8005a - - huawei,g7 - - lg,c50 - - lg,m216 - - longcheer,l8910 - - longcheer,l8150 - - motorola,harpia - - motorola,osprey - - motorola,surnia - - qcom,msm8916-mtp - - samsung,a3u-eur - - samsung,a5u-eur - - samsung,coreprimeltevzw - - samsung,e5 - - samsung,e7 - - samsung,fortuna3g - - samsung,gprimeltecan - - samsung,grandmax - - samsung,grandprimelte - - samsung,gt510 - - samsung,gt58 - - samsung,j3ltetw - - samsung,j5 - - samsung,j5x - - samsung,rossa - - samsung,serranove - - thwc,uf896 - - thwc,ufi001c - - wiko,chuppito - - wingtech,wt86518 - - wingtech,wt86528 - - wingtech,wt88047 - - yiming,uz801-v3 - - const: qcom,msm8916 - - - items: - - enum: - - xiaomi,riva - - xiaomi,rolex - - xiaomi,tiare - - const: qcom,msm8917 - - - items: - - enum: - - xiaomi,land - - const: qcom,msm8937 - - - items: - - enum: - - flipkart,rimob - - motorola,potter - - xiaomi,daisy - - xiaomi,mido - - xiaomi,tissot - - xiaomi,vince - - const: qcom,msm8953 - - items: - enum: - lg,bullhead @@ -240,11 +345,6 @@ properties: - xiaomi,libra - const: qcom,msm8992 - - items: - - enum: - - sony,karin_windy - - const: qcom,apq8094 - - items: - enum: - huawei,angler @@ -256,20 +356,6 @@ properties: - sony,suzuran-row - const: qcom,msm8994 - - items: - - enum: - - arrow,apq8096-db820c - - inforce,ifc6640 - - const: qcom,apq8096-sbc - - const: qcom,apq8096 - - - items: - - const: arrow,apq8096sg-db820c - - const: arrow,apq8096-db820c - - const: qcom,apq8096-sbc - - const: qcom,apq8096sg - - const: qcom,apq8096 - - items: - enum: - oneplus,oneplus3 @@ -303,86 +389,6 @@ properties: - xiaomi,sagit - const: qcom,msm8998 - - items: - - enum: - - 8dev,jalapeno - - alfa-network,ap120c-ac - - const: qcom,ipq4018 - - - items: - - enum: - - qcom,ipq4019-ap-dk01.1-c1 - - qcom,ipq4019-ap-dk04.1-c3 - - qcom,ipq4019-ap-dk07.1-c1 - - qcom,ipq4019-ap-dk07.1-c2 - - qcom,ipq4019-dk04.1-c1 - - const: qcom,ipq4019 - - - items: - - enum: - - qcom,ipq5018-rdp432-c2 - - tplink,archer-ax55-v1 - - const: qcom,ipq5018 - - - items: - - enum: - - qcom,ipq5210-rdp504 - - const: qcom,ipq5210 - - - items: - - enum: - - qcom,ipq5332-ap-mi01.2 - - qcom,ipq5332-ap-mi01.3 - - qcom,ipq5332-ap-mi01.6 - - qcom,ipq5332-ap-mi01.9 - - const: qcom,ipq5332 - - - items: - - enum: - - qcom,ipq5424-rdp466 - - const: qcom,ipq5424 - - - items: - - enum: - - mikrotik,rb3011 - - qcom,ipq8064-ap148 - - const: qcom,ipq8064 - - - items: - - enum: - - qcom,ipq8074-hk01 - - qcom,ipq8074-hk10-c1 - - qcom,ipq8074-hk10-c2 - - const: qcom,ipq8074 - - - items: - - enum: - - qcom,ipq9574-ap-al02-c2 - - qcom,ipq9574-ap-al02-c2-emmc - - qcom,ipq9574-ap-al02-c6 - - qcom,ipq9574-ap-al02-c7 - - qcom,ipq9574-ap-al02-c7-emmc - - qcom,ipq9574-ap-al02-c8 - - qcom,ipq9574-ap-al02-c9 - - const: qcom,ipq9574 - - - items: - - enum: - - qcom,ipq9650-rdp488 - - const: qcom,ipq9650 - - - items: - - enum: - - qcom,kaanapali-mtp - - qcom,kaanapali-qrd - - const: qcom,kaanapali - - - description: Sierra Wireless MangOH Green with WP8548 Module - items: - - const: swir,mangoh-green-wp8548 - - const: swir,wp8548 - - const: qcom,mdm9615 - - description: Qualcomm Technologies, Inc. Robotics RB1 items: - enum: @@ -403,6 +409,20 @@ properties: - thundercomm,rubikpi3 - const: qcom,qcm6490 + - items: + - enum: + - qcom,qcs404-evb-1000 + - qcom,qcs404-evb-4000 + - const: qcom,qcs404-evb + - const: qcom,qcs404 + + - items: + - enum: + - arduino,monza + - qcom,monaco-evk + - qcom,qcs8300-ride + - const: qcom,qcs8300 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform items: - enum: @@ -416,6 +436,31 @@ properties: - qcom,qru1000-idp - const: qcom,qru1000 + - items: + - enum: + - qcom,sa8155p-adp + - const: qcom,sa8155p + + - items: + - enum: + - qcom,sa8295p-adp + - qcom,sa8540p-ride + - const: qcom,sa8540p + + - items: + - enum: + - qcom,sa8775p-ride + - qcom,sa8775p-ride-r3 + - const: qcom,sa8775p + + - items: + - enum: + - qcom,lemans-evk + - qcom,qcs9100-ride + - qcom,qcs9100-ride-r3 + - const: qcom,qcs9100 + - const: qcom,sa8775p + - description: Qualcomm AR2 Gen1 platform items: - enum: @@ -828,14 +873,6 @@ properties: - const: google,zombie-sku514 - const: qcom,sc7280 - - description: Xiaomi Poco F1 - items: - - enum: - - xiaomi,beryllium-ebbg - - xiaomi,beryllium-tianma - - const: xiaomi,beryllium - - const: qcom,sdm845 - - items: - enum: - lenovo,flex-5g @@ -853,6 +890,11 @@ properties: - qcom,sc8280xp-qrd - const: qcom,sc8280xp + - items: + - enum: + - inforce,ifc6560 + - const: qcom,sda660 + - items: - enum: - lenovo,tbx605f @@ -867,11 +909,6 @@ properties: - sony,voyager-row - const: qcom,sdm630 - - items: - - enum: - - inforce,ifc6560 - - const: qcom,sda660 - - items: - enum: - fairphone,fp3 @@ -899,74 +936,13 @@ properties: - const: google,bonito - const: qcom,sdm670 - - items: + - description: Xiaomi Poco F1 + items: - enum: - - qcom,sdx55-mtp - - qcom,sdx55-telit-fn980-tlb - - qcom,sdx55-t55 - - const: qcom,sdx55 - - - items: - - enum: - - qcom,sdx65-mtp - - const: qcom,sdx65 - - - items: - - enum: - - qcom,sdx75-idp - - const: qcom,sdx75 - - - items: - - enum: - - qcom,ipq6018-cp01 - - qcom,ipq6018-cp01-c1 - - const: qcom,ipq6018 - - - items: - - enum: - - qcom,qcs404-evb-1000 - - qcom,qcs404-evb-4000 - - const: qcom,qcs404-evb - - const: qcom,qcs404 - - - items: - - enum: - - arduino,monza - - qcom,monaco-evk - - qcom,qcs8300-ride - - const: qcom,qcs8300 - - - items: - - enum: - - qcom,qcs615-ride - - qcom,talos-evk - - const: qcom,qcs615 - - const: qcom,sm6150 - - - items: - - enum: - - qcom,sa8155p-adp - - const: qcom,sa8155p - - - items: - - enum: - - qcom,sa8295p-adp - - qcom,sa8540p-ride - - const: qcom,sa8540p - - - items: - - enum: - - qcom,sa8775p-ride - - qcom,sa8775p-ride-r3 - - const: qcom,sa8775p - - - items: - - enum: - - qcom,lemans-evk - - qcom,qcs9100-ride - - qcom,qcs9100-ride-r3 - - const: qcom,qcs9100 - - const: qcom,sa8775p + - xiaomi,beryllium-ebbg + - xiaomi,beryllium-tianma + - const: xiaomi,beryllium + - const: qcom,sdm845 - items: - enum: @@ -989,6 +965,23 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - qcom,sdx55-mtp + - qcom,sdx55-telit-fn980-tlb + - qcom,sdx55-t55 + - const: qcom,sdx55 + + - items: + - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + + - items: + - enum: + - qcom,sdx75-idp + - const: qcom,sdx75 + - items: - enum: - oneplus,billie2 @@ -1024,6 +1017,13 @@ properties: - xiaomi,willow - const: qcom,sm6125 + - items: + - enum: + - qcom,qcs615-ride + - qcom,talos-evk + - const: qcom,qcs615 + - const: qcom,sm6150 + - items: - enum: - sony,pdx213 From bc7b17594a17dbd752c42e203d3669f08bf0a4f9 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 Jun 2026 16:19:52 +0200 Subject: [PATCH 019/864] arm64: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins Since commit 9c105255108b ("pinctrl: pinconf-generic: perform basic checks on pincfg properties"), the generic pinconf parser logs an error when a pin configuration node specifies more than one bias mode. Several ZynqMP boards described SDIO card-detect and write-protect pins with both bias-high-impedance and bias-pull-up, which triggers at pinctrl probe: generic pinconfig core: /firmware/zynqmp-firmware/pinctrl/.../conf-cd: cannot have multiple bias configurations On ZynqMP, bias-high-impedance enables tri-state while bias-pull-up enables the internal pull resistor; these are mutually exclusive bias settings and only pull-up is needed for CD/WP inputs. Drop the redundant bias-high-impedance property and keep bias-pull-up. Reported-by: Mikko Rapeli (Linaro) Closes: https://bugzilla.kernel.org/show_bug.cgi?id=221586 Link: https://patch.msgid.link/e01c8e60e1d9ed68c347f1a3741f89149109d8b7.1780496388.git.michal.simek@amd.com Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ---- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 2 -- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 -- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 1 - arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 -- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 1 - 10 files changed, 16 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 923a70d750bf..44834bf1c19c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -374,7 +374,6 @@ conf { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 563e750b0e08..49732de5fa4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -365,7 +365,6 @@ conf { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 6aff22d43361..f57987dad50f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -270,7 +270,6 @@ mux-cd { conf-cd { groups = "sdio0_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -283,7 +282,6 @@ mux-wp { conf-wp { groups = "sdio0_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -310,7 +308,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -323,7 +320,6 @@ mux-wp { conf-wp { groups = "sdio1_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index 53aa3dca1dca..737d445dc16b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -270,7 +270,6 @@ mux-cd { conf-cd { groups = "sdio0_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -283,7 +282,6 @@ mux-wp { conf-wp { groups = "sdio0_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 4ec8a400494e..41f312a82bb4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -320,7 +320,6 @@ mux-cd { conf-cd { groups = "sdio0_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index e172a30e7b21..a5bc521ab679 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -896,7 +896,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -909,7 +908,6 @@ mux-wp { conf-wp { groups = "sdio1_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index fe8f151ed706..32509083e54f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -359,7 +359,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 3ee8ab224722..96699be8430f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -371,7 +371,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 7f6c87d4d77e..52441e5c8739 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -895,7 +895,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; @@ -908,7 +907,6 @@ mux-wp { conf-wp { groups = "sdio1_wp_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 428b5558fbba..b34e4c93d249 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -750,7 +750,6 @@ mux-cd { conf-cd { groups = "sdio1_cd_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = ; power-source = ; From 568248504d837ce271f44bbbb3810385092b33a2 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 3 Jun 2026 16:19:53 +0200 Subject: [PATCH 020/864] arm: dts: xilinx: drop bias-high-impedance on SDIO CD/WP pins Zynq-7000 boards used the same invalid combination of bias-high-impedance and bias-pull-up on SDIO card-detect and write-protect pin groups. Keep only bias-pull-up, as in the arm64 ZynqMP fix. Link: https://patch.msgid.link/f8f0aa0d0a732127b5cb725871d06a7739f0a499.1780496388.git.michal.simek@amd.com Signed-off-by: Michal Simek --- arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts | 1 - arch/arm/boot/dts/xilinx/zynq-zc702.dts | 2 -- arch/arm/boot/dts/xilinx/zynq-zc706.dts | 2 -- 3 files changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts index 14f644156a6f..19b564019502 100644 --- a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts +++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts @@ -99,7 +99,6 @@ conf-cd { groups = "gpio0_34_grp"; io-standard = <3>; slew-rate = <0>; - bias-high-impedance; bias-pull-up; }; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc702.dts b/arch/arm/boot/dts/xilinx/zynq-zc702.dts index 6955637c5b1a..36e919aea84c 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc702.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc702.dts @@ -324,7 +324,6 @@ mux-cd { conf-cd { groups = "gpio0_0_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; @@ -337,7 +336,6 @@ mux-wp { conf-wp { groups = "gpio0_15_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; diff --git a/arch/arm/boot/dts/xilinx/zynq-zc706.dts b/arch/arm/boot/dts/xilinx/zynq-zc706.dts index 3b803c698473..1ce35eaa607b 100644 --- a/arch/arm/boot/dts/xilinx/zynq-zc706.dts +++ b/arch/arm/boot/dts/xilinx/zynq-zc706.dts @@ -237,7 +237,6 @@ mux-cd { conf-cd { groups = "gpio0_14_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; @@ -250,7 +249,6 @@ mux-wp { conf-wp { groups = "gpio0_15_grp"; - bias-high-impedance; bias-pull-up; slew-rate = <0>; power-source = <1>; From 2c19e75101ee17059bf10101f4cf0157f61776a2 Mon Sep 17 00:00:00 2001 From: Sanghoon Bae Date: Wed, 10 Jun 2026 14:03:26 +0900 Subject: [PATCH 021/864] arm64: dts: exynosautov920: Add hsi0 syscon node for PCIe PHY Add the syscon-hsi0 node to control PCIe PHY power, PLL settings, and device direction (RC/EP mode) on ExynosAutov920. Signed-off-by: Sanghoon Bae Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260610050326.2903402-3-sh86.bae@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index f1f5efcdb91e..e2f962dc1b3d 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1382,6 +1382,12 @@ cmu_hsi0: clock-controller@16000000 { "noc"; }; + syscon_hsi0: syscon@16030000 { + compatible = "samsung,exynosautov920-hsi0-sysreg", + "syscon"; + reg = <0x16030000 0x1000>; + }; + pinctrl_hsi0: pinctrl@16040000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x16040000 0x10000>; From b78d749d4ba7c217d2be644619a79a72e1fd5dfd Mon Sep 17 00:00:00 2001 From: Lukas Timmermann Date: Sun, 14 Jun 2026 22:16:35 +0200 Subject: [PATCH 022/864] ARM: dts: exynos: Add bluetooth support to manta Enable the bcm4330-bt device for manta boards on serial0. Also adds the necessary pin definitions and interrupt handling for wakeup. Co-developed-by: Alexandre Marquet Signed-off-by: Alexandre Marquet Signed-off-by: Lukas Timmermann Link: https://patch.msgid.link/20260614-manta-bluetooth-v2-1-52de06cabf9d@timmermann.space [krzk: Fixed invalid Co-developed-by for Lukas Timmermann] Signed-off-by: Krzysztof Kozlowski --- .../arm/boot/dts/samsung/exynos5250-manta.dts | 41 ++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/samsung/exynos5250-manta.dts b/arch/arm/boot/dts/samsung/exynos5250-manta.dts index 24a27b342227..76d3657eb22f 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-manta.dts +++ b/arch/arm/boot/dts/samsung/exynos5250-manta.dts @@ -461,6 +461,13 @@ acc_int: acc-int-pins { samsung,pin-pud = ; }; + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-2"; samsung,pin-function = ; @@ -488,6 +495,20 @@ bh1721fvc_reset: bh1721fvc-reset-pins { samsung,pin-pud = ; }; + bt_reg_on: bt-reg-on-pins { + samsung,pins = "gph0-0"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + bt_wake: bt-wake-pins { + samsung,pins = "gph1-3"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + msense_reset: msense-reset-pins { samsung,pins = "gpg2-0"; samsung,pin-function = ; @@ -536,7 +557,25 @@ &sd1_cmd { /* Bluetooth */ &serial_0 { - status = "disabled"; + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + + pinctrl-0 = <&bt_reg_on &bt_wake &bt_host_wakeup>; + pinctrl-names = "default"; + + shutdown-gpios = <&gph0 0 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gph1 3 GPIO_ACTIVE_HIGH>; + + interrupt-parent = <&gpx2>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; + + clocks = <&max77686 MAX77686_CLK_PMIC>; + clock-names = "lpo"; + }; }; /* GPS */ From 27dd768f89bef4ce0d584e8d5ae687124e4f1291 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 9 Jun 2026 06:16:41 -0700 Subject: [PATCH 023/864] arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0 Extend the gmac0 interrupt list to support 8 TX and 8 RX per-channel interrupts in addition to the combined macirq, enabling per-channel interrupt handling for improved DMA performance. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 36 +++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index b06c6d5d60ee..c936f8db1bd0 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -557,8 +557,40 @@ gmac0: ethernet@10810000 { compatible = "altr,socfpga-stmmac-agilex5", "snps,dwxgmac-2.10"; reg = <0x10810000 0x3500>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "tx-queue-0", + "tx-queue-1", + "tx-queue-2", + "tx-queue-3", + "tx-queue-4", + "tx-queue-5", + "tx-queue-6", + "tx-queue-7", + "rx-queue-0", + "rx-queue-1", + "rx-queue-2", + "rx-queue-3", + "rx-queue-4", + "rx-queue-5", + "rx-queue-6", + "rx-queue-7"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr AGILEX5_EMAC0_CLK>, From ea3aec9519e22c8c2bad7a4b7a3dd3880c5a44b0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 Jun 2026 16:55:34 +0200 Subject: [PATCH 024/864] arm64: dts: intel: keembay: Always use decimal interrupts Replace the sole hexadecimal interrupt number by a decimal number, for consistency with all other interrupt numbers. Signed-off-by: Geert Uytterhoeven Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi index ae00e9e54e82..b6323ebe7a5f 100644 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -71,7 +71,7 @@ timer { pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; soc { From 10cf797f3f8a50d5ac7a823117e5097b87c7e51d Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 23 Jun 2026 23:22:02 -0700 Subject: [PATCH 025/864] arm64: dts: socfpga: agilex5: Enable the SMMU The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different memory-mapped base address for its peripherals, which requires the SMMU to be active so that the Secure Device Manager (SDM) can correctly access those regions through address translation. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index c936f8db1bd0..153bb22002b5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -385,7 +385,6 @@ smmu: iommu@16000000 { interrupt-names = "eventq", "gerror", "priq"; dma-coherent; #iommu-cells = <1>; - status = "disabled"; }; spi0: spi@10da4000 { From 501a98280c6fa8959b5d7c032e6744c6b9f049ab Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 23 Jun 2026 23:22:03 -0700 Subject: [PATCH 026/864] arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes The SMMU is enabled and transactions going through it are cache coherent. Add the dma-coherent property to the XGMAC nodes to prevent redundant cache flush/invalidate operations and potential stale data issues. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 153bb22002b5..2096decb5655 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -608,6 +608,7 @@ gmac0: ethernet@10810000 { altr,sysmgr-syscon = <&sysmgr 0x44 0>; snps,clk-csr = <0>; iommus = <&smmu 1>; + dma-coherent; status = "disabled"; stmmac_axi_emac0_setup: stmmac-axi-config { @@ -721,6 +722,7 @@ gmac1: ethernet@10820000 { altr,sysmgr-syscon = <&sysmgr 0x48 0>; snps,clk-csr = <0>; iommus = <&smmu 2>; + dma-coherent; status = "disabled"; stmmac_axi_emac1_setup: stmmac-axi-config { @@ -834,6 +836,7 @@ gmac2: ethernet@10830000 { altr,sysmgr-syscon = <&sysmgr 0x4c 0>; snps,clk-csr = <0>; iommus = <&smmu 3>; + dma-coherent; status = "disabled"; stmmac_axi_emac2_setup: stmmac-axi-config { From d6d3f13d05994cd915f27a23942d6019294de609 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 24 Jun 2026 23:53:28 -0700 Subject: [PATCH 027/864] dt-bindings: arm: altera: Add Agilex72 SoCFPGA compatible strings Add the SoC and board compatible strings for the Intel SoCFPGA Agilex72 platform. Signed-off-by: Nazim Amirul Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 0b418d9d60db..3030cf46fe74 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -116,6 +116,12 @@ properties: - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 + - description: Agilex72 boards + items: + - enum: + - intel,socfpga-agilex72-socdk + - const: intel,socfpga-agilex72 + - description: Agilex7m boards items: - enum: From 5eb1916efe763147dfee408e282b77a607aa0c42 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 24 Jun 2026 23:53:29 -0700 Subject: [PATCH 028/864] arm64: dts: socfpga: agilex72: Add initial device tree Add initial device tree support for the Intel SoCFPGA Agilex72 platform. This introduces the SoC DTSI and the SoCDK board DTS as the first upstream submission for this platform. The Agilex72 SoC features a heterogeneous CPU cluster with Cortex-A520 and Cortex-A720 cores, and includes an SMMU v3 for memory management. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex72.dtsi | 156 ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex72_socdk.dts | 27 +++ 3 files changed, 184 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 088a03b89c99..270c70fdf084 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex72_socdk.dtb \ socfpga_agilex7m_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi new file mode 100644 index 000000000000..c29c2afcaab7 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, Altera Corporation + */ +/dts-v1/; +#include +#include + +/ { + compatible = "intel,socfpga-agilex72"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf_reserved: atf@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x100000>; + alignment = <0x1000>; + no-map; + }; + + service_reserved: svcbuffer@80100000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80100000 0x0 0xf00000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a520"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a520"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a720"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a720"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x300>; + }; + }; + + clocks { + uart_clk: uart-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + intc: interrupt-controller@7000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x7000000 0x0 0x10000>, + <0x0 0x7080000 0x0 0x100000>; + ranges; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + its: msi-controller@7040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x7040000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + interrupt-parent = <&intc>; + + smmu: iommu@c100000 { + compatible = "arm,smmu-v3"; + reg = <0x0c100000 0x30000>; + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "priq"; + dma-coherent; + #iommu-cells = <1>; + }; + + ocram: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0x80000>; + ranges = <0 0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + uart0: serial@9038000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9038000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@9039000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9039000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&uart_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts new file mode 100644 index 000000000000..998f19f492b3 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex72.dtsi" + +/ { + model = "Altera SoCFPGA Agilex72 SoCDK"; + compatible = "intel,socfpga-agilex72-socdk", "intel,socfpga-agilex72"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From d911a33fa8e9fd4c691bc8429180fe1885bc3f2f Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 30 Apr 2026 10:53:33 +0800 Subject: [PATCH 029/864] arm64: dts: imx93: update the tmu compatible string The i.MX93 TMU node compatible need to be updated to apply the SoC specific configuration and TMU errata workaround. Reviewed-by: Frank Li Signed-off-by: Jacky Bai Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index b9abe143cb56..06443d52a429 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -80,7 +80,7 @@ mu1: mailbox@44230000 { }; tmu: tmu@44482000 { - compatible = "fsl,qoriq-tmu"; + compatible = "fsl,imx93-tmu"; reg = <0x44482000 0x1000>; interrupts = ; clocks = <&clk IMX93_CLK_TMC_GATE>; From ec5c75673cb9d4c9a2a55a70d54a6ccb254f4ba4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 4 May 2026 19:54:40 -0400 Subject: [PATCH 030/864] arm64: dts: imx8mp-evk: add board-level mux for CAN2 and MICFIL The board integrates an on-board mux to route shared signals to either CAN2 or PDM (MICFIL). The mux is controlled by a GPIO. Add a pinctrl-based multiplexer node to describe this routing and ensure proper probe ordering of the dependent devices. Previously, MICFIL operation implicitly depended on the default level of PCA6416 GPIO3. After adding the pinctrl-multiplexer, make the dependency explicit. Reviewed-by: Ahmad Fatoum Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 23 ++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index a7f3acdc36d1..2e092b0b52d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -50,6 +50,25 @@ status { }; }; + can_mux: mux-controller-0 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pca6416 3 GPIO_ACTIVE_HIGH>; + }; + + can_mux_pinctrl: pinctrl-gpiomux { + compatible = "pinctrl-multiplexer"; + + can_fun: can-grp { + mux-states = <&can_mux 1>; + }; + + pdm_fun: pdm-grp { + mux-states = <&can_mux 0>; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, @@ -453,7 +472,7 @@ &flexcan1 { &flexcan2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-0 = <&pinctrl_flexcan2>, <&can_fun>; phys = <&flexcan_phy 1>; status = "disabled";/* can2 pin conflict with pdm */ }; @@ -720,7 +739,7 @@ &lcdif3 { &micfil { #sound-dai-cells = <0>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pdm>; + pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>; assigned-clocks = <&clk IMX8MP_CLK_PDM>; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <196608000>; From 368eb597c6ef0263931a3922648e8c7b83cd0536 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 4 May 2026 19:54:41 -0400 Subject: [PATCH 031/864] arm64: dts: imx8mp-evk: add flexcan2 overlay file Add flexcan2 overlay file, which enable flexcan2 node and disable micfil node. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ .../boot/dts/freescale/imx8mp-evk-flexcan2.dtso | 15 +++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 8ddaab127ab9..38b8f02bec82 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -361,6 +361,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb \ dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb + +imx8mp-evk-flexcan2-dtbs += imx8mp-evk.dtb imx8mp-evk-flexcan2.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-flexcan2.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb DTC_FLAGS_imx8mp-hummingboard-iiot := -@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-iiot.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso new file mode 100644 index 000000000000..f7d2674c45f7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +&flexcan2 { + status = "okay"; /* can2 pin conflict with pdm */ +}; + +&micfil { + status = "disabled"; +}; From c3600c97eb9c1a20a933a7fba08272955f7a7ccc Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Tue, 23 Jun 2026 22:48:14 +0200 Subject: [PATCH 032/864] dt-bindings: vendor-prefixes: Add Shenzhen Baijie Technology Co., Ltd. Shenzhen Baijie Technology Co., Ltd. focuses on R&D and production of embedded products as well as customization of embedded solutions. Link: https://szbaijie.com/ Acked-by: Conor Dooley Reviewed-by: Paul Kocialkowski Signed-off-by: Alexander Sverdlin Link: https://patch.msgid.link/20260623204824.691832-3-alexander.sverdlin@gmail.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..075fe48b4018 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -229,6 +229,8 @@ patternProperties: description: Azoteq (Pty) Ltd "^azw,.*": description: Shenzhen AZW Technology Co., Ltd. + "^baijie,.*": + description: Shenzhen Baijie Technology Co., Ltd. "^baikal,.*": description: BAIKAL ELECTRONICS, JSC "^bananapi,.*": From 1d81cb06c30746448deb73b6ce9ceccc9fb6ca37 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Tue, 23 Jun 2026 22:48:15 +0200 Subject: [PATCH 033/864] dt-bindings: arm: sunxi: Add Baijie HelperBoard A133 compatible Baijie HelperBoard A133 is a development board around their A133 Core board. Introduce a compatible for both the Core and the development boards. Acked-by: Conor Dooley Signed-off-by: Alexander Sverdlin Link: https://patch.msgid.link/20260623204824.691832-4-alexander.sverdlin@gmail.com Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index e6443c266fa1..82dd58b95f8a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -96,6 +96,12 @@ properties: - const: allwinner,ba10-tvbox - const: allwinner,sun4i-a10 + - description: Baijie A133 HelperBoard + items: + - const: baijie,helperboard-a133 + - const: baijie,helperboard-a133-core + - const: allwinner,sun50i-a100 + - description: BananaPi items: - const: lemaker,bananapi From 5e5e8a2e5a5e31fbe8858f08ef7ac44dff9ee351 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Tue, 23 Jun 2026 22:48:16 +0200 Subject: [PATCH 034/864] dt-bindings: input: sun4i-lradc-keys: Add A100/A133 compatible The Allwinner A100/A133 SoCs have an LRADC which is compatible with the versions in existing SoCs. Add a compatible string for A100, with the R329 fallback. Signed-off-by: Alexander Sverdlin Acked-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://patch.msgid.link/20260623204824.691832-5-alexander.sverdlin@gmail.com Signed-off-by: Chen-Yu Tsai --- .../bindings/input/allwinner,sun4i-a10-lradc-keys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index 6bdb8040be65..524c8b51f53f 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -23,6 +23,7 @@ properties: - const: allwinner,sun50i-r329-lradc - items: - enum: + - allwinner,sun50i-a100-lradc - allwinner,sun50i-h616-lradc - allwinner,sun20i-d1-lradc - const: allwinner,sun50i-r329-lradc From 8fa3a2bf77f0adb5440f25c3e2951543691e1536 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Tue, 23 Jun 2026 22:48:17 +0200 Subject: [PATCH 035/864] arm64: dts: allwinner: a100: Add LRADC node A100/A133 SoCs feature a Low Rate ADC (LRADC) for Key application. Specs: - Power supply voltage: 1.8 V - Reference voltage: 1.35 V - Interrupt support - Support Hold Key and General Key - Support normal, continue and single work mode - 6-bits resolution, sample rate up to 2 kHz - Voltage input range between 0 and 1.35 V Reviewed-by: Jernej Skrabec Signed-off-by: Alexander Sverdlin Link: https://patch.msgid.link/20260623204824.691832-6-alexander.sverdlin@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index b3fb1e0ee796..ba6020989ce9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -466,6 +466,16 @@ ths: thermal-sensor@5070400 { #thermal-sensor-cells = <1>; }; + lradc: lradc@5070800 { + compatible = "allwinner,sun50i-a100-lradc", + "allwinner,sun50i-r329-lradc"; + reg = <0x05070800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_LRADC>; + resets = <&ccu RST_BUS_LRADC>; + status = "disabled"; + }; + usb_otg: usb@5100000 { compatible = "allwinner,sun50i-a100-musb", "allwinner,sun8i-a33-musb"; From 7204944dcb8f1131b6303a5e9ca11128eb20ac21 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Tue, 23 Jun 2026 22:48:18 +0200 Subject: [PATCH 036/864] arm64: dts: allwinner: A133: add support for Baijie Helper A133 board Baijie Helper A133 board is a development board around Baijie A133 Core SBC. Features: - 1/2/4GiB LPDDR4 DRAM - 8/16/32GiB eMMC - AXP707 PMIC - USB-C OTG port in peripheral mode (via onboard hub) - 2 USB 2.0 ports - MicroSD slot and on-board eMMC module - Gigabit Ethernet - Bluetooth - WiFi Add initial support for both the Helper and Core boards, including UART, PMU, eMMC, USB, Ethernet, LRADC-connected buttons. UART1 can only be used for Bluetooth module, but BT-WiFi combo Allwinner AW869A chip has no mainline driver currently. Acked-by: Jernej Skrabec Signed-off-by: Alexander Sverdlin Link: https://patch.msgid.link/20260623204824.691832-7-alexander.sverdlin@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-a133-helperboard-core.dtsi | 197 ++++++++++++++++++ .../dts/allwinner/sun50i-a133-helperboard.dts | 148 +++++++++++++ 3 files changed, 346 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard-core.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 53e6b701e7d3..aa21f58a4be1 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h64-remix-mini-pc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a133-helperboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a133-liontron-h-a133l.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard-core.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard-core.dtsi new file mode 100644 index 000000000000..545972d2324a --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard-core.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Arm Ltd. + * Copyright (c) 2026 Alexander Sverdlin + */ + +/dts-v1/; + +#include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" + +/{ + model = "Baijie A133 HelperBoard Core"; + compatible = "baijie,helperboard-a133-core", + "allwinner,sun50i-a100"; + + aliases { + serial1 = &uart1; /* BT module */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&lradc { + vref-supply = <®_aldo1>; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + max-frequency = <100000000>; + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_eldo1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_dldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dcdc1>; + /* + * PL0/PL1 are the I2C connection to PMIC, but it would create a + * circular dependency: + * vcc-pl-supply = <®_aldo3>; + */ +}; + +&r_i2c0 { + status = "okay"; + + axp803: pmic@34 { + compatible = "x-powers,axp803"; + reg = <0x34>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */ + aldoin-supply = <®_vdd5v>; + dldoin-supply = <®_vdd5v>; + eldoin-supply = <®_vdd5v>; + fldoin-supply = <®_dcdc5>; + vin1-supply = <®_vdd5v>; + vin2-supply = <®_vdd5v>; + vin3-supply = <®_vdd5v>; + vin4-supply = <®_vdd5v>; + vin5-supply = <®_vdd5v>; + vin6-supply = <®_vdd5v>; + drivevbus-supply = <®_vdd5v>; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + /* PLL + LRADC analog reference */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll"; +}; + +®_aldo2 { + /* LPDDR */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd18-lpddr"; +}; + +®_aldo3 { + /* + * Port L, but linking it to &pio node would create a circular + * dependency because of PL0/PL1 I2C connection to PMIC + */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pl"; +}; + +®_dcdc1 { + /* Besides Port D it also powers analog part of USB IP and SoC I/O */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-cpu"; +}; + +/* DCDC3 is polyphased with DCDC2 */ + +®_dcdc4 { + /* Digital part of USB IP, "System" SoC power rail */ + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc-dram"; +}; + +/* DCDC6 unused */ +®_dcdc6 { + status = "disabled"; +}; + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg"; +}; + +®_dldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pe"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-csi"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pc"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "dvdd-csi"; +}; + +/* ELDO3 unused */ + +®_fldo1 { + /* CPUS power rail */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; +}; + +/* reg_drivevbus unused */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard.dts new file mode 100644 index 000000000000..694c0cacf906 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-helperboard.dts @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Arm Ltd. + * Copyright (c) 2026 Alexander Sverdlin + */ + +/dts-v1/; + +#include "sun50i-a133-helperboard-core.dtsi" + +#include +#include +#include + +/{ + model = "Baijie HelperBoard A133"; + compatible = "baijie,helperboard-a133", + "baijie,helperboard-a133-core", + "allwinner,sun50i-a100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ + }; + }; + + reg_vdd5v: vdd5v { + /* board wide 5V supply from a 12V->5V regulator */ + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii0_pins>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + allwinner,rx-delay-ps = <200>; + allwinner,tx-delay-ps = <200>; + status = "okay"; +}; + +&lradc { + wakeup-source; + status = "okay"; + + button-115 { + label = "K1"; + linux,code = ; + channel = <0>; + voltage = <114607>; + }; + + button-235 { + label = "K2"; + linux,code = ; + channel = <0>; + voltage = <234783>; + }; + + button-360 { + label = "K3"; + linux,code = ; + channel = <0>; + voltage = <360000>; + }; + + button-476 { + label = "K4"; + linux,code = ; + channel = <0>; + voltage = <476471>; + }; + + button-592 { + label = "K5"; + linux,code = ; + channel = <0>; + voltage = <591946>; + }; +}; + +&mdio0 { + reset-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ + reset-delay-us = <10000>; + reset-post-delay-us = <150000>; + + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + disable-wp; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&rgmii0_pins { + drive-strength = <30>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + /* + * Connected to a downstream port of an onboard hub, therefore only + * "peripheral" mode will work here. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vdd5v>; + status = "okay"; +}; From ffccbd6804e885f0fc23f0005f6bee7789a7a887 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 4 Jun 2026 10:38:20 +0800 Subject: [PATCH 037/864] arm64: dts: imx94: Correct PCIe outbound address space configuration Fix the PCIe outbound memory ranges for both pcie0 controllers on i.MX94. The memory window size was incorrectly set to 256MB during initial bring-up, but the hardware supports up to 4GB of outbound address space per controller. Additionally, the ECAM region cannot be mapped as I/O space. Use a memory-mapped region for I/O space instead, and relocate the 1MB I/O region to immediately follow the memory region at offset 0xf0000000 within each window. Update the outbound address space layout per controller as follows: - 3.5GB 64-bit prefetchable memory - 256MB 32-bit non-prefetchable memory - 1MB I/O Fixes: 8cd439f17758 ("arm64: dts: imx94: Add pcie0 and pcie0-ep supports") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index a6cb5a6e848b..1f9035e6cf15 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1374,8 +1374,9 @@ pcie0: pcie@4c300000 { <0 0x4c360000 0 0x10000>, <0 0x4c340000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; - ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, - <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>; + ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>, + <0x82000000 0x0 0xe0000000 0x9 0xe0000000 0x0 0x10000000>, + <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; From 6de3a7d7a4f653be4901d07425719c4e55805167 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 4 Jun 2026 10:38:21 +0800 Subject: [PATCH 038/864] arm64: dts: imx943: Correct PCIe outbound address space configuration Fix the PCIe outbound memory ranges for both pcie1 controllers on i.MX943. The memory window size was incorrectly set to 256MB during initial bring-up, but the hardware supports up to 4GB of outbound address space per controller. Additionally, the ECAM region cannot be mapped as I/O space. Use a memory-mapped region for I/O space instead, and relocate the 1MB I/O region to immediately follow the memory region at offset 0xf0000000 within each window. Update the outbound address space layout per controller as follows: - 3.5GB 64-bit prefetchable memory - 256MB 32-bit non-prefetchable memory - 1MB I/O Fixes: fa6067fd8ea7 ("arm64: dts: imx943: Add pcie1 and pcie1-ep supports") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index ed030d4bc7bd..cf5b3dbb47ff 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -218,8 +218,9 @@ pcie1: pcie@4c380000 { <0 0x4c3e0000 0 0x10000>, <0 0x4c3c0000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; - ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, - <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>; + ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>, + <0x82000000 0x0 0xe0000000 0xa 0xe0000000 0x0 0x10000000>, + <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; From da07acfd60891b499573b2720b1802a23032472d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 25 Jun 2026 17:17:47 -0500 Subject: [PATCH 039/864] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants. Also make 'interrupts' and 'interrupt-names' as required properties. Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- v2: Set the top level interrupts to include the widest contraints(1-17) Just have 1 list of all interrupt-names Update commit message to include 'interrupts' and 'interrupt-names' as required properties Change minItems 1 to maxItems 1 for non agilex5 variants Add same constraint for interrupt-names --- .../bindings/net/altr,socfpga-stmmac.yaml | 46 ++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index fc445ad5a1f1..63084f762373 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -63,11 +63,29 @@ properties: - const: ptp_ref interrupts: - maxItems: 1 + minItems: 1 + maxItems: 17 interrupt-names: + minItems: 1 items: - const: macirq + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 iommus: minItems: 1 @@ -149,10 +167,36 @@ required: - clocks - clock-names - altr,sysmgr-syscon + - interrupts + - interrupt-names allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: altr,socfpga-stmmac-agilex5 + then: + properties: + interrupts: + minItems: 17 + + interrupt-names: + minItems: 17 + + dma-coherent: true + else: + properties: + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + dma-coherent: false + unevaluatedProperties: false examples: From 0764f42a8ba90cc390070dd48dbc0afde5146f86 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 25 Jun 2026 17:25:56 -0500 Subject: [PATCH 040/864] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs. Signed-off-by: Dinh Nguyen --- v2: no changes --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 72 +++++++++++++++++-- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 2096decb5655..f54767d1526e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -702,8 +702,40 @@ gmac1: ethernet@10820000 { compatible = "altr,socfpga-stmmac-agilex5", "snps,dwxgmac-2.10"; reg = <0x10820000 0x3500>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "tx-queue-0", + "tx-queue-1", + "tx-queue-2", + "tx-queue-3", + "tx-queue-4", + "tx-queue-5", + "tx-queue-6", + "tx-queue-7", + "rx-queue-0", + "rx-queue-1", + "rx-queue-2", + "rx-queue-3", + "rx-queue-4", + "rx-queue-5", + "rx-queue-6", + "rx-queue-7"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr AGILEX5_EMAC1_CLK>, @@ -816,8 +848,40 @@ gmac2: ethernet@10830000 { compatible = "altr,socfpga-stmmac-agilex5", "snps,dwxgmac-2.10"; reg = <0x10830000 0x3500>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "tx-queue-0", + "tx-queue-1", + "tx-queue-2", + "tx-queue-3", + "tx-queue-4", + "tx-queue-5", + "tx-queue-6", + "tx-queue-7", + "rx-queue-0", + "rx-queue-1", + "rx-queue-2", + "rx-queue-3", + "rx-queue-4", + "rx-queue-5", + "rx-queue-6", + "rx-queue-7"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr AGILEX5_EMAC2_CLK>, From c10743c09d5d6183117a6fb96b50a8016f437cdd Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:02 +0200 Subject: [PATCH 041/864] arm64: dts: imx8mp-var-som-symphony: add input keys Add the Back, Home and Menu keys connected through the GPIO expander on the Symphony carrier board. Also enable the SNVS power key. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 291f65e36865..25f707012f62 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -13,6 +13,31 @@ chosen { stdout-path = &uart2; }; + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-menu { + label = "Menu"; + linux,code = ; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + gpio-leds { compatible = "gpio-leds"; @@ -72,6 +97,10 @@ usb3-sata-sel-hog { }; }; +&snvs_pwrkey { + status = "okay"; +}; + /* Console */ &uart2 { pinctrl-names = "default"; From 9497ab2868eec57352b72ada3efec10e0428bb3e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:03 +0200 Subject: [PATCH 042/864] arm64: dts: imx8mp-var-som-symphony: enable USB support Enable the USB controllers on the Symphony carrier board. Add the PTN5150 Type-C controller for USB role switching, enable the USB3 PHYs and controllers, configure the I2C bus used by the Type-C controller, and set the first USB port in OTG mode and the second port in host mode. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 80 ++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 25f707012f62..cb27853ba281 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -72,8 +72,11 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; /* GPIO expander */ @@ -95,6 +98,22 @@ usb3-sata-sel-hog { line-name = "usb3_sata_sel"; }; }; + + /* USB Type-C Controller */ + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; }; &snvs_pwrkey { @@ -108,6 +127,52 @@ &uart2 { status = "okay"; }; +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + srp-disable; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-comp-dis-tune-percent = <115>; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <122>; + status = "okay"; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; + status = "okay"; +}; + /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -129,12 +194,25 @@ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 >; }; + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 From 342414b800bfea45cbc118d51dc66a066411c033 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:04 +0200 Subject: [PATCH 043/864] arm64: dts: imx8mp-var-som-symphony: add TPM support Add the ST33KTPM2XI2C TPM device on the Symphony carrier board. Enable the I2C4 bus, add the PCAL6408 GPIO expander used by the TPM and describe the TPM reset line. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index cb27853ba281..7cf58198ef14 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -116,6 +116,31 @@ typec_dr_sw: endpoint { }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio", "sleep"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + pinctrl-2 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -201,6 +226,20 @@ MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c2 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 From 5babe7594543573b57bff15bdda7f3343789f02f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:05 +0200 Subject: [PATCH 044/864] arm64: dts: imx8mp-var-som-symphony: add external RTC Add the DS1337 RTC on the Symphony carrier board and disable the internal SNVS RTC. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 7cf58198ef14..cb3348aafa07 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -139,12 +139,21 @@ st33ktpm2xi2c: tpm@2e { label = "tpm"; reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; }; &snvs_pwrkey { status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + /* Console */ &uart2 { pinctrl-names = "default"; From 6b680f24454cb5ce8a87df430b622bb5a602c91e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:06 +0200 Subject: [PATCH 045/864] arm64: dts: imx8mp-var-som-symphony: enable header UARTs Enable UART1 and UART4 on the Symphony carrier board and add the corresponding pinctrl configurations. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index cb3348aafa07..fdac4ceb4c19 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -154,6 +154,13 @@ &snvs_rtc { status = "disabled"; }; +/* Header UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + /* Console */ &uart2 { pinctrl-names = "default"; @@ -161,6 +168,13 @@ &uart2 { status = "okay"; }; +/* Header UART */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usb3_0 { status = "okay"; }; @@ -261,6 +275,13 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 @@ -268,6 +289,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40 + >; + }; + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 From 0ff57bce947f361a19e0c29945ed72cedef1f913 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 10 Jun 2026 17:26:21 +0800 Subject: [PATCH 046/864] dt-bindings: soc: imx: fsl,imx93-media-blk-ctrl: Allow LVDS Display Bridge child node i.MX93 SoC mediamix blk-ctrl contains one LDB_CTRL register and one LVDS register which control video output through a LVDS interface. Allow the LVDS Display Bridge(LDB) child node and add the child node to example. i.MX93 LDB child node(bridge@20) is an addressable node, while i.MX93 Parallel Display Format Configuration(PDFC) child node(dpi-bridge) is a non-addressable node. Mixing the addressable and non-addressable child nodes is allowed according to discussion [1]. Link: https://lore.kernel.org/all/n6akxiayi3g6gxcqhreb4iaohmeokoalnqup6h5r2fwdt4zijt@u2wyps55ayqm/ [1] Signed-off-by: Liu Ying Reviewed-by: Rob Herring (Arm) Signed-off-by: Frank Li --- .../soc/imx/fsl,imx93-media-blk-ctrl.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index d828c2e82965..124f5c206ee3 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -26,6 +26,12 @@ properties: reg: maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#power-domain-cells': const: 1 @@ -92,6 +98,11 @@ properties: - compatible - ports + bridge@20: + type: object + $ref: /schemas/display/bridge/fsl,ldb.yaml# + unevaluatedProperties: false + allOf: - if: properties: @@ -112,6 +123,7 @@ allOf: - const: lcdif - const: isi - const: csi + bridge@20: false - if: properties: compatible: @@ -163,6 +175,8 @@ examples: <&clk IMX93_CLK_MIPI_DSI_GATE>; clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; + #address-cells = <1>; + #size-cells = <1>; #power-domain-cells = <1>; dpi-bridge { @@ -190,4 +204,29 @@ examples: }; }; }; + + bridge@20 { + compatible = "fsl,imx93-ldb"; + reg = <0x20 0x4>, <0x24 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; }; From 9c4d966c046c117ec690a24ef50a83605d004c7d Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 10 Jun 2026 17:26:22 +0800 Subject: [PATCH 047/864] arm64: dts: imx93: Add LVDS Display Bridge support Add LVDS Display Bridge(LDB) child node to mediamix blk-ctrl node so that video could be output through a LVDS interface. Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 06443d52a429..e926b6360a9d 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -178,6 +178,7 @@ &lcdif { port { lcdif_to_ldb: endpoint@1 { reg = <1>; + remote-endpoint = <&ldb_from_lcdif>; }; lcdif_to_dsi: endpoint@2 { @@ -186,6 +187,42 @@ lcdif_to_dsi: endpoint@2 { }; }; +&media_blk_ctrl { + #address-cells = <1>; + #size-cells = <1>; + + lvds_bridge: bridge@20 { + compatible = "fsl,imx93-ldb"; + reg = <0x20 0x4>, <0x24 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>; + assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + }; + }; + }; + }; +}; + &src { mlmix: power-domain@44461800 { compatible = "fsl,imx93-src-slice"; From 69e50e84bbcefdb534e1bd2a8e3f472be98aae2c Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 10 Jun 2026 17:26:23 +0800 Subject: [PATCH 048/864] arm64: dts: imx93-11x11-evk: Add DY1212W-4856 LVDS panel DY1212W-4856 [1] is a 12.1" (WXGA) TFT LCD panel with LVDS interface. The panel's 40-pin connector allows it to be directly connected to i.MX93 11x11 EVK board. Link: https://www.nxp.com/design/design-center/development-boards-and-designs/dy1212w-4856-tft-lcd-panel-with-lvds-interface:DY1212W-4856 [1] Signed-off-by: Liu Ying Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../imx93-11x11-evk-dy1212w-4856.dtso | 81 +++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 38b8f02bec82..447c5f7721d4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -592,6 +592,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-tianma-tm050rdh03.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb + +imx93-11x11-evk-dy1212w-4856-dtbs += imx93-11x11-evk.dtb imx93-11x11-evk-dy1212w-4856.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk-dy1212w-4856.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso new file mode 100644 index 000000000000..35f7c5699e3a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + panel-lvds { + compatible = "boe,ev121wxm-n10-1850"; + backlight = <&backlight_lvds>; + power-supply = <&buck4>; + + panel-timing { + /* + * Set clock frequency to 71142858Hz to accommodate + * IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate + * table. + */ + clock-frequency = <71142858>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vfront-porch = <3>; + vback-porch = <14>; + vsync-len = <6>; + }; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight_lvds { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +&media_blk_ctrl { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_VIDEO_PLL>; + /* + * Set IMX93_CLK_MEDIA_DISP_PIX rate to 71142858Hz to accommodate + * IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate table. + */ + assigned-clock-rates = <400000000>, <133333333>, <71142858>, <498000000>; + status = "okay"; +}; From c33b03ac7ff7ca0267ae7a4284a2b9258483614d Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 11 Jun 2026 10:18:59 +0200 Subject: [PATCH 049/864] arm64: dts: imx8mp-frdm: Add missing HDMI DDC pinctrl Configure HDMI DDC SCL/SDA pins to support reading EDID. Signed-off-by: Philipp Zabel Fixes: 95d7d7d2ad27 ("arm64: dts: imx8mp-frdm: add sd, ethernet, wifi, usb and hdmi support") Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts index 5fb9714215bf..f43330d1ff8b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -562,6 +562,8 @@ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 pinctrl_hdmi: hdmigrp { fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 >; }; From 67a6b5ef7edf76236f1afe5d11c35bb94a4e41f9 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Tue, 16 Jun 2026 18:52:00 +0800 Subject: [PATCH 050/864] arm64: dts: imx8mq-evk: add uart3 and bluetooth node Add uart3 and bluetooth node. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 22 ++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index e7d87ea81b69..b9b03416aa39 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -498,6 +498,19 @@ &uart1 { status = "okay"; }; +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -657,6 +670,15 @@ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 From e4e7ced4ad38d4b9a3883766ccb2d1dae0df4f34 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 4 Jun 2026 00:53:59 +0200 Subject: [PATCH 051/864] arm64: dts: imx8mm-var-som-symphony: add wakeup sources Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 857325ef4461..090752014ee2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -55,18 +55,21 @@ key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; }; @@ -187,6 +190,7 @@ ft5x06_ts: touchscreen@38 { touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { From 47f8149d31535adafff43ff23084a97600686ddd Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Thu, 4 Jun 2026 00:54:00 +0200 Subject: [PATCH 052/864] arm64: dts: imx8mm-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 090752014ee2..fd0a1862ce90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -168,6 +168,14 @@ pca6408: gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e { From dd7858bbdfa84beddf7d08bb82eacc8010221493 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:07 +0200 Subject: [PATCH 053/864] arm64: dts: imx8mp-var-som-symphony: enable PCIe Add the PCIe reference clock and enable the PCIe controller and PHY on the Symphony carrier board. Describe the PERST# reset GPIO and configure the PHY to use an external reference clock input. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index fdac4ceb4c19..698f02fc39a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,12 @@ led-0 { }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -146,6 +152,18 @@ rtc@68 { }; }; +&pcie { + reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; From dfee5fefc3ecd29794c79b3f5284d759cfdc869e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:08 +0200 Subject: [PATCH 054/864] arm64: dts: imx8mp-var-som-symphony: add HDMI support Enable the HDMI display pipeline and HDMI audio support on the Symphony carrier board. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 698f02fc39a5..0beaee5f81c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,18 @@ led-0 { }; }; + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -74,6 +86,43 @@ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { states = <3300000 0x0 1800000 0x1>; vin-supply = <&ldo5>; }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; }; &i2c3 { @@ -152,6 +201,10 @@ rtc@68 { }; }; +&lcdif3 { + status = "okay"; +}; + &pcie { reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; status = "okay"; @@ -253,6 +306,15 @@ &usdhc2 { }; &iomuxc { + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 From 6651fb350bff74652edf8fdd2193ad33d69a968d Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:09 +0200 Subject: [PATCH 055/864] arm64: dts: imx8mp-var-som-symphony: add capacitive touchscreen Add the FT5206 capacitive touchscreen controller on the Symphony carrier board. Describe the interrupt pin and touchscreen geometry. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 0beaee5f81c9..f8a4b5b2e9fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -195,6 +195,21 @@ st33ktpm2xi2c: tpm@2e { reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; }; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; @@ -306,6 +321,12 @@ &usdhc2 { }; &iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x16 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 From c0cb98e3230fd5959bb8075e059fef60d0477698 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:10 +0200 Subject: [PATCH 056/864] arm64: dts: imx8mp-var-som-symphony: enable ECSPI2 Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl configuration for the SPI signals and chip select GPIO. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index f8a4b5b2e9fb..387bbe3454c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -99,6 +99,13 @@ &aud2htx { status = "okay"; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &hdmi_pai { status = "okay"; }; @@ -327,6 +334,15 @@ MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x16 >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x12 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x12 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x12 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 From a062ace84151ca83d39e6470c0a23c51c0d343df Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:11 +0200 Subject: [PATCH 057/864] arm64: dts: imx8mp-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 387bbe3454c3..7f5109bb4182 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -193,6 +193,14 @@ pcal6408: gpio@21 { reg = <0x21>; #gpio-cells = <2>; gpio-controller; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e { From 2558c810a6d28614a8b076123762ff53f4acef5e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:12 +0200 Subject: [PATCH 058/864] arm64: dts: imx8mp-var-som-symphony: enable PWM1 Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-var-som-symphony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 7f5109bb4182..54cb5725c4bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -247,6 +247,12 @@ &pcie_phy { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -400,6 +406,12 @@ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 From 8d7fc066c18a99cd95226a660f4ddcf353d91bd8 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:13 +0200 Subject: [PATCH 059/864] arm64: dts: imx8mp-var-som-symphony: enable CAN Enable the FlexCAN2 controller on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-var-som-symphony.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 54cb5725c4bf..93dee9ec0b9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -106,6 +106,12 @@ &ecspi2 { status = "okay"; }; +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + &hdmi_pai { status = "okay"; }; @@ -357,6 +363,13 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 >; }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 From 0bfd9e56f4868b66bdafed6a9f867629899bc199 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:14 +0200 Subject: [PATCH 060/864] arm64: dts: imx8mp-var-som-symphony: add second Ethernet port Add support for the second Ethernet interface available on the Symphony carrier board. Enable the FEC controller, add the MaxLinear MXL86110 Gigabit Ethernet PHY on the MDIO bus, describe its reset and power configuration, and add the required RGMII pinctrl settings. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../dts/freescale/imx8mp-var-som-symphony.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 93dee9ec0b9b..e928a3d44b1d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -66,6 +66,16 @@ pcie0_refclk: pcie0-refclk { clock-frequency = <100000000>; }; + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -106,6 +116,33 @@ &ecspi2 { status = "okay"; }; +&eqos { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -363,6 +400,23 @@ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 >; }; + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 + >; + }; + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 From 417b121ab93cd5a0929a663b9dc5da5595e290d3 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 8 Jun 2026 16:41:15 +0200 Subject: [PATCH 061/864] arm64: dts: freescale: imx8mp-var-som: add I2C1 bus recovery GPIOs Add the GPIO pinctrl state and GPIO descriptors required for I2C1 bus recovery on the VAR-SOM-MX8M-PLUS. This allows the I2C controller to recover the bus if SDA or SCL are held low by a device. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 49467b48d0b0..61786eee0e82 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -180,8 +180,11 @@ led@1 { &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -415,6 +418,13 @@ MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x400001c2 >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x1c2 + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x1c2 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 From b9e9f549e9b65d85605fd3f7cb587d4df81e7d06 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Sun, 7 Jun 2026 15:12:17 +0200 Subject: [PATCH 062/864] ARM: dts: imx7d-pico: describe Bluetooth controller Ampak AP6335i Wi-Fi module atop i.MX7D Pico SoM also supports Bluetooth 4.1 via UART attached to "serial6" port. Describe it, so the controller can probe automatically on boot. This is based on "Pico i.MMX Development Kit for Android Things Hardware Manual" rev. B1 [1], Table 6 on page 12. Link: https://www.nxp.com/docs/en/user-guide/PICO-IMX7UL-USG.pdf [1] Signed-off-by: Lech Perczak Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi index a1574ccec89c..6d4e8087192c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi @@ -339,6 +339,20 @@ &uart7 { /* Bluetooth */ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm4329-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bluetooth>; + + max-speed = <3000000>; + + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + device-wakeup-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wakeup"; + }; }; &usbotg1 { @@ -401,6 +415,15 @@ &wdog1 { }; &iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x14 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 + >; + + }; + pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2 From 4596f1624bf3abdc7782fbca0385bc0a8afb3d51 Mon Sep 17 00:00:00 2001 From: Paul Gerber Date: Thu, 25 Jun 2026 07:14:44 +0200 Subject: [PATCH 063/864] dt-bindings: arm: fsl: add TQMa8MPxS board TQMa8MPxS is a SOM family using NXP i.MX8MP CPU family. MB-SMARC-2 is an evaluation mainbord for this SOM The SOM needs a mainboard, therefore we provide two compatibles here: "tq,imx8mp-" for the module and "tq,imx8mp--" Signed-off-by: Paul Gerber Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 86876311ec59..6237fb2ae50e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1310,6 +1310,18 @@ properties: - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM - const: fsl,imx8mp + - description: + TQMa8MPxS is a series of SOM featuring NXP i.MX8MP system-on-chip + variants. It has the SMARC-2.0 form factor and is designed to be + placed on different carrier boards. All CPU variants use the same + device tree hence only one compatible is needed. MB-SMARC-2 is a + carrier reference design. + items: + - enum: + - tq,imx8mp-tqma8mpqs-mb-smarc-2 # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM on MB-SMARC-2 + - const: tq,imx8mp-tqma8mpqs # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM + - const: fsl,imx8mp + - description: Variscite VAR-SOM-MX8M Plus based boards items: - const: variscite,var-som-mx8mp-symphony From 6f0c003f0ddbfde3a311d350d2b3c1c38ac95dd4 Mon Sep 17 00:00:00 2001 From: Paul Gerber Date: Thu, 25 Jun 2026 07:14:45 +0200 Subject: [PATCH 064/864] arm64: dts: freescale: add initial device tree for TQMa8MPQS with i.MX8MP This adds support for TQMa8MPQS module on MB-SMARC-2 board. Signed-off-by: Paul Gerber Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts | 380 ++++++ .../boot/dts/freescale/imx8mp-tqma8mpqs.dtsi | 1178 +++++++++++++++++ 3 files changed, 1559 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 447c5f7721d4..33ed09e49871 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -443,6 +443,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revc-jutouch-jt101tm023.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-toradex-smarc-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10-dtbs += imx8mp-tx8p-ml81-moduline-display-106.dtb \ imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts new file mode 100644 index 000000000000..f01af630a7c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2.dts @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +/dts-v1/; + +#include +#include "imx8mp-tqma8mpqs.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxS on MB-SMARC-2"; + compatible = "tq,imx8mp-tqma8mpqs-mb-smarc-2", "tq,imx8mp-tqma8mpqs", "fsl,imx8mp"; + chassis-type = "embedded"; + + chosen { + stdout-path = &uart3; + }; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + mmc0 = &usdhc3; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &snvs_rtc; + spi0 = &flexspi; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander0 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "X6"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + panel_lvds0: panel-lvds0 { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds0>; + power-supply = <®_lvds0>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + + panel_lvds1: panel-lvds1 { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds1>; + power-supply = <®_lvds1>; + status = "disabled"; + + port { + panel_in_lvds1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_lvds0: regulator-lvds0 { + compatible = "regulator-fixed"; + regulator-name = "LCD0_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds1: regulator-lvds1 { + compatible = "regulator-fixed"; + regulator-name = "LCD1_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x38000000>; + alloc-ranges = <0 0x40000000 0 0x78000000>; + linux,cma-default; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-asrc = <&easrc>; + audio-cpu = <&sai5>; + audio-codec = <&tlv320aic3x04>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; + + usb-connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "X4"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; +}; + +&easrc { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; +}; + +&eqos { + status = "okay"; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + }; +}; + +ðphy3 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + default-state = "keep"; + }; + }; +}; + +&fec { + status = "okay"; +}; + +&flexcan1 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clock-names = "mclk"; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + }; + + eeprom2: eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + +&ldb_lvds_ch1 { + remote-endpoint = <&panel_in_lvds1>; +}; + +&lcdif1 { + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcie_phy { + fsl,clkreq-unsupported; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +®_usdhc2_vmmc { + startup-delay-us = <100>; + off-on-delay-us = <200000>; + status = "okay"; +}; + +®_usdhc2_vqmmc { + status = "okay"; +}; + +&sai3 { + status = "okay"; +}; + +&sai5 { + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; + + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + no-mmc; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi new file mode 100644 index 000000000000..20d55eeead57 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs.dtsi @@ -0,0 +1,1178 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "TQ-Systems i.MX8MPlus TQMa8MPxS"; + compatible = "tq,imx8mp-tqma8mpqs", "fsl,imx8mp"; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "SDIO_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5>; + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&audio_blk_ctrl { + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, + <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <147333333>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 12 GPIO_ACTIVE_LOW>; +}; + +/* GBE0 */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + snps,force_thresh_dma_mode; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; + + ethphy3: ethernet-phy@3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + reset-gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + interrupt-parent = <&gpio2>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; +}; + +/* GBE1 */ +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy3>; + fsl,magic-packet; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66666666>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <&buck5>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "SLEEP", "BATLOW#", "", "LID", + "", "GPIO10", "CHARGING#", "CHG_PRSNT#", + "PMIC_IRQ#", "ESPI_CS1_ALERT#", "USB1_OTG_ID", "USB2_OTG_ID", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + pmic_irq_hog: pmic-irq-hog { + gpio-hog; + gpios = <8 0>; + input; + line-name = "PMIC_IRQ#"; + }; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hoggpio2>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "PERST#", "PEWAKE#", + "SDIO_CD#", "", "", "", + "", "", "", "SDIO_PWR_EN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + enet0-int-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "ENET0_INT#"; + }; + + enet1-int-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "ENET_INT#"; + }; + + pewake-hog { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PEWAKE#"; + }; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio3>; + + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "GPIO4", + "GPIO3", "", "", "", + "", "", "", "", + "TEMP_EVENT#", "", "", ""; + + temp-event-hog { + gpio-hog; + gpios = <28 0>; + input; + line-name = "TEMP_EVENT#"; + }; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_sdp>, <&pinctrl_espi_rst>; + + gpio-line-names = "RTC_INT#", "GPIO8", "", "", + "GPIO9", "ESPI_RST#", "", "", + "", "", "", "", + "", "", "", "", + "", "", "GBE0_SDP_DIR", "", + "GPIO7", "", "", "", + "", "GPIO0", "GPIO1", "", + "GPIO2", "GPIO6", "", ""; + + rtc-int-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "RTC_INT#"; + }; + + espi-reset-hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "ESPI_RST#"; + }; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + + gpio-line-names = "", "", "", "", + "", "GPIO5", "", "", + "", "", "GPIO12", "GPIO11", + "", "GPIO13", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + + dp-hpd-int-hog { + gpio-hog; + gpios = <21 0>; + input; + line-name = "DP_HPD_INT"; + }; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; +}; + +&i2c1 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + read-only; + vcc-supply = <&buck5>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio4>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + }; + + eeprom1: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <&buck5>; + }; + + /* protectable identification memory (part of M24C64-D @50) */ + eeprom@58 { + compatible = "atmel,24c64d-wl"; + reg = <0x58>; + size = <32>; + pagesize = <32>; + vcc-supply = <&buck5>; + }; + + /* protectable identification memory (part of M24C64-D @54) */ + eeprom@5c { + compatible = "atmel,24c64d-wl"; + reg = <0x5c>; + size = <32>; + pagesize = <32>; + vcc-supply = <&buck5>; + }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; + + inertial-sensor@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + vdd-supply = <&buck4>; + vddio-supply = <&buck4>; + }; +}; + +&i2c2 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + + /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + + regulators { + /* V_0V85_SOC: 0.85 .. 0.95 */ + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + /* VDD_ARM */ + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-ramp-delay = <3125>; + }; + + /* VCC3V3 -> VMMC, ... must not be changed */ + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V1 -> RAM, ... must not be changed */ + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_SNVS */ + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* V_1V8_ANA */ + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* unused */ + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + /* VCC SD IO - switched using SD2 VSELECT */ + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tmp1075>; + vs-supply = <&buck4>; + }; + + expander0: gpio@73 { + compatible = "nxp,pca9538"; + reg = <0x73>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&buck5>; + gpio-line-names = "LCD0_BKLT_EN", "LCD0_VDD_EN", + "LCD1_BKLT_EN", "LCD1_VDD_EN", + "DP_BRIDGE_EN", "HUB_RST#", + "ENET0_RESET#", "ENET1_RESET#"; + }; +}; + +&i2c3 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0xf>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; + toshiba,hpd-pin = <0>; + interrupts-extended = <&gpio5 21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + toshiba,pre-emphasis = /bits/ 8 <1 1>; + }; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <384000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c6>; + pinctrl-1 = <&pinctrl_i2c6_gpio>; + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +// Change parent clock of disp1 pixel clock to audio_pll2 +&media_blk_ctrl { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_500M>; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <1000000000>; + samsung,esc-clock-frequency = <10000000>; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&dsi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + clock-names = "ref"; + clocks = <&pcieclk 0>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MP_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; +}; + +&uart3 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; +}; + +&usb3_phy0 { + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_5v0>; + status = "okay"; +}; + +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + fsl,over-current-active-low; +}; + +&usb3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented, but not a full featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + /* SMARC-2 USB0 interface only supports USB 2.0 signals */ + maximum-speed = "high-speed"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + vqmmc-supply = <®_usdhc2_vqmmc>; + /* NOTE: CD / WP and VMMC support depends on mainboard */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_eqos_event: eqosevtgrp { + fsl,pins = , + ; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = ; + }; + + pinctrl_espi_rst: espirstgrp { + fsl,pins = ; + }; + + pinctrl_fec: fecgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec_event: fecevtgrp { + fsl,pins = , + ; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_sdp: gbegrp { + fsl,pins = , + ; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = , + ; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = , + , + , + , + , + , + ; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = , + , + ; + }; + + pinctrl_hoggpio2: hoggpio2grp { + fsl,pins = ; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = , + ; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = , + ; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = , + ; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = , + ; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_i2c6: i2c6grp { + fsl,pins = , + ; + }; + + pinctrl_i2c6_gpio: i2c6-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = , + ; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = ; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = ; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = ; + }; + + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94 + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x94 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x94 + MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x94 + MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x94 + >; + }; + + pinctrl_tc9595: tc9595grp { + fsl,pins = ; + }; + + pinctrl_tmp1075: tmp1075grp { + fsl,pins = ; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = , + ; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = , + ; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = , + ; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = , + ; + }; + + pinctrl_usbcon0: usb0congrp { + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = , + ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = ; + }; +}; From 0d8c74f493e941ff61ce4dcfee75f2891bd44454 Mon Sep 17 00:00:00 2001 From: Paul Gerber Date: Thu, 25 Jun 2026 07:14:46 +0200 Subject: [PATCH 065/864] arm64: dts: freescale: add LVDS overlays for TQMa8MPxS This adds overlays for the supported LVDS display tianma tm070jvhg33 for both LVDS channels. The display timings have to be specified explicitly. Using the typical pixel clock, the LDB clock can not be configured as the 7-fold of that. By setting pixel clock to 74.25 MHz, LDB can be configured to exactly 519.75 MHz. Signed-off-by: Paul Gerber Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 5 +++ ...qma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso | 43 +++++++++++++++++++ ...qma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso | 43 +++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 33ed09e49871..b56afb1956ca 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -502,6 +502,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb +imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtbo +imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-pcie1-ep-dtbs += imx8mq-evk.dtb imx-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk-pcie1-ep.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso new file mode 100644 index 000000000000..2cf1de8c05b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + status = "okay"; +}; + +&panel_lvds0{ + compatible = "tianma,tm070jvhg33"; + status = "okay"; + + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <64>; + hback-porch = <5>; + hsync-len = <1>; + vfront-porch = <40>; + vback-porch = <2>; + vsync-len = <1>; + de-active = <1>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso new file mode 100644 index 000000000000..cbad0cfab292 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtso @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Paul Gerber + */ + +/dts-v1/; +/plugin/; + +&backlight_lvds1 { + status = "okay"; +}; + +&panel_lvds1{ + compatible = "tianma,tm070jvhg33"; + status = "okay"; + + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <64>; + hback-porch = <5>; + hsync-len = <1>; + vfront-porch = <40>; + vback-porch = <2>; + vsync-len = <1>; + de-active = <1>; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; From 3ee55e19db02d25d7c1155c3a6ab954aacfc55c5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 25 Jun 2026 07:14:47 +0200 Subject: [PATCH 066/864] arm64: dts: freescale: Add dual-channel LVDS overlay for TQMa8MPxS This adds an overlay for the supported LVDS display AUO G133HAN01. Configure the video PLL frequency to exactly match typical pixel clock of 141.200 MHz. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...p-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso | 81 +++++++++++++++++++ 2 files changed, 83 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b56afb1956ca..430085123b4e 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -502,8 +502,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-imx219.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314-lvds-tm070jvhg33-imx219.dtb +imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtbo imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtbo imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33-dtbs += imx8mp-tqma8mpqs-mb-smarc-2.dtb imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds0-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpqs-mb-smarc-2-lvds1-tm070jvhg33.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso new file mode 100644 index 000000000000..2d2dfda944fa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpqs-mb-smarc-2-lvds-g133han01.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Martin Schmiedel + */ + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + status = "okay"; +}; + +&panel_lvds0 { + compatible = "auo,g133han01"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_in_lvds1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +// Update VIDEO_PLL1 frequency +&media_blk_ctrl { + assigned-clock-rates = <500000000>, <200000000>, + <0>, <0>, <500000000>, + <988400000>; +}; + +&pwm3 { + status = "okay"; +}; From d8f1b27c9f12d17dc48d1baa4e83246dfd3cbfaf Mon Sep 17 00:00:00 2001 From: Thomas Richard Date: Wed, 6 May 2026 14:13:04 +0200 Subject: [PATCH 067/864] ARM: dts: ti: var-som-om44: Add USB Ethernet controller node Add USB tree description, including the Gigabit Ethernet controller (LAN7500). Adding the LAN7500 node will allow the bootloader to patch the devicetree and set the MAC address. Reviewed-by: Nicolai Buchwitz Signed-off-by: Thomas Richard Link: https://patch.msgid.link/20260506-b4-var-som-om44-lan7500-v2-2-b8af59ab877c@bootlin.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi index 37d56b3010cf..9e04aa70f982 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-var-som-om44.dtsi @@ -322,4 +322,18 @@ &usbhshost { &usbhsehci { phys = <&hsusb1_phy>; + #address-cells = <1>; + #size-cells = <0>; + + usbhub: hub@1 { + compatible = "usb424,2514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet: ethernet@3 { + compatible = "usb424,7500"; + reg = <3>; + }; + }; }; From 381819c38460a20a2ff235c974146b20930e71d8 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 28 Apr 2026 12:47:27 +0530 Subject: [PATCH 068/864] arm: dts: ti: Add device tree support for PRU-ICSS on AM57xx The TI Sitara AM57xx series of devices consists of 2 PRU-ICSS instances (PRU-ICSS1 and PRU-ICSS2). This patch adds the device tree nodes for the PRU-ICSS2 instance to support DUAL-MAC mode of operation. Each PRU-ICSS instance consists of two PRU cores along with various peripherals such as the Interrupt Controller (PRU_INTC), the Industrial Ethernet Peripheral(IEP), the Real Time Media Independent Interface controller (MII_RT), and the Enhanced Capture (eCAP) event module. am57-pruss.dtsi - Adds IEP and eCAP peripheral as child nodes of the PRUSS subsystem node. am57xx-idk-common.dtsi - Adds PRU-ICSS2 instance node along with PRU eth port information and corresponding port configuration. It includes interrupt mapping for packet reception, HW timestamp collection, and PRU Ethernet ports in MII mode. am571x-idk.dts, am572x-idk.dts and am574x-idk.dts - GPIO configuration along with delay configuration for individual PRU Ethernet port. Signed-off-by: Roger Quadros Signed-off-by: Andrew F. Davis Signed-off-by: Murali Karicheri Signed-off-by: Basharath Hussain Khaja Signed-off-by: Parvathi Pudi Reviewed-by: MD Danish Anwar Link: https://patch.msgid.link/20260428072046.3022679-2-parvathi@couthit.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/am57-pruss.dtsi | 11 ++++ arch/arm/boot/dts/ti/omap/am571x-idk.dts | 8 ++- arch/arm/boot/dts/ti/omap/am572x-idk.dts | 10 +-- arch/arm/boot/dts/ti/omap/am574x-idk.dts | 10 +-- .../boot/dts/ti/omap/am57xx-idk-common.dtsi | 61 +++++++++++++++++++ 5 files changed, 91 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi b/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi index 46c5383f0eee..f73316625608 100644 --- a/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi +++ b/arch/arm/boot/dts/ti/omap/am57-pruss.dtsi @@ -170,6 +170,17 @@ pruss2_iepclk_mux: iepclk-mux@30 { }; }; + pruss2_iep: iep@2e000 { + compatible = "ti,am5728-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss2_iepclk_mux>; + }; + + pruss2_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss2_mii_rt: mii-rt@32000 { compatible = "ti,pruss-mii", "syscon"; reg = <0x32000 0x58>; diff --git a/arch/arm/boot/dts/ti/omap/am571x-idk.dts b/arch/arm/boot/dts/ti/omap/am571x-idk.dts index 322cf79d22e9..02653b440585 100644 --- a/arch/arm/boot/dts/ti/omap/am571x-idk.dts +++ b/arch/arm/boot/dts/ti/omap/am571x-idk.dts @@ -214,5 +214,11 @@ &pruss1_mdio { }; &pruss2_mdio { - status = "disabled"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ +}; + +&pruss2_eth { + ti,pruss-gp-mux-sel = <4>, /* MII2, needed for PRUSS1_MII0 */ + <4>; /* MII2, needed for PRUSS1_MII1 */ }; diff --git a/arch/arm/boot/dts/ti/omap/am572x-idk.dts b/arch/arm/boot/dts/ti/omap/am572x-idk.dts index 94a738cb0a4d..54a8ccb9ca14 100644 --- a/arch/arm/boot/dts/ti/omap/am572x-idk.dts +++ b/arch/arm/boot/dts/ti/omap/am572x-idk.dts @@ -28,10 +28,12 @@ &mmc2 { pinctrl-2 = <&mmc2_pins_ddr_rev20>; }; -&pruss1_mdio { - status = "disabled"; +&pruss2_eth0_phy { + reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; -&pruss2_mdio { - status = "disabled"; +&pruss2_eth1_phy { + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; diff --git a/arch/arm/boot/dts/ti/omap/am574x-idk.dts b/arch/arm/boot/dts/ti/omap/am574x-idk.dts index 47b9174d2353..47b6c6cb210c 100644 --- a/arch/arm/boot/dts/ti/omap/am574x-idk.dts +++ b/arch/arm/boot/dts/ti/omap/am574x-idk.dts @@ -40,10 +40,12 @@ &emif1 { status = "okay"; }; -&pruss1_mdio { - status = "disabled"; +&pruss2_eth0_phy { + reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; -&pruss2_mdio { - status = "disabled"; +&pruss2_eth1_phy { + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <2>; /* PHY datasheet states 1uS min */ }; diff --git a/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi index 43e3623f079c..5eccff3bb4b6 100644 --- a/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am57xx-idk-common.dtsi @@ -155,6 +155,52 @@ src_clk_x1: src_clk_x1 { compatible = "fixed-clock"; clock-frequency = <20000000>; }; + + /* Dual-MAC Ethernet application node on PRU-ICSS2 */ + pruss2_eth: pruss2-eth { + compatible = "ti,am57-prueth"; + ti,prus = <&pru2_0>, <&pru2_1>; + sram = <&ocmcram1>; + ti,mii-rt = <&pruss2_mii_rt>; + ti,iep = <&pruss2_iep>; + ti,ecap = <&pruss2_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss2_intc>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss2_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss2_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + +}; + +&pruss2_iep { + interrupt-parent = <&pruss2_intc>; + interrupts = <7 7 8>; + interrupt-names = "iep_cap_cmp"; }; &dra7_pmx_core { @@ -606,3 +652,18 @@ dpi_out: endpoint { }; }; }; + +&pruss2_mdio { + status = "okay"; + pruss2_eth0_phy: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + }; + + pruss2_eth1_phy: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + }; +}; From 81aad76217d0b07ffd71b033a4d11fa6b6255f1f Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 28 Apr 2026 12:47:28 +0530 Subject: [PATCH 069/864] arm: dts: ti: Add device tree support for PRU-ICSS on AM437x The TI Sitara AM437x series of devices consists of 2 PRU-ICSS instances (PRU-ICSS0 and PRU-ICSS1). This patch adds the device tree nodes for the PRU-ICSS1 instance to support DUAL-MAC mode of operation. Support for Ethernet over PRU is available only for ICSS1 instance. PRU-ICSS instance consists of two PRU cores along with various peripherals such as the Interrupt Controller (PRU_INTC), the Industrial Ethernet Peripheral(IEP), the Real Time Media Independent Interface controller (MII_RT), and the Enhanced Capture (eCAP) event module. am4372.dtsi - Adds IEP and eCAP peripheral as child nodes of the PRUSS subsystem node. am437x-idk-evm.dts - Adds PRU-ICSS instance node along with PRU eth port information and corresponding port configuration. It includes interrupt mapping for packet reception, HW timestamp collection, and PRU Ethernet ports in MII mode, GPIO configuration, boot strapping along with delay configuration for individual PRU Ethernet port and other required nodes. Signed-off-by: Roger Quadros Signed-off-by: Andrew F. Davis Signed-off-by: Murali Karicheri Signed-off-by: Basharath Hussain Khaja Signed-off-by: Parvathi Pudi Reviewed-by: MD Danish Anwar Link: https://patch.msgid.link/20260428072046.3022679-3-parvathi@couthit.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/am4372.dtsi | 11 ++ arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts | 103 ++++++++++++++++++- 2 files changed, 113 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi index 504fa6b57d39..494f251c8e6a 100644 --- a/arch/arm/boot/dts/ti/omap/am4372.dtsi +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -476,6 +476,17 @@ pruss1_mii_rt: mii-rt@32000 { reg = <0x32000 0x58>; }; + pruss1_iep: iep@2e000 { + compatible = "ti,am4376-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss1_iepclk_mux>; + }; + + pruss1_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss1_intc: interrupt-controller@20000 { compatible = "ti,pruss-intc"; reg = <0x20000 0x2000>; diff --git a/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts index 826f687c368a..2efa303d45be 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts @@ -168,6 +168,48 @@ led-out7 { default-state = "off"; }; }; + + /* Dual-MAC Ethernet application node on PRU-ICSS1 */ + pruss1_eth: pruss1-eth { + compatible = "ti,am4376-prueth"; + ti,prus = <&pru1_0>, <&pru1_1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss1_mii_rt>; + ti,iep = <&pruss1_iep>; + ti,ecap = <&pruss1_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss1_intc>; + + pinctrl-0 = <&pruss1_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss1_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss1_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss1_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss1_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 5>, <24 9 5>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; }; &am43xx_pinmux { @@ -303,6 +345,52 @@ AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) >; }; + pruss1_mdio_default: pruss1-mdio-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x88c, PIN_OUTPUT | MUX_MODE5) /* (A12) gpmc_clk.pr1_mdio_mdclk */ + AM4372_IOPAD(0xa70, PIN_INPUT | MUX_MODE8) /* (D24) xdma_event_intr0.pr1_mdio_data */ + AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE7) /* (AD23) cam1_data6.gpio4[20] */ + >; + }; + + pruss1_eth_default: pruss1-eth-default-pins { + pinctrl-single,pins = < + AM4372_IOPAD(0x8a0, PIN_INPUT | MUX_MODE2) /* (B22) dss_data0.pr1_mii_mt0_clk */ + AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE2) /* (B20) dss_data5.pr1_mii0_txd0 */ + AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE2) /* (A20) dss_data4.pr1_mii0_txd1 */ + AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE2) /* (C21) dss_data3.pr1_mii0_txd2 */ + AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE2) /* (B21) dss_data2.pr1_mii0_txd3 */ + AM4372_IOPAD(0x8cc, PIN_INPUT | MUX_MODE5) /* (B18) dss_data11.pr1_mii0_rxd0 */ + AM4372_IOPAD(0x8c8, PIN_INPUT | MUX_MODE5) /* (A18) dss_data10.pr1_mii0_rxd1 */ + AM4372_IOPAD(0x8c4, PIN_INPUT | MUX_MODE5) /* (B19) dss_data9.pr1_mii0_rxd2 */ + AM4372_IOPAD(0x8c0, PIN_INPUT | MUX_MODE5) /* (A19) dss_data8.pr1_mii0_rxd3 */ + AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE2) /* (A21) dss_data1.pr1_mii0_txen */ + AM4372_IOPAD(0x8d8, PIN_INPUT | MUX_MODE5) /* (C17) dss_data14.pr1_mii_mr0_clk */ + AM4372_IOPAD(0x8dc, PIN_INPUT | MUX_MODE5) /* (D17) dss_data15.pr1_mii0_rxdv */ + AM4372_IOPAD(0x8d4, PIN_INPUT | MUX_MODE5) /* (D19) dss_data13.pr1_mii0_rxer */ + AM4372_IOPAD(0x8d0, PIN_INPUT | MUX_MODE5) /* (C19) dss_data12.pr1_mii0_rxlink */ + AM4372_IOPAD(0xa40, PIN_INPUT | MUX_MODE5) /* (G20) gpio5_10.pr1_mii0_crs */ + AM4372_IOPAD(0xa38, PIN_INPUT | MUX_MODE5) /* (D25) gpio5_8.pr1_mii0_col */ + + AM4372_IOPAD(0x858, PIN_INPUT | MUX_MODE5) /* (E8) gpmc_a6.pr1_mii_mt1_clk */ + AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE5) /* (E7) gpmc_a5.pr1_mii1_txd0 */ + AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE5) /* (D7) gpmc_a4.pr1_mii1_txd1 */ + AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE5) /* (A4) gpmc_a3.pr1_mii1_txd2 */ + AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE5) /* (C6) gpmc_a2.pr1_mii1_txd3 */ + AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE5) /* (D8) gpmc_a11.pr1_mii1_rxd0 */ + AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE5) /* (G8) gpmc_a10.pr1_mii1_rxd1 */ + AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE5) /* (B4) gpmc_a9.pr1_mii1_rxd2 */ + AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE5) /* (F7) gpmc_a8.pr1_mii1_rxd3 */ + AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE5) /* (C3) gpmc_a0.pr1_mii1_txen */ + AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE5) /* (F6) gpmc_a7.pr1_mii_mr1_clk */ + AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE5) /* (C5) gpmc_a1.pr1_mii1_rxdv */ + AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE5) /* (B3) gpmc_wpn.pr1_mii1_rxer */ + AM4372_IOPAD(0xa4c, PIN_INPUT | MUX_MODE5) /* (E24) gpio5_13.pr1_mii1_rxlink */ + AM4372_IOPAD(0xa44, PIN_INPUT | MUX_MODE5) /* (F23) gpio5_11.pr1_mii1_crs */ + AM4372_IOPAD(0x878, PIN_INPUT | MUX_MODE5) /* (A3) gpmc_be1n.pr1_mii1_col */ + >; + }; + qspi_pins_default: qspi-default-pins { pinctrl-single,pins = < AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */ @@ -539,5 +627,18 @@ opp-100-600000000 { }; &pruss1_mdio { - status = "disabled"; + pinctrl-0 = <&pruss1_mdio_default>; + pinctrl-names = "default"; + status = "okay"; + + reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + + pruss1_eth0_phy: ethernet-phy@0 { + reg = <0>; + }; + + pruss1_eth1_phy: ethernet-phy@1 { + reg = <1>; + }; }; From 0f44a4dba71d0b72e9aafc5de56a7252699f21c9 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Tue, 28 Apr 2026 12:47:29 +0530 Subject: [PATCH 070/864] arm: dts: ti: Add device tree support for PRU-ICSS on AM335x The TI Sitara AM335x ICE-V2 consists of single PRU-ICSS instance, This patch adds the new device tree overlay file in-order to enable PRU-ICSS instance, along with makefile changes. PRU-ICSS instance consists of two PRU cores along with various peripherals such as the Interrupt Controller (PRU_INTC), the Industrial Ethernet Peripheral(IEP), the Real Time Media Independent Interface controller (MII_RT), and the Enhanced Capture (eCAP) event module. am33xx-l4.dtsi - Adds IEP and eCAP peripheral as child nodes of the PRUSS subsystem node. am335x-icev2-prueth.dtso - Adds PRU-ICSS instance node along with PRU eth port information and corresponding port configuration. It includes interrupt mapping for packet reception, HW timestamp collection, and PRU Ethernet ports in MII mode, GPIO configuration, boot strapping along with delay configuration for individual PRU Ethernet port and other required nodes. Signed-off-by: Roger Quadros Signed-off-by: Andrew F. Davis Signed-off-by: Murali Karicheri Signed-off-by: Basharath Hussain Khaja Signed-off-by: Parvathi Pudi Reviewed-by: MD Danish Anwar Link: https://patch.msgid.link/20260428072046.3022679-4-parvathi@couthit.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/Makefile | 4 + .../ti/omap/am335x-icev2-prueth-overlay.dtso | 156 ++++++++++++++++++ arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 11 ++ 3 files changed, 171 insertions(+) create mode 100644 arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile index 3a4d9204339b..498c36ccb5ea 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -88,6 +88,9 @@ dtb-$(CONFIG_ARCH_OMAP4) += \ am335x-bonegreen-hdmi-00a0-dtbs := am335x-bonegreen-eco.dtb \ am335x-bone-hdmi-00a0.dtbo +am335x-icev2-prueth-dtbs := am335x-icev2.dtb \ + am335x-icev2-prueth-overlay.dtbo + dtb-$(CONFIG_SOC_AM33XX) += \ am335x-baltos-ir2110.dtb \ am335x-baltos-ir3220.dtb \ @@ -106,6 +109,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-evmsk.dtb \ am335x-guardian.dtb \ am335x-icev2.dtb \ + am335x-icev2-prueth.dtb \ am335x-lxm.dtb \ am335x-mba335x.dtb \ am335x-moxa-uc-2101.dtb \ diff --git a/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso b/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso new file mode 100644 index 000000000000..ffed1f3d046a --- /dev/null +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT overlay for IDK AM335x + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&{/} { + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible = "ti,am3359-prueth"; + ti,prus = <&pru0>, <&pru1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss_mii_rt>; + ti,iep = <&pruss_iep>; + ti,ecap = <&pruss_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss_intc>; + + pinctrl-0 = <&pruss_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; +}; + +&am33xx_pinmux { + /* MDIO node for PRU-ICSS */ + pruss_mdio_default: pruss-mdio-default-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x88c, PIN_OUTPUT | MUX_MODE5) /* (V12) gpmc_clk.pr1_mdio_mdclk */ + AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE5) /* (T13) gpmc_csn3.pr1_mdio_data */ + >; + }; + + /* Pinmux configuration for PRU-ICSS */ + pruss_eth_default: pruss-eth-default-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8a0, PIN_INPUT | MUX_MODE2) /* (R1) lcd_data0.pr1_mii_mt0_clk */ + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE2) /* (T2) lcd_data5.pr1_mii0_txd0 */ + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE2) /* (T1) lcd_data4.pr1_mii0_txd1 */ + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE2) /* (R4) lcd_data3.pr1_mii0_txd2 */ + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE2) /* (R3) lcd_data2.pr1_mii0_txd3 */ + AM33XX_IOPAD(0x8cc, PIN_INPUT | MUX_MODE5) /* (U4) lcd_data11.pr1_mii0_rxd0 */ + AM33XX_IOPAD(0x8c8, PIN_INPUT | MUX_MODE5) /* (U3) lcd_data10.pr1_mii0_rxd1 */ + AM33XX_IOPAD(0x8c4, PIN_INPUT | MUX_MODE5) /* (U2) lcd_data9.pr1_mii0_rxd2 */ + AM33XX_IOPAD(0x8c0, PIN_INPUT | MUX_MODE5) /* (U1) lcd_data8.pr1_mii0_rxd3 */ + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE2) /* (R2) lcd_data1.pr1_mii0_txen */ + AM33XX_IOPAD(0x8d8, PIN_INPUT | MUX_MODE5) /* (V4) lcd_data14.pr1_mii_mr0_clk */ + AM33XX_IOPAD(0x8dc, PIN_INPUT | MUX_MODE5) /* (T5) lcd_data15.pr1_mii0_rxdv */ + AM33XX_IOPAD(0x8d4, PIN_INPUT | MUX_MODE5) /* (V3) lcd_data13.pr1_mii0_rxer */ + AM33XX_IOPAD(0x8d0, PIN_INPUT | MUX_MODE5) /* (V2) lcd_data12.pr1_mii0_rxlink */ + AM33XX_IOPAD(0x8e8, PIN_INPUT | MUX_MODE2) /* (V5) lcd_pclk.pr1_mii0_crs */ + + AM33XX_IOPAD(0x840, PIN_INPUT | MUX_MODE5) /* (R13) gpmc_a0.pr1_mii_mt1_clk */ + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE5) /* (R14) gpmc_a4.pr1_mii1_txd0 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE5) /* (T14) gpmc_a3.pr1_mii1_txd1 */ + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE5) /* (U14) gpmc_a2.pr1_mii1_txd2 */ + AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE5) /* (V14) gpmc_a1.pr1_mii1_txd3 */ + AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE5) /* (V16) gpmc_a8.pr1_mii1_rxd0 */ + AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE5) /* (T15) gpmc_a7.pr1_mii1_rxd1 */ + AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE5) /* (U15) gpmc_a6.pr1_mii1_rxd2 */ + AM33XX_IOPAD(0x854, PIN_INPUT | MUX_MODE5) /* (V15) gpmc_a5.pr1_mii1_rxd3 */ + AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE5) /* (U17) gpmc_wpn.pr1_mii1_txen */ + AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE5) /* (U16) gpmc_a9.pr1_mii_mr1_clk */ + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE5) /* (T16) gpmc_a10.pr1_mii1_rxdv */ + AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE5) /* (V17) gpmc_a11.pr1_mii1_rxer */ + AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE5) /* (U18) gpmc_be1n.pr1_mii1_rxlink */ + AM33XX_IOPAD(0x8ec, PIN_INPUT | MUX_MODE2) /* (R6) lcd_ac_bias_en.pr1_mii1_crs */ + >; + }; +}; + +&gpio3 { + mux-mii-hog { + status = "disabled"; + }; + + mux-mii-hog-0 { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ + output-low; + line-name = "MUX_MII_CTL1"; + }; +}; + +/* + * Disable CPSW switch node and + * MDIO configuration to prevent + * conflict with PRU-ICSS + */ +&mac_sw { + status = "disabled"; +}; + +&davinci_mdio_sw { + status = "disabled"; +}; + +/* PRU-ICSS MDIO configuration */ +&pruss_mdio { + pinctrl-0 = <&pruss_mdio_default>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + pruss_eth0_phy: ethernet-phy@1 { + reg = <1>; + }; + + pruss_eth1_phy: ethernet-phy@3 { + reg = <3>; + }; +}; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index 89d16fcc773e..a63ef307d918 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -896,6 +896,17 @@ pruss_mii_rt: mii-rt@32000 { reg = <0x32000 0x58>; }; + pruss_iep: iep@2e000 { + compatible = "ti,am3356-icss-iep"; + reg = <0x2e000 0x31c>; + clocks = <&pruss_iepclk_mux>; + }; + + pruss_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; + pruss_intc: interrupt-controller@20000 { compatible = "ti,pruss-intc"; reg = <0x20000 0x2000>; From 68f994ec51e279e63c8fc40c1bfa8add4b708111 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 8 Jun 2026 22:44:26 +0200 Subject: [PATCH 071/864] ARM: dts: ti: Add specific compatibles for SCM conf nodes writing-bindings.rst rules dictate that "syscon" must come with a specific compatible identifying the register layout. Add specific compatibles for these devices. This also allows to solve a different problem: "syscon" is contradictory to "simple-bus". A system controller with registers having their own functions is not really a trivial MMIO simple bus. These two cannot be used together, unless listed as an exception. Reviewed-by: Andreas Kemnade Signed-off-by: Krzysztof Kozlowski Reviewed-by: Conor Dooley Link: https://patch.msgid.link/20260608-n-dt-bindings-simple-bus-syscon-v3-3-4eba9ec1212a@oss.qualcomm.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 2 +- arch/arm/boot/dts/ti/omap/am437x-l4.dtsi | 2 +- arch/arm/boot/dts/ti/omap/dm814x.dtsi | 2 +- arch/arm/boot/dts/ti/omap/dm816x.dtsi | 2 +- arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap2430.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap3.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 6 +++--- 9 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index a63ef307d918..8a693c478bea 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -308,7 +308,7 @@ am33xx_pinmux: pinmux@800 { }; scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; + compatible = "ti,am3352-scm-conf", "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi index e08f356e71cb..30fcce33f4b7 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi @@ -301,7 +301,7 @@ am43xx_pinmux: pinmux@800 { }; scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; + compatible = "ti,am4372-scm-conf", "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/dm814x.dtsi b/arch/arm/boot/dts/ti/omap/dm814x.dtsi index 27d1f35a31fd..9e02bfa5c3a2 100644 --- a/arch/arm/boot/dts/ti/omap/dm814x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dm814x.dtsi @@ -432,7 +432,7 @@ control: control@140000 { ranges = <0 0x140000 0x20000>; scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; + compatible = "ti,dm814-scm-conf", "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/dm816x.dtsi b/arch/arm/boot/dts/ti/omap/dm816x.dtsi index a1e0e904e0f0..ee0090f7aa64 100644 --- a/arch/arm/boot/dts/ti/omap/dm816x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dm816x.dtsi @@ -100,7 +100,7 @@ dm816x_pinmux: pinmux@800 { /* Device Configuration Registers */ scm_conf: syscon@600 { - compatible = "syscon", "simple-bus"; + compatible = "ti,dm8168-scm-conf", "syscon", "simple-bus"; reg = <0x600 0x110>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index c8d325b0f57b..9df7648c4b79 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -64,7 +64,7 @@ scm: scm@0 { ranges = <0 0 0x2000>; scm_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; + compatible = "ti,dra7-scm-conf", "syscon", "simple-bus"; reg = <0x0 0x1400>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi index 222613d2a4d1..01bd471f9223 100644 --- a/arch/arm/boot/dts/ti/omap/omap2430.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap2430.dtsi @@ -50,7 +50,7 @@ omap2430_pmx: pinmux@30 { }; scm_conf: scm_conf@270 { - compatible = "syscon", + compatible = "ti,omap2-scm-conf", "syscon", "simple-bus"; reg = <0x270 0x240>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi index 959069e24730..447736d2e53c 100644 --- a/arch/arm/boot/dts/ti/omap/omap3.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3.dtsi @@ -116,7 +116,7 @@ omap3_pmx_core: pinmux@30 { }; scm_conf: scm_conf@270 { - compatible = "syscon", "simple-bus"; + compatible = "ti,omap3-scm-conf", "syscon", "simple-bus"; reg = <0x270 0x330>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi index 4c78a0b28fab..c1afc49f456c 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -681,7 +681,7 @@ omap4_pmx_core: pinmux@40 { }; omap4_padconf_global: omap4_padconf_global@5a0 { - compatible = "syscon", + compatible = "ti,omap4-sysc-padconf-global", "syscon", "simple-bus"; reg = <0x5a0 0x170>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi index 915870eb5c99..72849e1c95b0 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -96,8 +96,7 @@ omap5_pmx_core: pinmux@40 { }; omap5_padconf_global: omap5_padconf_global@5a0 { - compatible = "syscon", - "simple-bus"; + compatible = "ti,omap5-sysc-padconf-global", "syscon", "simple-bus"; reg = <0x5a0 0xec>; #address-cells = <1>; #size-cells = <1>; @@ -2311,7 +2310,8 @@ omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 { ranges = <0 0 0x60>; scm_wkup_pad_conf: scm_conf@0 { - compatible = "syscon", "simple-bus"; + compatible = "ti,omap5-scm-wkup-conf", + "syscon", "simple-bus"; reg = <0x0 0x60>; #address-cells = <1>; #size-cells = <1>; From 21e741f3922c40305d9225c7a3b2557e5d926cd4 Mon Sep 17 00:00:00 2001 From: Vidhu Sarwal Date: Fri, 26 Jun 2026 16:47:20 +0530 Subject: [PATCH 072/864] ARM: dts: ti: Fix typos in comments Fix comment typos found with codespell across DaVinci and OMAP board files: limitaion -> limitation swithes -> switches converstion -> conversion differnet -> different Signed-off-by: Vidhu Sarwal Link: https://patch.msgid.link/20260626111720.56688-1-vidhu.linux@gmail.com Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/davinci/da850-lcdk.dts | 2 +- arch/arm/boot/dts/ti/omap/am3517-evm.dts | 2 +- arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts | 2 +- arch/arm/boot/dts/ti/omap/omap4-panda-es.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts index 8390d71b000a..e70edd5274fe 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts @@ -366,7 +366,7 @@ nand@2000000,0 { * to NAND block 1 (NAND block 0 is not used by default)". * The same doc mentions that for ROM "Silicon Revision 2.1", * "Updated NAND boot mode to offer boot from block 0 or block 1". - * However the limitaion is left here by default for compatibility + * However the limitation is left here by default for compatibility * with older silicon and because it needs new boot pin settings * not possible in stock LCDK. */ diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts index 40f15da81043..a4357fa9f006 100644 --- a/arch/arm/boot/dts/ti/omap/am3517-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts @@ -213,7 +213,7 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; clock-frequency = <400000>; - /* User DIP swithes [1:8] / User LEDS [1:2] */ + /* User DIP switches [1:8] / User LEDS [1:2] */ tca6416: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts index 43cf4ade950b..76bfb364777e 100644 --- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -420,7 +420,7 @@ stmpe811@41 { st,mod-12b = <1>; /* 12-bit ADC */ st,ref-sel = <0>; /* internal ADC reference */ st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ - st,sample-time = <4>; /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; /* ADC conversion time: 80 clocks */ stmpe_adc { compatible = "st,stmpe-adc"; diff --git a/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts index a933fe560834..70c609811d11 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-panda-es.dts @@ -12,7 +12,7 @@ / { compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; }; -/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ +/* Audio routing is different between PandaBoard4430 and PandaBoardES */ &sound { ti,model = "PandaBoardES"; From 9c269fe7eae8cb60d8d6c326dd8955818722fae9 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Tue, 16 Jun 2026 12:43:09 +0200 Subject: [PATCH 073/864] arm64: dts: imx93-kontron: set memory node to 0x80000000/1GiB The start address of the DRAM area is 0x80000000. The minimal size of the DDR on the SoM is 1 GiB. Fixes: 2b52fd6035b7 ("arm64: dts: Add support for Kontron i.MX93 OSM-S SoM and BL carrier board") Signed-off-by: Frieder Schrempf Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi index c79b1df339db..f881912cde46 100644 --- a/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi @@ -15,9 +15,9 @@ aliases { rtc1 = &bbnsm_rtc; }; - memory@40000000 { + memory@80000000 { device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; + reg = <0x0 0x80000000 0 0x40000000>; }; chosen { From 3385e2f77182469940c136b9eeedf01f27b7441f Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Mon, 22 Jun 2026 11:35:06 +0200 Subject: [PATCH 074/864] arm64: dts: freescale: imx95-toradex-smarc: add alias for lpuart5 Add alias for lpuart5 so the UART gets a stable line number. Without this alias, the lpuart driver fails: fsl-lpuart 42590000.serial: failed to get alias id, errno -19 This prevents the Bluetooth controller connected to this UART from working. Fixes: 104a391bb6ff ("arm64: dts: freescale: imx95-toradex-smarc: Enable bluetooth on lpuart5") Signed-off-by: Francesco Dolcini Acked-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index 7d760470201f..a6c5398a81e3 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -24,6 +24,7 @@ aliases { serial1 = &lpuart1; serial2 = &lpuart6; serial3 = &lpuart3; + serial4 = &lpuart5; }; chosen { From b1b6c1c4d3c63d8097c933009bdb618d1be18305 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Thu, 25 Jun 2026 13:47:09 +0800 Subject: [PATCH 075/864] arm64: dts: imx8mp-ab2: Enable MU2 for DSP communication Enable the MU2 (Message Unit 2) node on the i.MX8MP Audio Board v2. MU2 is required for inter-processor communication between the application CPU and the HiFi4 DSP, allowing DSP firmware to exchange control and status messages with the Linux host. Without this change, the DSP driver cannot establish the message channel and DSP audio processing is non-functional. Fixes: bf68c18150efc ("arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2)") Signed-off-by: Shengjiu Wang Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts index 443e4fd5b9bf..285bf79864eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts @@ -775,6 +775,10 @@ &micfil { status = "okay"; }; +&mu2 { + status = "okay"; +}; + &pwm1 { pinctrl-0 = <&pinctrl_pwm1>; pinctrl-names = "default"; From 65a02d82c59dcf1148f8325c176fba6c2172564f Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 30 Jun 2026 10:30:05 +0800 Subject: [PATCH 076/864] arm64: dts: imx94: add PCIe Root Port node Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the root port node and pave the path to add the reset-gpios and so on properties in root port later. Signed-off-by: Richard Zhu Reviewed-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 11 +++++++++++ arch/arm64/boot/dts/freescale/imx943.dtsi | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 1f9035e6cf15..dfbb73603cb2 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1411,6 +1411,17 @@ pcie0: pcie@4c300000 { power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; fsl,max-link-speed = <3>; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie-ep@4c300000 { diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi index cf5b3dbb47ff..01152fd0efa5 100644 --- a/arch/arm64/boot/dts/freescale/imx943.dtsi +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi @@ -255,6 +255,17 @@ pcie1: pcie@4c380000 { power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; fsl,max-link-speed = <3>; status = "disabled"; + + pcie1_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_ep: pcie-ep@4c380000 { From eeaf1a44be8354c197107535727db9e1fa53472f Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 30 Jun 2026 10:30:06 +0800 Subject: [PATCH 077/864] arm64: dts: imx943-evk: add PCIe root port node and according properties Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the root port node and add the reset-gpios property in root port. Move the regulator to root port nodes as well, because that the PCI pwrctrl framework had been integrated into pci-imx6 driver. The backward compatibility is not a concern since i.MX94 is a newly introduced platform that is still under active development. Signed-off-by: Richard Zhu Reviewed-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 7cfd42468950..674410e541cb 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -1034,12 +1034,15 @@ &pcie0 { <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; - reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; - vpcie3v3aux-supply = <®_m2_wlan>; supports-clkreq; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_m2_wlan>; +}; + &pcie0_ep { pinctrl-0 = <&pinctrl_pcie0>; pinctrl-names = "default"; @@ -1058,12 +1061,15 @@ &pcie1 { <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; - reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; - vpcie3v3aux-supply = <®_slot_pwr>; supports-clkreq; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>; + vpcie3v3aux-supply = <®_slot_pwr>; +}; + &pcie1_ep { pinctrl-0 = <&pinctrl_pcie1>; pinctrl-names = "default"; From c41cd028e8fb138aa6243d224d637db15354ea95 Mon Sep 17 00:00:00 2001 From: Mark Tseng Date: Fri, 29 May 2026 18:05:08 +0800 Subject: [PATCH 078/864] arm64: dts: mediatek: mt8186: change CCI OPP scaling mapping The original CCI OPP table minimum frequency 500Mhz is too low to cause system stall, So it need update to new version, 1.4G ~ 0.8G. Signed-off-by: Mark Tseng Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 110 +++++++++++------------ 1 file changed, 55 insertions(+), 55 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index b91f88ffae0e..fded6345d422 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -48,79 +48,79 @@ cci_opp: opp-table-cci { compatible = "operating-points-v2"; opp-shared; - cci_opp_0: opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <600000>; - }; - - cci_opp_1: opp-560000000 { - opp-hz = /bits/ 64 <560000000>; - opp-microvolt = <675000>; - }; - - cci_opp_2: opp-612000000 { - opp-hz = /bits/ 64 <612000000>; - opp-microvolt = <693750>; - }; - - cci_opp_3: opp-682000000 { - opp-hz = /bits/ 64 <682000000>; - opp-microvolt = <718750>; - }; - - cci_opp_4: opp-752000000 { - opp-hz = /bits/ 64 <752000000>; - opp-microvolt = <743750>; - }; - - cci_opp_5: opp-822000000 { - opp-hz = /bits/ 64 <822000000>; - opp-microvolt = <768750>; - }; - - cci_opp_6: opp-875000000 { - opp-hz = /bits/ 64 <875000000>; - opp-microvolt = <781250>; - }; - - cci_opp_7: opp-927000000 { - opp-hz = /bits/ 64 <927000000>; + cci_opp_0: opp-800000000 { + opp-hz = /bits/ 64 <800000000>; opp-microvolt = <800000>; }; - cci_opp_8: opp-980000000 { - opp-hz = /bits/ 64 <980000000>; - opp-microvolt = <818750>; + cci_opp_1: opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <806250>; }; - cci_opp_9: opp-1050000000 { - opp-hz = /bits/ 64 <1050000000>; - opp-microvolt = <843750>; + cci_opp_2: opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-microvolt = <812500>; }; - cci_opp_10: opp-1120000000 { + cci_opp_3: opp-920000000 { + opp-hz = /bits/ 64 <920000000>; + opp-microvolt = <825000>; + }; + + cci_opp_4: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-microvolt = <831250>; + }; + + cci_opp_5: opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <837500>; + }; + + cci_opp_6: opp-1040000000 { + opp-hz = /bits/ 64 <1040000000>; + opp-microvolt = <850000>; + }; + + cci_opp_7: opp-1080000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <856250>; + }; + + cci_opp_8: opp-1120000000 { opp-hz = /bits/ 64 <1120000000>; opp-microvolt = <862500>; }; - cci_opp_11: opp-1155000000 { - opp-hz = /bits/ 64 <1155000000>; + cci_opp_9: opp-1160000000 { + opp-hz = /bits/ 64 <1160000000>; opp-microvolt = <887500>; }; - cci_opp_12: opp-1190000000 { - opp-hz = /bits/ 64 <1190000000>; - opp-microvolt = <906250>; + cci_opp_10: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <912500>; }; - cci_opp_13: opp-1260000000 { - opp-hz = /bits/ 64 <1260000000>; - opp-microvolt = <950000>; + cci_opp_11: opp-1240000000 { + opp-hz = /bits/ 64 <1240000000>; + opp-microvolt = <937500>; }; - cci_opp_14: opp-1330000000 { - opp-hz = /bits/ 64 <1330000000>; - opp-microvolt = <993750>; + cci_opp_12: opp-1280000000 { + opp-hz = /bits/ 64 <1280000000>; + opp-microvolt = <962500>; + }; + + cci_opp_13: opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <987500>; + }; + + cci_opp_14: opp-1360000000 { + opp-hz = /bits/ 64 <1360000000>; + opp-microvolt = <1012500>; }; cci_opp_15: opp-1400000000 { From 1f16e99cd8361b33758205eba587dbe40a82975a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jul 2026 16:37:45 +0800 Subject: [PATCH 079/864] arm64: dts: mediatek: mt8183-kukui: Add supply for SPI NOR flash The SPI NOR flash is powered from the always on 1.8V power rail through a load switch that is controlled by the security chip. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index a8e257b21a88..5ea499f349f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -849,6 +849,8 @@ w25q64dw: flash@0 { compatible = "winbond,w25q64dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; + /* Power actually controlled by security chip */ + vcc-supply = <&pp1800_alw>; }; }; From eb3e990db356964d64f5cc258d30776c0363f9e9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 2 Jul 2026 16:37:58 +0800 Subject: [PATCH 080/864] arm64: dts: mediatek: mt8188-geralt: Add supply for SPI NOR flash The SPI NOR flash is powered the "always on" 1.8V LDO regulated power rail. Add the supply for the SPI NOR flash. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 4cb23595d17b..f382f90c48f5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -645,6 +645,7 @@ flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <52000000>; + vcc-supply = <&pp1800_ldo_z1>; }; }; From 187e7567bfba38fc3759c0fbcd2886c5239ad415 Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Thu, 2 Jul 2026 02:56:57 +0800 Subject: [PATCH 081/864] arm64: dts: rockchip: Replace deprecated 'gpio' property with 'gpios' for 9Tripod X3568 v4 The 'gpio' property for fixed regulators has been deprecated in favor of the plural 'gpios' form according to the regulator-fixed binding. Update the USB host and USB OTG fixed regulators for the 9Tripod X3568 v4 board to use the modern 'gpios' property to conform with current devicetree binding standards. Signed-off-by: Coia Prant Link: https://patch.msgid.link/20260701185657.4092955-2-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts index 4db00489be40..2ac4f72b1585 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts @@ -205,7 +205,7 @@ vcc5v0_usb: regulator-vcc5v0-usb { vcc5v0_usb_host: regulator-vcc5v0-usb-host { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_usb_host_en>; regulator-name = "vcc5v0_usb_host"; @@ -217,7 +217,7 @@ vcc5v0_usb_host: regulator-vcc5v0-usb-host { vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_usb_otg_en>; regulator-name = "vcc5v0_usb_otg"; From 993555b5476cf02009c2ef5c21e8403baee945d1 Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Thu, 2 Jul 2026 02:56:56 +0800 Subject: [PATCH 082/864] arm64: dts: rockchip: Add AP6275S support for 9Tripod X3568 v4 Add the missing Broadcom Wi-Fi and Bluetooth child nodes for the 9Tripod X3568 v4 board. The Bluetooth subnode is attached to uart8 with hardware flow control enabled via RTS/CTS pins. The Wi-Fi subnode is connected via the sdmmc2 bus. Additionally, change the status of the i2s3_2ch node to "disabled" since the required rk3568-codec-digital driver for Bluetooth audio is currently unavailable in the mainline tree. Signed-off-by: Coia Prant Link: https://patch.msgid.link/20260701185657.4092955-1-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3568-9tripod-x3568-v4.dts | 56 +++++++++++++++++-- 1 file changed, 52 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts index 2ac4f72b1585..66f3cbb22a59 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts @@ -582,9 +582,9 @@ &i2s1_8ch { status = "okay"; }; -/* used for AP6275S Bluetooth Sound */ +/* required rk3568-codec-digital for AP6275S Bluetooth Sound */ &i2s3_2ch { - status = "okay"; + status = "disabled"; }; &mdio0 { @@ -664,6 +664,20 @@ &pdm { }; &pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { led_work_en: led_work_en { rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -699,6 +713,12 @@ vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + wifi-irq { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &pmu_io_domains { @@ -770,7 +790,19 @@ &sdmmc2 { sd-uhs-sdr104; vmmc-supply = <&vcc3v3_sys>; vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43752-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + }; }; &spdif { @@ -798,10 +830,26 @@ &uart4 { status = "okay"; }; -/* used for WiFi/BT AP6275S */ +/* used for AP6275S Bluetooth */ &uart8 { - pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + uart-has-rtscts; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; + shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + vddio-supply = <&vcc_1v8>; + }; }; &uart9 { From fe76e3493f9ea5e927f9ce6bfe7f8785ba2d0c44 Mon Sep 17 00:00:00 2001 From: Daniele Briguglio Date: Wed, 10 Jun 2026 15:58:58 +0200 Subject: [PATCH 083/864] dt-bindings: vendor-prefixes: Add youyeetoo Youyeetoo is the single board computer brand of Hong Kong Cybodev Tech Limited. Link: https://www.youyeetoo.com Signed-off-by: Daniele Briguglio Acked-by: Conor Dooley Link: https://patch.msgid.link/20260610-yy3588-board-v1-1-4bb7176b6826@superkali.me Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..804bcce2cdb3 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1925,6 +1925,8 @@ patternProperties: description: YSH & ATIL "^yones-toptech,.*": description: Yones Toptech Co., Ltd. + "^youyeetoo,.*": + description: Hong Kong Cybodev Tech Limited (youyeetoo) "^ys,.*": description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": From 1e476370fbb1def308e6da3785843f1d34529721 Mon Sep 17 00:00:00 2001 From: Daniele Briguglio Date: Wed, 10 Jun 2026 15:58:59 +0200 Subject: [PATCH 084/864] dt-bindings: arm: rockchip: Add Youyeetoo YY3588 The YY3588 is a single board computer based on the Rockchip RK3588. Add devicetree binding documentation for it. Signed-off-by: Daniele Briguglio Acked-by: Conor Dooley Link: https://patch.msgid.link/20260610-yy3588-board-v1-2-4bb7176b6826@superkali.me Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..e7894d2b8f56 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1347,6 +1347,11 @@ properties: - const: xunlong,orangepi-cm5 - const: rockchip,rk3588s + - description: Youyeetoo YY3588 + items: + - const: youyeetoo,yy3588 + - const: rockchip,rk3588 + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 From 1b3ab2f3f1f4970cbd992a02bcc5f90551d67966 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 10 Apr 2026 09:31:07 +0200 Subject: [PATCH 085/864] arm64: dts: qcom: milos: Add IMEM node Add a node for the IMEM found on Milos, which contains pil-reloc-info and the modem tables for IPA, among others. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260410-milos-imem-v3-2-d215385fa5ab@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index e97c9ca8320e..64c493b82733 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -2340,6 +2340,26 @@ scl-pins { }; }; + sram@14680000 { + compatible = "qcom,milos-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x2c000>; + ranges = <0x0 0x0 0x14680000 0x2c000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + + ipa_modem_tables: modem-tables-sram@3000 { + reg = <0x3000 0x2000>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; From 8e73ae5c34e4fbbd25a8324e3c0eb1e845d7f01e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 13 Apr 2026 11:05:28 +0200 Subject: [PATCH 086/864] arm64: dts: qcom: sm6115-pro1x: Correct touchscreen GPIO flags IRQ_TYPE_xxx flags are not correct in the context of GPIO flags. These are simple defines so they could be used in DTS but they will not have the same meaning: IRQ_TYPE_LEVEL_LOW = 8 = GPIO_TRANSITORY. Correct the touchscreen irq-gpios to use proper flags, assuming the author of the code wanted similar logical behavior: IRQ_TYPE_LEVEL_LOW => GPIO_ACTIVE_LOW Fixes: e46b455e67f8 ("arm64: dts: qcom: sm6115-pro1x: Add Goodix Touchscreen") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260413090527.53000-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 0f23eaef01f2..b290f0f4c0e1 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -151,7 +151,7 @@ touchscreen@14 { interrupts-extended = <&tlmm 80 IRQ_TYPE_LEVEL_LOW>; - irq-gpios = <&tlmm 80 IRQ_TYPE_LEVEL_LOW>; + irq-gpios = <&tlmm 80 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>; AVDD28-supply = <&ts_vdd_supply>; VDDIO-supply = <&ts_vddio_supply>; From 6cc812b7435a64cd9d66af107c6dfefb2e77a7cb Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Mon, 6 Apr 2026 22:24:40 +0200 Subject: [PATCH 087/864] arm64: dts: qcom: ipq6018: add pwm node Describe the PWM block on IPQ6018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20260406-ipq-pwm-v21-3-6ed1e868e4c2@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 40f1c262126e..7866844cc09f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -413,6 +413,16 @@ tcsr: syscon@1937000 { reg = <0x0 0x01937000 0x0 0x21000>; }; + pwm: pwm@1941010 { + compatible = "qcom,ipq6018-pwm"; + reg = <0x0 0x01941010 0x0 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + usb2: usb@70f8800 { compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; reg = <0x0 0x070f8800 0x0 0x400>; From 4b00afd17a28f44dc63a8602143f84e5f3fa592c Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 6 Apr 2026 22:24:41 +0200 Subject: [PATCH 088/864] arm64: dts: qcom: ipq5018: add pwm node Describe the PWM block on IPQ5018. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20260406-ipq-pwm-v21-4-6ed1e868e4c2@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 6f8004a22a1f..edff89257468 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + pwm: pwm@1941010 { + compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg = <0x7804000 0x1000>; From 70900a931713888b63c8daec10e708dad1d6e160 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 6 Apr 2026 22:24:42 +0200 Subject: [PATCH 089/864] arm64: dts: qcom: ipq5332: add pwm node Describe the PWM block on IPQ5332. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20260406-ipq-pwm-v21-5-6ed1e868e4c2@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index e227730d99a6..27504b7cfe9e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -334,6 +334,16 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + pwm: pwm@1941010 { + compatible = "qcom,ipq5332-pwm", "qcom,ipq6018-pwm"; + reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + sdhc: mmc@7804000 { compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x07805000 0x1000>; From 35d89e1e12f297b1dce579cbae924e087451acc7 Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 6 Apr 2026 22:24:43 +0200 Subject: [PATCH 090/864] arm64: dts: qcom: ipq9574: add pwm node Describe the PWM block on IPQ9574. Although PWM is in the TCSR area, make pwm its own node as simple-mfd has been removed from the bindings and as such hardware components should have its own node. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20260406-ipq-pwm-v21-6-6ed1e868e4c2@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 622cfa96ed2b..3f15c40f7841 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -445,6 +445,16 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + pwm: pwm@1941010 { + compatible = "qcom,ipq9574-pwm", "qcom,ipq6018-pwm"; + reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + status = "disabled"; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, From f470169a802ede2f3b17a7ede77974c6fe2f5668 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 21 Apr 2026 12:16:06 +0200 Subject: [PATCH 091/864] arm64: dts: qcom: monaco-arduino-monza: add USB-C controller and connector Add the Cypress USB Type-C controller and associated connector. The controller is connected over I2C12 and wired to the USB1 DWC3. The USB-C connector routes both high-speed and super-speed signals. Enable dual-role data and power over the USB-C connector. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260421101606.411335-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/monaco-arduino-monza.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 379b796f261f..95e78ed5da1f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -246,6 +246,46 @@ &i2c12 { status = "okay"; + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + pinctrl-0 = <&typec_default_state>; + pinctrl-names = "default"; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi_hs_ccg_p0: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi_ss_ccg_p0: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + max98091: audio-codec@10 { compatible = "maxim,max98091"; reg = <0x10>; @@ -393,6 +433,12 @@ perst-pins { }; }; + typec_default_state: typec-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; @@ -469,6 +515,14 @@ &usb_1 { status = "okay"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&ucsi_hs_ccg_p0>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&ucsi_ss_ccg_p0>; +}; + /* Internally connected to the MCU (e.g. for DFU). */ &usb_2 { dr_mode = "host"; From 30ae66afcacf1a240ed4b9ec0b71d3316f3d3842 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Sat, 18 Apr 2026 11:38:15 +0530 Subject: [PATCH 092/864] arm64: dts: qcom: hamoa: add audio PD remote heap region Reference the reserved memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Signed-off-by: Ekansh Gupta Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260418-hamoaaudio-v1-1-a92866f744a6@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 4ba751a65142..a0f42d27372a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -4371,6 +4372,9 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From 0215d65882b46a22780f6d27d21c94b2550527a0 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Mon, 6 Apr 2026 16:31:12 +0530 Subject: [PATCH 093/864] arm64: dts: qcom: lemans-evk: Rename hd3ss3220_ instance for primary port controller Rename the hd3ss3220_ instance to improve clarity and simplify usage when adding a secondary port controller. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Swati Agarwal Link: https://lore.kernel.org/r/20260406110113.1709886-2-swati.agarwal@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 34dfc8d22b6a..c8c54ad01223 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -63,7 +63,7 @@ port@1 { reg = <1>; usb0_con_ss_ep: endpoint { - remote-endpoint = <&hd3ss3220_in_ep>; + remote-endpoint = <&hd3ss3220_0_in_ep>; }; }; }; @@ -551,7 +551,7 @@ ports { port@0 { reg = <0>; - hd3ss3220_in_ep: endpoint { + hd3ss3220_0_in_ep: endpoint { remote-endpoint = <&usb0_con_ss_ep>; }; }; @@ -559,7 +559,7 @@ hd3ss3220_in_ep: endpoint { port@1 { reg = <1>; - hd3ss3220_out_ep: endpoint { + hd3ss3220_0_out_ep: endpoint { remote-endpoint = <&usb_0_dwc3_ss>; }; }; @@ -996,7 +996,7 @@ &usb_0_dwc3_hs { }; &usb_0_dwc3_ss { - remote-endpoint = <&hd3ss3220_out_ep>; + remote-endpoint = <&hd3ss3220_0_out_ep>; }; &usb_0_hsphy { From 224d718f2f6b084e9d362f98dcb3ba9feabe28fe Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Mon, 6 Apr 2026 16:31:13 +0530 Subject: [PATCH 094/864] arm64: dts: qcom: lemans-evk: Enable secondary USB controller in host mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable secondary USB controller in host mode on lemans EVK Platform. Secondary USB controller is connected to a Genesys Logic USB HUB GL3590 having 4 ports. The ports of hub that are present on lemans EVK standalone board are used as follows:- 1) port-1 is connected to HD3SS3220 Type-C port controller. 2) port-4 is used for the M.2 E key on corekit. Standard core kit uses UART for Bluetooth. This port is to be used only if user optionally replaces the WiFi card with the NFA765 chip which uses USB for Bluetooth. Remaining 2 ports will become functional when the interface plus mezzanine board is stacked on top of corekit: 3) port-2 is connected to another hub which is present on the mezz through which 4 type-A ports are connected. 4) port-3 is used for the M.2 B key for a 5G card when the mezz is connected. Secondary USB Controller ↓ GL3590 USB Hub (4 ports) | |-- Port 1 → HD3SS3220 Type‑C Port Controller → USB‑C Connector | |-- Port 2 → Mezzanine USB Hub (when mezz attached) | |-- Port 3 → M.2 B‑Key Slot (when mezz attached) | |-- Port 4 → M.2 E‑Key Slot (Default: BT via UART; USB only if NFA765 module is installed) Mark the second USB controller as host only capable and add the HD3SS3220 Type-C port controller along with Type-C connector for controlling vbus supply. Signed-off-by: Swati Agarwal Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260406110113.1709886-3-swati.agarwal@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 168 ++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index c8c54ad01223..0b01be78a737 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -69,6 +69,37 @@ usb0_con_ss_ep: endpoint { }; }; + connector-1 { + compatible = "usb-c-connector"; + label = "USB1-Type-C"; + data-role = "host"; + power-role = "source"; + + vbus-supply = <&usb1_vbus>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb1_con_hs_ep: endpoint { + remote-endpoint = <&usb_hub_2_1>; + }; + }; + + port@1 { + reg = <1>; + + usb1_con_ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_1_in_ep>; + }; + + }; + }; + }; + connector-2 { compatible = "gpio-usb-b-connector", "usb-b-connector"; label = "micro-USB"; @@ -161,6 +192,15 @@ usb0_vbus: regulator-usb0-vbus { enable-active-high; }; + usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + gpio = <&expander1 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + usb2_vbus: regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "usb2_vbus"; @@ -565,6 +605,39 @@ hd3ss3220_0_out_ep: endpoint { }; }; }; + + usb-typec@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + + interrupts-extended = <&pmm8654au_2_gpios 6 IRQ_TYPE_EDGE_FALLING>; + + id-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_id>, <&usb1_intr>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_1_in_ep: endpoint { + remote-endpoint = <&usb1_con_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_1_out_ep: endpoint { + remote-endpoint = <&usb_hub_3_1>; + }; + }; + }; + }; }; &i2c18 { @@ -756,6 +829,14 @@ usb0_intr_state: usb0-intr-state { power-source = <0>; }; + usb1_intr: usb1-intr-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; + usb2_id: usb2-id-state { pins = "gpio11"; function = "normal"; @@ -956,6 +1037,12 @@ usb_id: usb-id-state { function = "gpio"; bias-pull-up; }; + + usb1_id: usb1-id-state { + pins = "gpio51"; + function = "gpio"; + bias-pull-up; + }; }; &uart0 { @@ -1014,6 +1101,87 @@ &usb_0_qmpphy { status = "okay"; }; +&usb_1 { + dr_mode = "host"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + + peer-hub = <&usb_hub_3_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_2_1: endpoint { + remote-endpoint = <&usb1_con_hs_ep>; + }; + }; + + /* + * Port-4 is connected to M.2 E key connector on corekit. + */ + port@4 { + reg = <4>; + + usb_hub_2_4: endpoint { + }; + }; + }; + }; + + usb_hub_3_x: hub@2 { + compatible = "usb5e3,625"; + reg = <2>; + + peer-hub = <&usb_hub_2_x>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_3_1: endpoint { + remote-endpoint = <&hd3ss3220_1_out_ep>; + }; + }; + + port@4 { + reg = <4>; + + usb_hub_3_4: endpoint { + }; + }; + }; + }; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l7a>; + vdda18-supply = <&vreg_l6c>; + vdda33-supply = <&vreg_l9a>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l7a>; + + status = "okay"; +}; + &usb_2 { status = "okay"; }; From d5e3237dafb91c87e0204decddd22e6378b32769 Mon Sep 17 00:00:00 2001 From: Mahadevan P Date: Mon, 20 Apr 2026 15:30:02 +0530 Subject: [PATCH 095/864] arm64: dts: qcom: qcs6490-rb3gen2: Enable 4-lane DisplayPort Alt Mode Add the mode-switch property to the QMP combo PHY so that mode-switch events are routed to it, allowing the PHY to enter DisplayPort Alternate Mode. Expand the DP data-lanes assignment from two to four lanes to make use of the full link bandwidth available in this configuration. Signed-off-by: Mahadevan P Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260420-kodiak_4k-v1-1-83dfc66b8f06@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 37a3b51323ce..9c24802e476e 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -806,7 +806,7 @@ &mdss_dp { }; &mdss_dp_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; @@ -1422,6 +1422,7 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p912>; + mode-switch; orientation-switch; status = "okay"; From fdb2f446c4e6758802d678858b5811d46709d0e6 Mon Sep 17 00:00:00 2001 From: Ananthu C V Date: Fri, 24 Apr 2026 03:36:13 -0700 Subject: [PATCH 096/864] dt-bindings: sram: document glymur as compatible Add compatible for Qualcomm's glymur IMEM, a block of sram which can fall back to mmio-sram. Acked-by: Rob Herring (Arm) Signed-off-by: Ananthu C V Link: https://lore.kernel.org/r/20260424-glymur-imem-v5-1-18ede63cf063@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index eb695698a03e..5bf27c5f63e2 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -35,6 +35,7 @@ properties: - nvidia,tegra194-sysram - nvidia,tegra234-sysram - qcom,eliza-imem + - qcom,glymur-imem - qcom,hawi-imem - qcom,kaanapali-imem - qcom,milos-imem From 4c53f51b442ae8cc4545fc5ec349ce6ed7afb4cf Mon Sep 17 00:00:00 2001 From: Ananthu C V Date: Fri, 24 Apr 2026 03:36:14 -0700 Subject: [PATCH 097/864] arm64: dts: qcom: glymur: add IMEM and PIL regions Add an IMEM on glymur which falls back to mmio-sram and define the PIL relocation info region as its child, for post mortem tools to locate the loaded remoteprocs. Reviewed-by: Konrad Dybcio Signed-off-by: Ananthu C V Link: https://lore.kernel.org/r/20260424-glymur-imem-v5-2-18ede63cf063@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e753d948fec1..00ce22ceddc5 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -6967,6 +6967,22 @@ swao_tpdm_out: endpoint { }; }; + sram@14680000 { + compatible = "qcom,glymur-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x2c000>; + ranges = <0 0 0x14680000 0x2c000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,glymur-smmu-500", "qcom,smmu-500", From 347318325974e888dc18d9fd15dcc48f671886c9 Mon Sep 17 00:00:00 2001 From: Joe Sandom Date: Mon, 20 Apr 2026 10:13:13 +0100 Subject: [PATCH 098/864] arm64: dts: qcom: sm8550: add PCIe MHI register regions Add the MHI register regions to the pcie0 and pcie1 controller nodes to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2) via debugfs. The PCIe host driver uses this region to read the link_transition_count from the MHI registers. Reviewed-by: Konrad Dybcio Signed-off-by: Joe Sandom Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-1-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 396201905ef2..1f2cafb1c380 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2321,8 +2321,14 @@ pcie0: pcie@1c00000 { <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, @@ -2495,8 +2501,14 @@ pcie1: pcie@1c08000 { <0x0 0x40000000 0x0 0xf1d>, <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x1000>, - <0x0 0x40100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, From a23536d85805e455cbb6b101f05e48ab672edf9d Mon Sep 17 00:00:00 2001 From: Joe Sandom Date: Mon, 20 Apr 2026 10:13:14 +0100 Subject: [PATCH 099/864] arm64: dts: qcom: sm8550: add PCIe port labels Add labels to the root port nodes (pcie0_port0, pcie1_port0) to allow board DTS files to reference them for adding endpoint devices to each pcie root port. Update the pcieport0 reference to pcie0_port0 in sm8550-hdk.dts and sm8550-qrd.dts to match the label rename in sm8550.dtsi. Reviewed-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Signed-off-by: Joe Sandom Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-2-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index ee13e6136a82..e821b731bdc4 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1012,7 +1012,7 @@ &pcie0 { status = "okay"; }; -&pcieport0 { +&pcie0_port0 { wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 2fb2e0be5e4c..cf63109ff7bf 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -912,7 +912,7 @@ &pcie0 { status = "okay"; }; -&pcieport0 { +&pcie0_port0 { wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1f2cafb1c380..aee4947fe70e 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2455,7 +2455,7 @@ opp-16000000-3 { }; }; - pcieport0: pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2657,7 +2657,7 @@ opp-32000000-4 { }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From e60ad1f5206bc8029c0b087846e12c715792b201 Mon Sep 17 00:00:00 2001 From: Joe Sandom Date: Mon, 20 Apr 2026 10:13:15 +0100 Subject: [PATCH 100/864] arm64: dts: qcom: sm8550: move IPA properties to SoC device tree Move qcom,gsi-loader and memory-region properties from individual board DTS files into the SoC DTSI, since these are common to all SM8550-based boards. Reviewed-by: Dmitry Baryshkov Signed-off-by: Joe Sandom Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-3-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 -- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 -- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 ++ 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index e821b731bdc4..b79558938552 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -939,8 +939,6 @@ &i2c_master_hub_0 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sm8550/ipa_fws.mbn"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index cf63109ff7bf..f2effa55d819 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -818,8 +818,6 @@ fsa4480_sbu_mux: endpoint { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sm8550/ipa_fws.mbn"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index aee4947fe70e..83136efb7724 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3091,6 +3091,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; sram = <&ipa_modem_tables>; status = "disabled"; From c70e25c221cee14c4bcd51ff763b697a2d7096b4 Mon Sep 17 00:00:00 2001 From: Joe Sandom Date: Mon, 20 Apr 2026 10:13:16 +0100 Subject: [PATCH 101/864] dt-bindings: arm: qcom: document QCS8550 RB5Gen2 board Document the Qualcomm RB5gen2 from Thundercomm based on the QCS8550 chipset from Qualcomm. [1] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit/ Reviewed-by: Krzysztof Kozlowski Signed-off-by: Joe Sandom Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-4-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index dfbc82377fcf..2b9ba6f76bca 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1112,6 +1112,12 @@ properties: - const: qcom,qcs8550 - const: qcom,sm8550 + - items: + - enum: + - qcom,qcs8550-rb5gen2 + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - ayaneo,pocket-s2 From 33cae252054a694269f9dcd41b354063193c8f59 Mon Sep 17 00:00:00 2001 From: Joe Sandom Date: Mon, 20 Apr 2026 10:13:17 +0100 Subject: [PATCH 102/864] arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support The RB5gen2 is an embedded development platform for the QCS8550, based on the Snapdragon 8 Gen 2 SoC (SM8550). This change implements the main board, the vision mezzanine will be supported in a follow up patch. The main board has the following features: - Qualcomm Dragonwing QCS8550 SoC - Adreno GPU 740 - Spectra ISP - Adreno VPU 8550 - Adreno DPU 1295 - 1 x 1GbE Ethernet (USB Ethernet) - WIFI 7 + Bluetooth 5.4 - 1 x USB 2.0 Micro B (Debug) - 1 x USB 3.0 Type C (ADB, DP out) - 2 x USB 3.0 Type A - 1 x HDMI 1.4 Type A - 1 x DP 1.4 Type C - 2 x WSA8845 Speaker amplifiers - 2 x Speaker connectors - 1 x On Board PDM MIC - Accelerometer + Gyro Sensor - 96Boards compatible low-speed and high-speed connectors [1] - 7 x LED indicators (4 user, 2 radio, 1 power) - Buttons for power, volume up/down, force USB boot - 3 x Dip switches On-Board PMICs: - PMK8550 2.1 - PM8550 2.0 - PM8550VS 2.0 x4 - PM8550VE 2.0 - PM8550B 2.0 - PMR735D 2.0 - PM8010 1.1 x2 Product Page: [2] [1] https://www.96boards.org/specifications/ [2] https://www.thundercomm.com/product/qualcomm-rb5-gen-2-development-kit The default msi-map from sm8550.dtsi is deleted for both pcie0 and pcie1. The QPS615 PCIe switch on each port exposes more than two devices (1 USP + 3 DSPs), but Gunyah currently limits ITS device mappings to two per root complex to save memory. With msi-map present, the ITS MAPD command times out. Deleting msi-map causes the DWC controller to fall back to its internal iMSI-RX module, which handles MSIs without this limitation. Signed-off-by: Joe Sandom Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260420-rb5gen2-dts-v4-5-b461909c2de8@axon.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 1573 ++++++++++++++++++ 2 files changed, 1574 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f33c4e2f09c..1c857bd7991b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -190,6 +190,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs8550-rb5gen2.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts new file mode 100644 index 000000000000..9df8dcd6c62b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts @@ -0,0 +1,1573 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Axon Enterprise, Inc. + */ + +/dts-v1/; + +#include +#include +#include +#include "qcs8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 5 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d_a.dtsi" +#include "pmr735d_b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QCS8550 RB5Gen2"; + compatible = "qcom,qcs8550-rb5gen2", "qcom,qcs8550", "qcom,sm8550"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + clk40m: can-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + /* Lontium LT9611UXC fails FW upgrade and has timeouts with geni-i2c */ + /* Workaround is to use bit-banged I2C */ + i2c_hub_3_gpio: i2c { + compatible = "i2c-gpio"; + + sda-gpios = <&tlmm 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "green:status-3"; + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pm8550_gpios 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "blue:bt-power"; + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&pm8550b_gpios 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-2 { + label = "yellow:wlan"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&pm8550b_gpios 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; + + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&redriver_usb_con_ss>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&redriver_usb_con_sbu>; + }; + }; + }; + }; + }; + + lt9611_1v2: regulator-lt9611-1v2 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vreg_l14b_3p2>; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_l14b_3p2>; + }; + + pcie_upd_1p05: regulator-pcie-upd-1p05 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_UPD_1P05"; + gpio = <&tlmm 179 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_ntn_0p9>; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + enable-active-high; + regulator-enable-ramp-delay = <5000>; + pinctrl-0 = <&upd_1p05_en>; + pinctrl-names = "default"; + }; + + pcie_upd_3p3: regulator-pcie-upd-3p3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_UPD_3P3"; + gpio = <&tlmm 13 GPIO_ACTIVE_HIGH>; + vin-supply = <&pcie_upd_1p05>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + pinctrl-0 = <&upd_3p3_en>; + pinctrl-names = "default"; + }; + + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + vin-supply = <&vdd_ntn_1p8>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn0_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + + vdd_ntn1_0p9: regulator-vdd-ntn1-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN1_0P9"; + vin-supply = <&vdd_ntn1_1p8>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn1_1p8: regulator-vdd-ntn1-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN1_1P8"; + gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn1_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard"; + model = "QCS8550-RB5Gen2"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + pinctrl-0 = <&wlan_en>, <&bt_default>, <&sw_ctrl_default>, + <&pmk8550_sleep_clk>; + pinctrl-names = "default"; + + wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 82 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_s5g_0p85>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_s2g_0p852>; + vdddig-supply = <&vreg_s4e_0p95>; + vddrfa1p2-supply = <&vreg_s4g_1p25>; + vddrfa1p8-supply = <&vreg_s6g_1p86>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1760000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s1-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <835000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p752: ldo2 { + regulator-name = "vreg_l2d_0p752"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <808000>; + regulator-initial-mode = ; + }; + + vreg_s4d_0p628: smps4 { + regulator-name = "vreg_s4d_0p628"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <988000>; + regulator-initial-mode = ; + }; + + vreg_s5d_0p728: smps5 { + regulator-name = "vreg_s5d_0p728"; + regulator-min-microvolt = <572000>; + regulator-max-microvolt = <988000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <831000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s1e_0p72: smps1 { + regulator-name = "vreg_s1e_0p72"; + regulator-min-microvolt = <532000>; + regulator-max-microvolt = <852000>; + regulator-initial-mode = ; + }; + + vreg_s3e_0p75: smps3 { + regulator-name = "vreg_s3e_0p75"; + regulator-min-microvolt = <716000>; + regulator-max-microvolt = <884000>; + regulator-initial-mode = ; + }; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <870100>; + regulator-max-microvolt = <1152000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_s6e_0p728: smps6 { + regulator-name = "vreg_s6e_0p728"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s1-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s1f_0p728: smps1 { + regulator-name = "vreg_s1f_0p728"; + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_s3f_0p852: smps3 { + regulator-name = "vreg_s3f_0p852"; + regulator-min-microvolt = <688000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = ; + }; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <500000>; + regulator-initial-mode = ; + }; + + vreg_s5f_0p752: smps5 { + regulator-name = "vreg_s5f_0p752"; + regulator-min-microvolt = <716000>; + regulator-max-microvolt = <884000>; + regulator-initial-mode = ; + }; + + vreg_s7f_0p628: smps7 { + regulator-name = "vreg_s7f_0p628"; + regulator-min-microvolt = <516000>; + regulator-max-microvolt = <812000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s1g_1p256: smps1 { + regulator-name = "vreg_s1g_1p256"; + regulator-min-microvolt = <1172000>; + regulator-max-microvolt = <1388000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p852: smps2 { + regulator-name = "vreg_s2g_0p852"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1053200>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p752: smps3 { + regulator-name = "vreg_s3g_0p752"; + regulator-min-microvolt = <532000>; + regulator-max-microvolt = <1148000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1172000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1002600>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2192000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6g_1p86>; + vdd-l6-supply = <&vreg_s6g_1p86>; + vdd-l7-supply = <&vreg_bob1>; + + qcom,pmic-id = "m"; + + vreg_l1m_1p056: ldo1 { + regulator-name = "vreg_l1m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p056: ldo2 { + regulator-name = "vreg_l2m_1p056"; + regulator-min-microvolt = <1056000>; + regulator-max-microvolt = <1056000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p8: ldo4 { + regulator-name = "vreg_l4m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l5m_1p8: ldo5 { + regulator-name = "vreg_l5m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6m_1p8: ldo6 { + regulator-name = "vreg_l6m_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p9: ldo7 { + regulator-name = "vreg_l7m_2p9"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2904000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + + vdd-l1-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-l4-supply = <&vreg_bob2>; + vdd-l5-supply = <&vreg_s6g_1p86>; + vdd-l6-supply = <&vreg_bob1>; + vdd-l7-supply = <&vreg_bob1>; + + qcom,pmic-id = "n"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p1: ldo2 { + regulator-name = "vreg_l2n_1p1"; + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_2p8: ldo3 { + regulator-name = "vreg_l3n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l4n_2p8: ldo4 { + regulator-name = "vreg_l4n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5n_1p8: ldo5 { + regulator-name = "vreg_l5n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_3p3: ldo6 { + regulator-name = "vreg_l6n_3p3"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l7n_2p96: ldo7 { + regulator-name = "vreg_l7n_2p96"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpi_dma2 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm8550/a740_zap.mbn"; +}; + +&i2c_hub_2 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_usb_con_ss: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_phy_con_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + data-lanes = <0 1 2 3>; + }; + }; + + port@2 { + reg = <2>; + + redriver_usb_con_sbu: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; + }; +}; + +&i2c_hub_3_gpio { + clock-frequency = <400000>; + + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 7 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c_hub_4 { + status = "okay"; +}; + +&i2c_master_hub_0 { + status = "okay"; +}; + +&ipa { + firmware-name = "qcom/sm8550/ipa_fws.mbn"; + + status = "okay"; +}; + +&iris { + status = "okay"; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <4800000>; + + vdd-micb-supply = <&vreg_l15b_1p8>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&pcie0 { + vddpe-3v3-supply = <&pcie_upd_3p3>; + + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>, + <0x208 &apps_smmu 0x1402 0x1>, + <0x210 &apps_smmu 0x1403 0x1>, + <0x218 &apps_smmu 0x1404 0x1>, + <0x300 &apps_smmu 0x1407 0x1>, + <0x400 &apps_smmu 0x1408 0x1>, + <0x500 &apps_smmu 0x140c 0x1>, + <0x501 &apps_smmu 0x140e 0x1>; + + /delete-property/ msi-map; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie0_port0 { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c_hub_4 0x77>; + + resx-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_0_rst>, <&upd_ponrst>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + iommu-map = <0x0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>, + <0x208 &apps_smmu 0x1482 0x1>, + <0x210 &apps_smmu 0x1483 0x1>, + <0x218 &apps_smmu 0x1484 0x1>, + <0x300 &apps_smmu 0x1487 0x1>, + <0x400 &apps_smmu 0x1488 0x1>, + <0x500 &apps_smmu 0x148c 0x1>, + <0x501 &apps_smmu 0x148e 0x1>; + + /delete-property/ msi-map; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + +&pcie1_port0 { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn1_0p9>; + vdd18-supply = <&vdd_ntn1_1p8>; + vdd09-supply = <&vdd_ntn1_0p9>; + vddio1-supply = <&vdd_ntn1_1p8>; + vddio2-supply = <&vdd_ntn1_1p8>; + vddio18-supply = <&vdd_ntn1_1p8>; + + i2c-parent = <&i2c_hub_3_gpio 0x77>; + + resx-gpios = <&tlmm 65 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_1_rst>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x40000 0x0 0x0 0x0 0x0>; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + }; + }; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8550_pwm { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + led@3 { + reg = <3>; + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + linux,default-trigger = "none"; + default-state = "off"; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pmk8550_gpios { + pmk8550_sleep_clk: sleep-clk-state { + pins = "gpio3"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <0>; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&spi11 { + status = "okay"; + + can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + interrupts-extended = <&tlmm 55 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk40m>; + spi-max-frequency = <10000000>; + vdd-supply = <&vreg_l14b_3p2>; + xceiver-supply = <&vreg_l14b_3p2>; + }; +}; + +&swr0 { + status = "okay"; + + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + /* 32-35 for NFC secure element */ + /* 36-39 for fingerprint sensor */ + gpio-reserved-ranges = <32 8>; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio7"; + function = "gpio"; + }; + + upd_3p3_en: upd-3p3-en-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio40"; + function = "gpio"; + bias-disable; + }; + + ntn1_en: ntn1-en-state { + pins = "gpio42"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tc9563_0_rst: tc9563-0-rst-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tc9563_1_rst: tc9563-1-rst-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ntn0_en: ntn0-en-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wlan_en: wlan-en-state { + pins = "gpio80"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + + bt_default: bt-default-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio82"; + function = "gpio"; + bias-pull-down; + }; + + upd_1p05_en: upd-1p05-en-state { + pins = "gpio179"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + upd_ponrst: upd-ponrst-state { + pins = "gpio182"; + function = "gpio"; + drive-strength = <2>; + output-high; + }; +}; + +&uart7 { + status = "okay"; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vdd-hba-supply = <&vreg_l3g_1p2>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_phy_con_ss>; +}; + +&xo_board { + clock-frequency = <76800000>; +}; From dd3d4327240dbd5e4a256f7428f92f454e23edba Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Tue, 21 Apr 2026 16:17:43 +0800 Subject: [PATCH 103/864] arm64: dts: meson: a1: Add clk measure support Add the clock measure device to the A1 SoC family. Reviewed-by: Neil Armstrong Signed-off-by: Jian Hu Link: https://patch.msgid.link/20260421-clkmsr_a1_t7-v3-3-efc00b0f9e6b@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 348411411f3d..6f6a6145cba1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -576,6 +576,11 @@ saradc: adc@2c00 { status = "disabled"; }; + clock-measurer@3400 { + compatible = "amlogic,a1-clk-measure"; + reg = <0x0 0x3400 0x0 0x1c>; + }; + i2c1: i2c@5c00 { compatible = "amlogic,meson-axg-i2c"; status = "disabled"; From d0a92020bb87b45a235d9d1f9ce76494e9ed02ca Mon Sep 17 00:00:00 2001 From: Jian Hu Date: Tue, 21 Apr 2026 16:17:44 +0800 Subject: [PATCH 104/864] arm64: dts: amlogic: t7: Add clk measure support Add the clock measure device to the T7 SoC family. Signed-off-by: Jian Hu Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260421-clkmsr_a1_t7-v3-4-efc00b0f9e6b@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi index cc371fcd1896..c3dc479b137d 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -674,6 +674,11 @@ pwm_ao_gh: pwm@32000 { status = "disabled"; }; + clock-measurer@48000 { + compatible = "amlogic,t7-clk-measure"; + reg = <0x0 0x48000 0x0 0x1c>; + }; + pwm_ab: pwm@58000 { compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm"; reg = <0x0 0x58000 0x0 0x24>; From 3ecd66ea250b81dcc847253efa6e4d691e6523c8 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Mon, 29 Jun 2026 07:52:53 +0000 Subject: [PATCH 105/864] arm64: dts: amlogic: add some device nodes for A9 Add pinctrl and irqchip-gpio device nodes for A9 SoC. Signed-off-by: Xianwei Zhao Link: https://patch.msgid.link/20260629-a9-node-v2-1-dadd3401fccb@amlogic.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi | 140 ++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi index 660c8556a864..b0e0fadeed82 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-a9.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -97,6 +98,95 @@ soc { #size-cells = <2>; ranges; + apb: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,pinctrl-a9"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x340>; + + gpioz: gpio@c0 { + reg = <0 0xc0 0 0x20>, <0 0x18 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>; + }; + + gpiox: gpio@100 { + reg = <0 0x100 0 0x24>, <0 0xc 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 18>; + }; + + gpioh: gpio@140 { + reg = <0 0x140 0 0x20>, <0 0x2c 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 8>; + }; + + gpiom: gpio@1a0 { + reg = <0 0x1a0 0 0x20>, <0 0x20 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_M<<8) 8>; + }; + + gpiob: gpio@240 { + reg = <0 0x240 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; + }; + + gpioa: gpio@280 { + reg = <0 0x280 0 0x24>, <0 0x40 0 0xc>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_A<<8) 20>; + }; + + gpioy: gpio@2c0 { + reg = <0 0x2c0 0 0x20>, <0 0x30 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_Y<<8) 10>; + }; + + gpiocc: gpio@300 { + reg = <0 0x300 0 0x20>, <0 0x14 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_CC<<8) 2>; + }; + }; + + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,a9-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + }; + gic: interrupt-controller@ff800000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -114,6 +204,56 @@ aobus: bus@ffa00000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffa00000 0x0 0x100000>; + aobus_pinctrl: pinctrl@4000 { + compatible = "amlogic,pinctrl-a9"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x4000 0x0 0x0e0>; + + gpioao: gpio@1c { + reg = <0 0x1c 0 0x20>, <0 0x0 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&aobus_pinctrl 0 (AMLOGIC_GPIO_AO<<8) 13>; + }; + + gpioc: gpio@3c { + reg = <0 0x3c 0 0x20>, <0 0x10 0 0x4>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&aobus_pinctrl 0 (AMLOGIC_GPIO_C<<8) 7>; + }; + + gpiod: gpio@5c { + reg = <0 0x5c 0 0x24>, <0 0x8 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&aobus_pinctrl 0 (AMLOGIC_GPIO_D<<8) 18>; + }; + + test_n: gpio@c0 { + reg = <0 0xc0 0 0x20>; + reg-names = "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&aobus_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; + }; + }; + + gpio_ao_intc: interrupt-controller@4080 { + compatible = "amlogic,a9-gpio-ao-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x34>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <384 385 386 387 388 389 390 391 392 393 + 394 395 396 397 398 399 400 401 402 403>; + }; + uart_b: serial@1e000 { compatible = "amlogic,a9-uart", "amlogic,meson-s4-uart"; From c11865aa07e8a1b1b3c50b995f7175312a4045a8 Mon Sep 17 00:00:00 2001 From: Alexandre Messier Date: Mon, 6 Apr 2026 01:16:57 -0400 Subject: [PATCH 106/864] ARM: dts: qcom: msm8974pro-htc-m8: add status LEDs Add support for the notification LEDs on the HTC One M8. Two LEDs are available, one orange and one green. Together, they both form a single notification source, so use a multicolor LED node to describe this arrangement. Cc: Lee Jones Cc: Pavel Machek Cc: linux-leds@vger.kernel.org Signed-off-by: Alexandre Messier Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260406-m8-dts-additions-v2-1-c4c4bd50af48@me.ssier.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts index 402372834c53..37df271dbdeb 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -3,6 +3,7 @@ #include "pm8841.dtsi" #include "pm8941.dtsi" #include +#include / { model = "HTC One (M8)"; @@ -64,6 +65,30 @@ vreg_vph_pwr: vreg-vph-pwr { }; }; +&pm8941_lpg { + qcom,power-source = <1>; + + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@6 { + reg = <6>; + color = ; + }; + + led@7 { + reg = <7>; + color = ; + }; + }; +}; + &pm8941_vib { status = "okay"; }; From 858e8a50ba0c0c9caa45f25dfbbb8b6bb26154b0 Mon Sep 17 00:00:00 2001 From: Alexandre Messier Date: Mon, 6 Apr 2026 01:16:58 -0400 Subject: [PATCH 107/864] ARM: dts: qcom: msm8974pro-htc-m8: add NFC support Add the NFC chip used in the HTC One M8 to its device tree. The downstream vendor kernel used an I2C frequency of 384 kHz for this bus. Use the same value as the vendor. Signed-off-by: Alexandre Messier Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260406-m8-dts-additions-v2-2-c4c4bd50af48@me.ssier.org Signed-off-by: Bjorn Andersson --- .../arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts index 37df271dbdeb..f24882dbeef3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -65,6 +65,22 @@ vreg_vph_pwr: vreg-vph-pwr { }; }; +&blsp1_i2c3 { + clock-frequency = <384000>; + + status = "okay"; + + nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 144 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + firmware-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + }; +}; + &pm8941_lpg { qcom,power-source = <1>; From 132a69d4092737d35470adc0f9c89fc68caf6288 Mon Sep 17 00:00:00 2001 From: Alexandre Messier Date: Mon, 6 Apr 2026 01:16:59 -0400 Subject: [PATCH 108/864] ARM: dts: qcom: msm8974pro-htc-m8: add Bluetooth pins Add the required pin configuration to enable Bluetooth. Reviewed-by: Konrad Dybcio Signed-off-by: Alexandre Messier Link: https://lore.kernel.org/r/20260406-m8-dts-additions-v2-3-c4c4bd50af48@me.ssier.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts index f24882dbeef3..2edf407db567 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -354,10 +354,19 @@ cmd-data-pins { }; wcnss_pin_a: wcnss-pin-active-state { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; - function = "wlan"; - drive-strength = <6>; - bias-pull-down; + bt-pins { + pins = "gpio35", "gpio43", "gpio44"; + function = "bt"; + drive-strength = <2>; + bias-pull-down; + }; + + wlan-pins { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + drive-strength = <6>; + bias-pull-down; + }; }; }; From 811a24b0ec0c3ec74dbe324c390b75a2b92571ea Mon Sep 17 00:00:00 2001 From: Alexandre Messier Date: Mon, 6 Apr 2026 01:17:00 -0400 Subject: [PATCH 109/864] ARM: dts: qcom: msm8974pro-htc-m8: add touchscreen Add the touchscreen device node for the HTC One (M8). The downstream vendor kernel used an I2C frequency of 384 kHz for this bus. Use the same value as the vendor. Signed-off-by: Alexandre Messier Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260406-m8-dts-additions-v2-4-c4c4bd50af48@me.ssier.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts index 2edf407db567..66ad93e7dd20 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -65,6 +65,35 @@ vreg_vph_pwr: vreg-vph-pwr { }; }; +&blsp1_i2c2 { + clock-frequency = <384000>; + + status = "okay"; + + touch@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupts-extended = <&tlmm 18 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int_pin>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; +}; + &blsp1_i2c3 { clock-frequency = <384000>; @@ -353,6 +382,13 @@ cmd-data-pins { }; }; + ts_int_pin: ts-int-pin-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcnss_pin_a: wcnss-pin-active-state { bt-pins { pins = "gpio35", "gpio43", "gpio44"; From 9594ee0e018dd8657e601b866ae3789ba9eb2e74 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 10 Apr 2026 15:32:13 +0200 Subject: [PATCH 110/864] arm64: dts: qcom: hamoa: Add interconnects to primary USB3 controller Add the interconnect paths to enable drivers to vote on them, ensuring the necessary NoC bandwidth is available. This hasn't been done before, as prior to commit 05566ebcc0cd ("clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON"), this would cause an inexplicable crash upon resume from system suspend. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260410-topic-hamoa_usb_icc-v1-1-461e64304067@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index a0f42d27372a..62126a194576 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5322,6 +5322,13 @@ usb_1_ss0: usb@a600000 { resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&usb_south_anoc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", + "apps-usb"; + wakeup-source; iommus = <&apps_smmu 0x1420 0x0>; From 44c655a08c9ee9590e64f8306a66917bbb629970 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 11 May 2026 18:13:21 +0530 Subject: [PATCH 111/864] arm64: dts: qcom: glymur-crd: Add Embedded controller node Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Tested-by: Anthony Ruhier Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-3-e5437c39b7f8@oss.qualcomm.com [bjorn: Added i2c alias for &i2c9] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index e784b538f42e..f7478b59624e 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -22,6 +22,7 @@ aliases { i2c0 = &i2c0; i2c1 = &i2c4; i2c2 = &i2c5; + i2c3 = &i2c9; spi0 = &spi18; }; @@ -444,6 +445,22 @@ vreg_l4h_e0_1p2: ldo4 { }; }; +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + embedded-controller@76 { + compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -596,6 +613,12 @@ hall_int_n_default: hall-int-n-state { bias-disable; }; + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; From 093766c0f0dc9e3e2d03800239d5915929d21e92 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 11 May 2026 18:13:22 +0530 Subject: [PATCH 112/864] arm64: dts: qcom: x1-crd: Add Embedded controller node Add embedded controller node for Hamoa/Purwa CRDs which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Tested-by: Anthony Ruhier Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-4-e5437c39b7f8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index a9c5c523575e..9602d65c8b3d 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1074,6 +1074,16 @@ eusb6_repeater: redriver@4f { #phy-cells = <0>; }; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -1523,6 +1533,12 @@ &tlmm { <44 4>, /* SPI (TPM) */ <238 1>; /* UFS Reset */ + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From feadf3294f0e6b262f98a46753817993757e5a45 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Mon, 11 May 2026 18:13:23 +0530 Subject: [PATCH 113/864] arm64: dts: qcom: hamoa-iot-evk: Add Embedded controller node Add embedded controller node for Hamoa IOT EVK boards which adds fan control, temperature sensors, access to EC internal state changes and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Gaurav Kohli Tested-by: Gaurav Kohli Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P Tested-by: Anthony Ruhier Link: https://lore.kernel.org/r/20260511-add-driver-for-ec-v9-5-e5437c39b7f8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index c7ba4b353ddd..9fa86bb6438e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -839,6 +839,16 @@ eusb6_repeater: redriver@4f { pinctrl-0 = <&eusb6_reset_n>; pinctrl-names = "default"; }; + + embedded-controller@76 { + compatible = "qcom,hamoa-iot-evk-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; }; &i2c7 { @@ -1341,6 +1351,12 @@ right_tweeter: speaker@0,1 { }; &tlmm { + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio70"; function = "gpio"; From dd923fcc2151d2d077542870304bec94f094bae7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 25 May 2026 13:47:48 +0200 Subject: [PATCH 114/864] arm64: dts: qcom: hamoa: Fix xbl_tmp_buffer_mem size The EFI memtable (shown when booting with efi=debug) shows that the xbl_tmp_buffer_mem region size is 0x1c0000 bytes large not 0xc00000 bytes: efi: 0x000082800000-0x0000829bffff [Reserved | efi: 0x0000829c0000-0x000083efffff [Conventional| This fix aligns the size with the EFI reported size and makes /proc/iomem correctly show mem blocks matching the EFI memmap: 82800000-829bffff : reserved 829c0000-83efffff : System RAM Instead of: 82800000-833fffff : reserved 83400000-83efffff : System RAM before this change Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20260525114749.5939-2-johannes.goede@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 62126a194576..7f849f5b32d3 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -592,7 +592,7 @@ tz_stat_mem: tz-stat@82700000 { }; xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { - reg = <0x0 0x82800000 0x0 0xc00000>; + reg = <0x0 0x82800000 0x0 0x1c0000>; no-map; }; From 7d240c5dd34ae8560f8d0557fbbd7b0165eab486 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 25 May 2026 13:47:49 +0200 Subject: [PATCH 115/864] arm64: dts: qcom: hamoa: Remove mem-reservations which are already covered by EFI Remove reservations from reserved-memory which are already covered by the EFI memmap. AFAICT there is no need to have these in the DT and chances are that they might change with a BIOS update, so lets drop them. hyp_elf_package_mem + ncc_mem are together covered by efi: 0x000080800000-0x000080dfffff [Reserved | xbl_dtlog_mem is covered by: efi: 0x000081a00000-0x000081a3ffff [Reserved | pdp_ns_shared_mem is covered by: efi: 0x000081e00000-0x000081efffff [Reserved | gpu_prr_mem + tpm_control_mem are together covered by: efi: 0x000081f00000-0x000081f1ffff [Reserved | usb_ucsi_shared_mem is covered by: efi: 0x000081f20000-0x000081f2ffff [Reserved | pld_pep_mem + pld_gmu_mem + pld_pdp_mem are together covered by: efi: 0x000081f30000-0x000081f37fff [Reserved | tz_stat_mem is covered by: efi: 0x000082700000-0x0000827fffff [Reserved | xbl_tmp_buffer_mem is covered by: efi: 0x000082800000-0x0000829bffff [Reserved | Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20260525114749.5939-3-johannes.goede@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 60 ----------------------------- 1 file changed, 60 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 7f849f5b32d3..82b1d363d2de 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -475,16 +475,6 @@ gunyah_hyp_mem: gunyah-hyp@80000000 { no-map; }; - hyp_elf_package_mem: hyp-elf-package@80800000 { - reg = <0x0 0x80800000 0x0 0x200000>; - no-map; - }; - - ncc_mem: ncc@80a00000 { - reg = <0x0 0x80a00000 0x0 0x400000>; - no-map; - }; - cpucp_log_mem: cpucp-log@80e00000 { reg = <0x0 0x80e00000 0x0 0x40000>; no-map; @@ -505,11 +495,6 @@ tags_mem: tags-region@81400000 { no-map; }; - xbl_dtlog_mem: xbl-dtlog@81a00000 { - reg = <0x0 0x81a00000 0x0 0x40000>; - no-map; - }; - xbl_ramdump_mem: xbl-ramdump@81a40000 { reg = <0x0 0x81a40000 0x0 0x1c0000>; no-map; @@ -551,51 +536,6 @@ secdata_apss_mem: secdata-apss@81cff000 { no-map; }; - pdp_ns_shared_mem: pdp-ns-shared@81e00000 { - reg = <0x0 0x81e00000 0x0 0x100000>; - no-map; - }; - - gpu_prr_mem: gpu-prr@81f00000 { - reg = <0x0 0x81f00000 0x0 0x10000>; - no-map; - }; - - tpm_control_mem: tpm-control@81f10000 { - reg = <0x0 0x81f10000 0x0 0x10000>; - no-map; - }; - - usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { - reg = <0x0 0x81f20000 0x0 0x10000>; - no-map; - }; - - pld_pep_mem: pld-pep@81f30000 { - reg = <0x0 0x81f30000 0x0 0x6000>; - no-map; - }; - - pld_gmu_mem: pld-gmu@81f36000 { - reg = <0x0 0x81f36000 0x0 0x1000>; - no-map; - }; - - pld_pdp_mem: pld-pdp@81f37000 { - reg = <0x0 0x81f37000 0x0 0x1000>; - no-map; - }; - - tz_stat_mem: tz-stat@82700000 { - reg = <0x0 0x82700000 0x0 0x100000>; - no-map; - }; - - xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { - reg = <0x0 0x82800000 0x0 0x1c0000>; - no-map; - }; - adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { reg = <0x0 0x84b00000 0x0 0x800000>; no-map; From cc827d6650db0d63d64abe1f7df227d8dc471547 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 1 May 2026 09:14:51 +0200 Subject: [PATCH 116/864] arm64: dts: qcom: milos: Add display (MDSS) Add device nodes for display: MDSS, DPU, DSI and DSI PHY. DisplayPort is not added for now. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260501-milos-mdss-v3-9-58bfc58c0e13@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 211 +++++++++++++++++++++++++++- 1 file changed, 209 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 64c493b82733..7a475b530213 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2025, Luca Weiss */ +#include #include #include #include @@ -1979,6 +1980,212 @@ camcc: clock-controller@adb0000 { #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,milos-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,milos-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz = /bits/ 64 <402000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz = /bits/ 64 <535000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0 0x0ae94000 0x0 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,milos-dsi-phy-4nm"; + reg = <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x300>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,milos-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; @@ -1987,8 +2194,8 @@ dispcc: clock-controller@af00000 { <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, /* dsi0_phy_pll_out_byteclk */ - <0>, /* dsi0_phy_pll_out_dsiclk */ + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, /* dp0_phy_pll_link_clk */ <0>; /* dp0_phy_pll_vco_div_clk */ From ac456227d22952b656ad291ebd2d3d3e498e3d95 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 29 Apr 2026 15:05:40 +0530 Subject: [PATCH 117/864] arm64: dts: qcom: sm8750: wire UFS to ice instance The Inline Crypto Engine (ICE) exists as a standalone DT node, but the UFS node lacks the required qcom,ice phandle reference. Add the qcom,ice property to explicitly associate the UFS controller with its ICE instance. Fixes: d288abc3a70e ("arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC") Signed-off-by: Kuldeep Singh Tested-by: Wenjia Zhang # on sm8750-mtp Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429-sm8750_ice_dt_fix-v1-1-2540dc337082@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index fafed417c66f..6bcda7c38dbf 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5445,6 +5445,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phy-names = "ufsphy"; #reset-cells = <1>; + qcom,ice = <&ice>; status = "disabled"; From 14a53a14a615915eeff73ca77e4267247f31f7ce Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 23 Apr 2026 18:55:31 +0530 Subject: [PATCH 118/864] arm64: dts: qcom: kaanapali: Add TRNG node Add the kaanpali nodes for the True Random Number Generator (TRNG). Signed-off-by: Kuldeep Singh Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260423-knp_rng-v1-1-9df6c0391a8f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 7aa9653bd456..8f8125f1de34 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -1513,6 +1513,11 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + rng: rng@10c3000 { + compatible = "qcom,kaanapali-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + ipcc: mailbox@1106000 { compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; reg = <0x0 0x01106000 0x0 0x1000>; From 921f145639e4626ae232b1ef0e935081e6d44043 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Wed, 20 May 2026 22:14:57 +0800 Subject: [PATCH 119/864] arm64: dts: qcom: Remove sa8775p-ride board The sa8775p-ride board development mostly happened back to year 2023, and it hadn't got any major update since then, except Wasim's refactor[1] last year which had no functional change for the board. Propose to stop maintaining the board for reasons below. - The Lemans development had moved to QCS9100/9075 EVK and Ride board for a long time. - Qualcomm stopped maintaining Meta Build (NHLOS firmware) for this target years ago. There is not too much point to continuing maintaining the DT, as DT usually depends on NHLOS firmware. Link: https://lore.kernel.org/all/20250803110113.401927-1-wasim.nazir@oss.qualcomm.com/ [1] Cc: Wasim Nazir Cc: Shazad Hussain Cc: Andrew Halaney Cc: Bartosz Golaszewski Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260520141457.988130-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 - arch/arm64/boot/dts/qcom/lemans-auto.dtsi | 104 ------------------- arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts | 17 --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 17 --- 4 files changed, 140 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/lemans-auto.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts delete mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1c857bd7991b..fb1a99a3e01c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -217,8 +217,6 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride-r3.dtb sc7180-acer-aspire1-el2-dtbs := sc7180-acer-aspire1.dtb sc7180-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += sc7180-acer-aspire1.dtb sc7180-acer-aspire1-el2.dtb sc7180-ecs-liva-qc710-el2-dtbs := sc7180-ecs-liva-qc710.dtb sc7180-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi b/arch/arm64/boot/dts/qcom/lemans-auto.dtsi deleted file mode 100644 index 8db958d60fd1..000000000000 --- a/arch/arm64/boot/dts/qcom/lemans-auto.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2023, Linaro Limited - */ - -/dts-v1/; - -#include "lemans.dtsi" - -/delete-node/ &pil_camera_mem; -/delete-node/ &pil_adsp_mem; -/delete-node/ &q6_adsp_dtb_mem; -/delete-node/ &q6_gdsp0_dtb_mem; -/delete-node/ &pil_gdsp0_mem; -/delete-node/ &pil_gdsp1_mem; -/delete-node/ &q6_gdsp1_dtb_mem; -/delete-node/ &q6_cdsp0_dtb_mem; -/delete-node/ &pil_cdsp0_mem; -/delete-node/ &pil_gpu_mem; -/delete-node/ &pil_cdsp1_mem; -/delete-node/ &q6_cdsp1_dtb_mem; -/delete-node/ &pil_cvp_mem; -/delete-node/ &pil_video_mem; -/delete-node/ &gunyah_md_mem; - -/ { - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - tz_ffi_mem: tz-ffi@91c00000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x91c00000 0x0 0x1400000>; - no-map; - }; - - pil_camera_mem: pil-camera@95200000 { - reg = <0x0 0x95200000 0x0 0x500000>; - no-map; - }; - - pil_adsp_mem: pil-adsp@95c00000 { - reg = <0x0 0x95c00000 0x0 0x1e00000>; - no-map; - }; - - pil_gdsp0_mem: pil-gdsp0@97b00000 { - reg = <0x0 0x97b00000 0x0 0x1e00000>; - no-map; - }; - - pil_gdsp1_mem: pil-gdsp1@99900000 { - reg = <0x0 0x99900000 0x0 0x1e00000>; - no-map; - }; - - pil_cdsp0_mem: pil-cdsp0@9b800000 { - reg = <0x0 0x9b800000 0x0 0x1e00000>; - no-map; - }; - - pil_gpu_mem: pil-gpu@9d600000 { - reg = <0x0 0x9d600000 0x0 0x2000>; - no-map; - }; - - pil_cdsp1_mem: pil-cdsp1@9d700000 { - reg = <0x0 0x9d700000 0x0 0x1e00000>; - no-map; - }; - - pil_cvp_mem: pil-cvp@9f500000 { - reg = <0x0 0x9f500000 0x0 0x700000>; - no-map; - }; - - pil_video_mem: pil-video@9fc00000 { - reg = <0x0 0x9fc00000 0x0 0x700000>; - no-map; - }; - - audio_mdf_mem: audio-mdf-region@ae000000 { - reg = <0x0 0xae000000 0x0 0x1000000>; - no-map; - }; - - hyptz_reserved_mem: hyptz-reserved@beb00000 { - reg = <0x0 0xbeb00000 0x0 0x11500000>; - no-map; - }; - - trusted_apps_mem: trusted-apps@d1900000 { - reg = <0x0 0xd1900000 0x0 0x3800000>; - no-map; - }; - }; - - firmware { - scm { - memory-region = <&tz_ffi_mem>; - }; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts deleted file mode 100644 index b25f0b2c9410..000000000000 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride-r3.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2023, Linaro Limited - */ - -/dts-v1/; - -#include "lemans-auto.dtsi" - -#include "lemans-pmics.dtsi" -#include "lemans-ride-common.dtsi" -#include "lemans-ride-ethernet-aqr115c.dtsi" - -/ { - model = "Qualcomm SA8775P Ride Rev3"; - compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p"; -}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts deleted file mode 100644 index 2d9028cd60be..000000000000 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2023, Linaro Limited - */ - -/dts-v1/; - -#include "lemans-auto.dtsi" - -#include "lemans-pmics.dtsi" -#include "lemans-ride-common.dtsi" -#include "lemans-ride-ethernet-88ea1512.dtsi" - -/ { - model = "Qualcomm SA8775P Ride"; - compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; -}; From d4d10c9bc434018a6b960eca238076633d375fe3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 17 May 2026 17:56:07 +0300 Subject: [PATCH 120/864] arm64: dts: qcom: sdm845: consolidate IPA properties Move generic IPA-related properties to the base DTSI file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-1-3c3764c1b4a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 3 --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++ arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 2 -- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 2 -- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 3 +-- 11 files changed, 4 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index e0c3566761bf..5ac2e058827c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -472,9 +472,6 @@ &gpu { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 091568642faa..97c79b51ff42 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -428,8 +428,6 @@ &i2c10 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index a6c2519a418d..90136a9b7ea3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -551,8 +551,6 @@ rmi4_f12: rmi4-f12@12 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/OnePlus/enchilada/ipa_fws.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 0d915ecb0444..a404a23086d4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -913,8 +913,6 @@ &mss_pil { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/Samsung/starqltechn/ipa_fws.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index f21b914f22b5..e31c784eff3d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -530,8 +530,6 @@ audio-codec@34 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/SHIFT/axolotl/ipa_fws.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 54e58ca04693..cc14d9fa3b05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -285,8 +285,6 @@ &ibb { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/Xiaomi/beryllium/ipa_fws.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index a44d6e776c82..96d4f7496f2f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -409,8 +409,6 @@ &ibb { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm845/Xiaomi/polaris/ipa_fws.mbn"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 4ae8627d6dbc..13b85624c186 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2780,6 +2780,9 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + sram = <&ipa_modem_tables>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index f04865381870..e38b768d16a1 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -565,8 +565,6 @@ panel_in_edp: endpoint { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm850/HUAWEI/AL09/ipa_fws.elf"; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index e41200839dbe..981074a40e38 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -584,8 +584,6 @@ ecsh: hid@5c { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm850/LENOVO/81JL/ipa_fws.elf"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index a676d3ea01b9..1dab0582eae6 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -384,9 +384,8 @@ digitizer@9 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sdm850/samsung/w737/ipa_fws.elf"; + status = "okay"; }; From dc88d56f27e02936e3a2dd2014f63bf1cc03ad1b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 17 May 2026 17:56:08 +0300 Subject: [PATCH 121/864] arm64: dts: qcom: sm6350: consolidate IPA properties Move generic IPA-related properties to the base DTSI file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-2-3c3764c1b4a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 3 +++ arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 3 +-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d6adf68563cb..5d2c1d4977b4 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1307,6 +1307,9 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&pil_ipa_fw_mem>; + sram = <&ipa_modem_tables>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 23f950067a08..d959ee541d37 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -711,9 +711,8 @@ vreg_l7p: ldo7 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&pil_ipa_fw_mem>; firmware-name = "qcom/sm7225/fairphone4/ipa_fws.mbn"; + status = "okay"; }; From c07c36059723f78b83753904ef65c77898950b28 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 17 May 2026 17:56:09 +0300 Subject: [PATCH 122/864] arm64: dts: qcom: sm8350: consolidate IPA properties Move generic IPA-related properties to the base DTSI file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-3-3c3764c1b4a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 5 ++--- arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 2 -- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 2 -- arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 3 +-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 +++ 5 files changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 5f975d009465..6d3f9c73a2cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -923,8 +923,7 @@ irq-pins { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&pil_ipa_fw_mem>; - status = "okay"; firmware-name = "qcom/sm8350/ipa_fws.mbn"; + + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 3bd5e57cbcda..6b10464e8774 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -290,8 +290,6 @@ &i2c11 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&pil_ipa_fw_mem>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index 8bee57f3b25a..b25f223d6190 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -378,7 +378,5 @@ &usb_2_qmpphy { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&pil_ipa_fw_mem>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 7ae1eb0a7cce..ba862b4f9890 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -553,9 +553,8 @@ &i2c17 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&pil_ipa_fw_mem>; firmware-name = "qcom/sm8350/Sony/sagami/ipa_fws.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c830953156ec..abb4d46e2594 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1866,6 +1866,9 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&pil_ipa_fw_mem>; + sram = <&ipa_modem_tables>; status = "disabled"; From e9824e30e64044993e0fc4d3abddd7ec1e40db6d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 17 May 2026 17:56:11 +0300 Subject: [PATCH 123/864] arm64: dts: qcom: sm8650: consolidate IPA properties Move generic IPA-related properties to the base DTSI file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-5-3c3764c1b4a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 3 +-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 3 +-- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 +++ 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index eabc828c05b4..80bd2437f154 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -888,9 +888,8 @@ lt9611_out: endpoint { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sm8650/ipa_fws.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index a3982ae22929..a28d70c85fa3 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -861,9 +861,8 @@ redriver_ss_in: endpoint { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sm8650/ipa_fws.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 160ead25ecf7..74381ac363ee 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4397,6 +4397,9 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + sram = <&ipa_modem_tables>; status = "disabled"; From 2279111cca4b1371138168f08990b10f3b8c6375 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 17 May 2026 17:56:12 +0300 Subject: [PATCH 124/864] arm64: dts: qcom: kodiak: consolidate IPA properties Move generic IPA-related properties to the base DTSI file. The herobrine has special software configuration, so delete the memory-region property which wasn't set for it beforehand. Also delete the property for several IoT devices, which don't enable IPA memory at this point (and don't seem to have IPA supported by the modem firmware). Co-developed-by: Stanislav Zaikin Signed-off-by: Stanislav Zaikin Signed-off-by: Dmitry Baryshkov Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-6-3c3764c1b4a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 3 +++ arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 3 +-- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 -- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 3 +-- arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++++ arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++++ arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 4 ++++ arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts | 3 --- arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts | 2 -- 10 files changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index fa540d8c2615..781be681b9a3 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2646,6 +2646,9 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + sram = <&ipa_modem_tables>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 04cb9230d29f..aa7c525237b9 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -913,9 +913,8 @@ &i2c9 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/qcm6490/fairphone5/ipa_fws.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index bf18c4852081..fef9fb51642d 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -501,8 +501,6 @@ &i2c1 { &ipa { firmware-name = "qcom/qcm6490/particle/tachyon/ipa_fws.mbn"; - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 797f37596bf1..1398a4dfb037 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -553,9 +553,8 @@ &i2c13 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/qcm6490/SHIFT/otter/ipa_fws.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index bb5a42b038f1..6c1a73f18ec1 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -504,6 +504,10 @@ &i2c13 { status = "okay"; }; +&ipa { + /delete-property/ memory-region; +}; + &lpass_audiocc { compatible = "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index a5ad796cb65d..7de63ee37a84 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -653,6 +653,10 @@ redriver_usb_con_sbu: endpoint { }; }; +&ipa { + /delete-property/ memory-region; +}; + &mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index f47efca42d48..e701cc39210f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -774,6 +774,10 @@ lt9611_out: endpoint { }; }; +&ipa { + /delete-property/ memory-region; +}; + &lpass_audiocc { compatible = "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi index b721a8546800..ac89724ee099 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-lte-sku.dtsi @@ -22,7 +22,9 @@ mdata_mem: mpss-metadata { }; &ipa { + /delete-property/ memory-region; qcom,gsi-loader = "modem"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts index 3c836e196b19..d94571c05a59 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai.dts @@ -727,9 +727,6 @@ fsa4480_sbu_mux: endpoint { &ipa { firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn"; - memory-region = <&ipa_fw_mem>; - - qcom,gsi-loader = "self"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts index cb59c122f6f6..7db9ae1c3cef 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-nothing-spacewar.dts @@ -971,8 +971,6 @@ nfc@28 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; firmware-name = "qcom/sm7325/nothing/spacewar/ipa_fws.mbn"; status = "okay"; From 273cec70d297885181977ad37a2192f73bfe373d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 17 May 2026 17:56:13 +0300 Subject: [PATCH 125/864] ARM: dts: qcom: sdx55: consolidate IPA properties Move generic IPA-related properties to the base DTSI file. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Link: https://lore.kernel.org/r/20260517-ipa-loader-v1-7-3c3764c1b4a3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 -- arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts | 2 -- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 3 +++ 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts index 082f7ed1a01f..d23b8ec08af4 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts @@ -237,8 +237,6 @@ &blsp1_uart3 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts index e336a15b45c4..1e80ddad591e 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-telit-fn980-tlb.dts @@ -237,8 +237,6 @@ &blsp1_uart3 { }; &ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 05b79281df57..e9982c46bc2f 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -510,6 +510,9 @@ ipa: ipa@1e40000 { qcom,smem-state-names = "ipa-clock-enabled-valid", "ipa-clock-enabled"; + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + status = "disabled"; }; From 9f41cb88adfe769a87762eff1a7d0d8a2df42560 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 7 May 2026 22:34:09 -0700 Subject: [PATCH 126/864] arm64: dts: qcom: Add gpio device node for pm8010 Add gpio device nodes in pm8010*.dtsi files for any consumers to be able to use the GPIOs. Signed-off-by: Fenglin Wu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-pm8010_gpio-v1-3-3bce9da8d2ba@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/pm8010-kaanapali.dtsi | 20 +++++++++++++++++++ arch/arm64/boot/dts/qcom/pm8010.dtsi | 20 +++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi index bfc58a6589d3..6a8f1accd260 100644 --- a/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8010-kaanapali.dtsi @@ -75,6 +75,16 @@ pm8010_m_e1_temp_alarm: temp-alarm@2400 { interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pm8010_m_e1_gpios: gpio@c000 { + compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8010_m_e1_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pm8010_n_e1: pmic@d { @@ -89,5 +99,15 @@ pm8010_n_e1_temp_alarm: temp-alarm@2400 { interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pm8010_n_e1_gpios: gpio@c000 { + compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8010_n_e1_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8010.dtsi b/arch/arm64/boot/dts/qcom/pm8010.dtsi index ef330194946b..031fcf38f3d1 100644 --- a/arch/arm64/boot/dts/qcom/pm8010.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8010.dtsi @@ -64,6 +64,16 @@ pm8010_m_temp_alarm: temp-alarm@2400 { interrupts = <0xc 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pm8010_m_gpios: gpio@c000 { + compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8010_m_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pm8010_n: pmic@d { @@ -78,5 +88,15 @@ pm8010_n_temp_alarm: temp-alarm@2400 { interrupts = <0xd 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pm8010_n_gpios: gpio@c000 { + compatible = "qcom,pm8010-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm8010_n_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; }; From d9b05c984304740699d7e47625d5e093b014c76b Mon Sep 17 00:00:00 2001 From: Dipa Mantre Date: Wed, 15 Apr 2026 16:27:08 +0530 Subject: [PATCH 127/864] arm64: dts: qcom: kaanapali: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Dipa Mantre Reviewed-by: Konrad Dybcio Reviewed-by: Gaurav Kohli Link: https://lore.kernel.org/r/20260415-cpufreq_kaanapali-v1-1-1fa94105d5c2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 8f8125f1de34..ae3172be9433 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -48,6 +48,7 @@ cpu0: cpu@0 { power-domains = <&cpu_pd0>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -65,6 +66,7 @@ cpu1: cpu@100 { power-domains = <&cpu_pd1>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -76,6 +78,7 @@ cpu2: cpu@200 { power-domains = <&cpu_pd2>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu3: cpu@300 { @@ -87,6 +90,7 @@ cpu3: cpu@300 { power-domains = <&cpu_pd3>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu4: cpu@400 { @@ -98,6 +102,7 @@ cpu4: cpu@400 { power-domains = <&cpu_pd4>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu5: cpu@500 { @@ -109,6 +114,7 @@ cpu5: cpu@500 { power-domains = <&cpu_pd5>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 0>; + #cooling-cells = <2>; }; cpu6: cpu@10000 { @@ -120,6 +126,7 @@ cpu6: cpu@10000 { power-domains = <&cpu_pd6>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 1>; + #cooling-cells = <2>; l2_1: l2-cache { compatible = "cache"; @@ -137,6 +144,7 @@ cpu7: cpu@10100 { power-domains = <&cpu_pd7>; power-domain-names = "psci"; clocks = <&pdp_scmi_perf 1>; + #cooling-cells = <2>; }; cpu-map { From f9665fc0681c1a0edc03be9900ba3f318fe3c5bd Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Fri, 22 May 2026 10:00:26 +0000 Subject: [PATCH 128/864] arm64: dts: qcom: Add Display Port audio on Arduino Monza Add support for Display port Audio on Arduino VENTUNO-Q board. Signed-off-by: Srinivas Kandagatla CC: Loic Poulain Reviewed-by: Konrad Dybcio Tested-by: Loic Poulain Link: https://lore.kernel.org/r/20260522100026.94760-1-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/monaco-arduino-monza.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 95e78ed5da1f..8b3ed73feb6e 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -118,6 +118,22 @@ platform { sound-dai = <&q6apm>; }; }; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; }; vdc_3v3: regulator-3v3 { From 34a4ec6910e68ce06eb7201fa36778ca59a1e510 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 28 May 2026 14:03:43 +0200 Subject: [PATCH 129/864] arm64: dts: qcom: talos: Fix GMU unit address Correct unit address of GMU node to match 'reg' property and fix dtc W=1 warnings like: talos.dtsi:2020.20-2055.5: Warning (simple_bus_reg): /soc@0/gmu@506a000: simple-bus unit address format error, expected "506d000" Fixes: 8de397a5618a ("arm64: dts: qcom: talos: Add gpu and rgmu nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260528120342.46343-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index fb1bbc51bb8a..70df5db19e9a 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2017,7 +2017,7 @@ opp-435000000 { }; }; - gmu: gmu@506a000 { + gmu: gmu@506d000 { compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; reg = <0x0 0x0506d000 0x0 0x2c000>; From 8d52cc232a3c951492a7b90c4172b778d6de1568 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:35:59 +0800 Subject: [PATCH 130/864] arm64: dts: qcom: lemans: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the lemans device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-1-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 353a6e6fd3ac..a10322c5bc35 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3197,6 +3197,7 @@ tpdm@4003000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dcc"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3256,6 +3257,7 @@ tpdm@400f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3724,6 +3726,7 @@ tpdm@4b09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3744,6 +3747,7 @@ tpdm@4b0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3764,6 +3768,7 @@ tpdm@4b0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3784,6 +3789,7 @@ tpdm@4b0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3804,6 +3810,7 @@ tpdm@4b0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3824,6 +3831,7 @@ aoss_cti: cti@4b13000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_aoss"; }; funnel@4b83000 { @@ -4145,6 +4153,7 @@ tpdm@6860000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_actpm"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -4165,6 +4174,7 @@ tpdm@6861000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_apss"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4247,6 +4257,7 @@ tpdm@68a0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_silver"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -4267,6 +4278,7 @@ tpdm@68b0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_gold"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -4287,6 +4299,7 @@ tpdm@68c0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_ext"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -9179,6 +9192,7 @@ arch_timer: timer { turing-llm-tpdm { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_cdsp_llm_0"; qcom,cmb-element-bits = <32>; From 422f5eff44d89367b700235bad829d1430f798a2 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:00 +0800 Subject: [PATCH 131/864] arm64: dts: qcom: talos: Add label properties to CoreSight devices Add label properties to CTI and TPDM nodes in the talos device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-2-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 59 +++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 70df5db19e9a..e506a16c9070 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -2242,6 +2242,7 @@ cti@6010000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss"; }; cti@6011000 { @@ -2250,6 +2251,7 @@ cti@6011000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_1"; }; cti@6012000 { @@ -2258,6 +2260,7 @@ cti@6012000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_2"; }; cti@6013000 { @@ -2266,6 +2269,7 @@ cti@6013000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_3"; }; cti@6014000 { @@ -2274,6 +2278,7 @@ cti@6014000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_4"; }; cti@6015000 { @@ -2282,6 +2287,7 @@ cti@6015000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_5"; }; cti@6016000 { @@ -2290,6 +2296,7 @@ cti@6016000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_6"; }; cti@6017000 { @@ -2298,6 +2305,7 @@ cti@6017000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_7"; }; cti@6018000 { @@ -2306,6 +2314,7 @@ cti@6018000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_8"; }; cti@6019000 { @@ -2314,6 +2323,7 @@ cti@6019000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_9"; }; cti@601a000 { @@ -2322,6 +2332,7 @@ cti@601a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_10"; }; cti@601b000 { @@ -2330,6 +2341,7 @@ cti@601b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_11"; }; cti@601c000 { @@ -2338,6 +2350,7 @@ cti@601c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_12"; }; cti@601d000 { @@ -2346,6 +2359,7 @@ cti@601d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_13"; }; cti@601e000 { @@ -2354,6 +2368,7 @@ cti@601e000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_14"; }; cti@601f000 { @@ -2362,6 +2377,7 @@ cti@601f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss_15"; }; funnel@6041000 { @@ -2594,6 +2610,7 @@ cti@683b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdsp6"; }; tpdm@6840000 { @@ -2602,6 +2619,7 @@ tpdm@6840000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_vsense"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -2622,6 +2640,7 @@ tpdm@684c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_prng"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -2641,6 +2660,7 @@ tpdm@6850000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pimem"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -2662,6 +2682,7 @@ tpdm@6860000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -2705,6 +2726,7 @@ cti@6867000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_cdsp"; }; tpdm@6870000 { @@ -2713,6 +2735,7 @@ tpdm@6870000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dcc"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -2733,6 +2756,7 @@ tpdm@699c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_wcss"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -2755,6 +2779,7 @@ tpdm@69c0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_monaq"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -2798,6 +2823,7 @@ tpdm@69d0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qm"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -2818,6 +2844,7 @@ tpdm@6a00000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ddr"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -2838,6 +2865,7 @@ cti@6a02000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_ddr_dl0"; }; cti@6a03000 { @@ -2846,6 +2874,7 @@ cti@6a03000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_ddr_dl0_1"; }; cti@6a10000 { @@ -2854,6 +2883,7 @@ cti@6a10000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_ddr_dl1"; }; cti@6a11000 { @@ -2862,6 +2892,7 @@ cti@6a11000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_ddr_dl1_1"; }; funnel@6a05000 { @@ -2932,6 +2963,7 @@ tpdm@6b02000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -2952,6 +2984,7 @@ tpdm@6b03000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -2972,6 +3005,7 @@ cti@6b04000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao"; }; cti@6b05000 { @@ -2980,6 +3014,7 @@ cti@6b05000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao_1"; }; cti@6b06000 { @@ -2988,6 +3023,7 @@ cti@6b06000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao_2"; }; cti@6b07000 { @@ -2996,6 +3032,7 @@ cti@6b07000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao_3"; }; funnel@6b08000 { @@ -3102,6 +3139,7 @@ cti@6b21000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_aop_m3"; }; tpdm@6b48000 { @@ -3110,6 +3148,7 @@ tpdm@6b48000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_west"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3129,6 +3168,7 @@ cti@6c13000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_titan"; /* Not all required clocks can be enabled from the OS */ status = "fail"; @@ -3140,6 +3180,7 @@ cti@6c20000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_venus"; status = "disabled"; }; @@ -3149,6 +3190,7 @@ tpdm@6c28000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_center"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3168,6 +3210,7 @@ cti@6c29000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_dlct"; }; cti@6c2a000 { @@ -3176,6 +3219,7 @@ cti@6c2a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_dlct_1"; }; cti@7020000 { @@ -3184,6 +3228,7 @@ cti@7020000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_2"; }; etm@7040000 { @@ -3212,6 +3257,7 @@ cti@7120000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_3"; }; etm@7140000 { @@ -3240,6 +3286,7 @@ cti@7220000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_4"; }; etm@7240000 { @@ -3268,6 +3315,7 @@ cti@7320000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_5"; }; etm@7340000 { @@ -3296,6 +3344,7 @@ cti@7420000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_6"; }; etm@7440000 { @@ -3324,6 +3373,7 @@ cti@7520000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_7"; }; etm@7540000 { @@ -3352,6 +3402,7 @@ cti@7620000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_8"; }; etm@7640000 { @@ -3380,6 +3431,7 @@ cti@7720000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_apb_9"; }; etm@7740000 { @@ -3554,6 +3606,7 @@ tpdm@7830000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_olc"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3597,6 +3650,7 @@ tpdm@7860000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_apss"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3640,6 +3694,7 @@ tpdm@78a0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_silver"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3659,6 +3714,7 @@ tpdm@78b0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_gold"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3726,6 +3782,7 @@ cti@78e0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss"; }; cti@78f0000 { @@ -3734,6 +3791,7 @@ cti@78f0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_1"; }; cti@7900000 { @@ -3742,6 +3800,7 @@ cti@7900000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss_2"; }; remoteproc_cdsp: remoteproc@8300000 { From 9ed9c973c6213bb4880fc44dffb266f0330586be Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:01 +0800 Subject: [PATCH 132/864] arm64: dts: qcom: monaco: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the monaco device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-3-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 29 ++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index e4c8466f941b..c1fb92135b3b 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3049,6 +3049,7 @@ tpdm@400f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3311,6 +3312,7 @@ tpdm@4841000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_prng"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3330,6 +3332,7 @@ tpdm@4850000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pimem"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3351,6 +3354,7 @@ tpdm@4860000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dl_ch_south"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3444,6 +3448,7 @@ tpdm@4980000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3487,6 +3492,7 @@ tpdm@4ac0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_mmnoc_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3559,6 +3565,7 @@ tpdm@4ad0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlct"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3811,6 +3818,7 @@ tpdm@4b09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3830,6 +3838,7 @@ tpdm@4b0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3849,6 +3858,7 @@ tpdm@4b0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3868,6 +3878,7 @@ tpdm@4b0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3887,6 +3898,7 @@ tpdm@4b0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3906,6 +3918,7 @@ cti@4b13000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_aoss"; }; tpdm@4b80000 { @@ -3914,6 +3927,7 @@ tpdm@4b80000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3981,6 +3995,7 @@ cti@4b8b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_cdsp_1"; }; tpdm@4c40000 { @@ -3989,6 +4004,7 @@ tpdm@4c40000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_gpdsp_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4082,6 +4098,7 @@ tpdm@4c50000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dl_south"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4154,6 +4171,7 @@ tpdm@4e00000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ddr"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4244,6 +4262,7 @@ tpdm@4e10000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ddr_ch0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4287,6 +4306,7 @@ tpdm@4e20000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ddr_ch1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4612,6 +4632,7 @@ cti@682b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_apss"; }; tpdm@6860000 { @@ -4620,6 +4641,7 @@ tpdm@6860000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_actpm"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -4639,6 +4661,7 @@ tpdm@6861000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_apss"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4719,6 +4742,7 @@ tpdm@68a0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_gold"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -4738,6 +4762,7 @@ tpdm@68b0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llm_silver"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -4757,6 +4782,7 @@ tpdm@68c0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ext_dsb"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4776,6 +4802,7 @@ cti@68e0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_llm_gold"; }; cti@68f0000 { @@ -4784,6 +4811,7 @@ cti@68f0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_llm_silver"; }; cti@6900000 { @@ -4792,6 +4820,7 @@ cti@6900000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_ext_dsb"; }; sdhc_1: mmc@87c4000 { From d1a21366e880051e453e99aec217dea3e1ffa441 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:02 +0800 Subject: [PATCH 133/864] arm64: dts: qcom: kodiak: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the kodiak device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-4-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 781be681b9a3..90e50c245c0c 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -3520,6 +3520,7 @@ tpdm@600f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -3539,6 +3540,7 @@ cti@6010000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_qdss"; }; funnel@6041000 { @@ -3688,6 +3690,7 @@ cti@6b00000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao"; }; cti@6b01000 { @@ -3696,6 +3699,7 @@ cti@6b01000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao_1"; }; cti@6b02000 { @@ -3704,6 +3708,7 @@ cti@6b02000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao_2"; }; cti@6b03000 { @@ -3712,6 +3717,7 @@ cti@6b03000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_swao_3"; }; funnel@6b04000 { @@ -3866,6 +3872,7 @@ tpdm@6b09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3885,6 +3892,7 @@ tpdm@6b0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3904,6 +3912,7 @@ tpdm@6b0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3923,6 +3932,7 @@ tpdm@6b0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -3942,6 +3952,7 @@ tpdm@6b0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -3961,6 +3972,7 @@ cti@6b11000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_aoss"; }; etm@7040000 { From 39a2bf8662412df24ec00378ccdfe667d0529002 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:03 +0800 Subject: [PATCH 134/864] arm64: dts: qcom: kaanapali: Add label properties to CoreSight devices Add label properties to TPDM nodes in the kaanapali device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-5-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index ae3172be9433..2c00c70d67b4 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -4372,6 +4372,7 @@ tpdm@10003000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dcc"; qcom,cmb-element-bits = <32>; @@ -4427,6 +4428,7 @@ tpdm@1000f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; @@ -4490,6 +4492,7 @@ tpdm@11000000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_modem_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4578,6 +4581,7 @@ tpdm@1102c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_gcc"; qcom,dsb-msrs-num = <32>; @@ -4596,6 +4600,7 @@ tpdm@11180000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4615,6 +4620,7 @@ tpdm@11183000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_cmsr1"; qcom,dsb-element-bits = <32>; qcom,cmb-element-bits = <32>; @@ -4634,6 +4640,7 @@ tpdm@11184000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_cmsr2"; qcom,dsb-element-bits = <32>; qcom,cmb-element-bits = <32>; @@ -4653,6 +4660,7 @@ tpdm@11185000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_dpm1"; qcom,cmb-element-bits = <64>; @@ -4671,6 +4679,7 @@ tpdm@11186000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_dpm2"; qcom,cmb-element-bits = <64>; @@ -4790,6 +4799,7 @@ tpdm@111a3000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pmu"; qcom,dsb-msrs-num = <32>; @@ -4808,6 +4818,7 @@ tpdm@111a4000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qrng"; out-ports { port { @@ -4824,6 +4835,7 @@ tpdm@111a5000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlmm"; qcom,dsb-msrs-num = <32>; @@ -4842,6 +4854,7 @@ tpdm@111a6000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_north_dsb"; qcom,dsb-msrs-num = <32>; @@ -4860,6 +4873,7 @@ tpdm@111a7000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_south_dsb"; qcom,dsb-msrs-num = <32>; @@ -4878,6 +4892,7 @@ tpdm@111a8000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_cx"; out-ports { port { @@ -4894,6 +4909,7 @@ tpdm@111a9000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_mxa"; out-ports { port { @@ -4910,6 +4926,7 @@ tpdm@111aa000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_mxc"; out-ports { port { @@ -4926,6 +4943,7 @@ tpdm@111ab000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc_cmb0"; out-ports { port { @@ -4942,6 +4960,7 @@ tpdm@111ac000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc_cmb1"; out-ports { port { @@ -4958,6 +4977,7 @@ tpdm@111ad000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc_cmb2"; out-ports { port { @@ -4974,6 +4994,7 @@ tpdm@111ae000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc_cmb3"; out-ports { port { @@ -4990,6 +5011,7 @@ tpdm@111af000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc_cmb4"; out-ports { port { @@ -5006,6 +5028,7 @@ tpdm@111b3000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pcie_rscc"; out-ports { port { @@ -5195,6 +5218,7 @@ tpdm@111d0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qm"; out-ports { port { @@ -5211,6 +5235,7 @@ tpdm@11303000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_4"; qcom,cmb-element-bits = <64>; @@ -5352,6 +5377,7 @@ tpdm@11309000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; @@ -5370,6 +5396,7 @@ tpdm@1130a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; @@ -5388,6 +5415,7 @@ tpdm@1130b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; @@ -5406,6 +5434,7 @@ tpdm@1130c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; @@ -5424,6 +5453,7 @@ tpdm@1130d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -5443,6 +5473,7 @@ tpdm@11422000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipa"; qcom,dsb-msrs-num = <32>; @@ -7129,6 +7160,7 @@ timer { tpdm-cdsp-llm { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_cdsp_llm"; qcom,cmb-element-bits = <32>; out-ports { @@ -7142,6 +7174,7 @@ tpdm_cdsp_llm_out: endpoint { tpdm-cdsp-llm2 { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_cdsp_llm2"; qcom,cmb-element-bits = <32>; out-ports { @@ -7155,6 +7188,7 @@ tpdm_cdsp_llm2_out: endpoint { tpdm-modem1 { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_modem_1"; qcom,cmb-element-bits = <32>; out-ports { @@ -7168,6 +7202,7 @@ tpdm_modem1_out: endpoint { tpdm-modem2 { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_modem_2"; qcom,cmb-element-bits = <64>; out-ports { From 9dd195e59a479ff6d605935d78e9e9bc0877bc02 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:04 +0800 Subject: [PATCH 135/864] arm64: dts: qcom: sm8750: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the sm8750 device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-6-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 6bcda7c38dbf..802c2cca477c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4161,6 +4161,7 @@ tpdm@1000f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -4225,6 +4226,7 @@ tpdm@10800000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_modem_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4305,6 +4307,7 @@ cti@1080b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_mss_qdsp6"; }; tpdm@1082c000 { @@ -4313,6 +4316,7 @@ tpdm@1082c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_gcc"; qcom,dsb-msrs-num = <32>; @@ -4331,6 +4335,7 @@ tpdm@10841000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_prng"; qcom,cmb-msrs-num = <32>; @@ -4349,6 +4354,7 @@ tpdm@1084e000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_mm_bcv"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -4368,6 +4374,7 @@ tpdm@1084f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_mm_lmh"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -4387,6 +4394,7 @@ tpdm@10850000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_mm_dpm"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -4451,6 +4459,7 @@ tpdm@10980000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -4539,6 +4548,7 @@ cti@1098b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_cdsp_qdsp"; }; tpdm@109a3000 { @@ -4547,6 +4557,7 @@ tpdm@109a3000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pmu"; qcom,cmb-msrs-num = <32>; qcom,dsb-msrs-num = <32>; @@ -4566,6 +4577,7 @@ tpdm@109a4000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc"; qcom,cmb-msrs-num = <32>; @@ -4584,6 +4596,7 @@ tpdm@109a5000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlmm"; qcom,dsb-msrs-num = <32>; @@ -4602,6 +4615,7 @@ tpdm@109a6000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_north_dsb"; qcom,dsb-msrs-num = <32>; @@ -4620,6 +4634,7 @@ tpdm@109a7000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_south_dsb"; qcom,dsb-msrs-num = <32>; @@ -4638,6 +4653,7 @@ tpdm@109a8000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_cmb0"; qcom,cmb-msrs-num = <32>; @@ -4656,6 +4672,7 @@ tpdm@109a9000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_cmb1"; qcom,cmb-msrs-num = <32>; @@ -4674,6 +4691,7 @@ tpdm@109aa000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_cmb2"; qcom,cmb-msrs-num = <32>; @@ -4825,6 +4843,7 @@ tpdm@109d0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qm"; qcom,dsb-msrs-num = <32>; @@ -4958,6 +4977,7 @@ tpdm@10b09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -4977,6 +4997,7 @@ tpdm@10b0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -4996,6 +5017,7 @@ tpdm@10b0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -5015,6 +5037,7 @@ tpdm@10b0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -5034,6 +5057,7 @@ tpdm@10b0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -6851,6 +6875,7 @@ timer { tpdm-cdsp-llm { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_cdsp_llm"; qcom,cmb-element-bits = <32>; out-ports { @@ -6864,6 +6889,7 @@ tpdm_cdsp_llm_out: endpoint { tpdm-cdsp-llm2 { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_cdsp_llm2"; qcom,cmb-element-bits = <32>; out-ports { @@ -6877,6 +6903,7 @@ tpdm_cdsp_llm2_out: endpoint { tpdm-modem1 { compatible = "qcom,coresight-static-tpdm"; + label = "tpdm_modem_1"; qcom,dsb-element-bits = <32>; out-ports { From 310a5d6a7b65ee161c91bf1cd3a3bf19074275af Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Apr 2026 19:36:05 +0800 Subject: [PATCH 136/864] arm64: dts: qcom: hamoa: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the hamoa device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20260414-add-label-to-coresight-device-v2-7-5017d07358f2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 82b1d363d2de..054f9c4ad192 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -6780,6 +6780,7 @@ tpdm@10003000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_prng"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -6837,6 +6838,7 @@ tpdm@1000f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dcc"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -6975,6 +6977,7 @@ tpdm@10800000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_tmess_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -6994,6 +6997,7 @@ tpdm@1082c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dl_south_0"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7013,6 +7017,7 @@ tpdm@10841000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -7032,6 +7037,7 @@ tpdm@10844000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qm"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7075,6 +7081,7 @@ cti@1098b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_cdsp_cscti"; }; tpdm@109d0000 { @@ -7083,6 +7090,7 @@ tpdm@109d0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_lpass"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7103,6 +7111,7 @@ tpdm@10ac0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_gcc"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7123,6 +7132,7 @@ tpdm@10ac1000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rpdm_mxa"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7357,6 +7367,7 @@ tpdm@10b09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dl_south_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7376,6 +7387,7 @@ tpdm@10b0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7395,6 +7407,7 @@ tpdm@10b0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7414,6 +7427,7 @@ tpdm@10b0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7433,6 +7447,7 @@ tpdm@10b0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlct"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7452,6 +7467,7 @@ tpdm@10b20000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_dlmm"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7522,6 +7538,7 @@ tpdm@10c08000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_1"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7570,6 +7587,7 @@ tpdm@10c28000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ddr_lpi"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -7589,6 +7607,7 @@ tpdm@10c29000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7722,6 +7741,7 @@ tpdm@10c38000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7741,6 +7761,7 @@ tpdm@10c39000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_mx"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7837,6 +7858,7 @@ tpdm@10cc1000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7941,6 +7963,7 @@ tpdm@10d08000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_7"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -7960,6 +7983,7 @@ tpdm@10d09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_6"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -7979,6 +8003,7 @@ tpdm@10d0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_5"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -7998,6 +8023,7 @@ tpdm@10d0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_4"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -8017,6 +8043,7 @@ tpdm@10d0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_3"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -8036,6 +8063,7 @@ tpdm@10d0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_0"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -8055,6 +8083,7 @@ tpdm@10d0e000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_1"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -8074,6 +8103,7 @@ tpdm@10d0f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_llcc_2"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; From d529495c991a2b7d07c01622e8b3cb5ec066acee Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 27 Jun 2026 19:50:15 +0200 Subject: [PATCH 137/864] dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850 Add SoC ID for Qualcomm Snapdragon SDM850. Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260627-sda850-v2-1-44bf46ade42e@ixit.cz Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 1af73c0ad41c..2cf433f61d5e 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -184,6 +184,7 @@ #define QCOM_ID_IPQ8078 344 #define QCOM_ID_SDM636 345 #define QCOM_ID_SDA636 346 +#define QCOM_ID_SDM850 348 #define QCOM_ID_SDM632 349 #define QCOM_ID_SDA632 350 #define QCOM_ID_SDA450 351 From 8610507901a0cd17640596b1e19d3a7b10cac1b3 Mon Sep 17 00:00:00 2001 From: Xin Xu Date: Thu, 25 Jun 2026 19:50:48 +0800 Subject: [PATCH 138/864] arm64: dts: qcom: sm8250-xiaomi-elish: Add pm8008 PMIC Add the pm8008 PMIC node on i2c15 with seven LDOs, using GPIO84 as interrupt and GPIO76 as reset. Signed-off-by: Xin Xu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/tencent_D4AB219A942591742C3A6DA4DFB0EBA49505@qq.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-xiaomi-elish-common.dtsi | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 51b57c697a75..05c366eaeff1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -599,6 +599,82 @@ fuel-gauge@55 { }; }; +&i2c15 { + clock-frequency = <400000>; + + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 76 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s8c_1p35>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_bob>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_default>; + pinctrl-names = "default"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + }; + }; + }; +}; + &mdss { status = "okay"; }; @@ -801,6 +877,20 @@ bt_en_state: bt-default-state { bias-pull-up; }; + pm8008_int_default: pm8008-int-default-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pm8008_reset_default: pm8008-reset-default-state { + pins = "gpio76"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + wlan_en_state: wlan-default-state { pins = "gpio20"; function = "gpio"; From 9f1d0a996df2a68f97002e38d8a6371607ab13ca Mon Sep 17 00:00:00 2001 From: Xin Xu Date: Thu, 25 Jun 2026 20:05:36 +0800 Subject: [PATCH 139/864] arm64: dts: qcom: sm8250: Add cam_mclk3_default pinctrl Add a default pin configuration for CAM_MCLK3 (GPIO97), which is used as a master clock for camera sensors on SM8250 boards. Signed-off-by: Xin Xu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/tencent_47473BB31C9142449F8C7C1BE69D9071510A@qq.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7076720413ab..05e765616112 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5165,6 +5165,13 @@ mclk-pins { }; }; + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio97"; + function = "cam_mclk"; + drive-strength = <4>; + bias-disable; + }; + cci0_default: cci0-default-state { cci0_i2c0_default: cci0-i2c0-default-pins { /* SDA, SCL */ From e221d444dc0bb4b0f244038b7655419498643667 Mon Sep 17 00:00:00 2001 From: Xin Xu Date: Thu, 25 Jun 2026 20:08:14 +0800 Subject: [PATCH 140/864] arm64: dts: qcom: sm8250-xiaomi-elish: Add ov8856 front camera Add the ov8856 front camera, connected on CCI1 to CSIPHY4 and powered by pm8008 LDOs and other supplies. Signed-off-by: Xin Xu Link: https://lore.kernel.org/r/tencent_A89D858754397A68C4C830EA0487CB255A05@qq.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-xiaomi-elish-common.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 05c366eaeff1..19aff83ecf7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -531,6 +532,61 @@ vreg_l7f_1p8: ldo7 { }; }; +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + + ports { + port@4 { + csiphy4_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1>; + bus-type = ; + remote-endpoint = <&ov8856_front_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + camera_front: camera@10 { + compatible = "ovti,ov8856"; + reg = <0x10>; + + avdd-supply = <&vreg_l5p>; + dovdd-supply = <&vreg_l1c_1p8>; + dvdd-supply = <&vreg_l1p>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "xvclk"; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <19200000>; + + reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&cam_mclk3_default &camera_front_active>; + pinctrl-names = "default"; + + orientation = <0>; /* Front facing */ + rotation = <270>; + + port { + ov8856_front_ep: endpoint { + data-lanes = <1 2>; + link-frequencies = /bits/ 64 + <720000000 360000000>; + remote-endpoint = <&csiphy4_ep>; + }; + }; + }; +}; + &cdsp { firmware-name = "qcom/sm8250/xiaomi/elish/cdsp.mbn"; status = "okay"; @@ -891,6 +947,13 @@ pm8008_reset_default: pm8008-reset-default-state { bias-pull-up; }; + camera_front_active: camera-front-active-state { + pins = "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wlan_en_state: wlan-default-state { pins = "gpio20"; function = "gpio"; From cc8748ed4da16233d5b3f27e86a412a991645aed Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 23 May 2026 11:45:35 +0200 Subject: [PATCH 141/864] arm64: dts: qcom: sdm845-oneplus: Update compatible to include model We know the driver is reporting s3706b, introduce the compatible so we can more easily introduce quirks for weird touchscreen replacements in followup series. Reviewed-by: Konrad Dybcio Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20260523-synaptics-rmi4-dt-v2-2-0645122babdc@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 90136a9b7ea3..439779f308e3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -520,7 +520,7 @@ &i2c12 { clock-frequency = <400000>; synaptics-rmi4-i2c@20 { - compatible = "syna,rmi4-i2c"; + compatible = "syna,rmi4-s3706b", "syna,rmi4-i2c"; reg = <0x20>; #address-cells = <1>; #size-cells = <0>; From 2f57d03ea7b78fe24fe6f965d65fe1ff9eac60ed Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 3 Jul 2026 00:15:11 +0530 Subject: [PATCH 142/864] arm64: dts: qcom: sm8750: Add wakeup-source property to usb controller USB controller on SM8750 can be configured as a wakeup capable device. Add wakeup-source property indicating the same. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260702184511.442129-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 802c2cca477c..900dac6bf6d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2893,6 +2893,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, dma-coherent; usb-role-switch; + wakeup-source; status = "disabled"; From c09cd72be7fdfc348ceecfe414ff9698bc3561f3 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 3 Jul 2026 00:14:40 +0530 Subject: [PATCH 143/864] arm64: dts: qcom: kaanapali: Add missing properties to usb controller USB controller on Kaanapali SoC is capable of switching role betwen device and host and also is a wakeup capable device. Add usb-role-switch and wakeup-source properties to the controller node accordingly. Signed-off-by: Krishna Kurapati Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260702184440.442037-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 2c00c70d67b4..8bd029698270 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -3570,6 +3570,9 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, tx-fifo-resize; dma-coherent; + usb-role-switch; + wakeup-source; + status = "disabled"; ports { From 39ea7cb4019245ce488ea547b3ec68a3d7d57aef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:19:14 +0200 Subject: [PATCH 144/864] ARM: dts: intel: arria10: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index ba4c0ca89788..3c684f1278bf 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -447,7 +447,7 @@ gmac0: ethernet@ff800000 { gmac1: ethernet@ff802000 { compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x48 8>; - reg = <0xff802000 0x2000>; + reg = <0xff802000 0x2000>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; /* Filled in by bootloader */ From b99bc64c0fd91d0dea4147919184b7c8db9c615b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:35 +0200 Subject: [PATCH 145/864] ARM: dts: nxp: ls: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts index 38281b904301..7341945de3ce 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts @@ -190,7 +190,7 @@ tbi1: tbi-phy@1f { }; &esdhc { - status = "okay"; + status = "okay"; }; &qspi { From 5206b2eec56ee5d50b02a0aac2c8a66f76556d37 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 3 Jul 2026 17:06:49 +0200 Subject: [PATCH 146/864] arm64: dts: freescale: imx95-var-dart: enable NETC block control Enable the NETC and NETCMIX block control nodes on the DART-MX95 SoM. These block control nodes are required to enable and use the NETC Ethernet ports. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi index a20fadacaa6d..f3b44a866917 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi @@ -176,6 +176,10 @@ &mu7 { status = "okay"; }; +&netc_blk_ctrl { + status = "okay"; +}; + &netc_emdio { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>; @@ -213,6 +217,10 @@ &netc_timer { status = "okay"; }; +&netcmix_blk_ctrl { + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; From 68427905850302612bd68dcec7baf791ca6f8032 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 17:53:08 +0200 Subject: [PATCH 147/864] arm64: dts: imx95-var-dart: wm8904: Add INL1 as DMICDAT1 On the DART-MX95 platform, INL1/DMICDAT1 is used as the DMIC data line. Add the wlf,in1l-as-dmicdat1 property to reflect this configuration. This enables the internal MUX to switch between the ADC and DMIC as the capture input. Co-developed-by: Alexander Herfurtner Signed-off-by: Alexander Herfurtner Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi index f3b44a866917..b4c55bd33858 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart.dtsi @@ -158,6 +158,8 @@ wm8904: audio-codec@1a { /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; /* GPIO1 = DMIC_CLK, don't touch others */ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; }; }; From 66738404bd0ab5b515d32bf4bd64f2cbe91a4b4d Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:30 +0800 Subject: [PATCH 148/864] arm64: dts: imx8mm-evk: Add power supply property to Root Port node Add the power supply property to the Root Port child node to support the new PCI pwrctrl framework. Legacy power supply property is retained for backward compatibility with existing kernels. New device trees should specify power supply at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e03aba825c18..ec49cbbfd9ce 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -542,6 +542,7 @@ &pcie0 { assigned-clock-rates = <10000000>, <250000000>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie0>; supports-clkreq; status = "okay"; @@ -562,6 +563,7 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie0>; }; &sai2 { From 6320522f617d020b0e65cabb4cc4b35518fc8222 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:31 +0800 Subject: [PATCH 149/864] arm64: dts: imx8mp-evk: Add power supply properties to Root Port node Add the power supply properties to the Root Port child nodes to support the new PCI pwrctrl framework. Legacy power supply properties are retained for backward compatibility with existing kernels. New device trees should specify power supplies at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2e092b0b52d9..3b1b90af34a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -791,6 +791,7 @@ &pcie0 { pinctrl-0 = <&pinctrl_pcie0>; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio2 7 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie0>; vpcie3v3aux-supply = <®_pcie0>; supports-clkreq; @@ -805,6 +806,8 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie0>; + vpcie3v3aux-supply = <®_pcie0>; }; &pwm1 { From 919519e84ea2aaf9ccab968e0aa9d97586bd9ab8 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:32 +0800 Subject: [PATCH 150/864] arm64: dts: imx8mq-evk: Add power supply properties to Root Port node Add the power supply properties to the Root Port child nodes to support the new PCI pwrctrl framework. Legacy power supply properties are retained for backward compatibility with existing kernels. New device trees should specify power supplies at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index b9b03416aa39..1f07f1089026 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -403,6 +403,7 @@ &pcie1 { <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>, <&clk IMX8MQ_CLK_PCIE2_AUX>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie1>; vpcie3v3aux-supply = <®_pcie1>; vph-supply = <&vgen5_reg>; @@ -422,6 +423,8 @@ &pcie1_ep { &pcie1_port0 { reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie1>; + vpcie3v3aux-supply = <®_pcie1>; }; &pgc_gpu { From c4dad11102b34dfcb8facb29b0270f8fd71206d3 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:33 +0800 Subject: [PATCH 151/864] arm64: dts: imx8dxl/qm/qxp: Add power supply properties to Root Port node Add the power supply properties to the Root Port child nodes to support the new PCI pwrctrl framework. Legacy power supply properties are retained for backward compatibility with existing kernels. New device trees should specify power supplies at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 78e8d41e6791..0ede0c7ed422 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -677,6 +677,7 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; status = "okay"; @@ -692,6 +693,8 @@ &pcie0_ep { &pcieb_port0 { reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcieb>; + vpcie3v3aux-supply = <®_pcieb>; }; &sai0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index f706c86137c0..9e49ac377162 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -812,6 +812,7 @@ &pciea { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pciea>; vpcie3v3aux-supply = <®_pciea>; supports-clkreq; @@ -820,6 +821,8 @@ &pciea { &pciea_port0 { reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pciea>; + vpcie3v3aux-supply = <®_pciea>; }; &pcieb { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 2af32eca612a..857a6e512228 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -732,6 +732,7 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; supports-clkreq; @@ -748,6 +749,8 @@ &pcie0_ep { &pcieb_port0 { reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcieb>; + vpcie3v3aux-supply = <®_pcieb>; }; &scu_key { From d61fa5049fcfd3a9d048038acf6c0d5993baee12 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:34 +0800 Subject: [PATCH 152/864] arm64: dts: imx95: Move power supply properties to Root Port node Move the power supply properties from the PCIe controller nodes to the Root Port child nodes to support the new PCI pwrctrl framework. Since i.MX95 is the new platform that under development phase, it should be fine to simply move the power supply properties. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 7d820a0f80b2..6aedcbbe915a 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -555,8 +555,6 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_m2_pwr>; - vpcie3v3aux-supply = <®_m2_pwr>; supports-clkreq; status = "disabled"; }; @@ -570,6 +568,8 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_m2_pwr>; + vpcie3v3aux-supply = <®_m2_pwr>; }; &sai1 { diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 2e463bc7c601..340ab0253ec2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -542,8 +542,6 @@ &pcie0 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie0>; - vpcie3v3aux-supply = <®_pcie0>; supports-clkreq; status = "okay"; }; @@ -557,6 +555,8 @@ &pcie0_ep { &pcie0_port0 { reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie0>; + vpcie3v3aux-supply = <®_pcie0>; }; &pcie1 { @@ -564,8 +564,6 @@ &pcie1 { pinctrl-names = "default"; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_slot_pwr>; - vpcie3v3aux-supply = <®_slot_pwr>; status = "okay"; }; @@ -578,6 +576,8 @@ &pcie1_ep { &pcie1_port0 { reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_slot_pwr>; + vpcie3v3aux-supply = <®_slot_pwr>; }; &sai1 { From c74766834b2e1431883ddf54990e3ad16a5354a4 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:28 +0800 Subject: [PATCH 153/864] ARM: dts: imx6qdl-sabresd: Add power supply property to Root Port node Add the power supply property to the Root Port child node to support the new PCI pwrctrl framework. Legacy power supply property is retained for backward compatibility with existing kernels. New device trees should specify power supply at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index fe9046c03ddd..60fe0f973668 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -756,12 +756,14 @@ &pcie { pinctrl-0 = <&pinctrl_pcie>; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie>; status = "okay"; }; &pcie_port0 { reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie>; }; &pwm1 { From c5e2405cff364ecdaea89cb24a7b53c89c0b98e4 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 1 Jul 2026 18:52:29 +0800 Subject: [PATCH 154/864] ARM: dts: imx6sx-sdb: Add power supply property to Root Port node Add the power supply property to the Root Port child node to support the new PCI pwrctrl framework. Legacy power supply property is retained for backward compatibility with existing kernels. New device trees should specify power supply at the Root Port level to utilize the pwrctrl framework. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index 338de4d144b2..2d3521ea0caa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -284,12 +284,14 @@ &pcie { pinctrl-0 = <&pinctrl_pcie>; /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; + /* This property is deprecated, use power supply from the Root Port node. */ vpcie-supply = <®_pcie_gpio>; status = "okay"; }; &pcie_port0 { reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + vpcie3v3-supply = <®_pcie_gpio>; }; &lcdif1 { From 77c0d4cfd43353e8bdebc4eab8e579518e2dbf5f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 12:05:55 +0200 Subject: [PATCH 155/864] dt-bindings: arm: fsl: add Variscite DART-MX8M PLUS Boards Add DT compatible strings for Variscite DART-MX8MP SoM and Variscite development carrier Board. Acked-by: Conor Dooley Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 6237fb2ae50e..f96f3d31dac1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1322,6 +1322,12 @@ properties: - const: tq,imx8mp-tqma8mpqs # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM - const: fsl,imx8mp + - description: Variscite DART-MX8M Plus based boards + items: + - const: variscite,var-dart-mx8mp-sonata # Variscite DART-MX8MP on Sonata Development Board + - const: variscite,var-dart-mx8mp # Variscite DART-MX8MP SOM + - const: fsl,imx8mp + - description: Variscite VAR-SOM-MX8M Plus based boards items: - const: variscite,var-som-mx8mp-symphony From d08607aa231e026cd94b4c33077f8b8d28731952 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 12:05:56 +0200 Subject: [PATCH 156/864] arm64: dts: freescale: Add support for Variscite DART-MX8M-PLUS Add device tree support for the Variscite DART-MX8MP system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8M Plus MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mp-var-dart.dtsi | 475 ++++++++++++++++++ 1 file changed, 475 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi new file mode 100644 index 000000000000..889e41f2af14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart.dtsi @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX8M-PLUS + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-plus/dart-mx8m-plus/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "Variscite DART-MX8M-PLUS Module"; + compatible = "variscite,var-dart-mx8mp", "fsl,imx8mp"; + + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 8 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&mu2 { + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <11536000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* BT module */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0xc0 + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x150 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0xc0 + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 + >; + }; +}; From 41cd3d91ca8595f48cae5169ff8e4089c88670f2 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 1 Jul 2026 12:05:57 +0200 Subject: [PATCH 157/864] arm64: dts: imx8mp-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-PLUS system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - HDMI support - GPIO Expanders - RTC module - TPM module - CAN peripherals Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-var-dart-sonata.dts | 733 ++++++++++++++++++ 2 files changed, 734 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 430085123b4e..01d4ddfde098 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -453,6 +453,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts new file mode 100644 index 000000000000..983d67a0c1de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-dart-sonata.dts @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX8M-PLUS + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-var-dart.dtsi" + +/ { + model = "Variscite DART-MX8M-PLUS on Sonata-Board"; + compatible = "variscite,var-dart-mx8mp-sonata", + "variscite,var-dart-mx8mp", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-emmc { + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + label = "eMMC"; + linux,default-trigger = "mmc2"; + }; + }; + + native-hdmi-connector { + compatible = "hdmi-connector"; + label = "HDMI OUT"; + type = "a"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&hdmi_tx_out>; + }; + }; + }; + + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vmmc_usdhc2>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; +}; + +&aud2htx { + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; + + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + clocks = <&clk40m>; + spi-max-frequency = <20000000>; + }; +}; + +&eqos { + mdio { + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&hdmi_pai { + status = "okay"; +}; + +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + status = "okay"; + + ports { + port@1 { + hdmi_tx_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + eth10g-en-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "eth10g_sel"; + }; + + pcie2-en-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "pcie2_sel"; + }; + + /* RGB_SEL + * Keep signal low and not floating + */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6408>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&lcdif3 { + status = "okay"; +}; + +&pcie { + reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +/* Console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Header */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy0 { + fsl,phy-tx-vref-tune-percent = <122>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-comp-dis-tune-percent = <115>; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + status = "okay"; +}; + +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&xcvr { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x1c6 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16 + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x16 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x12 + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x12 + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x1d0 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x00 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x00 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x00 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x00 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x00 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x00 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 + MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0xc6 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c2 + >; + }; + + pinctrl_pca6408: pca6408grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x1c6 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0xc0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; From 5e7e00f811fb1808352a22d18e20aa8026c6d73c Mon Sep 17 00:00:00 2001 From: Khristine Andreea Barbulescu Date: Tue, 30 Jun 2026 14:54:03 +0200 Subject: [PATCH 158/864] arm64: dts: s32g: describe GPIO and EIRQ resources in SIUL2 pinctrl node Update the SIUL2 pinctrl node to describe the additional register ranges and DT properties used by the updated SIUL2 driver. Besides the MSCR and IMCR ranges used for pinmux and pin configuration, the SIUL2 block also provides PGPDO and PGPDI registers for GPIO output and input operations, as well as an EIRQ register window for external interrupt configuration. The driver supports both legacy pinctrl-only DTs and extended DTs with GPIO and IRQ. Reflect these resources in the SIUL2 pinctrl node by adding: - the PGPDO and PGPDI register ranges - the EIRQ register range - gpio-controller, #gpio-cells and gpio-ranges - interrupt-controller, #interrupt-cells and interrupts Keep the hardware description aligned with the updated SIUL2 driver, where pinctrl, GPIO data access and the EIRQ register block are described under the same device node. Signed-off-by: Khristine Andreea Barbulescu Reviewed-by: Bartosz Golaszewski Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 21 ++++++++++++++++++++- arch/arm64/boot/dts/freescale/s32g3.dtsi | 21 ++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 809019ea0e29..8dc0c5d9f368 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -135,7 +135,26 @@ pinctrl: pinctrl@4009c240 { /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ window: DISR0..IFEER0 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; jtag_pins: jtag-pins { jtag-grp0 { diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 22e80fc03f9c..129d6ad8e5c6 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -193,7 +193,26 @@ pinctrl: pinctrl@4009c240 { /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ window: DISR0..IFEER0 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; jtag_pins: jtag-pins { jtag-grp0 { From 6e62bc736674601a8764f01217ac539e75d71fc8 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:26 +0800 Subject: [PATCH 159/864] arm64: dts: imx8mp-evk: add typec node The first USB port features a Type-C connector with dual data role and dual power role capabilities. Add the Type-C device node and enable the corresponding USB controller and phy node. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 69 ++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 3b1b90af34a0..627fbe2b6a16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx8mp.dtsi" / { @@ -655,6 +656,35 @@ adv7535_out: endpoint { }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + orientation-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + }; + }; }; &i2c3 { @@ -873,6 +903,38 @@ &uart2 { status = "okay"; }; +&usb3_phy0 { + fsl,phy-tx-vref-tune-percent = <122>; + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-comp-dis-tune-percent = <115>; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -1201,6 +1263,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + pinctrl_usb1_vbus: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 From 05d5a7fcb2399d4398a651dcf3b4a01290418435 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:27 +0800 Subject: [PATCH 160/864] arm64: dts: imx8mp-evk: add usb3_phy1 tuning properties Add some tuning properties for usb3_phy1 to improve signal. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 627fbe2b6a16..7bdd641292fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -936,6 +936,8 @@ usb3_data_hs: endpoint { }; &usb3_phy1 { + fsl,phy-tx-preemp-amp-tune-microamp = <1800>; + fsl,phy-tx-vref-tune-percent = <116>; status = "okay"; }; From 94aad340fbf22a8a2484879c1e862c856d0e946f Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:28 +0800 Subject: [PATCH 161/864] arm64: dts: imx95: switch usb3 controller to flattened model Switch to use flattened model for USB3 controller. To enable USB controller with restricted DMA access range to work correctly, add a simple-bus to constrain the dma address. Note: This changes the USB controller compatible string from "fsl,imx95-dwc3" to "nxp,imx95-dwc3". This requires a kernel with CONFIG_USB_DWC3_IMX enabled; otherwise, the new DTB will not be compatible with older one. As i.MX95 is a new SoC and is still under development, it's acceptable at development early phase. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 62 ++++++++++++------------ 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index d6c549c16047..305751046d66 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1867,37 +1867,6 @@ pmu@49252000 { }; }; - usb3: usb@4c010010 { - compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; - reg = <0x0 0x4c010010 0x0 0x04>, - <0x0 0x4c1f0000 0x0 0x20>; - clocks = <&scmi_clk IMX95_CLK_HSIO>, - <&scmi_clk IMX95_CLK_32K>; - clock-names = "hsio", "suspend"; - interrupts = ; - #address-cells = <2>; - #size-cells = <2>; - ranges; - power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; - dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; - status = "disabled"; - - usb3_dwc3: usb@4c100000 { - compatible = "snps,dwc3"; - reg = <0x0 0x4c100000 0x0 0x10000>; - clocks = <&scmi_clk IMX95_CLK_HSIO>, - <&scmi_clk IMX95_CLK_24M>, - <&scmi_clk IMX95_CLK_32K>; - clock-names = "bus_early", "ref", "suspend"; - interrupts = ; - phys = <&usb3_phy>, <&usb3_phy>; - phy-names = "usb2-phy", "usb3-phy"; - snps,gfladj-refclk-lpm-sel-quirk; - snps,parkmode-disable-ss-quirk; - iommus = <&smmu 0xe>; - }; - }; - hsio_blk_ctl: syscon@4c0100c0 { compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; reg = <0x0 0x4c0100c0 0x0 0x1>; @@ -1906,6 +1875,37 @@ hsio_blk_ctl: syscon@4c0100c0 { power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; }; + bus@4c100000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges; + + usb3: usb3_dwc3: usb@4c100000 { + compatible = "nxp,imx95-dwc3", "nxp,imx8mp-dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>, + <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + reg-names = "core", "blkctl", "glue"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_24M>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "hsio", "bus_early", "ref", "suspend"; + interrupts = , + ; + interrupt-names = "dwc_usb3", "wakeup"; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + iommus = <&smmu 0xe>; + status = "disabled"; + }; + }; + usb3_phy: phy@4c1f0040 { compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; reg = <0x0 0x4c1f0040 0x0 0x40>, From b9fff21cbd480f47f04debbce6c14f48dd715f0a Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 30 Jun 2026 18:36:29 +0800 Subject: [PATCH 162/864] arm64: dts: imx8mq-evk: add typec node The first USB port features a Type-C connector with dual data role and dual power role capabilities. Add the Type-C device node and enable the corresponding USB controller and phy node. Signed-off-by: Xu Yang Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 59 ++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index 1f07f1089026..5ea04703ddd7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include #include "imx8mq.dtsi" / { @@ -330,6 +331,35 @@ vgen6_reg: vgen6 { }; }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + orientation-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + }; + }; }; &lcdif { @@ -514,6 +544,28 @@ bluetooth { }; }; +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + &usb3_phy1 { status = "okay"; }; @@ -666,6 +718,13 @@ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 From 5ede58393a7064164dce027e6cb05a64662a7173 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:19:52 +0200 Subject: [PATCH 163/864] ARM: dts: allwinner: sun8i-h3: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706101951.341727-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts index 2b0566d4b386..88550da5af62 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts @@ -73,7 +73,7 @@ reg_vcc_dram: vcc-dram { enable-active-high; gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ vin-supply = <®_vcc5v0>; - }; + }; reg_vdd_sys: vdd-sys { compatible = "regulator-fixed"; @@ -85,7 +85,7 @@ reg_vdd_sys: vdd-sys { enable-active-high; gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ vin-supply = <®_vcc5v0>; - }; + }; wifi_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; From 9995c8146bb98a20c2b0a6d99ce3c4ec29b59d41 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sat, 6 Jun 2026 22:54:41 +0200 Subject: [PATCH 164/864] dt-bindings: arm: sunxi: Add NetCube Systems OpenNMC (dobermann) The OpenNMC is an open replacement for APC SmartSlot management cards based on the Nagami System-on-Module. Signed-off-by: Lukas Schmid Acked-by: Krzysztof Kozlowski Acked-by: Conor Dooley Link: https://patch.msgid.link/20260606205452.2386930-2-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai --- Documentation/devicetree/bindings/arm/sunxi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 82dd58b95f8a..f04db28c630a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -604,6 +604,7 @@ properties: - description: NetCube Systems Nagami SoM based boards items: - enum: + - netcube,dobermann - netcube,nagami-basic-carrier - netcube,nagami-keypad-carrier - const: netcube,nagami From 5b0fd777eb345036fc8de9ec1c6c7b6966d90be7 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sat, 6 Jun 2026 22:54:42 +0200 Subject: [PATCH 165/864] riscv: dts: allwinner: d1s-t113: Add uart4 pinctrl required by NetCube Systems OpenNMC Added the "uart4_pb_pins" pinctrl used by the OpenNMC Signed-off-by: Lukas Schmid Reviewed-by: Andre Przywara Link: https://patch.msgid.link/20260606205452.2386930-3-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index a810ad3eb2a2..13b1e5716604 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -191,6 +191,12 @@ uart3_pb_pins: uart3-pb-pins { pins = "PB6", "PB7"; function = "uart3"; }; + + /omit-if-no-ref/ + uart4_pb_pins: uart4-pb-pins { + pins = "PB2", "PB3"; + function = "uart4"; + }; }; ccu: clock-controller@2001000 { From 8a5c37efceec9d2ef0dd447ea1d0787224f04845 Mon Sep 17 00:00:00 2001 From: Lukas Schmid Date: Sat, 6 Jun 2026 22:54:43 +0200 Subject: [PATCH 166/864] ARM: dts: allwinner: add support for NetCube Systems OpenNMC (dobermann) NetCube Systems OpenNMC is an open replacement for APC SmartSlot Management Cards. It is based on the Nagami System-on-Module. It breaks out the following interfaces: - 10/100 Mbps Ethernet - USB Type-C OTG using a TUSB320 (usb0) - USB Type-C Console Port using a CH340 (uart3) - USB Type-A Host with internal CH334 USB-Hub (usb1) - MicroSD Slot with Card-Detect (mmc0) - WiFi/Bluetooth using the modules built-in ESP32 - SmartSlot serial interface (uart4) - DS3232 RTC with CR1220 Battery Backup - Extension connector providing SPI,I2C,USB,CAN,UART for future use. Signed-off-by: Lukas Schmid Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20260606205452.2386930-4-lukas.schmid@netcube.li [wens@kernel.org: Change "sunxi" in subject to "allwinner"] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 2 + .../sun8i-t113s-netcube-dobermann.dts | 149 ++++++++++++++++++ 2 files changed, 151 insertions(+) create mode 100644 arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-dobermann.dts diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index f71392a55df8..0fc954d41595 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -201,6 +201,7 @@ DTC_FLAGS_sun8i-h3-orangepi-pc := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@ DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@ DTC_FLAGS_sun8i-t113s-netcube-nagami-basic-carrier := -@ +DTC_FLAGS_sun8i-t113s-netcube-dobermann := -@ DTC_FLAGS_sun8i-v3s-netcube-kumquat := -@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ @@ -261,6 +262,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ sun8i-t113s-mangopi-mq-r-t113.dtb \ + sun8i-t113s-netcube-dobermann.dtb \ sun8i-t113s-netcube-nagami-basic-carrier.dtb \ sun8i-t113s-netcube-nagami-keypad-carrier.dtb \ sun8i-t3-cqa3t-bv3.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-dobermann.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-dobermann.dts new file mode 100644 index 000000000000..d7765caffe2a --- /dev/null +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-dobermann.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-t113s-netcube-nagami.dtsi" + +#include + +/ { + model = "NetCube Systems OpenNMC (dobermann)"; + compatible = "netcube,dobermann", "netcube,nagami", + "allwinner,sun8i-t113s"; + + aliases { + serial2 = &uart4; // UART on SmartSlot + rtc0 = &ds3232; + rtc1 = &rtc; // not battery backed + }; + + leds { + compatible = "gpio-leds"; + + led_heartbeat_green: led-heartbeat-green { + gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */ + linux,default-trigger = "heartbeat"; + color = ; + function = LED_FUNCTION_HEARTBEAT; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + tusb320: typec@60 { + compatible = "ti,tusb320"; + reg = <0x60>; + interrupts-extended = <&pio 3 22 IRQ_TYPE_LEVEL_LOW>; /* PD22 */ + }; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; +}; + +/* microSD Card Slot on the board */ +&mmc0 { + vmmc-supply = <®_vcc3v3>; + disable-wp; + bus-width = <4>; + cd-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */ + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "SMART_TX", "SMART_RX", // PB + "EXT_IO3", "EXT_IO2", "CONSOLE_TX", "CONSOLE_RX", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "eMMC_CLK", "eMMC_CMD", // PC + "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "USB_SEC_EN", "EXT_SPI_nCS", "EXT_SPI_SCK", + "EXT_SPI_MOSI", "EXT_SPI_MISO", "EXT_IO5", "EXT_IO4", + "SMART_SEL", "", "", "", + "I2C2_SCL", "I2C2_SDA", "TUSB320_nINT", "", + "", "", "", "", + "", "", "", "", + "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE + "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "", + "ETH_MDC", "ETH_MDIO", "I2C3_nINT", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "uSD_D1", "uSD_D0", "uSD_CLK", "uSD_CMD", // PF + "uSD_D3", "uSD_D2", "TUSB320_ID", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "ESP_TXD", "ESP_RXD", + "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA", + "EXT_IO1", "EXT_IO0", "LED_HEARTBEAT", "SD_DETECT", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* SmartSlot serial */ +&uart4 { + pinctrl-0 = <&uart4_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + extcon = <&tusb320 0>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + status = "okay"; +}; From a858dab4807ab8259e00e537e8b3853b3bc7a882 Mon Sep 17 00:00:00 2001 From: Nisarg Rajput Date: Tue, 2 Jun 2026 03:38:08 +0000 Subject: [PATCH 167/864] ARM: dts: allwinner: enable overlay support for sun8i-h2-plus pi boards Add DTC_FLAGS -@ for all H2+ pi-class devices to enable device-tree overlay support. This follows the same approach used for H3 pi boards in commit 0801a3a9f35854c91f1f3ab8e879c3d14912d214 ("arm: dts: Enable device-tree overlay support for sun8i-h3 pi devices"). The -@ flag populates the __symbols__ node in the DTB which is required for applying device-tree overlays from the bootloader or firmware. Boards affected: - sun8i-h2-plus-bananapi-m2-zero - sun8i-h2-plus-libretech-all-h3-cc - sun8i-h2-plus-orangepi-r1 Signed-off-by: Nisarg Rajput Link: https://patch.msgid.link/BESPR10MB9223FFB989C825881E02F0CAD2122@BESPR10MB9223.EURPRD10.PROD.OUTLOOK.COM [wens@kernel.org: Move statements into common overlay block] [wens@kernel.org: Drop sun8i-h2-plus-orangepi-zero from commit message] [wens@kernel.org: Change "arm" in subject to "ARM"] Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 0fc954d41595..75b2b6a2f7a6 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -182,6 +182,9 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-wits-pro-a20-dkt.dtb # Enables support for device-tree overlays for all pis +DTC_FLAGS_sun8i-h2-plus-bananapi-m2-zero := -@ +DTC_FLAGS_sun8i-h2-plus-libretech-all-h3-cc := -@ +DTC_FLAGS_sun8i-h2-plus-orangepi-r1 := -@ DTC_FLAGS_sun8i-h2-plus-orangepi-zero := -@ DTC_FLAGS_sun8i-h3-orangepi-lite := -@ DTC_FLAGS_sun8i-h3-bananapi-m2-plus := -@ From f237e4d3ca4a3e9da9ca2832097ffbc5ba612c9f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:16 +0200 Subject: [PATCH 168/864] ARM: dts: ti: omap: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706101815.341184-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Kevin Hilman (TI) --- .../ti/omap/am335x-icev2-prueth-overlay.dtso | 126 +++++++++--------- arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi | 2 +- arch/arm/boot/dts/ti/omap/dm8148-evm.dts | 4 +- arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi | 2 +- arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 2 +- .../dts/ti/omap/motorola-mapphone-common.dtsi | 10 +- arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi | 2 +- .../dts/ti/omap/omap3-overo-common-lcd35.dtsi | 2 +- .../dts/ti/omap/omap3-overo-common-lcd43.dtsi | 2 +- 10 files changed, 77 insertions(+), 77 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso b/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso index ffed1f3d046a..c0f32c889f69 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso +++ b/arch/arm/boot/dts/ti/omap/am335x-icev2-prueth-overlay.dtso @@ -19,61 +19,61 @@ #include &{/} { - /* Dual-MAC Ethernet application node on PRU-ICSS */ - pruss_eth: pruss-eth { - compatible = "ti,am3359-prueth"; - ti,prus = <&pru0>, <&pru1>; - sram = <&ocmcram>; - ti,mii-rt = <&pruss_mii_rt>; - ti,iep = <&pruss_iep>; - ti,ecap = <&pruss_ecap>; - interrupts = <20 2 2>, <21 3 3>; - interrupt-names = "rx_hp", "rx_lp"; - interrupt-parent = <&pruss_intc>; + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible = "ti,am3359-prueth"; + ti,prus = <&pru0>, <&pru1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss_mii_rt>; + ti,iep = <&pruss_iep>; + ti,ecap = <&pruss_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss_intc>; - pinctrl-0 = <&pruss_eth_default>; - pinctrl-names = "default"; + pinctrl-0 = <&pruss_eth_default>; + pinctrl-names = "default"; - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - pruss_emac0: ethernet-port@0 { - reg = <0>; - phy-handle = <&pruss_eth0_phy>; - phy-mode = "mii"; - interrupts = <20 2 2>, <26 6 6>, <23 6 6>; - interrupt-names = "rx", "emac_ptp_tx", - "hsr_ptp_tx"; - /* Filled in by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - }; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; - pruss_emac1: ethernet-port@1 { - reg = <1>; - phy-handle = <&pruss_eth1_phy>; - phy-mode = "mii"; - interrupts = <21 3 3>, <27 9 7>, <24 9 7>; - interrupt-names = "rx", "emac_ptp_tx", - "hsr_ptp_tx"; - /* Filled in by bootloader */ - local-mac-address = [00 00 00 00 00 00]; - }; - }; - }; + pruss_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; }; &am33xx_pinmux { /* MDIO node for PRU-ICSS */ - pruss_mdio_default: pruss-mdio-default-pins { - pinctrl-single,pins = < + pruss_mdio_default: pruss-mdio-default-pins { + pinctrl-single,pins = < AM33XX_IOPAD(0x88c, PIN_OUTPUT | MUX_MODE5) /* (V12) gpmc_clk.pr1_mdio_mdclk */ AM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE5) /* (T13) gpmc_csn3.pr1_mdio_data */ - >; - }; + >; + }; /* Pinmux configuration for PRU-ICSS */ - pruss_eth_default: pruss-eth-default-pins { - pinctrl-single,pins = < + pruss_eth_default: pruss-eth-default-pins { + pinctrl-single,pins = < AM33XX_IOPAD(0x8a0, PIN_INPUT | MUX_MODE2) /* (R1) lcd_data0.pr1_mii_mt0_clk */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE2) /* (T2) lcd_data5.pr1_mii0_txd0 */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE2) /* (T1) lcd_data4.pr1_mii0_txd1 */ @@ -105,14 +105,14 @@ AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE5) /* (T16) gpmc_a10.pr1_mii1_rxdv */ AM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE5) /* (V17) gpmc_a11.pr1_mii1_rxer */ AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE5) /* (U18) gpmc_be1n.pr1_mii1_rxlink */ AM33XX_IOPAD(0x8ec, PIN_INPUT | MUX_MODE2) /* (R6) lcd_ac_bias_en.pr1_mii1_crs */ - >; - }; + >; + }; }; &gpio3 { - mux-mii-hog { + mux-mii-hog { status = "disabled"; - }; + }; mux-mii-hog-0 { gpio-hog; @@ -129,28 +129,28 @@ mux-mii-hog-0 { * conflict with PRU-ICSS */ &mac_sw { - status = "disabled"; + status = "disabled"; }; &davinci_mdio_sw { - status = "disabled"; + status = "disabled"; }; /* PRU-ICSS MDIO configuration */ &pruss_mdio { - pinctrl-0 = <&pruss_mdio_default>; - pinctrl-names = "default"; - reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; - reset-delay-us = <2>; /* PHY datasheet states 1uS min */ - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; + pinctrl-0 = <&pruss_mdio_default>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2>; /* PHY datasheet states 1uS min */ + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; - pruss_eth0_phy: ethernet-phy@1 { - reg = <1>; - }; + pruss_eth0_phy: ethernet-phy@1 { + reg = <1>; + }; - pruss_eth1_phy: ethernet-phy@3 { - reg = <3>; - }; + pruss_eth1_phy: ethernet-phy@3 { + reg = <3>; + }; }; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index 8a693c478bea..57a45609f9f5 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -1870,7 +1870,7 @@ SYSC_OMAP2_SOFTRESET | gpio2: gpio@0 { compatible = "ti,omap4-gpio"; - gpio-ranges = <&am33xx_pinmux 0 34 18>, + gpio-ranges = <&am33xx_pinmux 0 34 18>, <&am33xx_pinmux 18 77 4>, <&am33xx_pinmux 22 56 10>; gpio-controller; diff --git a/arch/arm/boot/dts/ti/omap/dm8148-evm.dts b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts index 57a9eef09f6f..8236d9eb438a 100644 --- a/arch/arm/boot/dts/ti/omap/dm8148-evm.dts +++ b/arch/arm/boot/dts/ti/omap/dm8148-evm.dts @@ -99,7 +99,7 @@ partition@780000 { }; &mmc1 { - status = "disabled"; + status = "disabled"; }; &mmc2 { @@ -111,7 +111,7 @@ &mmc2 { }; &mmc3 { - status = "disabled"; + status = "disabled"; }; &pincntl { diff --git a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi index 338449b32a18..76ebc6c3c3e5 100644 --- a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi @@ -177,7 +177,7 @@ mpu_ck: mpu_ck@15dc { compatible = "ti,gate-clock"; clocks = <&sysclk2_ck>; ti,bit-shift = <1>; - reg = <0x15dc>; + reg = <0x15dc>; }; audio_pll_a_ck: audio_pll_a_ck@35c { diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index 9df7648c4b79..a595745afe59 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -1695,9 +1695,9 @@ uart4: serial@0 { reg = <0x0 0x100>; interrupts = ; clock-frequency = <48000000>; - status = "disabled"; dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; dma-names = "tx", "rx"; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi index a0c53d9c2625..28b4f12b82a7 100644 --- a/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/motorola-mapphone-common.dtsi @@ -91,22 +91,22 @@ &cpu_thermal { }; &cpu_alert0 { - temperature = <80000>; /* millicelsius */ + temperature = <80000>; /* millicelsius */ }; &cpu0 { - /* + /* * Note that the 1.2GiHz mode is enabled for all SoC variants for * the Motorola Android Linux v3.0.8 based kernel. */ - operating-points = < - /* kHz uV */ + operating-points = < + /* kHz uV */ 300000 1025000 600000 1200000 800000 1313000 1008000 1375000 1200000 1375000 - >; + >; }; &dss { diff --git a/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi index 0e942513560d..6c4916ec41b4 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-cm-t3x30.dtsi @@ -29,7 +29,7 @@ OMAP3_CORE1_IOPAD(0x219a, PIN_INPUT_PULLUP | MUX_MODE4) /* uart3_cts_rctx.gpio_1 >; }; - hsusb0_pins: hsusb0-pins { + hsusb0_pins: hsusb0-pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0) /* hsusb0_clk.hsusb0_clk */ OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0) /* hsusb0_stp.hsusb0_stp */ diff --git a/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi index aa4fcdbedd8f..519f7b42a59a 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-n950-n9.dtsi @@ -287,7 +287,7 @@ lis302: lis302@1d { pinctrl-names = "default"; pinctrl-0 = <&accelerator_pins>; - interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ + interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ /* click flags */ st,click-single-x; diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi index 0da561a23f36..2f7a4a717359 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd35.dtsi @@ -103,7 +103,7 @@ ads7846reg: ads7846-reg { backlight { compatible = "gpio-backlight"; - + pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ diff --git a/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi index 981f02f088f8..35701f596972 100644 --- a/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3-overo-common-lcd43.dtsi @@ -134,7 +134,7 @@ ads7846reg: ads7846-reg { backlight { compatible = "gpio-backlight"; - + pinctrl-names = "default"; pinctrl-0 = <&backlight_pins>; gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; /* gpio_145 */ From 36d3d0f740d75dc0274b72720c044f476ff0e242 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 2 Jul 2026 15:52:43 +0200 Subject: [PATCH 169/864] ARM: dts: ti/omap: embt2ws: use mulit-led for RGB LED The device has one single RGB LED. Explicitly declare it as such by combing the LEDs into one. Suggested-by: Pavel Machek Signed-off-by: Andreas Kemnade Link: https://patch.msgid.link/20260702-b200multiled-v1-1-c1799ad45c96@kemnade.info Signed-off-by: Kevin Hilman (TI) --- arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts index e253e0775ea9..e11d1931c42a 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -64,6 +64,13 @@ key-lock { }; }; + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_STATUS; + leds = <&led_r>, <&led_g>, <&led_b>; + }; + cb_v18: regulator-cb-v18 { pinctrl-names = "default"; pinctrl-0 = <&cb_v18_pins>; @@ -368,19 +375,19 @@ led-controller@66 { #address-cells = <1>; #size-cells = <0>; - led@0 { + led_g: led@0 { reg = <0>; color = ; function = LED_FUNCTION_STATUS; }; - led@2 { + led_b: led@2 { reg = <2>; color = ; function = LED_FUNCTION_STATUS; }; - led@4 { + led_r: led@4 { reg = <4>; color = ; function = LED_FUNCTION_STATUS; From 5b372595d4b4cd471f49901498a920c983310c47 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 10 Apr 2026 10:17:01 +0200 Subject: [PATCH 170/864] arm64: dts: qcom: milos: Add IPA node Add the description of the IPA block in the Milos SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260410-milos-ipa-v2-1-c699b6b8cf27@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 44 +++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 7a475b530213..c6594c86e86e 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1648,6 +1648,50 @@ adreno_smmu: iommu@3da0000 { dma-coherent; }; + ipa: ipa@3f40000 { + compatible = "qcom,milos-ipa"; + + reg = <0x0 0x03f40000 0x0 0x10000>, + <0x0 0x03f50000 0x0 0x5000>, + <0x0 0x03e04000 0x0 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, + <&smp2p_ipa_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_ipa_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_IPA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "memory", + "config"; + + iommus = <&apps_smmu 0x4a0 0x0>, + <&apps_smmu 0x4a2 0x0>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_ipa_out 0>, + <&smp2p_ipa_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + sram = <&ipa_modem_tables>; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,milos-mpss-pas"; reg = <0x0 0x04080000 0x0 0x10000>; From 47dd81735741b60b53dc2ccd4a48b0ec74c9adc7 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 10 Apr 2026 10:17:02 +0200 Subject: [PATCH 171/864] arm64: dts: qcom: milos-fairphone-fp6: Enable IPA Configure and enable the node for IPA which enables mobile data on this device. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260410-milos-ipa-v2-2-c699b6b8cf27@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index ebdca0e2d2f3..2fc93e64b520 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -700,6 +700,15 @@ vibrator@5a { }; }; +&ipa { + firmware-name = "qcom/milos/fairphone/fp6/ipa_fws.mbn"; + memory-region = <&ipa_fw_mem>; + + qcom,gsi-loader = "self"; + + status = "okay"; +}; + &pm8550vs_c { status = "okay"; }; From 93d60582eb52e50ea11f95397a2b3633b12efa66 Mon Sep 17 00:00:00 2001 From: Xin Liu Date: Mon, 27 Apr 2026 01:23:25 -0700 Subject: [PATCH 172/864] arm64: dts: qcom: talos: Add EL2 overlay for talos-evk Add support for building an EL2 combined DTB for the talos-evk in the Qualcomm DTS Makefile. The new talos-evk-el2.dtb is generated by combining the base talos-evk.dtb with the talos-el2.dtbo overlay, enabling EL2-specific configurations required by the platform. Signed-off-by: Xin Liu Link: https://lore.kernel.org/r/20260427082325.1895450-1-xin.liu@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index fb1a99a3e01c..6be0fbb095a7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -400,6 +400,10 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb + +talos-evk-el2-dtbs := talos-evk.dtb talos-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += talos-evk-el2.dtb talos-evk-usb1-peripheral-dtbs := talos-evk.dtb talos-evk-usb1-peripheral.dtbo dtb-$(CONFIG_ARCH_QCOM) += talos-evk-usb1-peripheral.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtbo From bf949e86fb5c3034b70b62c9ee31b3d88d5f7fb5 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 28 Apr 2026 13:54:21 +0800 Subject: [PATCH 173/864] arm64: dts: qcom: monaco: fix wrong connection for the replicator Fix the wrong connection for the qdss replicator device. Fixes: 4f791e008807a ("arm64: dts: qcom: monaco: Add CTCU and ETR nodes") Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260428-fix-monaco-coresight-dt-v2-1-2293259bbd10@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index c1fb92135b3b..4f2163f0addf 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -3017,14 +3017,6 @@ in-ports { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - - swao_rep_out0: endpoint { - remote-endpoint = <&qdss_rep_in>; - }; - }; - port@1 { reg = <1>; @@ -3741,6 +3733,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; From f52102fc9ccbbb3c4bc01a29f3194fe07f9602f5 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Fri, 1 May 2026 11:11:29 +0200 Subject: [PATCH 174/864] arm64: dts: qcom: sc8280xp-blackrock: switch to uefi rtc offset On many Qualcomm platforms the PMIC RTC control and time registers are read-only so that the RTC time can not be updated. Instead an offset needs be stored in some machine-specific non-volatile memory, which a driver can take into account. On platforms where the offset is stored in a Qualcomm specific UEFI variable the variables are also accessed in a non-standard way, which means that the OS cannot assume that the variable service is available by the time the RTC driver probes. Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is stored in a UEFI variable so that the OS can determine whether to wait for it to become available. [1]: https://lore.kernel.org/r/20250423075143.11157-4-johan+linaro@kernel.org Fixes: 16a7fed11714 ("arm64: dts: qcom: sc8280xp-blackrock: dt definition for WDK2023") Signed-off-by: Jens Glathe Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260501-blackrock-rtc-v1-1-bddf3e37fa94@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 125af356e24b..47282e3ba866 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -763,20 +763,11 @@ &pmk8280_pon_resin { }; &pmk8280_rtc { - nvmem-cells = <&rtc_offset>; - nvmem-cell-names = "offset"; + qcom,uefi-rtc-info; status = "okay"; }; -&pmk8280_sdam_6 { - status = "okay"; - - rtc_offset: rtc-offset@bc { - reg = <0xbc 0x4>; - }; -}; - &pmk8280_vadc { channel@144 { reg = ; From a8c0bd4233a9612f200a27f535b66e71eec289a6 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Tue, 31 Mar 2026 11:47:11 +0200 Subject: [PATCH 175/864] arm64: dts: qcom: msm8953-flipkart-rimob: Enable display and GPU Add the description for the display panel found on this phone. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-3-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8953-flipkart-rimob.dts | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts index ef4faf763132..5a9d71d1e466 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts @@ -78,6 +78,13 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/msm8953/flipkart/rimob/a506_zap.mbn"; +}; &hsusb_phy { vdd-supply = <&pm8953_l3>; @@ -87,11 +94,70 @@ &hsusb_phy { status = "okay"; }; +&ibb { + qcom,discharge-resistor-kohms = <32>; +}; + +&lab { + qcom,soft-start-us = <800>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm8953_s3>; + vddio-supply = <&pm8953_l6>; + + status = "okay"; + + panel: panel@0 { + compatible = "flipkart,rimob-panel-nt35532-cs"; + reg = <0>; + + backlight = <&pmi8950_wled>; + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + avdd-supply = <&lab>; + avee-supply = <&ibb>; + vci-supply = <&pm8953_l17>; + vddi-supply = <&pm8953_l6>; + + pinctrl-0 = <&panel_default>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + vcca-supply = <&pm8953_l3>; + + status = "okay"; +}; + &pm8953_resin { linux,code = ; status = "okay"; }; +&pmi8950_wled { + qcom,current-limit-microamp = <10000>; + qcom,num-strings = <3>; + qcom,ovp-millivolt = <29500>; + + status = "okay"; +}; + &rpm_requests { regulators { compatible = "qcom,rpm-pm8953-regulators"; @@ -238,6 +304,13 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <0 4>, <135 4>; + panel_default: panel-default-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + gpio_key_default: gpio-key-default-state { pins = "gpio85"; function = "gpio"; From 15c3536da9227b5850b566f48b2135a7ecc8faf2 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Tue, 31 Mar 2026 11:47:12 +0200 Subject: [PATCH 176/864] arm64: dts: qcom: msm8953-flipkart-rimob: Enable WiFi/Bluetooth Configure and enable the WCNSS which provides WiFi and Bluetooth on this device using the WCN3660B chip. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-4-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8953-flipkart-rimob.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts index 5a9d71d1e466..db5c9f04bf1a 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts @@ -326,3 +326,18 @@ &usb3 { &usb3_dwc3 { dr_mode = "peripheral"; }; + +&wcnss { + vddpx-supply = <&pm8953_l5>; + + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; + + vddxo-supply = <&pm8953_l7>; + vddrfa-supply = <&pm8953_l19>; + vddpa-supply = <&pm8953_l9>; + vdddig-supply = <&pm8953_l5>; +}; From 74a12ff179901fcec9217ead7d2be368ddff0dd1 Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Tue, 31 Mar 2026 11:47:13 +0200 Subject: [PATCH 177/864] arm64: dts: qcom: msm8953-flipkart-rimob: Enable touchscreen This device uses a Goodix GT5688 touch controller, connected to i2c_3. Add it to the device tree. Reviewed-by: Konrad Dybcio Signed-off-by: Cristian Cozzolino Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-5-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8953-flipkart-rimob.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts index db5c9f04bf1a..060129c72264 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts @@ -94,6 +94,31 @@ &hsusb_phy { status = "okay"; }; +&i2c_3 { + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt5688"; + reg = <0x5d>; + + interrupts-extended = <&tlmm 65 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tsp_int_rst_default>; + pinctrl-names = "default"; + + irq-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>; + + VDDIO-supply = <&pm8953_l6>; + AVDD28-supply = <&pm8953_l10>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <1920>; + touchscreen-inverted-x; + touchscreen-inverted-y; + }; +}; + &ibb { qcom,discharge-resistor-kohms = <32>; }; @@ -311,6 +336,13 @@ panel_default: panel-default-state { bias-disable; }; + tsp_int_rst_default: tsp-int-rst-default-state { + pins = "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + gpio_key_default: gpio-key-default-state { pins = "gpio85"; function = "gpio"; From 349ba5a82f0c9f4cfd817dd961e57a545977a66d Mon Sep 17 00:00:00 2001 From: Cristian Cozzolino Date: Tue, 31 Mar 2026 11:47:14 +0200 Subject: [PATCH 178/864] arm64: dts: qcom: msm8953-flipkart-rimob: Enable Hall sensor Enable the Hall effect sensor (flip cover) for Billion Capture+. The GPIO is mapped to SW_LID events as in other qcom devices. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Cozzolino Link: https://lore.kernel.org/r/20260331-rimob-new-features-v5-6-5fcf42a29c12@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8953-flipkart-rimob.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts index 060129c72264..978820348fa5 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-flipkart-rimob.dts @@ -47,9 +47,18 @@ framebuffer@90001000 { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&gpio_key_default>; + pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_key_default>; pinctrl-names = "default"; + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 46 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + key-volume-up { label = "Volume Up"; gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; @@ -329,6 +338,13 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <0 4>, <135 4>; + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + panel_default: panel-default-state { pins = "gpio61"; function = "gpio"; From cc62a79bfa39e057c73828c1ed369b63d832edca Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 5 May 2026 17:08:33 +0200 Subject: [PATCH 179/864] arm64: dts: qcom: sm6350: Add interconnects for GPU, MPSS & CDSP Add some interconnect paths for the GPU, the MPSS (modem) and CDSP. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260505-sm6350-misc-v1-1-0b9efc22690c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 5d2c1d4977b4..da4d49760f2c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1530,6 +1530,9 @@ gpu: gpu@3d00000 { iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GRAPHICS_3D QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; #cooling-cells = <2>; @@ -1691,6 +1694,9 @@ mpss: remoteproc@4080000 { <&rpmhpd SM6350_MSS>; power-domain-names = "cx", "mss"; + interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + memory-region = <&pil_modem_mem>; qcom,qmp = <&aoss_qmp>; @@ -1730,6 +1736,9 @@ cdsp: remoteproc@8300000 { <&rpmhpd SM6350_MX>; power-domain-names = "cx", "mx"; + interconnects = <&compute_noc MASTER_NPU QCOM_ICC_TAG_ALWAYS + &compute_noc SLAVE_CDSP_GEM_NOC QCOM_ICC_TAG_ALWAYS>; + memory-region = <&pil_cdsp_mem>; qcom,qmp = <&aoss_qmp>; From edda2a710b87fd49bd991895f34195b6ea37e286 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 5 May 2026 17:08:34 +0200 Subject: [PATCH 180/864] arm64: dts: qcom: sm6350: Add PIL info region Define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260505-sm6350-misc-v1-2-0b9efc22690c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index da4d49760f2c..947e17b5a5eb 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2823,6 +2823,11 @@ sram@14680000 { ipa_modem_tables: modem-tables@28000 { reg = <0x28000 0x2000>; }; + + pil-reloc@2a94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x2a94c 0xc8>; + }; }; apps_smmu: iommu@15000000 { From f6e65005fe55c3d09287851523de06367cbf0bc2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 5 May 2026 17:08:35 +0200 Subject: [PATCH 181/864] arm64: dts: qcom: sm7225-fairphone-fp4: Fix address in fb node name 'reg' is 0xa0000000 so the node name is missing a zero. Add it, so that the reg and address in the node name matches. No functional impact. Fixes: 4cbea668767d ("arm64: dts: qcom: sm7225: Add device tree for Fairphone 4") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260505-sm6350-misc-v1-3-0b9efc22690c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index d959ee541d37..711a120753ad 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -48,7 +48,7 @@ chosen { stdout-path = "serial0:115200n8"; - framebuffer0: framebuffer@a000000 { + framebuffer0: framebuffer@a0000000 { compatible = "simple-framebuffer"; reg = <0 0xa0000000 0 (2340 * 1080 * 4)>; width = <1080>; From 12975c0f09c58ccf305b1383131790ea3cf6cedb Mon Sep 17 00:00:00 2001 From: Val Packett Date: Wed, 6 May 2026 18:16:53 -0300 Subject: [PATCH 182/864] arm64: dts: qcom: sm7325: Add Motorola Edge 30 (dubai) DTS The Motorola Edge 30 is a smartphone released in 2022. This commit has the following features working: - Display (simplefb) - Touchscreen - Power and volume buttons - Storage (UFS 3.1) - Battery (ADSP battmgr) - USB (Type-C, 2.0, dual-role) - Wi-Fi and Bluetooth (WCN6750 hw1.0) As there are 2 display panel options, prepare for full display support by creating a common dtsi and per-panel dts files, as is done for other upstreamed devices. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett Link: https://lore.kernel.org/r/20260506212319.682749-2-val@packett.cool Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/sm7325-motorola-dubai-common.dtsi | 1454 +++++++++++++++++ .../dts/qcom/sm7325-motorola-dubai-csot.dts | 13 + .../dts/qcom/sm7325-motorola-dubai-tianma.dts | 13 + 4 files changed, 1482 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-csot.dts create mode 100644 arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-tianma.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6be0fbb095a7..5a1c56cf98f6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -347,6 +347,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-csot.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi new file mode 100644 index 000000000000..3860ab8508a0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-common.dtsi @@ -0,0 +1,1454 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2026, Val Packett + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include +#include + +#include "sm7325.dtsi" +#include "pm7325.dtsi" +#include "pm7250b.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/ { + chassis-type = "handset"; + + aliases { + bluetooth0 = &bluetooth; + serial0 = &uart5; + serial1 = &uart7; + wifi0 = &wifi; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_mem>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,sm7325-pmic-glink", + "qcom,qcm6490-pmic-glink", + "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@ae000000 { + compatible = "ramoops"; + reg = <0x0 0xae000000 0x0 0xc0000>; + console-size = <0x40000>; + mem-type = <2>; + pmsg-size = <0x40000>; + record-size = <0x3f800>; + }; + + removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x5100000>; + no-map; + }; + + framebuffer_mem: framebuffer@e1000000 { + reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + thermal-zones { + cam-flash-thermal { + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-skin-thermal { + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + chg-thermal { + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-1-thermal { + thermal-sensors = <&pmk8350_adc_tm 5>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-2-thermal { + thermal-sensors = <&pmk8350_adc_tm 6>; + + /* Reports negative temperature. */ + status = "disabled"; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + + // S2B is really ebi.lvl but it's there for supply map completeness sake. + vreg_s2b_0p7: smpb2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b_0p7"; + + regulator-min-microvolt = <65535>; + regulator-max-microvolt = <65535>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&bt_en>; + pinctrl-names = "default"; + vddaon-supply = <&mos_0p95_aon_s10c>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&mos_0p95_dig_s10c>; + vddio-supply = <&vdd18_io>; + vddrfa0p8-supply = <&vdd09_pmu_rfa_i>; + vddrfa1p2-supply = <&vdd13_pmu_rfa_i>; + vddrfa1p7-supply = <&vdd19_pmu_rfa_i>; + vddrfa2p2-supply = <&vdd22_wlpa_s1c>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_s2b_0p7>; + vdd-l5-supply = <&vreg_s2b_0p7>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>; + vdd-l8-supply = <&vreg_s7b_0p952>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>; + vdd-l13-supply = <&vreg_s7b_0p952>; + vdd-l14-l16-supply = <&vreg_s8b_1p256>; + + /* + * S2, L4-L5 are ARCs: + * S2 - ebi.lvl, + * L4 - lmx.lvl, + * l5 - lcx.lvl. + * + * L10 are unused. + */ + + vdd19_pmu_rfa_i: + vreg_s1b_1p856: smps1 { + regulator-name = "vreg_s1b_1p856"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + mos_0p95_aon_s10c: + mos_0p95_dig_s10c: + vdd09_pmu_rfa_i: + vreg_s7b_0p952: smps7 { + regulator-name = "vreg_s7b_0p952"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_rfa_i: + vreg_s8b_1p256: smps8 { + regulator-name = "vreg_s8b_1p256"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdd_a_usbhs_3p1: + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p6: ldo3 { + regulator-name = "vreg_l3b_0p6"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vdd_a_dsi_0_1p2: + vdd_a_ufs_0_1p2: + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p776: ldo11 { + regulator-name = "vreg_l11b_1p776"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p8: ldo12 { + regulator-name = "vreg_l12b_0p8"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p8: ldo13 { + regulator-name = "vreg_l13b_0p8"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p2: ldo14 { + regulator-name = "vreg_l14b_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p88: ldo15 { + regulator-name = "vreg_l15b_0p88"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p2: ldo16 { + regulator-name = "vreg_l16b_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; + }; + + vdd18_io: + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1b_1p856>; + vdd-l2-l8-supply = <&vreg_s1b_1p856>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s7b_0p952>; + + vdd-bob-supply = <&vph_pwr>; + + /* + * S2, S5, S7, S10 are ARCs: + * S2 - cx.lvl, + * S5 - mss.lvl, + * S7 - gfx.lvl, + * S10 - mx.lvl. + */ + + vdd22_wlpa_s1c: + vreg_s1c_2p2: smps1 { + regulator-name = "vreg_s1c_2p2"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_0p676: smps9 { + regulator-name = "vreg_s9c_0p676"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vdd_a_usbhs_1p8: + vdd_qfprom: + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + iovdd_ts: + vreg_l2c_1p8: ldo2 { + regulator-name = "vreg_l2c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vdd_ts: + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8_3p0: ldo4 { + regulator-name = "vreg_l4c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8_3p0: ldo5 { + regulator-name = "vreg_l5c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_3p3: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vdd_a_dsi_0_0p9: + vdd_a_ufs_0_core: + vdd_a_usbhs_core: + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + disp_iovcc_1p8: + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + disp_vci_3p0: + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + audio_sw_vcc: + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7325/motorola/dubai/a660_zap.mbn"; +}; + +&i2c4 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + interrupts-extended = <&tlmm 6 IRQ_TYPE_LEVEL_LOW>; + + vcc-supply = <&audio_sw_vcc>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&ipa { + firmware-name = "qcom/sm7325/motorola/dubai/yupik_ipa_fws.mbn"; + memory-region = <&ipa_fw_mem>; + + qcom,gsi-loader = "self"; + + status = "okay"; +}; + +&pm7250b_adc { + channel@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "chg_skin_therm"; + }; + + channel@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + chg-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm7250b_gpios { + gpio-line-names = "FG_ALERT_N", /* GPIO_1 */ + "SLAVECP_INT", + "NC", + "NC", + "NC", + "DOUBLER_STAT", + "NC", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "NC"; +}; + +&pm7325_gpios { + gpio-line-names = "PA_THERM1", /* GPIO_1 */ + "NC", + "NC", + "PA_THERM2", + "CBL_PWR_N", + "KYPD_VOL_UP_N", + "NC", + "NC", + "NC", + "NC"; /* GPIO_10 */ + + kypd_vol_up_n: kypd-volp-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + power-source = <1>; + }; +}; + +&pm8350c_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC"; /* GPIO_9 */ +}; + +&pm8350c_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + cam-flash-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + chg-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm-1@5 { + reg = <5>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + pa-therm-2@6 { + reg = <6>; + io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO4_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_gpios { + gpio-line-names = "NC", /* GPIO_0 */ + "NC", + "TP_PMK_GPIO_3", + "PMK_OPTION"; /* GPIO_4 */ +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@44 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@145 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_cam_flash_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; + + channel@147 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_chg_therm"; + }; + + channel@14a { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_pa_therm1"; + }; + + channel@14d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_pa_therm2"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-pull-down; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-pull-down; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7325/motorola/dubai/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7325/motorola/dubai/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7325/motorola/dubai/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/sm7325/motorola/dubai/wpss.mbn"; + + status = "okay"; +}; + +&rmtfs_mem { + qcom,vmid = , + ; +}; + +&spi13 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vdd_ts>; + vddio-supply = <&iovdd_ts>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_int_n>, <&ts_reset_n>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + gpio-line-names = "NC", /* GPIO_0 */ + "NC", + "NC", + "NC", + "SMARTPA_I2C_SDA", + "SMARTPA_I2C_SCK", + "AUD_4480_DET", + "AUD_4480_INT", + "FASTCHARGE_I2C_SDA", + "FASTCHARGE_I2C_SCL", + "SM_GPSLNA_EN_GPIO10", /* GPIO_10 */ + "NC", + "PERI_I2C_SDA", + "PERI_I2C_SCL", + "NC", + "NC", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "NC", + "DISP_LDO_EN", + "CAM_FW_RST_N", /* GPIO_20 */ + "CAM_RM_RST_N", + "DBG_UART_TXD", + "DBG_UART_RXD", + "TOPSB_INT_N", + "MCAM_LDO_EN", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "UART_BT_RTS_AP_CTS", + "UART_BT_CTS_AP_RTS", + "UART_BT_RX_AP_TX", /* GPIO_30 */ + "UART_BT_TX_AP_RX", + "FRONT_60M_INT", + "FRONT_60M_RST", + "FP_INT", + "FP_RST", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_SE_SPI_NREST", /* GPIO_40 */ + "NFC_IRQ", + "RF_LDO_GPIO42_EN", + "GOOGLE_KEY_INT", /* no such key exists */ + "DISP_RST_N", + "SB_INT_N", + "HAP_RST_N", + "HAP_INT", + "ESE_SPI_MISO", + "ESE_SPI_MOSI", + "ESE_SPI_CLK", /* GPIO_50 */ + "ESE_SPI_CS", + "TP_SPI_MISO", + "TP_SPI_MOSI", + "TP_SPI_CLK", + "TP_SPI_CS_N", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "HW_ID_1", /* GPIO_60 */ + "HW_ID_2", + "CAM_PMU_EN", + "WIDE_DVDD_LDO_EN", + "CAM_MCLK0", + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", /* GPIO_70 */ + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", + "CCI_I2C_SDA2", + "CCI_I2C_SCL2", + "CCI_I2C_SDA3", + "CCI_I2C_SCL3", + "CAM_RT_RST_N", + "CAM_RU_RST_N", + "FCAM_LDO_EN", + "DISP_TE", /* GPIO_80 */ + "TP_INT_N", + "FORCED_USB_BOOT", + "SM_CDC_RST_N", + "WLAN_EN", + "BT_EN", + "WCN_SW_CTRL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "MOS_AS_EN", /* GPIO_90 */ + "NC", + "", + "NC", + "BT_FM_SLIMBUS_CLK", + "BT_FM_SLIMBUS_DATA", + "NC", + "RFCONN_DET_1", + "RF_CON_DET_2", + "RF_CON_DET_3", + "NC", /* GPIO_100 */ + "NC", + "NC", + "ACCEL_INT", + "NC", + "TP_RST_N", + "NC", + "NC", + "NC", + "UIM2_DATA", + "UIM2_CLK", /* GPIO_110 */ + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "UIM1_PRESENT", + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", /* GPIO_120 */ + "PA_MUTING", + "SM_GRFC5", + "LAA_RX", + "SM_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", + "WLAN_COEX_UART_RX", + "WLAN_COEX_UART_TX", + "NC", + "NC", /* GPIO_130 */ + "SM_GRFC12", + "NC", + "QLINK0_REQUEST", + "QLINK0_ENABLE", + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", /* GPIO_140 */ + "SAR_INT_N", + "PROX_INT_N", + "", + "SM_SWR_TX_CLK", + "SM_SWR_TX_DATA0", + "SM_SWR_TX_DATA1", + "SM_SWR_RX_CLK", + "SM_SWR_RX_DATA0", + "SM_SWR_RX_DATA1", + "NC", /* GPIO_150 */ + "NC", + "NC", + "NC", + "SB_MI2S_SCK", + "SB_MI2S_WS", + "SB_MI2S_RXDAT_AP_TX", + "SB_MI2S_TXDAT_AP_RX", + "NC", + "SNS_I3C0_SDA", + "SNS_I3C0_SCL", /* GPIO_160 */ + "SSC_I2C4_SDA", + "SSC_I2C4_SCL", + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "NC", + "NC", + "", + "", + "", + "", /* GPIO_170 */ + "SSC_BT_UART4_TX", + "SSC_BT_UART4_RX", + "NC", + "NC"; + gpio-reserved-ranges = <48 4>, /* SPI (eSE - embedded Secure Element) */ + <56 4>; /* SPI (fingerprint reader) */ + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + oled_reset_n: oled-reset-n-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + aw86224_reset_default: aw86224-reset-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + aw86224_int_default: aw86224-int-default-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + mdp_vsync_p: mdp-vsync-p-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_int_n: ts-int-n-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + bt_en: bt-en-state { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + + ts_reset_n: ts-int-n-state { + pins = "gpio105"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + + max-speed = <3200000>; + + qcom,local-bd-address-broken; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vdd_a_ufs_0_core>; + vdda-pll-supply = <&vdd_a_ufs_0_1p2>; + + status = "okay"; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + maximum-speed = "high-speed"; + + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda18-supply = <&vdd_a_usbhs_1p8>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm7325/motorola/dubai/vpu20_1v.mbn"; + + status = "okay"; +}; + +&wifi { + qcom,calibration-variant = "Motorola_dubai"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-csot.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-csot.dts new file mode 100644 index 000000000000..d53a729f71da --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-csot.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2026, Val Packett + */ + +/dts-v1/; + +#include "sm7325-motorola-dubai-common.dtsi" + +/ { + model = "Motorola Edge 30 (CSOT)"; + compatible = "motorola,dubai", "qcom,sm7325"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-tianma.dts b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-tianma.dts new file mode 100644 index 000000000000..7b843c407f88 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-motorola-dubai-tianma.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2026, Val Packett + */ + +/dts-v1/; + +#include "sm7325-motorola-dubai-common.dtsi" + +/ { + model = "Motorola Edge 30 (Tianma)"; + compatible = "motorola,dubai", "qcom,sm7325"; +}; From a8fd72fcf305534f0a8da095de2cce467b73e66c Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Thu, 7 May 2026 22:16:07 +0800 Subject: [PATCH 183/864] arm64: dts: qcom: sc8280xp: Move PHY, PERST, and Wake GPIOs to PCIe port nodes Since describing the PCIe PHY directly under the RC node is now deprecated, move the references to the respective PCIe port nodes. And also move the PCIe PERST and wake GPIOs from the controller nodes to the corresponding PCIe port nodes on sc8280xp-based platforms: - sa8295p-adp - sa8540p-ride - sc8280xp-crd - sc8280xp-huawei-gaokun3 - sc8280xp-lenovo-thinkpad-x13s - sc8280xp-microsoft-arcata - sc8280xp-microsoft-blackrock Signed-off-by: Xilin Wu Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-8280-move-perst-wake-v1-1-5b33cef2d807@radxa.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 32 ++++++++++++------- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 16 ++++++---- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 22 +++++++------ .../boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 14 ++++---- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++------ .../dts/qcom/sc8280xp-microsoft-arcata.dts | 22 +++++++------ .../dts/qcom/sc8280xp-microsoft-blackrock.dts | 14 ++++---- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++--------- 8 files changed, 95 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index d28d69162427..512de3597581 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -453,15 +453,17 @@ &mdss1_dp3_phy { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -472,15 +474,17 @@ &pcie2a_phy { &pcie3a { num-lanes = <2>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -489,15 +493,17 @@ &pcie3a_phy { }; &pcie3b { - perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; +&pcie3b_port0 { + reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie3b_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -506,15 +512,17 @@ &pcie3b_phy { }; &pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 44177e9b64b5..83d5f1d9e79b 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -366,15 +366,17 @@ &pcie2a { <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "disabled"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -387,15 +389,17 @@ &pcie3a { <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index dcdeefd28728..67f0576f2824 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -628,9 +628,6 @@ keyboard@68 { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -646,10 +643,12 @@ &pcie2a_phy { status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; +&pcie3a { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -665,12 +664,14 @@ &pcie3a_phy { status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -687,6 +688,9 @@ &pcie4_phy { }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index f3c00be67081..aa408f435b28 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -739,9 +739,6 @@ &mdss0_dp1_out { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -757,12 +754,14 @@ &pcie2a_phy { status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -772,6 +771,9 @@ &pcie4 { }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index abd9c5a67b9f..7b21eca62908 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -933,9 +933,6 @@ keyboard@68 { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -951,10 +948,12 @@ &pcie2a_phy { status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; +&pcie3a { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -970,12 +969,14 @@ &pcie3a_phy { status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -985,6 +986,9 @@ &pcie4 { }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index f2b4470d4407..3d589f05b90e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -486,9 +486,6 @@ &mdss0_dp1_out { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -504,10 +501,12 @@ &pcie2a_phy { status = "okay"; }; -&pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; +&pcie3a { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie3a_default>; @@ -523,12 +522,14 @@ &pcie3a_phy { status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -538,6 +539,9 @@ &pcie4 { }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 47282e3ba866..9da2ffb318d0 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -624,9 +624,6 @@ &mdss0_dp2_phy { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -642,12 +639,14 @@ &pcie2a_phy { status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -657,6 +656,9 @@ &pcie4 { }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a2bd6b10e475..1c2bb7b07d93 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2220,9 +2220,6 @@ pcie4: pcie@1c00000 { power-domains = <&gcc PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie4_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie4_port0: pcie@0 { @@ -2230,6 +2227,8 @@ pcie4_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie4_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2331,9 +2330,6 @@ pcie3b: pcie@1c08000 { power-domains = <&gcc PCIE_3B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3b_port0: pcie@0 { @@ -2341,6 +2337,8 @@ pcie3b_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3b_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2442,9 +2440,6 @@ pcie3a: pcie@1c10000 { power-domains = <&gcc PCIE_3A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3a_port0: pcie@0 { @@ -2452,6 +2447,8 @@ pcie3a_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3a_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2556,9 +2553,6 @@ pcie2b: pcie@1c18000 { power-domains = <&gcc PCIE_2B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2b_port0: pcie@0 { @@ -2566,6 +2560,8 @@ pcie2b_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie2b_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2667,9 +2663,6 @@ pcie2a: pcie@1c20000 { power-domains = <&gcc PCIE_2A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2a_port0: pcie@0 { @@ -2677,6 +2670,8 @@ pcie2a_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie2a_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From dd06f466da5247cbdcaed2bca738701b044bd8da Mon Sep 17 00:00:00 2001 From: Antony Kurniawan Soemardi Date: Sun, 10 May 2026 07:01:37 +0000 Subject: [PATCH 184/864] ARM: dts: qcom: pm8921: add labels for ADC channels Add label properties to all XOADC ADC channel nodes in the PM8921 PMIC device tree. This allows userspace and drivers to identify channels by name rather than relying on datasheet name. Acked-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Antony Kurniawan Soemardi Link: https://lore.kernel.org/r/20260510-pm8xxx-xoadc-label-v6-2-49700fd03005@smankusors.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/pm8921.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom/pm8921.dtsi b/arch/arm/boot/dts/qcom/pm8921.dtsi index 535cb6a2543f..15246f4bd267 100644 --- a/arch/arm/boot/dts/qcom/pm8921.dtsi +++ b/arch/arm/boot/dts/qcom/pm8921.dtsi @@ -75,50 +75,62 @@ pm8921_xoadc: xoadc@197 { vcoin: adc-channel@0 { reg = <0x00 0x00>; + label = "vcoin"; }; vbat: adc-channel@1 { reg = <0x00 0x01>; + label = "vbat"; }; dcin: adc-channel@2 { reg = <0x00 0x02>; + label = "dcin"; }; vph_pwr: adc-channel@4 { reg = <0x00 0x04>; + label = "vph_pwr"; }; batt_therm: adc-channel@8 { reg = <0x00 0x08>; + label = "batt_therm"; }; batt_id: adc-channel@9 { reg = <0x00 0x09>; + label = "batt_id"; }; usb_vbus: adc-channel@a { reg = <0x00 0x0a>; + label = "usb_vbus"; }; die_temp: adc-channel@b { reg = <0x00 0x0b>; + label = "die_temp"; }; ref_625mv: adc-channel@c { reg = <0x00 0x0c>; + label = "ref_625mv"; }; ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; + label = "ref_1250mv"; }; chg_temp: adc-channel@e { reg = <0x00 0x0e>; + label = "chg_temp"; }; ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; + label = "ref_muxoff"; }; }; }; From eba1bea1123924f8bf187ad175d1667036f34e80 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 6 Jan 2026 21:35:13 -0800 Subject: [PATCH 185/864] arm64: dts: qcom: ipq5332: Add CMN PLL node for networking hardware Add the CMN PLL node required for networking hardware operation on IPQ5332. The CMN PLL core runs at 6 GHz on this platform, differing from others like IPQ9574. Configure the reference clock path where XO (48 MHz or 96 MHz) routes through the WiFi block's multiplier/divider to provide a stable 48 MHz reference to the CMN PLL. .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-4-f9f7e4efbd79@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/ipq5332-rdp-common.dtsi | 17 ++++++++++- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++- 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi index 8967861be5fd..e364a5deec49 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -2,7 +2,7 @@ /* * IPQ5332 RDP board common device tree source * - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ /dts-v1/; @@ -55,6 +55,17 @@ &blsp1_uart0 { status = "okay"; }; +/* + * The bootstrap pins for the board select the XO clock frequency that + * supports 48 MHZ or 96 MHZ. This setting automatically enables the + * right dividers, to ensure the reference clock output from WiFi to + * the CMN PLL is 48 MHZ. + */ +&ref_48mhz_clk { + clock-div = <1>; + clock-mult = <1>; +}; + &sleep_clk { clock-frequency = <32000>; }; @@ -63,6 +74,10 @@ &xo_board { clock-frequency = <24000000>; }; +&xo_clk { + clock-frequency = <48000000>; +}; + /* PINCTRL */ &tlmm { gpio_keys_default: gpio-keys-default-state { diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 27504b7cfe9e..529abeb1f3bd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -2,10 +2,11 @@ /* * IPQ5332 device tree source * - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ #include +#include #include #include #include @@ -16,6 +17,12 @@ / { #size-cells = <2>; clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible = "fixed-factor-clock"; + clocks = <&xo_clk>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -25,6 +32,11 @@ xo_board: xo-board-clk { compatible = "fixed-clock"; #clock-cells = <0>; }; + + xo_clk: xo-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus { @@ -167,6 +179,20 @@ usbphy0: phy@7b000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq5332-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_48mhz_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", + "ahb", + "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ5332_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <6000000000>; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x721>; From 985650336dcfe8fa640196a49956c5983dfe2696 Mon Sep 17 00:00:00 2001 From: Luo Jie Date: Tue, 6 Jan 2026 21:35:14 -0800 Subject: [PATCH 186/864] arm64: dts: qcom: ipq5332: Represent xo_board as fixed-factor clock The xo_board clock is derived from the 48 MHz WiFi output clock (divided by 2), and not a standalone fixed frequency source. The previous implementation incorrectly modelled it as a fixed-clock with fixed frequency, which doesn't reflect the actual hardware clock tree. Update for fixed-factor-clock compatibility, and properly reference the source clock. Reviewed-by: Konrad Dybcio Signed-off-by: Luo Jie Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-5-f9f7e4efbd79@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 7 ++++++- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi index e364a5deec49..3bbf748f2e5c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -70,8 +70,13 @@ &sleep_clk { clock-frequency = <32000>; }; +/* + * The frequency of xo_board is fixed to 24 MHZ, which is routed + * from WiFi output clock 48 MHZ divided by 2. + */ &xo_board { - clock-frequency = <24000000>; + clock-div = <2>; + clock-mult = <1>; }; &xo_clk { diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 529abeb1f3bd..fbc6c4d37fa3 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -29,7 +29,8 @@ sleep_clk: sleep-clk { }; xo_board: xo-board-clk { - compatible = "fixed-clock"; + compatible = "fixed-factor-clock"; + clocks = <&ref_48mhz_clk>; #clock-cells = <0>; }; From 88f8e2ca76ee9999c1f21d020362e6588a6d5ef5 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Mon, 30 Mar 2026 10:13:48 +0000 Subject: [PATCH 187/864] arm64: dts: qcom: sm6125: Use 64 bit addressing SM6125's SMMU uses 36bit VAs, which is a good indicator that we should increase (dma-)ranges - and by extension #address- and #size-cells to prevent things from getting lost in translation (both literally and figuratively). Do so. Fixes: 7bb7c90e0ac1 ("arm64: dts: qcom: Add Redmi Note 8T") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202603141433.MDqfoVHn-lkp@intel.com/ Reviewed-by: Konrad Dybcio Signed-off-by: Biswapriyo Nath Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-1-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 153 ++++++++++++++------------- 1 file changed, 78 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 6e84c226948c..a3caf5c87ae7 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -374,22 +374,23 @@ smem: smem { }; soc@0 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x00 0xffffffff>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; tcsr_mutex: hwlock@340000 { compatible = "qcom,tcsr-mutex"; - reg = <0x00340000 0x20000>; + reg = <0x0 0x00340000 0x0 0x20000>; #hwlock-cells = <1>; }; tlmm: pinctrl@500000 { compatible = "qcom,sm6125-tlmm"; - reg = <0x00500000 0x400000>, - <0x00900000 0x400000>, - <0x00d00000 0x400000>; + reg = <0x0 0x00500000 0x0 0x400000>, + <0x0 0x00900000 0x0 0x400000>, + <0x0 0x00d00000 0x0 0x400000>; reg-names = "west", "south", "east"; interrupts = ; gpio-controller; @@ -672,7 +673,7 @@ qup_uart4_default: qup-uart4-default-state { gcc: clock-controller@1400000 { compatible = "qcom,gcc-sm6125"; - reg = <0x01400000 0x1f0000>; + reg = <0x0 0x01400000 0x0 0x1f0000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -682,7 +683,7 @@ gcc: clock-controller@1400000 { hsusb_phy1: phy@1613000 { compatible = "qcom,msm8996-qusb2-phy"; - reg = <0x01613000 0x180>; + reg = <0x0 0x01613000 0x0 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_AHB2PHY_USB_CLK>, @@ -695,18 +696,18 @@ hsusb_phy1: phy@1613000 { rng: rng@1b53000 { compatible = "qcom,prng-ee"; - reg = <0x01b53000 0x1000>; + reg = <0x0 0x01b53000 0x0 0x1000>; clocks = <&gcc GCC_PRNG_AHB_CLK>; clock-names = "core"; }; spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -720,12 +721,13 @@ spmi_bus: spmi@1c40000 { rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x045f0000 0x7000>; + reg = <0x0 0x045f0000 0x0 0x7000>; }; sdhc_1: mmc@4744000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x04744000 0x1000>, <0x04745000 0x1000>; + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>; reg-names = "hc", "cqhci"; interrupts = , @@ -752,7 +754,7 @@ sdhc_1: mmc@4744000 { sdhc_2: mmc@4784000 { compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; - reg = <0x04784000 0x1000>; + reg = <0x0 0x04784000 0x0 0x1000>; reg-names = "hc"; interrupts = , @@ -780,7 +782,8 @@ sdhc_2: mmc@4784000 { ufs_mem_hc: ufshc@4804000 { compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg = <0x0 0x04804000 0x0 0x3000>, + <0x0 0x04810000 0x0 0x8000>; reg-names = "std", "ice"; interrupts = ; @@ -825,7 +828,7 @@ ufs_mem_hc: ufshc@4804000 { ufs_mem_phy: phy@4807000 { compatible = "qcom,sm6125-qmp-ufs-phy"; - reg = <0x04807000 0xdb8>; + reg = <0x0 0x04807000 0x0 0xdb8>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, @@ -846,7 +849,7 @@ ufs_mem_phy: phy@4807000 { gpi_dma0: dma-controller@4a00000 { compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0x04a00000 0x60000>; + reg = <0x0 0x04a00000 0x0 0x60000>; interrupts = , , , @@ -864,19 +867,19 @@ gpi_dma0: dma-controller@4a00000 { qupv3_id_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x04ac0000 0x2000>; + reg = <0x0 0x04ac0000 0x0 0x2000>; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0x123 0x0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; i2c0: i2c@4a80000 { compatible = "qcom,geni-i2c"; - reg = <0x04a80000 0x4000>; + reg = <0x0 0x04a80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; interrupts = ; @@ -893,7 +896,7 @@ i2c0: i2c@4a80000 { spi0: spi@4a80000 { compatible = "qcom,geni-spi"; - reg = <0x04a80000 0x4000>; + reg = <0x0 0x04a80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; clock-names = "se"; interrupts = ; @@ -910,7 +913,7 @@ spi0: spi@4a80000 { i2c1: i2c@4a84000 { compatible = "qcom,geni-i2c"; - reg = <0x04a84000 0x4000>; + reg = <0x0 0x04a84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; interrupts = ; @@ -927,7 +930,7 @@ i2c1: i2c@4a84000 { i2c2: i2c@4a88000 { compatible = "qcom,geni-i2c"; - reg = <0x04a88000 0x4000>; + reg = <0x0 0x04a88000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; interrupts = ; @@ -944,7 +947,7 @@ i2c2: i2c@4a88000 { spi2: spi@4a88000 { compatible = "qcom,geni-spi"; - reg = <0x04a88000 0x4000>; + reg = <0x0 0x04a88000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; interrupts = ; @@ -961,7 +964,7 @@ spi2: spi@4a88000 { i2c3: i2c@4a8c000 { compatible = "qcom,geni-i2c"; - reg = <0x04a8c000 0x4000>; + reg = <0x0 0x04a8c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; interrupts = ; @@ -978,7 +981,7 @@ i2c3: i2c@4a8c000 { i2c4: i2c@4a90000 { compatible = "qcom,geni-i2c"; - reg = <0x04a90000 0x4000>; + reg = <0x0 0x04a90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; interrupts = ; @@ -995,7 +998,7 @@ i2c4: i2c@4a90000 { uart4: serial@4a90000 { compatible = "qcom,geni-debug-uart"; - reg = <0x04a90000 0x4000>; + reg = <0x0 0x04a90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; clock-names = "se"; interrupts = ; @@ -1007,7 +1010,7 @@ uart4: serial@4a90000 { gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; - reg = <0x04c00000 0x60000>; + reg = <0x0 0x04c00000 0x0 0x60000>; interrupts = , , , @@ -1025,19 +1028,19 @@ gpi_dma1: dma-controller@4c00000 { qupv3_id_1: geniqup@4cc0000 { compatible = "qcom,geni-se-qup"; - reg = <0x04cc0000 0x2000>; + reg = <0x0 0x04cc0000 0x0 0x2000>; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; clock-names = "m-ahb", "s-ahb"; iommus = <&apps_smmu 0x143 0x0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; i2c5: i2c@4c80000 { compatible = "qcom,geni-i2c"; - reg = <0x04c80000 0x4000>; + reg = <0x0 0x04c80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; interrupts = ; @@ -1054,7 +1057,7 @@ i2c5: i2c@4c80000 { spi5: spi@4c80000 { compatible = "qcom,geni-spi"; - reg = <0x04c80000 0x4000>; + reg = <0x0 0x04c80000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; clock-names = "se"; interrupts = ; @@ -1071,7 +1074,7 @@ spi5: spi@4c80000 { i2c6: i2c@4c84000 { compatible = "qcom,geni-i2c"; - reg = <0x04c84000 0x4000>; + reg = <0x0 0x04c84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; interrupts = ; @@ -1088,7 +1091,7 @@ i2c6: i2c@4c84000 { spi6: spi@4c84000 { compatible = "qcom,geni-spi"; - reg = <0x04c84000 0x4000>; + reg = <0x0 0x04c84000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; clock-names = "se"; interrupts = ; @@ -1105,7 +1108,7 @@ spi6: spi@4c84000 { i2c7: i2c@4c88000 { compatible = "qcom,geni-i2c"; - reg = <0x04c88000 0x4000>; + reg = <0x0 0x04c88000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; clock-names = "se"; interrupts = ; @@ -1122,7 +1125,7 @@ i2c7: i2c@4c88000 { i2c8: i2c@4c8c000 { compatible = "qcom,geni-i2c"; - reg = <0x04c8c000 0x4000>; + reg = <0x0 0x04c8c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; interrupts = ; @@ -1139,7 +1142,7 @@ i2c8: i2c@4c8c000 { spi8: spi@4c8c000 { compatible = "qcom,geni-spi"; - reg = <0x04c8c000 0x4000>; + reg = <0x0 0x04c8c000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; clock-names = "se"; interrupts = ; @@ -1156,7 +1159,7 @@ spi8: spi@4c8c000 { i2c9: i2c@4c90000 { compatible = "qcom,geni-i2c"; - reg = <0x04c90000 0x4000>; + reg = <0x0 0x04c90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; interrupts = ; @@ -1173,7 +1176,7 @@ i2c9: i2c@4c90000 { spi9: spi@4c90000 { compatible = "qcom,geni-spi"; - reg = <0x04c90000 0x4000>; + reg = <0x0 0x04c90000 0x0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; clock-names = "se"; interrupts = ; @@ -1191,9 +1194,9 @@ spi9: spi@4c90000 { usb3: usb@4ef8800 { compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; - reg = <0x04ef8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x0 0x04ef8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; ranges; clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, @@ -1228,7 +1231,7 @@ usb3: usb@4ef8800 { usb3_dwc3: usb@4e00000 { compatible = "snps,dwc3"; - reg = <0x04e00000 0xcd00>; + reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = ; iommus = <&apps_smmu 0x100 0x0>; phys = <&hsusb_phy1>; @@ -1244,12 +1247,12 @@ usb3_dwc3: usb@4e00000 { sram@4690000 { compatible = "qcom,rpm-stats"; - reg = <0x04690000 0x10000>; + reg = <0x0 0x04690000 0x0 0x10000>; }; mdss: display-subsystem@5e00000 { compatible = "qcom,sm6125-mdss"; - reg = <0x05e00000 0x1000>; + reg = <0x0 0x05e00000 0x0 0x1000>; reg-names = "mdss"; interrupts = ; @@ -1269,16 +1272,16 @@ mdss: display-subsystem@5e00000 { iommus = <&apps_smmu 0x400 0x0>; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; status = "disabled"; mdss_mdp: display-controller@5e01000 { compatible = "qcom,sm6125-dpu"; - reg = <0x05e01000 0x83208>, - <0x05eb0000 0x3000>; + reg = <0x0 0x05e01000 0x0 0x83208>, + <0x0 0x05eb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; interrupt-parent = <&mdss>; @@ -1348,7 +1351,7 @@ opp-400000000 { mdss_dsi0: dsi@5e94000 { compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x05e94000 0x400>; + reg = <0x0 0x05e94000 0x0 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -1417,9 +1420,9 @@ opp-187500000 { mdss_dsi0_phy: phy@5e94400 { compatible = "qcom,sm6125-dsi-phy-14nm"; - reg = <0x05e94400 0x100>, - <0x05e94500 0x300>, - <0x05e94800 0x188>; + reg = <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -1441,7 +1444,7 @@ mdss_dsi0_phy: phy@5e94400 { dispcc: clock-controller@5f00000 { compatible = "qcom,sm6125-dispcc"; - reg = <0x05f00000 0x20000>; + reg = <0x0 0x05f00000 0x0 0x20000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, @@ -1470,7 +1473,7 @@ dispcc: clock-controller@5f00000 { apps_smmu: iommu@c600000 { compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; - reg = <0x0c600000 0x80000>; + reg = <0x0 0x0c600000 0x0 0x80000>; interrupts = , , , @@ -1544,74 +1547,74 @@ apps_smmu: iommu@c600000 { apcs_glb: mailbox@f111000 { compatible = "qcom,sm6125-apcs-hmss-global", "qcom,msm8994-apcs-kpss-global"; - reg = <0x0f111000 0x1000>; + reg = <0x0 0x0f111000 0x0 0x1000>; #mbox-cells = <1>; }; timer@f120000 { compatible = "arm,armv7-timer-mem"; - #address-cells = <1>; + #address-cells = <2>; #size-cells = <1>; - ranges; - reg = <0x0f120000 0x1000>; + reg = <0x0 0x0f120000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; clock-frequency = <19200000>; frame@f121000 { frame-number = <0>; interrupts = , ; - reg = <0x0f121000 0x1000>, - <0x0f122000 0x1000>; + reg = <0x0 0x0f121000 0x1000>, + <0x0 0x0f122000 0x1000>; }; frame@f123000 { frame-number = <1>; interrupts = ; - reg = <0x0f123000 0x1000>; + reg = <0x0 0x0f123000 0x1000>; status = "disabled"; }; frame@f124000 { frame-number = <2>; interrupts = ; - reg = <0x0f124000 0x1000>; + reg = <0x0 0x0f124000 0x1000>; status = "disabled"; }; frame@f125000 { frame-number = <3>; interrupts = ; - reg = <0x0f125000 0x1000>; + reg = <0x0 0x0f125000 0x1000>; status = "disabled"; }; frame@f126000 { frame-number = <4>; interrupts = ; - reg = <0x0f126000 0x1000>; + reg = <0x0 0x0f126000 0x1000>; status = "disabled"; }; frame@f127000 { frame-number = <5>; interrupts = ; - reg = <0x0f127000 0x1000>; + reg = <0x0 0x0f127000 0x1000>; status = "disabled"; }; frame@f128000 { frame-number = <6>; interrupts = ; - reg = <0x0f128000 0x1000>; + reg = <0x0 0x0f128000 0x1000>; status = "disabled"; }; }; intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; - reg = <0x0f200000 0x20000>, - <0x0f300000 0x100000>; + reg = <0x0 0x0f200000 0x0 0x20000>, + <0x0 0x0f300000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; From 222f161a873f198301497f22ae0dd089f30e9b75 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Mon, 30 Mar 2026 10:13:50 +0000 Subject: [PATCH 188/864] arm64: dts: qcom: sm6125-xiaomi-ginkgo: Enable vibrator Enable the vibrator on the PMI632 which is used on this phone. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Biswapriyo Nath Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-3-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi index 7eecd9dc3028..88691f1fa3a1 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -12,6 +12,7 @@ #include #include "sm6125.dtsi" #include "pm6125.dtsi" +#include "pmi632.dtsi" /delete-node/ &adsp_pil_mem; /delete-node/ &cont_splash_mem; @@ -115,6 +116,10 @@ &hsusb_phy1 { status = "okay"; }; +&pmi632_vib { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; From 3df39679bfcb46a3475b0e8d0b31cfcb07def9c4 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Mon, 30 Mar 2026 10:13:51 +0000 Subject: [PATCH 189/864] arm64: dts: qcom: sm6125: Enable USB-C port handling Plug in USB-C related bits and pieces to enable USB role switching. Also, remove dr_mode to enable OTG capability. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Biswapriyo Nath Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-4-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a3caf5c87ae7..86de1560bdef 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1241,7 +1241,20 @@ usb3_dwc3: usb@4e00000 { snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; maximum-speed = "high-speed"; - dr_mode = "peripheral"; + + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dwc3_hs: endpoint { + }; + }; + }; }; }; From c1da9374c3e08c6eb06106256cac3875fb5c467f Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Mon, 30 Mar 2026 10:13:52 +0000 Subject: [PATCH 190/864] arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add PMI632 Type-C property The USB-C port is used for powering external devices and transfer data from/to them. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Biswapriyo Nath Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-5-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi index 88691f1fa3a1..f66ff5f7693b 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -116,6 +116,33 @@ &hsusb_phy1 { status = "okay"; }; +&pmi632_typec { + status = "okay"; + + connector { + compatible = "usb-c-connector"; + + power-role = "dual"; + data-role = "dual"; + self-powered; + + typec-power-opmode = "default"; + pd-disable; + + port { + pmi632_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + }; +}; + +&pmi632_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <1000000>; + status = "okay"; +}; + &pmi632_vib { status = "okay"; }; @@ -316,3 +343,7 @@ &uart4 { &usb3 { status = "okay"; }; + +&usb_dwc3_hs { + remote-endpoint = <&pmi632_hs_in>; +}; From 474dedd7f653be26ce5385f46ff2b7a3282a359f Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Mon, 30 Mar 2026 10:13:54 +0000 Subject: [PATCH 191/864] arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add IR transmitter The IR transmitting LED is connected to SPI8 controller. Reviewed-by: Sean Young Reviewed-by: Konrad Dybcio Signed-off-by: Biswapriyo Nath Link: https://lore.kernel.org/r/20260330-ginkgo-add-usb-ir-vib-v3-7-c4b778b0d7f8@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi index f66ff5f7693b..7d8481173171 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -99,6 +99,10 @@ key-volume-up { }; }; +&gpi_dma1 { + status = "okay"; +}; + &pm6125_gpios { vol_up_n: vol-up-n-state { pins = "gpio5"; @@ -160,6 +164,10 @@ &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm6125-regulators"; @@ -332,6 +340,18 @@ &sdhc_2 { status = "okay"; }; +&spi8 { + status = "okay"; + + irled@1 { + compatible = "ir-spi-led"; + reg = <1>; + + duty-cycle = /bits/ 8 <30>; + spi-max-frequency = <1000000>; + }; +}; + &tlmm { gpio-reserved-ranges = <0 4>, <30 4>; }; From 204242d747e67e7483256fc927d0ab19a63a54d2 Mon Sep 17 00:00:00 2001 From: Xilin Wu Date: Thu, 7 May 2026 22:25:14 +0800 Subject: [PATCH 192/864] arm64: dts: qcom: sc8280xp: Add reg and clocks for QoS configuration Add register ranges for the SC8280XP interconnect providers so the driver can program the NoC QoS registers. Move the real NoC providers under soc@0, keep clk_virt and mc_virt as virtual top-level providers, and add the clocks required for QoS programming on aggre1_noc and aggre2_noc. Signed-off-by: Xilin Wu Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260507-sc8280xp-qos-v1-3-15135858cd98@radxa.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 157 +++++++++++++++---------- 1 file changed, 97 insertions(+), 60 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 1c2bb7b07d93..5784c5dc171c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -314,78 +314,18 @@ scm: scm { }; }; - aggre1_noc: interconnect-aggre1-noc { - compatible = "qcom,sc8280xp-aggre1-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect-aggre2-noc { - compatible = "qcom,sc8280xp-aggre2-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - clk_virt: interconnect-clk-virt { compatible = "qcom,sc8280xp-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - config_noc: interconnect-config-noc { - compatible = "qcom,sc8280xp-config-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - dc_noc: interconnect-dc-noc { - compatible = "qcom,sc8280xp-dc-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect-gem-noc { - compatible = "qcom,sc8280xp-gem-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_noc: interconnect-lpass-ag-noc { - compatible = "qcom,sc8280xp-lpass-ag-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - mc_virt: interconnect-mc-virt { compatible = "qcom,sc8280xp-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - mmss_noc: interconnect-mmss-noc { - compatible = "qcom,sc8280xp-mmss-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - nspa_noc: interconnect-nspa-noc { - compatible = "qcom,sc8280xp-nspa-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - nspb_noc: interconnect-nspb-noc { - compatible = "qcom,sc8280xp-nspb-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect-system-noc { - compatible = "qcom,sc8280xp-system-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -2152,6 +2092,63 @@ rng: rng@10d3000 { clock-names = "core"; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sc8280xp-config-noc"; + reg = <0 0x01500000 0 0x2c000>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sc8280xp-system-noc"; + reg = <0 0x01680000 0 0x1a400>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible = "qcom,sc8280xp-aggre1-noc"; + reg = <0 0x016c0000 0 0x3af80>; + + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sc8280xp-aggre2-noc"; + reg = <0 0x01700000 0 0x3af80>; + + clocks = <&gcc GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sc8280xp-mmss-noc"; + reg = <0 0x01740000 0 0x1fa80>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + pcie4: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-sc8280xp"; @@ -3374,6 +3371,14 @@ lpasscc: clock-controller@33e0000 { #reset-cells = <1>; }; + lpass_noc: interconnect@3c40000 { + compatible = "qcom,sc8280xp-lpass-ag-noc"; + reg = <0 0x03c40000 0 0xf080>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-690.0", "qcom,adreno"; @@ -3949,6 +3954,22 @@ opp-6 { }; }; + dc_noc: interconnect@90e0000 { + compatible = "qcom,sc8280xp-dc-noc"; + reg = <0 0x090e0000 0 0x5080>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,sc8280xp-gem-noc"; + reg = <0 0x09100000 0 0xb8400>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, @@ -5999,6 +6020,14 @@ cpufreq_hw: cpufreq@18591000 { #clock-cells = <1>; }; + nspa_noc: interconnect@1b0c0000 { + compatible = "qcom,sc8280xp-nspa-noc"; + reg = <0 0x1b0c0000 0 0x10000>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + remoteproc_nsp0: remoteproc@1b300000 { compatible = "qcom,sc8280xp-nsp0-pas"; reg = <0 0x1b300000 0 0x10000>; @@ -6134,6 +6163,14 @@ compute-cb@14 { }; }; + nspb_noc: interconnect@210c0000 { + compatible = "qcom,sc8280xp-nspb-noc"; + reg = <0 0x210c0000 0 0x10000>; + + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + remoteproc_nsp1: remoteproc@21300000 { compatible = "qcom,sc8280xp-nsp1-pas"; reg = <0 0x21300000 0 0x10000>; From 365dfdeb96a830b8df2521e03f080cae3e55d79a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 16:34:02 +0200 Subject: [PATCH 193/864] arm64: dts: qcom: sm8650: Correct and complete DP address spaces DisplayPort block on Qualcomm SM8650 has few too short address space ranges and misses four more spaces. Complete the hardware description, which in the future might be important for full feature support. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-6-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 74381ac363ee..dcdc2ce57a81 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5875,11 +5875,15 @@ mdss_dsi1_phy: phy@ae97000 { mdss_dp0: displayport-controller@af54000 { compatible = "qcom,sm8650-dp"; - reg = <0 0xaf54000 0 0x104>, - <0 0xaf54200 0 0xc0>, - <0 0xaf55000 0 0x770>, - <0 0xaf56000 0 0x9c>, - <0 0xaf57000 0 0x9c>; + reg = <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>, + <0x0 0x0af58000 0x0 0x400>, + <0x0 0x0af59000 0x0 0x400>, + <0x0 0x0af5a000 0x0 0x600>, + <0x0 0x0af5b000 0x0 0x600>; interrupts-extended = <&mdss 12>; From ae607f8cd3a1c22c75d52034964b546c95a4d8f2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 16:34:03 +0200 Subject: [PATCH 194/864] arm64: dts: qcom: sm8750: Correct and complete DP address spaces DisplayPort block on Qualcomm SM8750 has few too short address space ranges and misses four more spaces. Complete the hardware description, which in the future might be important for full feature support. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-7-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 900dac6bf6d9..58a457c00feb 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3358,11 +3358,15 @@ mdss_dsi1_phy: phy@ae97000 { mdss_dp0: displayport-controller@af54000 { compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; - reg = <0x0 0xaf54000 0x0 0x104>, - <0x0 0xaf54200 0x0 0xc0>, - <0x0 0xaf55000 0x0 0x770>, - <0x0 0xaf56000 0x0 0x9c>, - <0x0 0xaf57000 0x0 0x9c>; + reg = <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>, + <0x0 0x0af58000 0x0 0x400>, + <0x0 0x0af59000 0x0 0x400>, + <0x0 0x0af5a000 0x0 0x600>, + <0x0 0x0af5b000 0x0 0x600>; interrupts-extended = <&mdss 12>; From 4fd832d6aed496c7111746d2c1e36b006659f89d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Apr 2026 16:34:04 +0200 Subject: [PATCH 195/864] arm64: dts: qcom: sm8750: Correct DPU VBIF address space size VBIF register range is 0x3000 long, so correct the code even though missing part seems without practical impact. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260405-dts-qcom-display-regs-v2-8-34f4024c65dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 58a457c00feb..8967b3817f55 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3074,7 +3074,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, mdss_mdp: display-controller@ae01000 { compatible = "qcom,sm8750-dpu"; reg = <0x0 0x0ae01000 0x0 0x93000>, - <0x0 0x0aeb0000 0x0 0x2008>; + <0x0 0x0aeb0000 0x0 0x3000>; reg-names = "mdp", "vbif"; From 115894bc201b0cd1799d239875a1b40924f0ef7b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 18 May 2026 11:54:39 +0200 Subject: [PATCH 196/864] arm64: dts: qcom: hamoa: Fix clocks for HSPHYs The tertiary controller's HSPHY has its own toggle in TCSR, while the primary one is wired directly to the XO clock. Fix that. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260518-topic-hamoa_hsphy_clk-v1-1-d85203756505@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 054f9c4ad192..60f485a4892e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -2809,7 +2809,7 @@ usb_1_ss0_hsphy: phy@fd3000 { reg = <0 0x00fd3000 0 0x154>; #phy-cells = <0>; - clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; @@ -2951,7 +2951,7 @@ usb_1_ss2_hsphy: phy@fde000 { reg = <0 0x00fde000 0 0x154>; #phy-cells = <0>; - clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; + clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; From 82a766b68cd4d323b302a28082fbb7924f1146e6 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Mon, 18 May 2026 04:16:17 -0700 Subject: [PATCH 197/864] arm64: dts: qcom: glymur: Fix unit-address mismatch for spmi_bus2 The spmi_bus2 node was named spmi@c48000, but its reg property specifies the base address as 0x0c448000. Fix the node name to spmi@c448000 to match the actual register base address. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Gopikrishna Garmidi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260518-glymur-fix-spmi-bus2-unit-addr-v1-1-27d6edca51e8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 00ce22ceddc5..97a6f5e03e90 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5251,7 +5251,7 @@ spmi_bus1: spmi@c437000 { #size-cells = <0>; }; - spmi_bus2: spmi@c48000 { + spmi_bus2: spmi@c448000 { reg = <0x0 0x0c448000 0x0 0x4000>, <0x0 0x0c8e0000 0x0 0x10000>, <0x0 0x0c44c000 0x0 0x8000>; From 0a4015962f8115bdca3c0c4d0420f2ff85409194 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 14 May 2026 00:22:22 +0530 Subject: [PATCH 198/864] arm64: dts: qcom: kaanapali: Add qcrypto node support Add qcrypto and cryptobam support for kaanapali target. Reviewed-by: Konrad Dybcio Signed-off-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260514-knp_qce-v2-3-890e3372eef8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 8bd029698270..0518488f358b 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2558,6 +2558,31 @@ ice: crypto@1d88000 { power-domains = <&gcc GCC_UFS_PHY_GDSC>; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v2.0.0"; + reg = <0x0 0x01dc4000 0x0 0x22000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0xc0 0x0>, + <&apps_smmu 0xc1 0x0>; + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,kaanapali-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0xc0 0x0>, + <&apps_smmu 0xc1 0x0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 711e6f11640f800f649d416b260c7f8555b0c955 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Mon, 29 Jun 2026 03:22:57 -0700 Subject: [PATCH 199/864] arm64: dts: qcom: glymur-crd: Move common board nodes to shared DTSI Mahua CRD is pin-to-pin compatible with Glymur CRD, as verified against schematics; only the external peripherals connected differ. Move the common board nodes from glymur-crd.dts to glymur-crd.dtsi to enable reuse by Mahua CRD. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Pankaj Patil Signed-off-by: Gopikrishna Garmidi Link: https://lore.kernel.org/r/20260629-glymur-mahua-common-nodes-v3-1-98cc00943359@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 399 ----------------------- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 396 ++++++++++++++++++++++ 2 files changed, 396 insertions(+), 399 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index c98dfb3941fa..6125617de82a 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -8,198 +8,9 @@ #include "glymur.dtsi" #include "glymur-crd.dtsi" -#include - / { model = "Qualcomm Technologies, Inc. Glymur CRD"; compatible = "qcom,glymur-crd", "qcom,glymur"; - - pmic-glink { - compatible = "qcom,glymur-pmic-glink", - "qcom,pmic-glink"; - #address-cells = <1>; - #size-cells = <0>; - - connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in: endpoint { - remote-endpoint = <&usb_0_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_0_qmpphy_out>; - }; - }; - }; - }; - - connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - power-role = "dual"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - pmic_glink_hs_in1: endpoint { - remote-endpoint = <&usb_1_dwc3_hs>; - }; - }; - - port@1 { - reg = <1>; - - pmic_glink_ss_in1: endpoint { - remote-endpoint = <&usb_1_qmpphy_out>; - }; - }; - }; - }; - }; - - vreg_edp_3p3: regulator-edp-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_EDP_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&edp_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; - - vreg_misc_3p3: regulator-misc-3p3 { - compatible = "regulator-fixed"; - - regulator-name = "VREG_MISC_3P3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-0 = <&misc_3p3_reg_en>; - pinctrl-names = "default"; - - regulator-boot-on; - }; -}; - -&i2c0 { - clock-frequency = <400000>; - - status = "okay"; - - touchpad@2c { - compatible = "hid-over-i2c"; - reg = <0x2c>; - - hid-descr-addr = <0x20>; - interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; - - pinctrl-0 = <&tpad_default>; - pinctrl-names = "default"; - - wakeup-source; - }; - - keyboard@3a { - compatible = "hid-over-i2c"; - reg = <0x3a>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; - - pinctrl-0 = <&kybd_default>; - pinctrl-names = "default"; - - wakeup-source; - }; -}; - -&i2c8 { - clock-frequency = <400000>; - - status = "okay"; - - touchscreen@38 { - compatible = "hid-over-i2c"; - reg = <0x38>; - - hid-descr-addr = <0x1>; - interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; - - pinctrl-0 = <&ts0_default>; - pinctrl-names = "default"; - }; -}; - -&i2c5 { - clock-frequency = <400000>; - - status = "okay"; - - ptn3222_0: redriver@43 { - compatible = "nxp,ptn3222"; - reg = <0x43>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; - - ptn3222_1: redriver@47 { - compatible = "nxp,ptn3222"; - reg = <0x47>; - - reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; - - vdd3v3-supply = <&vreg_l8b_e0_1p50>; - vdd1v8-supply = <&vreg_l15b_e0_1p8>; - - #phy-cells = <0>; - }; -}; - -&mdss { - status = "okay"; }; &mdss_dp0 { @@ -217,213 +28,3 @@ &mdss_dp1 { &mdss_dp1_out { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; - -&mdss_dp3 { - /delete-property/ #sound-dai-cells; - - status = "okay"; - - aux-bus { - panel { - compatible = "samsung,atna60cl08", "samsung,atna33xc20"; - enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; - power-supply = <&vreg_edp_3p3>; - - pinctrl-0 = <&edp_bl_en>; - pinctrl-names = "default"; - - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss_dp3_out>; - }; - }; - }; - }; -}; - -&mdss_dp3_out { - data-lanes = <0 1 2 3>; - link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; - - remote-endpoint = <&edp_panel_in>; -}; - -&mdss_dp3_phy { - vdda-phy-supply = <&vreg_l2f_e1_0p83>; - vdda-pll-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&pmh0110_f_e0_gpios { - misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio6"; - function = "normal"; - bias-disable; - input-disable; - output-enable; - drive-push-pull; - power-source = <1>; /* 1.8 V */ - qcom,drive-strength = ; - }; -}; - -&smb2370_j_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&smb2370_k_e2_eusb2_repeater { - vdd18-supply = <&vreg_l15b_e0_1p8>; - vdd3-supply = <&vreg_l7b_e0_2p79>; -}; - -&tlmm { - edp_bl_en: edp-bl-en-state { - pins = "gpio18"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - edp_reg_en: edp-reg-en-state { - pins = "gpio70"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - - kybd_default: kybd-default-state { - pins = "gpio67"; - function = "gpio"; - bias-disable; - }; - - tpad_default: tpad-default-state { - pins = "gpio3"; - function = "gpio"; - bias-disable; - }; - - ts0_default: ts0-default-state { - int-n-pins { - pins = "gpio51"; - function = "gpio"; - bias-disable; - }; - - reset-n-pins { - pins = "gpio48"; - function = "gpio"; - drive-strength = <16>; - bias-disable; - }; - }; -}; - -&usb_0 { - status = "okay"; -}; - -&usb_0_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in>; -}; - -&usb_0_hsphy { - vdd-supply = <&vreg_l3f_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&smb2370_j_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l3f_e0_0p72>; - refgen-supply = <&vreg_l2f_e0_0p82>; - - status = "okay"; -}; - -&usb_0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in>; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3_hs { - remote-endpoint = <&pmic_glink_hs_in1>; -}; - -&usb_1_hsphy { - vdd-supply = <&vreg_l3f_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&smb2370_k_e2_eusb2_repeater>; - - status = "okay"; -}; - -&usb_1_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l1h_e0_0p89>; - refgen-supply = <&vreg_l2f_e0_0p82>; - - status = "okay"; -}; - -&usb_1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss_in1>; -}; - -&usb_hs { - status = "okay"; -}; - -&usb_hs_phy { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_1>; - - status = "okay"; -}; - -&usb_mp { - status = "okay"; -}; - -&usb_mp_hsphy0 { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - phys = <&ptn3222_0>; - - status = "okay"; -}; - -&usb_mp_hsphy1 { - vdd-supply = <&vreg_l2h_e0_0p72>; - vdda12-supply = <&vreg_l4h_e0_1p2>; - - status = "okay"; -}; - -&usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; - refgen-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; - -&usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; - refgen-supply = <&vreg_l4f_e1_1p08>; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index f7478b59624e..db6f5419b4bc 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -11,6 +11,7 @@ #include "smb2370.dtsi" /* SPMI2: SID-9/10/11 */ #include +#include / { model = "Qualcomm Technologies, Inc. Glymur CRD"; @@ -69,6 +70,101 @@ switch-lid { }; }; + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -461,6 +557,135 @@ embedded-controller@76 { }; }; +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_0: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; + + ptn3222_1: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + + reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0_1p50>; + vdd1v8-supply = <&vreg_l15b_e0_1p8>; + + #phy-cells = <0>; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l15b_e0_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna60cl08", "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1_0p83>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -579,6 +804,19 @@ key_vol_up_default: key-vol-up-default-state { }; }; +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + &pmk8850_rtc { qcom,no-alarm; }; @@ -602,11 +840,35 @@ &remoteproc_cdsp { status = "okay"; }; +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0_1p8>; + vdd3-supply = <&vreg_l7b_e0_2p79>; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + hall_int_n_default: hall-int-n-state { pins = "gpio92"; function = "gpio"; @@ -619,6 +881,12 @@ ec_int_n_default: ec-int-n-state { bias-disable; }; + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -711,6 +979,27 @@ wake-n-pins { }; }; + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + wcn_wlan_bt_en: wcn-wlan-bt-en-state { pins = "gpio116", "gpio117"; function = "gpio"; @@ -749,3 +1038,110 @@ bluetooth { vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; }; }; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l3f_e0_0p72>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l1h_e0_0p89>; + refgen-supply = <&vreg_l2f_e0_0p82>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_hs { + status = "okay"; +}; + +&usb_hs_phy { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2h_e0_0p72>; + vdda12-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l4h_e0_1p2>; + vdda-pll-supply = <&vreg_l2h_e0_0p72>; + refgen-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; From 67641246eabd0629b11e767c233d92b855a64f45 Mon Sep 17 00:00:00 2001 From: Vinayak Katoch Date: Wed, 1 Jul 2026 15:35:31 +0530 Subject: [PATCH 200/864] arm64: dts: qcom: glymur: Add memory-region for audio PD Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Signed-off-by: Vinayak Katoch Reviewed-by: Ekansh Gupta Link: https://lore.kernel.org/r/20260701-glymur-audio-v1-1-2c3862d95a09@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 97a6f5e03e90..1651cf2b624e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -664,6 +665,14 @@ smem_mem: smem@ffe00000 { hwlocks = <&tcsr_mutex 3>; no-map; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; }; smp2p-adsp { @@ -4067,6 +4076,9 @@ fastrpc { compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; #address-cells = <1>; #size-cells = <0>; From eca50d95b60cdcabb82a8e1b727fad2547e52f1d Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Tue, 2 Jun 2026 09:51:35 -0700 Subject: [PATCH 201/864] arm64: dts: qcom: glymur: Fix gcc clock specifier for usb_mp_qmpphy nodes usb_mp_qmpphy0 and usb_mp_qmpphy1 have #clock-cells set to 0 so they take no specifier. Drop the erroneous QMP_USB43DP_USB3_PIPE_CLK argument. This fixes the following dtbs_check warning: clock-controller@100000 (qcom,glymur-gcc): clocks: [[59, 0], ..... [0]] is too long from schema $id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml Fixes: 4eee57dd4df9f ("arm64: dts: qcom: glymur: Add USB related nodes") Signed-off-by: Gopikrishna Garmidi Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Pankaj Patil Link: https://lore.kernel.org/r/20260602-glymur-fix-usb-mp-qmpphy-clock-specifier-v1-1-19c6f44d5655@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 1651cf2b624e..190379c77437 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -796,8 +796,8 @@ gcc: clock-controller@100000 { <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, - <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */ + <&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */ <0>, /* USB4 PHY 0 pcie pipe */ <0>, /* USB4 PHY 0 Max pipe */ <0>, /* USB4 PHY 1 pcie pipe */ From f64ef325f1d9ca9d005b7124c2bf065bb0b99c3d Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Fri, 22 May 2026 15:26:39 +0530 Subject: [PATCH 202/864] arm64: dts: glymur-crd: Add reset GPIO to touchscreen node The touchscreen module on Glymur/Mahua CRDs is different from the one used on Hamoa CRDs and requires the reset-gpios to be wired to the device. Without this in place the reset line will remain permanently asserted during resume leaving the device offline and causing all I2C transactions to fail with -ENXIO. Error Logs: i2c_hid_of 3-0038: failed to change power setting. i2c_hid_of 3-0038: PM: dpm_run_callback(): i2c_hid_core_pm_resume [i2c_hid] returns -6 i2c_hid_of 3-0038: PM: failed to resume async: error -6 Add the reset GPIO so the driver can deassert the line on resume, restoring I2C communication with the device. Fixes: e6bf559f7eb9 ("arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen") Signed-off-by: Pradyot Kumar Nayak Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260522-arm64-dts-glymur-crd-add-reset-gpio-to-touchscreen-v1-1-c7653924acdc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index db6f5419b4bc..7d3c6bbd31d2 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -640,6 +640,8 @@ touchscreen@38 { vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_l15b_e0_1p8>; + reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ts0_default>; pinctrl-names = "default"; }; From 859c3b73d40f961c4d1a5459effea6d9a947f879 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 6 Jul 2026 07:42:23 +0100 Subject: [PATCH 203/864] arm64: dts: glymur: Add LPASS macro codecs and pinctrl Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur for proper sound support. Also add GPR (Generic Pack router) node along with APM (Audio Process Manager) and PRM (Proxy resource Manager) audio services. Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Signed-off-by: Sibi Sankar Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20260706064224.1328576-2-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 263 +++++++++++++++++++++++++++ 1 file changed, 263 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 190379c77437..10a95003e2bb 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -21,7 +21,9 @@ #include #include #include +#include #include +#include #include #include @@ -4137,9 +4139,138 @@ compute-cb@8 { dma-coherent; }; }; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x20>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; + swr0: soundwire@6c80000 { + compatible = "qcom,soundwire-v3.1.0"; + reg = <0x0 0x06c80000 0x0 0x10000>; + interrupts = ; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + label = "WSA"; + + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_wsamacro: codec@6c90000 { + compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06c90000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA"; + }; + + swr3: soundwire@6ca0000 { + compatible = "qcom,soundwire-v3.1.0"; + reg = <0x0 0x06ca0000 0x0 0x10000>; + interrupts = ; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + label = "WSA2"; + + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + lpass_wsa2macro: codec@6cb0000 { + compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06cb0000 0x0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + sound-name-prefix = "WSA2"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,glymur-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -4154,6 +4285,138 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + lpass_vamacro: codec@7660000 { + compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; + reg = <0x0 0x07660000 0x0 0x2000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-pinctrl"; + reg = <0x0 0x07760000 0x0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + lpass_ag_noc: interconnect@7e40000 { compatible = "qcom,glymur-lpass-ag-noc"; reg = <0x0 0x07e40000 0x0 0xe080>; From 67be5d3da3455db75684344aab871c68701b6094 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 6 Jul 2026 07:42:24 +0100 Subject: [PATCH 204/864] arm64: dts: qcom: glymur-crd: add Audio sound card node Add the sound card of Glymur-crd board with the routing for speakers. Add device nodes for the sound support with WSA884x smart speakers and playback via speakers and recording via DMIC microphones. Co-developed-by: Mohammad Rafi Shaik Signed-off-by: Mohammad Rafi Shaik Reviewed-by: Konrad Dybcio Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20260706064224.1328576-3-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 7d3c6bbd31d2..23297b0ff216 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -237,6 +237,54 @@ vreg_wwan: regulator-wwan { pinctrl-names = "default"; }; + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-CRD"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + wcn7850-pmu { compatible = "qcom,wcn7850-pmu"; @@ -647,6 +695,13 @@ touchscreen@38 { }; }; +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + qcom,dmic-sample-rate = <4800000>; + vdd-micb-supply = <&vreg_l1b_e0_1p8>; +}; + &mdss { status = "okay"; }; @@ -852,6 +907,62 @@ &smb2370_k_e2_eusb2_repeater { vdd3-supply = <&vreg_l7b_e0_2p79>; }; +&swr0 { + status = "okay"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0_1p8>; + vdd-io-supply = <&vreg_l18b_e0_1p2>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ From e1a6af9411568dd4b135892d0f0905d676816196 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Mon, 6 Jul 2026 12:25:59 +0530 Subject: [PATCH 205/864] arm64: dts: qcom: glymur: add CPU capacity-dmips-mhz The Glymur SoC has two distinct core types within the same Oryon microarchitecture generation: - qcom,oryon-2-2 (cpu0-cpu5, cluster 0) - qcom,oryon-2-1 (cpu6-cpu11, cluster 1; cpu12-cpu17, cluster 2) Without capacity-dmips-mhz the Energy Aware Scheduler treats all 18 cores as equal, leading to suboptimal task placement and frequency selection. In particular, heavy tasks may be pinned to cluster 0 driving them to maximum frequency/voltage while cluster 1/2 sit idle. Fix this by using distinct capacity-dmips-mhz numbers. Values are derived from DPC (DMIPS-per-clock) measurements at the 825.6 MHz nominal operating point: oryon-2-2: 1024 (normalised baseline) oryon-2-1: 1372 (ratio ~1.34x vs oryon-2-2) Signed-off-by: Pradyot Kumar Nayak Link: https://lore.kernel.org/r/20260706-add-cpu-capacity-dmips-mhz-v1-1-85deced44b20@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 10a95003e2bb..25421f25adc4 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -43,6 +43,7 @@ cpu0: cpu@0 { compatible = "qcom,oryon-2-2"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; power-domains = <&cpu_pd0>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; @@ -60,6 +61,7 @@ cpu1: cpu@100 { compatible = "qcom,oryon-2-2"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; power-domains = <&cpu_pd1>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; @@ -71,6 +73,7 @@ cpu2: cpu@200 { compatible = "qcom,oryon-2-2"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; power-domains = <&cpu_pd2>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; @@ -82,6 +85,7 @@ cpu3: cpu@300 { compatible = "qcom,oryon-2-2"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; power-domains = <&cpu_pd3>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; @@ -93,6 +97,7 @@ cpu4: cpu@400 { compatible = "qcom,oryon-2-2"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; power-domains = <&cpu_pd4>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; @@ -104,6 +109,7 @@ cpu5: cpu@500 { compatible = "qcom,oryon-2-2"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; power-domains = <&cpu_pd5>, <&scmi_perf 0>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_0>; @@ -115,6 +121,7 @@ cpu6: cpu@10000 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x10000>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd6>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; @@ -132,6 +139,7 @@ cpu7: cpu@10100 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x10100>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd7>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; @@ -143,6 +151,7 @@ cpu8: cpu@10200 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x10200>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd8>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; @@ -154,6 +163,7 @@ cpu9: cpu@10300 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x10300>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd9>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; @@ -165,6 +175,7 @@ cpu10: cpu@10400 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x10400>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd10>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; @@ -176,6 +187,7 @@ cpu11: cpu@10500 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x10500>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd11>, <&scmi_perf 1>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_1>; @@ -187,6 +199,7 @@ cpu12: cpu@20000 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x20000>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd12>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; @@ -204,6 +217,7 @@ cpu13: cpu@20100 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x20100>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd13>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; @@ -215,6 +229,7 @@ cpu14: cpu@20200 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x20200>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd14>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; @@ -226,6 +241,7 @@ cpu15: cpu@20300 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x20300>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd15>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; @@ -237,6 +253,7 @@ cpu16: cpu@20400 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x20400>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd16>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; @@ -248,6 +265,7 @@ cpu17: cpu@20500 { compatible = "qcom,oryon-2-1"; reg = <0x0 0x20500>; enable-method = "psci"; + capacity-dmips-mhz = <1372>; power-domains = <&cpu_pd17>, <&scmi_perf 2>; power-domain-names = "psci", "perf"; next-level-cache = <&l2_2>; From 7803dfda924f3c892ca93aab34a93619a67b7fe2 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 17 Jun 2026 16:37:53 +0530 Subject: [PATCH 206/864] dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoC Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Reviewed-by: Rob Herring (Arm) Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,glymur-evacc.yaml | 72 +++++++++++++++++++ include/dt-bindings/clock/qcom,glymur-evacc.h | 38 ++++++++++ 2 files changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml create mode 100644 include/dt-bindings/clock/qcom,glymur-evacc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml new file mode 100644 index 000000000000..fb0bc1acc920 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm EVA Clock & Reset Controller on Glymur SoC + +maintainers: + - Taniya Das + +description: | + Qualcomm EVA clock control module which supports the clocks, resets and + power domains for the EVA instances on Glymur SoC. + + See also: + - include/dt-bindings/clock/qcom,glymur-evacc.h + +properties: + compatible: + const: qcom,glymur-evacc + + clocks: + items: + - description: Interface clock from GCC + - description: Board XO source + - description: Sleep clock source + + power-domains: + items: + - description: MMCX power domain + - description: MXC power domain + + required-opps: + description: + Required OPP nodes for the MMCX and MXC power domains. + items: + - description: MMCX performance point + - description: MXC performance point + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + clock-controller@ab00000 { + compatible = "qcom,glymur-evacc"; + reg = <0x0ab00000 0x10000>; + clocks = <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,glymur-evacc.h b/include/dt-bindings/clock/qcom,glymur-evacc.h new file mode 100644 index 000000000000..35a7b4550351 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-evacc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H + +/* EVA_CC clocks */ +#define EVA_CC_AHB_CLK 0 +#define EVA_CC_AHB_CLK_SRC 1 +#define EVA_CC_MVS0_CLK 2 +#define EVA_CC_MVS0_CLK_SRC 3 +#define EVA_CC_MVS0_DIV_CLK_SRC 4 +#define EVA_CC_MVS0_FREERUN_CLK 5 +#define EVA_CC_MVS0_SHIFT_CLK 6 +#define EVA_CC_MVS0C_CLK 7 +#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define EVA_CC_MVS0C_FREERUN_CLK 9 +#define EVA_CC_MVS0C_SHIFT_CLK 10 +#define EVA_CC_PLL0 11 +#define EVA_CC_SLEEP_CLK 12 +#define EVA_CC_SLEEP_CLK_SRC 13 +#define EVA_CC_XO_CLK 14 +#define EVA_CC_XO_CLK_SRC 15 + +/* EVA_CC power domains */ +#define EVA_CC_MVS0_GDSC 0 +#define EVA_CC_MVS0C_GDSC 1 + +/* EVA_CC resets */ +#define EVA_CC_INTERFACE_BCR 0 +#define EVA_CC_MVS0_BCR 1 +#define EVA_CC_MVS0C_CLK_ARES 2 +#define EVA_CC_MVS0C_BCR 3 +#define EVA_CC_MVS0C_FREERUN_CLK_ARES 4 + +#endif /* _DT_BINDINGS_CLK_QCOM_EVACC_GLYMUR_H */ From f135aa4dc1aa43bd55edb028f02e96c7ec8b2e63 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 17 Jun 2026 16:37:55 +0530 Subject: [PATCH 207/864] arm64: dts: qcom: glymur: Add EVA clock controller node Add the device node for the EVA clock controller (evacc) for Qualcomm Glymur SoC. This clock controller provides clocks and resets to the EVA hardware block. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-4-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 25421f25adc4..dcedd7a98651 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -5319,6 +5320,23 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + evacc: clock-controller@abf0000 { + compatible = "qcom,glymur-evacc"; + reg = <0x0 0x0abf0000 0x0 0x10000>; + clocks = <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,glymur-dispcc"; reg = <0x0 0x0af00000 0x0 0x20000>; From 53275adfb07d416a32004612227265939d0df00d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 May 2026 13:56:36 +0300 Subject: [PATCH 208/864] arm64: dts: qcom: sc8280xp: sort reserved memory regions Move memory region reserved for the GPU to its proper place in DT. Fixes: 6e9612ced0c9 ("arm64: dts: qcom: sc8280xp: create common zap-shader node") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-2-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 5784c5dc171c..02d4c2e30bb7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -632,11 +632,6 @@ reserved-region@85b00000 { no-map; }; - pil_gpu_mem: gpu-mem@8bf00000 { - reg = <0 0x8bf00000 0 0x2000>; - no-map; - }; - pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; @@ -652,6 +647,11 @@ pil_nsp0_mem: cdsp0-region@8a100000 { no-map; }; + pil_gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + pil_nsp1_mem: cdsp1-region@8c600000 { reg = <0 0x8c600000 0 0x1e00000>; no-map; From 3a52eef16b979617156fa6e2ead24ca4d1336f0b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 May 2026 13:56:37 +0300 Subject: [PATCH 209/864] arm64: dts: qcom: sc8280xp: Add Iris core Add the required nodes to enable Iris core on SC8280XP. [ bod: added interconnect tags ] Signed-off-by: Konrad Dybcio [ johan: use sm8350 videocc defines ] Signed-off-by: Johan Hovold [ bod: dropped video encoder/decoder declarations ] Signed-off-by: Bryan O'Donoghue [ db: dropped llcc icc, switched to sc8280xp compat, corrected OPP table ] Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-3-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 99 ++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 02d4c2e30bb7..d507f8fbaafb 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -11,13 +11,16 @@ #include #include #include +#include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -632,6 +635,11 @@ reserved-region@85b00000 { no-map; }; + pil_video_mem: video-region@86700000 { + reg = <0 0x86700000 0 0x500000>; + no-map; + }; + pil_adsp_mem: adsp-region@86c00000 { reg = <0 0x86c00000 0 0x2000000>; no-map; @@ -4225,6 +4233,97 @@ usb_1_dwc3_ss: endpoint { }; }; + iris: video-codec@aa00000 { + compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus"; + reg = <0x0 0x0aa00000 0x0 0x100000>; + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd SC8280XP_MX>, + <&rpmhpd SC8280XP_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mx", + "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "bus", "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + operating-points-v2 = <&iris_opp_table>; + iommus = <&apps_smmu 0x2a00 0x400>; + memory-region = <&pil_video_mem>; + + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533000000 { + opp-hz = /bits/ 64 <533000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + videocc: clock-controller@abf0000 { + compatible = "qcom,sc8280xp-videocc"; + reg = <0 0x0abf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd SC8280XP_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + cci0: cci@ac4a000 { compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; reg = <0 0x0ac4a000 0 0x1000>; From 595eb4144f2ecc58e8e56e07ae94407b5a696031 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 15 May 2026 13:56:38 +0300 Subject: [PATCH 210/864] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Enable Iris and point the driver to the correct firmware file. Signed-off-by: Konrad Dybcio Signed-off-by: Johan Hovold Signed-off-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-4-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7b21eca62908..91ba02d28bc3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -932,6 +932,12 @@ keyboard@68 { }; }; +&iris { + firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcvss8280.mbn"; + + status = "okay"; +}; + &pcie2a { vddpe-3v3-supply = <&vreg_nvme>; From a2b0c5eba7431e914c85ce9b2c14a4f23e577874 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 May 2026 13:56:39 +0300 Subject: [PATCH 211/864] arm64: dts: qcom: sm8350: add Iris device Add Iris and video clock controller devices, describing the Iris2 core present on this platform. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-5-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 81 ++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index abb4d46e2594..dd205f54000f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -2750,6 +2752,85 @@ usb_2_dwc3: usb@a800000 { }; }; + iris: video-codec@aa00000 { + compatible = "qcom,sm8350-iris", "qcom,sm8250-venus"; + reg = <0x0 0x0aa00000 0x0 0x100000>; + interrupts = ; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + power-domains = <&videocc MVS0C_GDSC>, + <&videocc MVS0_GDSC>, + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mx", + "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "bus", "core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + operating-points-v2 = <&iris_opp_table>; + iommus = <&apps_smmu 0x2100 0x400>; + memory-region = <&pil_video_mem>; + + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + }; + }; + + videocc: clock-controller@abf0000 { + compatible = "qcom,sm8350-videocc"; + reg = <0 0x0abf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,sm8350-mdss"; reg = <0 0x0ae00000 0 0x1000>; From 4a59255c6318881fdad69f8ba62a6003cc2a989f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 May 2026 13:56:40 +0300 Subject: [PATCH 212/864] arm64: dts: qcom: sm8350-hdk: enable Iris core Enable video en/decoder on the SM8350 HDK board. The firmware is not (yet) a part of linux-firmware and needs to be extracted from Android data. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260515-iris-sc8280xp-v7-6-2e21f6db1897@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 6d3f9c73a2cc..d98ec4bcfd87 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -472,6 +472,12 @@ lt9611_out: endpoint { }; }; +&iris { + firmware-name = "qcom/vpu/vpu20_p4_sm8350.mbn"; + + status = "okay"; +}; + &mdss { status = "okay"; }; From cb745bd973afab3085e9f41d619b44e31568f185 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 25 Jun 2026 11:13:36 +0200 Subject: [PATCH 213/864] arm64: dts: hisilicon: hi3798cv200: Drop unused clock-names and reset-names Neither Linux drivers nor DT bindings ever described or used clock-names and reset-names for this SoC. The binding allows clock-names only for atmel,at91sam9g45-ehci and atmel,at91rm9200-ohci, but not for HiSilicon. reset-names were never allowed. Drop them from DTS to fix dtbs_check warnings: hi3798cv200-poplar.dtb: usb@9880000 (generic-ohci): False schema does not allow ['bus', 'clk12', 'clk48'] hi3798cv200-poplar.dtb: usb@9880000 (generic-ohci): Unevaluated properties are not allowed ('reset-names' was unexpected) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 2f4ad5da5e33..e5010c9d4c39 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -633,9 +633,7 @@ ohci: usb@9880000 { clocks = <&crg HISTB_USB2_BUS_CLK>, <&crg HISTB_USB2_12M_CLK>, <&crg HISTB_USB2_48M_CLK>; - clock-names = "bus", "clk12", "clk48"; resets = <&crg 0xb8 12>; - reset-names = "bus"; phys = <&usb2_phy1_port0>; phy-names = "usb"; status = "disabled"; @@ -648,11 +646,9 @@ ehci: usb@9890000 { clocks = <&crg HISTB_USB2_BUS_CLK>, <&crg HISTB_USB2_PHY_CLK>, <&crg HISTB_USB2_UTMI_CLK>; - clock-names = "bus", "phy", "utmi"; resets = <&crg 0xb8 12>, <&crg 0xb8 16>, <&crg 0xb8 13>; - reset-names = "bus", "phy", "utmi"; phys = <&usb2_phy1_port0>; phy-names = "usb"; status = "disabled"; From 73ff3f98b8ab7630977ab6de2ce672918da8e774 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:35:01 +0200 Subject: [PATCH 214/864] arm64: dts: hisilicon: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index d0912ca5f237..2d376b3d30dd 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -236,13 +236,13 @@ cluster3_l2: l2-cache3 { gic: interrupt-controller@8d000000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x30000>; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x30000>; reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ <0x0 0x8d100000 0 0x300000>, /* GICR */ <0x0 0xfe000000 0 0x10000>, /* GICC */ From 7f9fc91718bd7e69c3c82123f3c05748a3f2793d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:35:16 +0200 Subject: [PATCH 215/864] arm64: dts: mediatek: Correct indentation and whitespace Correct spaces or mix of tabs+spaces into proper tab-indented lines and remove other whitespace violations. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi | 6 +++--- arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi index b702ff066636..b210845277e1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama.dtsi @@ -86,7 +86,7 @@ touchscreen: touchscreen@10 { }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; clock-frequency = <400000>; @@ -101,7 +101,7 @@ eeprom@58 { }; &i2c4 { - pinctrl-names = "default"; + pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins>; status = "okay"; clock-frequency = <400000>; @@ -381,5 +381,5 @@ &qca_wifi { }; &i2c_tunnel { - google,remote-bus = <2>; + google,remote-bus = <2>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts index 095279e55d50..cc8c913d2763 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts @@ -19,6 +19,6 @@ / { }; &panel { - status = "okay"; - compatible = "boe,tv101wum-nl6"; + status = "okay"; + compatible = "boe,tv101wum-nl6"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index b0c97930a0e6..ce27f314d19d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -7,7 +7,7 @@ * * Copyright (C) 2025 Collabora Ltd. * Louis-Alexis Eyraud - * AngeloGioacchino Del Regno + * AngeloGioacchino Del Regno */ #include "mt6365.dtsi" From d3cfc81d95384d555f5ffdd8730af186f302a0e8 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 20 Jun 2026 01:07:48 -0400 Subject: [PATCH 216/864] riscv: dts: spacemit: Use symbolic PDMA request numbers on K1 The PDMA request numbers (DRQ) are fixed values specific to the SoC from a hardware perspective. The detailed definition can be found in K1 User Manual [1], Chapter 9.4.3 DMA Connectivity & Assignments. Add a DTS header file to define the symbolic names for the DRQs of non-secure DMA peripherals. Convert the K1 SPI3 node to these macros. Link: https://www.spacemit.com/community/document/info?lang=en&nodepath=hardware/key_stone/k1/k1_docs/k1_usermanual/9.Top_System.md [1] Signed-off-by: Guodong Xu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260620-b4-k1-pdma-req-macros-v4-1-3cf77d0bd0d6@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-pdma.h | 56 ++++++++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 4 +- 2 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/spacemit/k1-pdma.h diff --git a/arch/riscv/boot/dts/spacemit/k1-pdma.h b/arch/riscv/boot/dts/spacemit/k1-pdma.h new file mode 100644 index 000000000000..7e5ad3d7111d --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-pdma.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DMA request number (DRQ) definitions for non-secure peripherals of + * the SpacemiT K1 PDMA. + * + * Copyright (c) 2026 Guodong Xu + */ + +#ifndef _DTS_SPACEMIT_K1_PDMA_H +#define _DTS_SPACEMIT_K1_PDMA_H + +#define K1_PDMA_UART0_TX 3 +#define K1_PDMA_UART0_RX 4 +#define K1_PDMA_UART2_TX 5 +#define K1_PDMA_UART2_RX 6 +#define K1_PDMA_UART3_TX 7 +#define K1_PDMA_UART3_RX 8 +#define K1_PDMA_UART4_TX 9 +#define K1_PDMA_UART4_RX 10 +#define K1_PDMA_I2C0_TX 11 +#define K1_PDMA_I2C0_RX 12 +#define K1_PDMA_I2C1_TX 13 +#define K1_PDMA_I2C1_RX 14 +#define K1_PDMA_I2C2_TX 15 +#define K1_PDMA_I2C2_RX 16 +#define K1_PDMA_I2C4_TX 17 +#define K1_PDMA_I2C4_RX 18 +#define K1_PDMA_SPI3_TX 19 +#define K1_PDMA_SPI3_RX 20 +#define K1_PDMA_I2S0_TX 21 +#define K1_PDMA_I2S0_RX 22 +#define K1_PDMA_I2S1_TX 23 +#define K1_PDMA_I2S1_RX 24 +#define K1_PDMA_UART5_TX 25 +#define K1_PDMA_UART5_RX 26 +#define K1_PDMA_UART6_TX 27 +#define K1_PDMA_UART6_RX 28 +#define K1_PDMA_UART7_TX 29 +#define K1_PDMA_UART7_RX 30 +#define K1_PDMA_UART8_TX 31 +#define K1_PDMA_UART8_RX 32 +#define K1_PDMA_UART9_TX 33 +#define K1_PDMA_UART9_RX 34 +#define K1_PDMA_I2C5_TX 35 +#define K1_PDMA_I2C5_RX 36 +#define K1_PDMA_I2C6_TX 37 +#define K1_PDMA_I2C6_RX 38 +#define K1_PDMA_I2C7_TX 39 +#define K1_PDMA_I2C7_RX 40 +#define K1_PDMA_I2C8_TX 41 +#define K1_PDMA_I2C8_RX 42 +#define K1_PDMA_CAN0_RX 43 +#define K1_PDMA_QSPI_RX 44 +#define K1_PDMA_QSPI_TX 45 + +#endif /* _DTS_SPACEMIT_K1_PDMA_H */ diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 08a0f28d011f..7d414e15d2cc 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -6,6 +6,8 @@ #include #include +#include "k1-pdma.h" + /dts-v1/; / { #address-cells = <2>; @@ -1094,7 +1096,7 @@ spi3: spi@d401c000 { clock-names = "core", "bus"; resets = <&syscon_apbc RESET_SSP3>; interrupts = <55>; - dmas = <&pdma 20>, <&pdma 19>; + dmas = <&pdma K1_PDMA_SPI3_RX>, <&pdma K1_PDMA_SPI3_TX>; dma-names = "rx", "tx"; status = "disabled"; }; From 1ff741220d7b11993569b5c3572e96722026bca4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:51 +0200 Subject: [PATCH 217/864] ARM: dts: mediatek: mt8127: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt8127.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt8127.dtsi b/arch/arm/boot/dts/mediatek/mt8127.dtsi index aced173c2a52..bd61ec7e70c0 100644 --- a/arch/arm/boot/dts/mediatek/mt8127.dtsi +++ b/arch/arm/boot/dts/mediatek/mt8127.dtsi @@ -75,7 +75,7 @@ uart_clk: dummy26m { compatible = "fixed-clock"; clock-frequency = <26000000>; #clock-cells = <0>; - }; + }; }; timer { From 7d3670ccf61b99283ebe44ba19f5e4643ef7cde7 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Wed, 3 Jun 2026 12:41:34 +0000 Subject: [PATCH 218/864] arm64: dts: qcom: milos-nothing-asteroids: Drop simplefb The dummy panel compatible 'boe,bf068mwm-td0' is missing documentation and gives a warning. The 'interconnects' property is also missing from the binding. Dropping the nodes here and will just submit panel binding & driver for use with MSM DRM. Signed-off-by: Alexander Koskovich Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260603-asteroids-drop-simplefb-v1-1-34d73477c9d4@pm.me Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/milos-nothing-asteroids.dts | 38 ------------------- 1 file changed, 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts b/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts index 7393978926e4..787acef4a4c8 100644 --- a/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts +++ b/arch/arm64/boot/dts/qcom/milos-nothing-asteroids.dts @@ -25,31 +25,7 @@ aliases { }; chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - stdout-path = "serial0:115200n8"; - - framebuffer0: framebuffer@e3940000 { - compatible = "simple-framebuffer"; - reg = <0x0 0xe3940000 0x0 (2392 * 1080 * 4)>; - width = <1080>; - height = <2392>; - stride = <(1080 * 4)>; - format = "a8r8g8b8"; - panel = <&panel>; - interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; - clocks = <&gcc GCC_DISP_HF_AXI_CLK>; - - /* Dummy panel for simple-framebuffer dimension info */ - panel: dummy-panel { - compatible = "boe,bf068mwm-td0"; - height-mm = <157>; - width-mm = <71>; - }; - }; }; gpio-keys { @@ -131,15 +107,6 @@ ramoops@81f20000 { mem-type = <2>; pmsg-size = <0x200000>; }; - - /* - * ABL is powering down display and controller if this node is - * not named exactly "splash_region". - */ - splash_region@e3940000 { - reg = <0x0 0xe3940000 0x0 0x2b00000>; - no-map; - }; }; }; @@ -507,11 +474,6 @@ vreg_l12f: ldo12 { }; }; -&dispcc { - /* Disable for now so simple-framebuffer continues working */ - status = "disabled"; -}; - &gcc { protected-clocks = , , , , From 2a906f0b4f037b3fe5f790a48f88549a86288fdf Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 28 Apr 2026 13:06:59 -0700 Subject: [PATCH 219/864] arm64: dts: qcom: Add #{address,size}-cells to Chromium-based /firmware Chromium/Depthcharge bootloaders may dynamically add a few device nodes to a system's DTB under a /firmware node. A typical DT looks something like the following: / { firmware { ranges; coreboot { compatible = "coreboot"; reg = <...>; ...; }; }; }; Notably, the /firmware node has an empty 'ranges', but does not have address/size-cells. Commit 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") started requiring #address-cells for a device's parent if we want to use the reg resource in a device node. This leads to errors like the following: [ 7.763870] coreboot_table firmware:coreboot: probe with driver coreboot_table failed with error -22 Add appropriate #{address,size}-cells to work around the problem. Note that Google has also patched the Depthcharge bootloader source to add {address,size}-cells [1], but bootloader updates are typically delivered only via Google OS updates. Not all users install Google software updates, and even if they do, Google may not produce updated binaries for all/older devices. [1] https://lore.kernel.org/all/20241209092809.GA3246424@google.com/ https://crrev.com/c/6051580 ("coreboot: Insert #address-cells and #size-cells for firmware node") Closes: https://lore.kernel.org/all/aeKlYzTiL0OB1y3g@google.com/ Fixes: 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") Signed-off-by: Brian Norris Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20260428200712.2660635-8-briannorris@chromium.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index b398f69917f0..cd4a0e281cf8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -99,6 +99,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + /* FIXED REGULATORS - parents above children */ /* This is the top level supply and variable voltage */ diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5c5e4f1dd221..58ea0532c0fb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -25,6 +25,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + /* * FIXED REGULATORS * From e0511284f0c14e2929aa6cec435a9cb8bec259b1 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 May 2026 14:59:26 +0300 Subject: [PATCH 220/864] arm64: dts: qcom: sm6115: add venus device Define the video en/decoding device present on the SM6115 platform. The core, AR50LT, is mostly compatible with the one present on the Agatti devices, so it uses qcom,qcm2290-venus as a fallback. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260515-iris-sm6115-v2-3-2ab75229de61@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 65 ++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index bd94eb87d6f9..3520802d1fed 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1853,6 +1853,71 @@ adreno_smmu: iommu@59a0000 { #iommu-cells = <2>; }; + venus: video-codec@5a00000 { + compatible = "qcom,sm6115-venus", + "qcom,qcm2290-venus"; + reg = <0x0 0x5a00000 0x0 0xf0000>; + interrupts = ; + + power-domains = <&gcc GCC_VENUS_GDSC>, + <&gcc GCC_VCODEC0_GDSC>, + <&rpmpd SM6115_VDDCX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + operating-points-v2 = <&venus_opp_table>; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "throttle", + "vcodec0_core", + "vcodec0_bus"; + + memory-region = <&pil_video_mem>; + iommus = <&apps_smmu 0x860 0x0>, + <&apps_smmu 0x880 0x0>; + + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG + &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; + interconnect-names = "video-mem", + "cpu-cfg"; + + status = "disabled"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133333333 { + opp-hz = /bits/ 64 <133333333>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,sm6115-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; From 43611ba2955c1f349a0694b7ad7ab6a2794910df Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 15 May 2026 14:59:27 +0300 Subject: [PATCH 221/864] arm64: dts: qcom: qrb4210-rb2: enable venus device Enable the Venus en/decoding device on the Qualcomm RB2 board. The HFI Gen2 firmware for AR50Lt platforms doesn't work on RB2, so fix the firmware in the DT for now. Signed-off-by: Dmitry Baryshkov Reviewed-by: Vishnu Reddy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260515-iris-sm6115-v2-4-2ab75229de61@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 22baee407fbe..9b05f6d843cf 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -741,6 +741,12 @@ &usb_qmpphy_out { remote-endpoint = <&pmi632_ss_in>; }; +&venus { + firmware-name = "qcom/venus-6.0/venus.mbn"; + + status = "okay"; +}; + &wifi { /* SoC */ vdd-0.8-cx-mx-supply = <&vreg_l8a_0p664>; From f91dec5bd0ec57632a17a2d27806e27d9f2429d0 Mon Sep 17 00:00:00 2001 From: David Wales Date: Fri, 5 Jun 2026 23:19:11 +1000 Subject: [PATCH 222/864] dt-bindings: arm: qcom: Add Motorola Moto G2 (2014) Document the Motorola Moto G2 (2014), which is a smartphone based on the Qualcomm MSM8226 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: David Wales Link: https://lore.kernel.org/r/20260605-device-motorola-titan-mainline-v4-1-08a7be31f05c@disroot.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2b9ba6f76bca..3257a1e1f5f9 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -187,6 +187,7 @@ properties: - microsoft,makepeace - microsoft,moneypenny - motorola,falcon + - motorola,titan - samsung,ms013g - samsung,s3ve3g - const: qcom,msm8226 From 28236bb8f50216fe98f895b31d593e8d8ddb8a27 Mon Sep 17 00:00:00 2001 From: David Wales Date: Fri, 5 Jun 2026 23:19:12 +1000 Subject: [PATCH 223/864] ARM: dts: qcom: msm8226: Support Motorola Moto G2 (2014) Add device tree for Motorola Moto G2 (2014) (motorola-titan) smartphone based on the Qualcomm MSM8226 SoC. Initially supported features: - Buttons (Volume Down/Up, Power) - eMMC - Hall Effect Sensor - Simple framebuffer display - Vibrator Based on device tree for similar device msm8226-motorola-falcon. Initial commit for falcon notes that dhob and shob reserved-memory regions seem to be related to a Motorola specific mechanism. [1] [1] https://github.com/LineageOS/android_kernel_motorola_msm8226/blob/cm-14.1/Documentation/devicetree/bindings/misc/hob_ram.txt Reviewed-by: Konrad Dybcio Signed-off-by: David Wales Reviewed-by: Dmitry Baryshkov Link: https://github.com/LineageOS/android_kernel_motorola_msm8226/blob/cm-14.1/Documentation/devicetree/bindings/misc/hob_ram.txt Link: https://lore.kernel.org/r/20260605-device-motorola-titan-mainline-v4-2-08a7be31f05c@disroot.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8226-motorola-titan.dts | 350 ++++++++++++++++++ 2 files changed, 351 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/msm8226-motorola-titan.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 32a44b02d2fa..4ffc03122784 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += \ msm8226-motorola-falcon.dtb \ + msm8226-motorola-titan.dtb \ qcom-apq8016-sbc.dtb \ qcom-apq8026-asus-sparrow.dtb \ qcom-apq8026-huawei-sturgeon.dtb \ diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-titan.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-titan.dts new file mode 100644 index 000000000000..1609fb21c544 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-titan.dts @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, David Wales + */ + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &smem_region; + +/ { + model = "Motorola Moto G2 (2014)"; + compatible = "motorola,titan", "qcom,msm8226"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* eMMC */ + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <720>; + height = <1280>; + stride = <(720 * 3)>; + format = "r8g8b8"; + vsp-supply = <®_lcd_pos>; + vsn-supply = <®_lcd_neg>; + vddio-supply = <&vddio_disp_vreg>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + vddio_disp_vreg: regulator-vddio-disp { + compatible = "regulator-fixed"; + regulator-name = "vddio_disp"; + + gpio = <&tlmm 10 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0xfa0000>; + no-map; + }; + + dhob@f500000 { + reg = <0x0f500000 0x40000>; + no-map; + }; + + shob@f540000 { + reg = <0x0f540000 0x2000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x400000>; + no-map; + }; + }; +}; + +&blsp1_i2c4 { + status = "okay"; + + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + + pinctrl-0 = <®_lcd_default>; + pinctrl-names = "default"; + + reg_lcd_pos: outp { + regulator-name = "outp"; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5600000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + }; + + reg_lcd_neg: outn { + regulator-name = "outn"; + regulator-min-microvolt = <5400000>; + regulator-max-microvolt = <5600000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pm8226_vib { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + /* Hall effect sensor */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + pm8226_lvs1: lvs1 { + /* Pull-up for I2C lines */ + regulator-always-on; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&smbb { + qcom,fast-charge-safe-current = <2000000>; + qcom,fast-charge-current-limit = <1900000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,minimum-input-voltage = <4300000>; + + status = "okay"; +}; + +&usb { + extcon = <&smbb>; + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; + +&tlmm { + reg_lcd_default: reg-lcd-default-state { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; From 97c5fe2c932bfb1857f0f29e2f1389a20264c304 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 7 Jun 2026 16:12:18 +0200 Subject: [PATCH 224/864] arm64: dts: qcom: qcm6490-shift-otter: Convert fb to use memory-region Instead of manually specifying reg, reuse the memory region. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260607-shift8-fb-v1-1-72b9dac25f4a@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index 1398a4dfb037..e5366cfd3a02 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -39,9 +39,9 @@ chosen { stdout-path = "serial0:115200n8"; - framebuffer0: framebuffer@a000000 { + framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0xe1000000 0x0 (2400 * 1080 * 4)>; + memory-region = <&cont_splash_mem>; width = <1080>; height = <2400>; stride = <(1080 * 4)>; From dcef71a03f5bb375a5da48b666ad47c6c8855278 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 7 Jun 2026 16:12:19 +0200 Subject: [PATCH 225/864] arm64: dts: qcom: qcm6490-fairphone-fp5: Convert fb to use memory-region Instead of manually specifying reg, reuse the memory region. This fixed mismatch of the node naming (0xe1000000 X framebuffer@a000000) Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260607-shift8-fb-v1-2-72b9dac25f4a@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index aa7c525237b9..82b404510fed 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -40,9 +40,9 @@ chosen { #size-cells = <2>; ranges; - framebuffer0: framebuffer@a000000 { + framebuffer { compatible = "simple-framebuffer"; - reg = <0x0 0xe1000000 0x0 (2700 * 1224 * 4)>; + memory-region = <&cont_splash_mem>; width = <1224>; height = <2700>; stride = <(1224 * 4)>; From 00dd037fc31452962eba38cdb46feafb0b70d96e Mon Sep 17 00:00:00 2001 From: Navya Malempati Date: Fri, 22 May 2026 16:40:13 +0530 Subject: [PATCH 226/864] arm64: dts: qcom: monaco: Remove the little/big_cpu_sleep_0 idle states Firmware supports both CPU power collapse (little/big_cpu_sleep_0) and CPU PLL/rail power collapse (little/big_cpu_sleep_1) idle states. However, CPU power collapse modes are often not utilized in favor of performance, so remove the CPU power collapse modes for monaco, aligning with SM8350/SM8450/SM8550/SM8650. Rename little/big_cpu_sleep_1 as little/big_cpu_sleep_0 since it is now the only CPU idle state in use. Signed-off-by: Navya Malempati Reviewed-by: Maulik Shah Link: https://lore.kernel.org/r/20260522-ml_cpuidle-v1-1-fd311cf33fb4@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 36 +++++++--------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 4f2163f0addf..16f977170bfe 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -309,16 +309,6 @@ idle-states { entry-method = "psci"; little_cpu_sleep_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <449>; - exit-latency-us = <801>; - min-residency-us = <1574>; - local-timer-stop; - }; - - little_cpu_sleep_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -329,16 +319,6 @@ little_cpu_sleep_1: cpu-sleep-0-1 { }; big_cpu_sleep_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <549>; - exit-latency-us = <901>; - min-residency-us = <1774>; - local-timer-stop; - }; - - big_cpu_sleep_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -681,49 +661,49 @@ psci { cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; + domain-idle-states = <&big_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; + domain-idle-states = <&little_cpu_sleep_0>; }; cluster_pd0: power-domain-cluster0 { From f212c011af87e65c5147bfd61d786d681be91d40 Mon Sep 17 00:00:00 2001 From: Navya Malempati Date: Fri, 22 May 2026 16:40:14 +0530 Subject: [PATCH 227/864] arm64: dts: qcom: lemans: Remove the gold_cpu_sleep idle state Firmware supports both CPU power collapse (gold_cpu_sleep_0) and CPU PLL/rail power collapse (gold_rail_cpu_sleep_0) idle states. However, CPU power collapse mode is not utilized in favor of performance, so remove it for lemans, aligning with SM8350/SM8450/SM8550/SM8650. Rename gold_rail_cpu_sleep_0 from cpu-sleep-1 to cpu-sleep-0 since it is now the only CPU idle state in use. Signed-off-by: Navya Malempati Reviewed-by: Maulik Shah Link: https://lore.kernel.org/r/20260522-ml_cpuidle-v1-2-fd311cf33fb4@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 36 +++++++--------------------- 1 file changed, 9 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index a10322c5bc35..fea7f7816e30 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -297,17 +297,7 @@ core3 { idle-states { entry-method = "psci"; - gold_cpu_sleep_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-power-collapse"; - arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <549>; - exit-latency-us = <901>; - min-residency-us = <1774>; - local-timer-stop; - }; - - gold_rail_cpu_sleep_0: cpu-sleep-1 { + gold_rail_cpu_sleep_0: cpu-sleep-0 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -566,57 +556,49 @@ psci { cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_cpu_sleep_0>, - <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_rail_cpu_sleep_0>; }; cluster_0_pd: power-domain-cluster0 { From ea85f665ffa09e2b7b9b54dac50dbaf0cd88685c Mon Sep 17 00:00:00 2001 From: Hongyang Zhao Date: Sun, 7 Jun 2026 12:17:26 +0800 Subject: [PATCH 228/864] arm64: dts: qcom: kodiak: Move PCIe GPIOs and PHYs to root ports The Qualcomm PCIe binding deprecates perst-gpios and wake-gpios on the host bridge and expects board reset and wake GPIOs to be described on the root port. PERST# is described there as reset-gpios. Move the PCIe PHY references in kodiak.dtsi to the PCIe0 and PCIe1 root port nodes, and move the board-specific PCIe reset and wake GPIOs in the Kodiak DTs to the corresponding root ports. Keep the PHY and GPIO resources on the same root port nodes so the Qualcomm PCIe driver can parse the root port binding instead of falling back to the legacy host bridge GPIO parsing. Signed-off-by: Hongyang Zhao Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260607-rubikpi-bugfix-next-20260605-v2-1-7bf229978bcd@thundersoft.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 10 ++++------ .../boot/dts/qcom/qcm6490-particle-tachyon.dts | 14 +++++++++----- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 14 ++++++++------ .../dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- 7 files changed, 47 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 90e50c245c0c..b951dd682543 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2286,9 +2286,6 @@ pcie0: pcie@1c00000 { power-domains = <&gcc GCC_PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_n>; dma-coherent; @@ -2300,6 +2297,8 @@ pcie0_port: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2416,9 +2415,6 @@ pcie1: pcie@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -2434,6 +2430,8 @@ pcie1_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index fef9fb51642d..94eebb7de7b9 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -543,9 +543,6 @@ &mdss_dp_out { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; @@ -559,9 +556,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -577,6 +577,10 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pmk8350_adc_tm { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 6c1a73f18ec1..82ebd88f9aba 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -526,9 +526,6 @@ &lpass_va_macro { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; pinctrl-names = "default"; @@ -542,10 +539,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names = "default"; @@ -570,6 +569,11 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +}; + &pm7325_gpios { pm7325_adc_default: adc-default-state { pins = "gpio2"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 9c24802e476e..e9a932c90d14 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -841,8 +841,6 @@ &mdss_edp_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -867,6 +865,8 @@ &pcie1_phy { }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 7de63ee37a84..c8eed8ba93f5 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -688,9 +688,6 @@ &mdss_dsi_phy { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -706,10 +703,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -736,6 +735,9 @@ &pcie1_phy { }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index e701cc39210f..d8a9a7e47bdc 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -816,9 +816,6 @@ &mdss_dsi_phy { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -834,10 +831,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -853,6 +852,11 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8cac4ce9c851..6bb806931b79 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -418,7 +418,6 @@ &lpass_va_macro { &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; @@ -433,6 +432,10 @@ &pcie1_phy { vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pmk8350_vadc { channel@3 { reg = ; From c800e4c8a6481b4648945a53630907e414205cf6 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 4 Jun 2026 23:06:16 -0700 Subject: [PATCH 229/864] dt-bindings: cache: qcom,llcc: Document Maili SoC Add documentation for the Last Level Cache Controller (LLCC) bindings for Qualcomm Maili SoC which is fully compatible with the one found on Qualcomm Hawi. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260604-maili-llcc-v2-1-dd24f05bc197@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/cache/qcom,llcc.yaml | 63 ++++++++++--------- 1 file changed, 34 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 34e3a2d78592..a1340226a0d0 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -19,35 +19,40 @@ description: | properties: compatible: - enum: - - qcom,eliza-llcc - - qcom,glymur-llcc - - qcom,hawi-llcc - - qcom,ipq5424-llcc - - qcom,kaanapali-llcc - - qcom,qcs615-llcc - - qcom,qcs8300-llcc - - qcom,qdu1000-llcc - - qcom,sa8775p-llcc - - qcom,sar1130p-llcc - - qcom,sar2130p-llcc - - qcom,sc7180-llcc - - qcom,sc7280-llcc - - qcom,sc8180x-llcc - - qcom,sc8280xp-llcc - - qcom,sdm670-llcc - - qcom,sdm845-llcc - - qcom,shikra-llcc - - qcom,sm6350-llcc - - qcom,sm7150-llcc - - qcom,sm8150-llcc - - qcom,sm8250-llcc - - qcom,sm8350-llcc - - qcom,sm8450-llcc - - qcom,sm8550-llcc - - qcom,sm8650-llcc - - qcom,sm8750-llcc - - qcom,x1e80100-llcc + oneOf: + - enum: + - qcom,eliza-llcc + - qcom,glymur-llcc + - qcom,hawi-llcc + - qcom,ipq5424-llcc + - qcom,kaanapali-llcc + - qcom,qcs615-llcc + - qcom,qcs8300-llcc + - qcom,qdu1000-llcc + - qcom,sa8775p-llcc + - qcom,sar1130p-llcc + - qcom,sar2130p-llcc + - qcom,sc7180-llcc + - qcom,sc7280-llcc + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + - qcom,sdm670-llcc + - qcom,sdm845-llcc + - qcom,shikra-llcc + - qcom,sm6350-llcc + - qcom,sm7150-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + - qcom,sm8550-llcc + - qcom,sm8650-llcc + - qcom,sm8750-llcc + - qcom,x1e80100-llcc + - items: + - enum: + - qcom,maili-llcc + - const: qcom,hawi-llcc reg: minItems: 1 From 346e9112f3dab91a5cf3100a99ec256ff0b7f0fe Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Wed, 27 May 2026 19:13:41 -0700 Subject: [PATCH 230/864] ARM: dts: qcom: msm8960: expressatt: Add coreriver,tc360-touchkey Add the tc360 touchkey. It's unknown if this is the actual model of the touchkey, as downstream doesn't mention a variant, but this works. Link: https://github.com/LineageOS/android_kernel_samsung_d2/blob/stable/cm-12.0-YNG4N/drivers/input/keyboard/cypress_touchkey_236/Makefile#L5 Assisted-by: Claude:claude-opus-4.6 Reviewed-by: Dmitry Baryshkov Signed-off-by: Rudraksha Gupta Reviewed-by: Konrad Dybcio Link: https://github.com/LineageOS/android_kernel_samsung_d2/blob/stable/cm-12.0-YNG4N/drivers/input/keyboard/cypress_touchkey_236/Makefile#L5 Link: https://lore.kernel.org/r/20260527-expressatt-touchkey-v2-1-049dca41fc3a@gmail.com Signed-off-by: Bjorn Andersson --- .../qcom/qcom-msm8960-samsung-expressatt.dts | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 5a39abd6f3ce..5a3d88e31cf5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -52,6 +52,40 @@ key-volume-down { linux,code = ; }; }; + + touchkey_enable: touchkey-enable { + compatible = "regulator-fixed"; + regulator-name = "touchkey_enable"; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + i2c-gpio-touchkey { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + sda-gpios = <&tlmm 71 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 72 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + pinctrl-0 = <&touchkey_i2c_pins>; + pinctrl-names = "default"; + i2c-gpio,delay-us = <2>; + + touchkey@20 { + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupts-extended = <&tlmm 52 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&touchkey_irq_pin>; + pinctrl-names = "default"; + + vddio-supply = <&touchkey_enable>; + vdd-supply = <&pm8921_l29>; + vcc-supply = <&pm8921_l29>; + + linux,keycodes = ; + }; + }; }; &gsbi2 { @@ -198,6 +232,20 @@ firmware-pins { bias-disable; }; }; + + touchkey_i2c_pins: touchkey-i2c-state { + pins = "gpio71", "gpio72"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchkey_irq_pin: touchkey-irq-state { + pins = "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; &pm8921 { @@ -420,6 +468,12 @@ pm8921_l25: l25 { bias-pull-down; }; + pm8921_l29: l29 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + /* Low Voltage Switch */ pm8921_lvs1: lvs1 { bias-pull-down; From 6a3568f938c9ff2cb493f82dc595b4dc2760f517 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Thu, 7 May 2026 11:08:31 +0530 Subject: [PATCH 231/864] arm64: dts: qcom: x1e80100: Add CAMCC block definition Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration of previous CAMCC blocks with the exception of having two required power-domains not just one. And update the compatible for camcc and videocc nodes on Purwa to match with their respective Purwa (X1P42100) specific drivers. Reviewed-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-6-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/qcom/purwa.dtsi | 10 ++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 60f485a4892e..90f170becab4 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -5501,6 +5502,22 @@ videocc: clock-controller@aaf0000 { #power-domain-cells = <1>; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,x1e80100-camcc"; + reg = <0x0 0x0ade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,x1e80100-mdss"; reg = <0 0x0ae00000 0 0x1000>; diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 9ab4f26b35f2..25cd547caab8 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -6,6 +6,8 @@ /* X1P42100 is heavily based on hamoa, with some meaningful differences */ #include "hamoa.dtsi" +#include + /delete-node/ &bwmon_cluster0; /delete-node/ &cluster_pd2; /delete-node/ &cpu_map_cluster2; @@ -36,6 +38,10 @@ /delete-node/ &thermal_gpuss_6; /delete-node/ &thermal_gpuss_7; +&camcc { + compatible = "qcom,x1p42100-camcc"; +}; + &gcc { compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; }; @@ -256,3 +262,7 @@ &thermal_nsp3 { &tsens3 { status = "disabled"; }; + +&videocc { + compatible = "qcom,x1p42100-videocc"; +}; From 1ba506e6438f5ddc26b02783009f6aa2978237eb Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Fri, 8 May 2026 03:30:06 +0100 Subject: [PATCH 232/864] arm64: dts: qcom: msm8996: add blsp2_spi5 node Add the blsp2_spi5 SPI controller node together with its default and sleep pinctrl states. Signed-off-by: Christopher Obbard Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260508-wip-obbardc-msm8996-blsp2_spi4-v2-1-8b81a95b1ed7@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2f67e665996f..818e5660df91 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1632,6 +1632,30 @@ blsp2_i2c5_default: blsp2-i2c5-state { /* Sleep state for BLSP2_I2C5 is missing.. */ + blsp2_spi5_default: blsp2-spi5-default-state { + spi-pins { + pins = "gpio58", "gpio59", "gpio61"; + function = "blsp_spi11"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio60"; + function = "blsp_spi11"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp2_spi5_sleep: blsp2-spi5-sleep-state { + pins = "gpio58", "gpio59", "gpio60", "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + cdc_reset_active: cdc-reset-active-state { pins = "gpio64"; function = "gpio"; @@ -3433,6 +3457,23 @@ blsp2_i2c5: i2c@75b9000 { status = "disabled"; }; + blsp2_spi5: spi@75b9000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x75b9000 0x600>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_spi5_default>; + pinctrl-1 = <&blsp2_spi5_sleep>; + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_i2c6: i2c@75ba000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x75ba000 0x1000>; From 07d76600a3c59e01430c9a793dc646941be423b9 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Tue, 9 Jun 2026 11:12:06 +0200 Subject: [PATCH 233/864] arm64: dts: qcom: monaco-arduino-monza: Add fan controller and thermal cooling Enable the CCI1 bus and add support for the Microchip EMC2305 fan controller on the Monaco Arduino Monza board. The controller is virtually implemented by the onboard MCU. Add a new active trip point to the cpuss0 thermal zone and associate it with onboard fan cooling. The CPU subsystem sensor is used as the thermal reference until support for a more appropriate onboard/skin sensor becomes available (via spmi-adc5-gen3). Reviewed-by: Konrad Dybcio Signed-off-by: Loic Poulain Link: https://lore.kernel.org/r/20260609091206.522331-1-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/monaco-arduino-monza.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 8b3ed73feb6e..46ce0722f98f 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -7,6 +7,7 @@ #include #include +#include #include #include "monaco.dtsi" @@ -172,6 +173,26 @@ vreg_nvme: regulator-3p3-m2 { }; }; +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + fan_controller: fan-controller@2f { + compatible = "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + }; + }; +}; + ðernet0 { phy-mode = "2500base-x"; phy-handle = <&hsgmii_phy0>; @@ -425,6 +446,27 @@ &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; }; +&thermal_zones { + cpuss-0-0-thermal { + polling-delay = <2000>; + + trips { + cpuss0_active: cpuss-active { + temperature = <32000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map-active { + trip = <&cpuss0_active>; + cooling-device = <&fan 0 THERMAL_NO_LIMIT>; + }; + }; + }; +}; + &tlmm { pcie0_default_state: pcie0-default-state { wake-pins { From e53655dac60665ffc736914f336493c5f45977a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:37 +0200 Subject: [PATCH 234/864] arm64: dts: qcom: sc8280xp-arcata: Enable backlight MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add backlight nodes and enable backlight so that it can be controlled with the corresponding buttons found on Surface Pro Type Cover keyboards. Signed-off-by: Jérôme de Bretagne Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-1-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index 3d589f05b90e..a3951ee74a85 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -46,6 +46,15 @@ wcd938x: audio-codec { #sound-dai-cells = <1>; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmc8280c_lpg 3 1000000>; + enable-gpios = <&pmc8280_1_gpios 8 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + pmic-glink { compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; @@ -557,6 +566,10 @@ &pcie4_phy { status = "okay"; }; +&pmc8280c_lpg { + status = "okay"; +}; + &pmk8280_pon_pwrkey { status = "okay"; }; @@ -857,6 +870,13 @@ &lpass_tlmm { status = "okay"; }; +&pmc8280_1_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio8"; + function = "normal"; + }; +}; + &pmc8280_2_gpios { wwan_sw_en: wwan-sw-en-state { pins = "gpio1"; @@ -864,6 +884,13 @@ wwan_sw_en: wwan-sw-en-state { }; }; +&pmc8280c_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio8"; + function = "func1"; + }; +}; + &pmr735a_gpios { hastings_reg_en: hastings-reg-en-state { pins = "gpio1"; From 587ea6a79584b5323e5eb3e2435c858177cca49c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:38 +0200 Subject: [PATCH 235/864] arm64: dts: qcom: sc8280xp-arcata: Enable the eDP display MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the vreg_edp_3p3, edp_reg_en and mdss0_dp3 nodes to enable the Surface Pro 9 5G eDP-based LCD display (LG LP129WT232166). Signed-off-by: Jérôme de Bretagne Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-2-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 64 +++++++++++++++++-- 1 file changed, 59 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index a3951ee74a85..49cd55a2653f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -136,6 +136,22 @@ pmic_glink_con1_sbu: endpoint { }; }; + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 36 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -344,7 +360,6 @@ vreg_l6b: ldo6 { regulator-max-microvolt = <880000>; regulator-initial-mode = ; regulator-boot-on; - regulator-always-on; // FIXME: VDD_A_EDP_0_0P9 }; }; @@ -448,10 +463,6 @@ &dispcc0 { status = "okay"; }; -&dispcc1 { - status = "okay"; -}; - &gpi_dma0 { status = "okay"; }; @@ -494,6 +505,42 @@ &mdss0_dp1_out { remote-endpoint = <&usb_1_qmpphy_dp_in>; }; +&mdss0_dp3 { + compatible = "qcom,sc8280xp-edp"; + /delete-property/ #sound-dai-cells; + + data-lanes = <0 1 2 3>; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; + }; + }; + }; + }; +}; + +&mdss0_dp3_out { + remote-endpoint = <&edp_panel_in>; +}; + +&mdss0_dp3_phy { + compatible = "qcom,sc8280xp-edp-phy"; + vdda-phy-supply = <&vreg_l6b>; + vdda-pll-supply = <&vreg_l3b>; + + status = "okay"; +}; + &pcie2a { vddpe-3v3-supply = <&vreg_nvme>; @@ -914,6 +961,13 @@ hstp-sw-ctrl-pins { }; }; + edp_reg_en: edp-reg-en-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + nvme_reg_en: nvme-reg-en-state { pins = "gpio135"; function = "gpio"; From 784b0cdc237d98f1ae7c6adec0165676c98a2614 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:39 +0200 Subject: [PATCH 236/864] arm64: dts: qcom: sc8280xp-arcata: add USB-C orientation GPIOs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the USB-C orientation GPIOs so that the orientation is known for the two USB-C ports on the left-side. Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-3-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index 49cd55a2653f..a47c4218354d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -60,6 +60,8 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; /* Left-side top port */ connector@0 { From 16065c4ec1e7ca595f4fa363dc2251c6bdf1f6b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:40 +0200 Subject: [PATCH 237/864] arm64: dts: qcom: sc8280xp-arcata: Fix top USB-C DP alt mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The top USB-C port (usb0) didn't switch to DP alt mode, as reusing the same GPIO 101 as on the SC8280XP CRD or Lenovo ThinkPad X13s was not working on the Surface Pro 9 5G. Investigation [1] by Jens on the Windows Dev Kit (WDK2023), the other sc8280xp-based "blackrock" model from Microsoft, found a reference to GPIO 100 in the DSDT in addition to 101. Switching to GPIO 100 fixed the issue on blackrock, as it does on arcata to enable external screen when using the left-side top USB-C port. [1] https://lore.kernel.org/all/20250609-blackrock-usb0-mux-v1-1-7903c3b071e4@oldschoolsolutions.biz/ Cc: Jens Glathe Fixes: f6231a2eefd4 ("arm64: dts: qcom: sc8280xp: Add Microsoft Surface Pro 9 5G") Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-4-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index a47c4218354d..7cac24d91828 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -270,7 +270,7 @@ map1 { usb0-sbu-mux { compatible = "pericom,pi3usb102", "gpio-sbu-mux"; - enable-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + enable-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb0_sbu_default>; @@ -1083,7 +1083,7 @@ tx-pins { usb0_sbu_default: usb0-sbu-state { oe-n-pins { - pins = "gpio101"; + pins = "gpio100"; function = "gpio"; bias-disable; drive-strength = <16>; From f4360ff09b75b31a7d9d8088f8c3cae361709cbb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:41 +0200 Subject: [PATCH 238/864] arm64: dts: qcom: sc8280xp-arcata: Enable 4-lane DP support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow up to 4 lanes for the DisplayPort link from the PHYs to the controllers and allow mode-switch events to reach the QMP Combo PHYs for the 2 left-side USB-C ports. Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-5-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index 7cac24d91828..b07192ba016b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -494,7 +494,7 @@ &mdss0_dp0 { }; &mdss0_dp0_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_0_qmpphy_dp_in>; }; @@ -503,7 +503,7 @@ &mdss0_dp1 { }; &mdss0_dp1_out { - data-lanes = <0 1>; + data-lanes = <0 1 2 3>; remote-endpoint = <&usb_1_qmpphy_dp_in>; }; @@ -844,6 +844,7 @@ &usb_0_qmpphy { vdda-phy-supply = <&vreg_l9d>; vdda-pll-supply = <&vreg_l4d>; + mode-switch; orientation-switch; status = "okay"; @@ -881,6 +882,7 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l4b>; vdda-pll-supply = <&vreg_l3b>; + mode-switch; orientation-switch; status = "okay"; From 0e5e1b74ccc902a7dc9e3eb5cbe299362bf1fa13 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:42 +0200 Subject: [PATCH 239/864] arm64: dts: qcom: sc8280xp-arcata: Add volume up/down GPIO keys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Configure gpio6 to serve as volume down and gpio9 as volume up to enable the volume up/down keys located at the top of the screen. Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-6-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index b07192ba016b..40d7c4a808ad 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "sc8280xp.dtsi" @@ -55,6 +56,31 @@ backlight: backlight { pinctrl-names = "default"; }; + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_down_n>, <&vol_up_n>; + pinctrl-names = "default"; + + key-vol-down { + label = "Volume Down"; + gpios = <&pmc8280_1_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-vol-up { + label = "Volume Up"; + gpios = <&pmc8280_1_gpios 9 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + pmic-glink { compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; @@ -926,6 +952,22 @@ edp_bl_en: edp-bl-en-state { pins = "gpio8"; function = "normal"; }; + + vol_down_n: vol-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + input-enable; + bias-pull-up; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio9"; + function = "normal"; + power-source = <1>; + input-enable; + bias-pull-up; + }; }; &pmc8280_2_gpios { From d7879682e7fc86a03cb26632c4316211be8b30d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:43 +0200 Subject: [PATCH 240/864] arm64: dts: qcom: sc8280xp-arcata: Add lid switch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the lid switch for the Microsoft Surface Pro 9 5G using GPIO pin 180. Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-7-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index 40d7c4a808ad..ed7ba11b8ffc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -7,6 +7,7 @@ #include #include +#include #include #include "sc8280xp.dtsi" @@ -59,7 +60,7 @@ backlight: backlight { gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&vol_down_n>, <&vol_up_n>; + pinctrl-0 = <&hall_int_n_default>, <&vol_down_n>, <&vol_up_n>; pinctrl-names = "default"; key-vol-down { @@ -79,6 +80,15 @@ key-vol-up { linux,can-disable; wakeup-source; }; + + switch-lid { + label = "lid"; + gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; }; pmic-glink { @@ -1014,6 +1024,13 @@ edp_reg_en: edp-reg-en-state { bias-disable; }; + hall_int_n_default: hall-int-n-state { + pins = "gpio180"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + nvme_reg_en: nvme-reg-en-state { pins = "gpio135"; function = "gpio"; From e1cf7b2332ddd90d65f74ab48f5e237ac7304b3d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:44 +0200 Subject: [PATCH 241/864] arm64: dts: qcom: sc8280xp-arcata: model the PMU of the on-board wcn6855 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align the Surface Pro 9 5G with the other sc8280xp-based models as done in this patch series [1] from Bartosz. Add a node for the PMU of the WCN6855 and rework the inputs of the wifi and bluetooth nodes to consume the PMU's outputs. With this we can drop the regulator-always-on properties from vreg_s11b and vreg_s12b as they will now be enabled by the power sequencing driver. Use the fixed BT vddrfa1p7-supply supply name to align with bindings. [1] https://lore.kernel.org/all/20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org/ Cc: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Reviewed-by: Bartosz Golaszewski Link: https://lore.kernel.org/all/20241018-sc8280xp-pwrseq-v6-0-8da8310d9564@linaro.org/ Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-8-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 103 +++++++++++++++--- 1 file changed, 89 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index ed7ba11b8ffc..1094933cf8b4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -340,6 +340,70 @@ usb1_sbu_mux: endpoint { }; }; }; + + wcn6855-pmu { + compatible = "qcom,wcn6855-pmu"; + + pinctrl-0 = <&bt_default>, <&wlan_en>; + pinctrl-names = "default"; + + wlan-enable-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&vreg_s10b>; + vddaon-supply = <&vreg_s12b>; + vddpmu-supply = <&vreg_s12b>; + vddpmumx-supply = <&vreg_s12b>; + vddpmucx-supply = <&vreg_s12b>; + vddrfa0p95-supply = <&vreg_s12b>; + vddrfa1p3-supply = <&vreg_s11b>; + vddrfa1p9-supply = <&vreg_s1c>; + vddpcie1p3-supply = <&vreg_s11b>; + vddpcie1p9-supply = <&vreg_s1c>; + + regulators { + vreg_pmu_rfa_cmn_0p8: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn_0p8"; + }; + + vreg_pmu_aon_0p8: ldo1 { + regulator-name = "vreg_pmu_aon_0p8"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p8: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p8"; + }; + + vreg_pmu_btcmx_0p8: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p8"; + }; + + vreg_pmu_pcie_1p8: ldo5 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo6 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_rfa_0p8: ldo7 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo8 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo9 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; }; &apps_rsc { @@ -366,7 +430,6 @@ vreg_s11b: smps11 { regulator-min-microvolt = <1272000>; regulator-max-microvolt = <1272000>; regulator-initial-mode = ; - regulator-always-on; }; vreg_s12b: smps12 { @@ -374,7 +437,6 @@ vreg_s12b: smps12 { regulator-min-microvolt = <984000>; regulator-max-microvolt = <984000>; regulator-initial-mode = ; - regulator-always-on; }; vreg_l3b: ldo3 { @@ -640,6 +702,16 @@ wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + qcom,calibration-variant = "MS_SP9_5G"; }; }; @@ -824,20 +896,16 @@ &uart2 { bluetooth { compatible = "qcom,wcn6855-bt"; - vddio-supply = <&vreg_s10b>; - vddbtcxmx-supply = <&vreg_s12b>; - vddrfacmn-supply = <&vreg_s12b>; - vddrfa0p8-supply = <&vreg_s12b>; - vddrfa1p2-supply = <&vreg_s11b>; - vddrfa1p7-supply = <&vreg_s1c>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; + vddaon-supply = <&vreg_pmu_aon_0p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; max-speed = <3200000>; - - enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; - swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>; - - pinctrl-0 = <&bt_default>; - pinctrl-names = "default"; }; }; @@ -1183,4 +1251,11 @@ reset-pins { bias-disable; }; }; + + wlan_en: wlan-en-state { + pins = "gpio134"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; }; From 1ba745a53172ae43a6b92ff288d449d888feb853 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:45 +0200 Subject: [PATCH 242/864] arm64: dts: qcom: sc8280xp-arcata: Switch to uefi rtc offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align with the reference implementation from the ThinkPad X13s: Switch to using the Qualcomm specific UEFI variable that is used by the UEFI firmware (and Windows) to store the RTC offset. Use the new 'qcom,uefi-rtc-info' property to indicate that the offset is stored in a UEFI variable so that the OS can determine whether to wait for it to become available. Cc: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-9-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index 1094933cf8b4..f66196cea46b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -736,20 +736,11 @@ &pmk8280_pon_resin { }; &pmk8280_rtc { - nvmem-cells = <&rtc_offset>; - nvmem-cell-names = "offset"; + qcom,uefi-rtc-info; status = "okay"; }; -&pmk8280_sdam_6 { - status = "okay"; - - rtc_offset: rtc-offset@bc { - reg = <0xbc 0x4>; - }; -}; - &qup0 { status = "okay"; }; From 3d7646cea76fc08126534b428b299c326b3c66ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Thu, 4 Jun 2026 18:18:46 +0200 Subject: [PATCH 243/864] arm64: dts: qcom: sc8280xp-arcata: Drop duplicate DMIC supplies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align with the reference implementation from the ThinkPad X13s. The audio-routing setup specifies two power supplies for each DMIC, but only one of them can be active at the same time. Drop the redundant routes to the pull-up "VA MIC BIASn" supplies as done in commit a2e617f4e698 ("arm64: dts: qcom: sc8280xp-x13s: Drop duplicate DMIC supplies"). There is no functional difference except that we skip briefly switching to pull-up mode when shutting down the microphone. Cc: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Jérôme de Bretagne Link: https://lore.kernel.org/r/20260604-surface-sp9-5g-for-next-v3-10-6aa6f6612c10@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index f66196cea46b..89c4ba267b07 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -780,9 +780,6 @@ &sound { "VA DMIC0", "MIC BIAS1", "VA DMIC1", "MIC BIAS1", "VA DMIC2", "MIC BIAS3", - "VA DMIC0", "VA MIC BIAS1", - "VA DMIC1", "VA MIC BIAS1", - "VA DMIC2", "VA MIC BIAS3", "TX SWR_ADC1", "ADC2_OUTPUT"; wcd-playback-dai-link { From f135fd1bc76d052f1bf4b1cc987cd47fe0a71d8a Mon Sep 17 00:00:00 2001 From: Yedaya Katsman Date: Mon, 8 Jun 2026 23:10:23 +0300 Subject: [PATCH 244/864] arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Fixup panel compatible The change to the panel compatible was missed, fix it. This compatible is already in the driver. Fixes: 493cb869874c ("arm64: dts: qcom: sm6125-xiaomi-laurel-sprout: Enable MDSS and add panel") Signed-off-by: Yedaya Katsman Reviewed-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260608-b4-compatible-s6e8fc0-fixup-v2-1-d23f373603a3@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index b9d9439e230b..139f2b401af5 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -198,7 +198,7 @@ &mdss_dsi0 { status = "okay"; panel@0 { - compatible = "samsung,s6e8fco-m1906f9"; + compatible = "samsung,s6e8fc0-m1906f9"; reg = <0>; reset-gpios = <&tlmm 90 GPIO_ACTIVE_LOW>; From 054a4ba10d02ee3a03ae71fd0fe4463794df973b Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:07 +0530 Subject: [PATCH 245/864] arm64: dts: qcom: sdm845: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sdm845 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-3-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 13b85624c186..745ca60fc8ed 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5105,7 +5105,7 @@ dispcc: clock-controller@af00000 { pdc_intc: interrupt-controller@b220000 { compatible = "qcom,sdm845-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; + reg = <0 0x0b220000 0 0x10000>; qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; #interrupt-cells = <2>; interrupt-parent = <&intc>; From 5474c37216819283bccef8bfdba998bd4e15f9bf Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:08 +0530 Subject: [PATCH 246/864] arm64: dts: qcom: sdm670: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sdm670 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-4-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 30844b150c80..5c60ea36f04a 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1646,7 +1646,7 @@ usb_1_dwc3: usb@a600000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sdm670-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; + reg = <0 0x0b220000 0 0x10000>; qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, <54 534 24>, <79 559 15>, <94 609 15>, <115 630 7>; From fb537f6b472785ac47c93565e746aed219f8aa17 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:09 +0530 Subject: [PATCH 247/864] arm64: dts: qcom: sc7180: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sc7180 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-5-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index fa65c485172f..18f9cb82639a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3514,7 +3514,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sc7180-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; + reg = <0 0x0b220000 0 0x10000>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; interrupt-parent = <&intc>; From 82bcc4504f24100b86500843d4ac2e723e940052 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:10 +0530 Subject: [PATCH 248/864] arm64: dts: qcom: sc7280: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sc7280 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-6-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index b951dd682543..ac048ec9aeb5 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -5756,7 +5756,7 @@ opp-810000000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; + reg = <0 0x0b220000 0 0x10000>; qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, <69 86 1>, From 75a65b596d3aed11c398127bbb241560a9365205 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:11 +0530 Subject: [PATCH 249/864] arm64: dts: qcom: sc8180x: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sc8180x spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-7-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 45391768e245..b532e33a2639 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3554,7 +3554,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sc8180x-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; + reg = <0 0x0b220000 0 0x10000>; qcom,pdc-ranges = <0 480 94>, <94 609 31>; #interrupt-cells = <2>; interrupt-parent = <&intc>; From adf6aaa7afa618016daa64cb76afc8dad06c6e94 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:12 +0530 Subject: [PATCH 250/864] arm64: dts: qcom: sm8150: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm8150 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-8-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 0e101096209a..661848ef5eee 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4174,7 +4174,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm8150-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>; + reg = <0 0x0b220000 0 0x10000>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; From 713ae69ac61195b557633f709d94a8d959b5babd Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:13 +0530 Subject: [PATCH 251/864] arm64: dts: qcom: sc8280xp: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sc8280xp spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-9-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d507f8fbaafb..f02795c8b31c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5441,7 +5441,7 @@ dispcc0: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, From f70d152b66cc8730b1a226a38bee90aa0e8ed608 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:14 +0530 Subject: [PATCH 252/864] arm64: dts: qcom: sm8250: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm8250 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-10-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 05e765616112..271778f16895 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5053,7 +5053,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm8250-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>; #interrupt-cells = <2>; From 39be29e1f8440b532ac8ef8e6f33ae2a7074a0f1 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:15 +0530 Subject: [PATCH 253/864] arm64: dts: qcom: sm8350: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm8350 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-11-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index dd205f54000f..72ecfaeefdd3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3258,7 +3258,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm8350-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; + reg = <0 0x0b220000 0 0x10000>, <0 0x17c000f0 0 0x60>; qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, From 987150965d14d86b0b2c865069cfc74275d56220 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:16 +0530 Subject: [PATCH 254/864] arm64: dts: qcom: sm8450: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm8450 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-12-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 56cb6e959e4e..7ddd0f5f539c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3728,7 +3728,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, <94 609 31>, <125 63 1>, <126 716 12>; #interrupt-cells = <2>; From 02f185df7dec96031a5139b4273fc21c652fe7e9 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:17 +0530 Subject: [PATCH 255/864] arm64: dts: qcom: sm8550: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm8550 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-13-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 83136efb7724..7599b7b7e645 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -4620,7 +4620,7 @@ usb_1_dwc3_ss: endpoint { pdc: interrupt-controller@b220000 { compatible = "qcom,sm8550-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>, <138 251 5>; From ce4014c270718611b9ad11f8c98c518fafdb1617 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:18 +0530 Subject: [PATCH 256/864] arm64: dts: qcom: sm8650: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm8650 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-14-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index dcdc2ce57a81..babf6638a24c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5998,7 +5998,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm8650-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; interrupt-parent = <&intc>; From 31cbb1901bd332dbfd7503f20251e604dcd6d4a5 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:19 +0530 Subject: [PATCH 257/864] arm64: dts: qcom: sm4450: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm4450 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-15-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi index 696e2e0841ad..b7dc40f3778c 100644 --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -464,7 +464,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm4450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 494 31>, <125 63 1>; #interrupt-cells = <2>; From c39df6b350ef51a9374fbd7c399a56b563be8deb Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:20 +0530 Subject: [PATCH 258/864] arm64: dts: qcom: x1e80100: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on x1e80100 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-16-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 90f170becab4..b672a763047a 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -6015,7 +6015,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,x1e80100-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + reg = <0 0x0b220000 0 0x10000>, <0 0x174000f0 0 0x64>; qcom,pdc-ranges = <0 480 42>, <42 251 5>, <47 522 52>, <99 609 32>, From 3d8497841d4c831ba313c1ba0b8bbad554edc72f Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:21 +0530 Subject: [PATCH 259/864] arm64: dts: qcom: sm6350: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sm6350 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-17-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 947e17b5a5eb..51e0cb5cce66 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2569,7 +2569,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; + reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x17c000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 655 12>, <138 139 15>; #interrupt-cells = <2>; From 3e7c9c6b4deaf647c46308fdb6d0f71e74c402b1 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:22 +0530 Subject: [PATCH 260/864] arm64: dts: qcom: sar2130p: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sar2130p spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-18-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 3c9529bb2f76..767f7cc218f1 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -2417,7 +2417,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sar2130p-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, From 0e89a53d7cc5f0827202137211740f7452d16dc4 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:23 +0530 Subject: [PATCH 261/864] arm64: dts: qcom: talos: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on talos spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-19-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index e506a16c9070..d23d2325f5ff 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -4683,7 +4683,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,qcs615-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x30000>, + reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x17c000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; interrupt-parent = <&intc>; From f69294f2cf6f59693c62e2ef30ceaadbd17c1e6b Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:24 +0530 Subject: [PATCH 262/864] arm64: dts: qcom: monaco: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on monaco spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-20-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 16f977170bfe..acf41e869305 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -6086,7 +6086,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,qcs8300-pdc", "qcom,pdc"; - reg = <0x0 0xb220000 0x0 0x30000>, + reg = <0x0 0xb220000 0x0 0x10000>, <0x0 0x17c000f0 0x0 0x64>; interrupt-parent = <&intc>; #interrupt-cells = <2>; From 9693db25077ae8ec29702b55126e13540ca9a09e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:25 +0530 Subject: [PATCH 263/864] arm64: dts: qcom: lemans: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on lemans spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-21-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index fea7f7816e30..4b706b1da4d6 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5868,7 +5868,7 @@ dispcc0: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x30000>, + reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x17c000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 40>, <40 140 14>, From 152ca0d83314f72a0f56d200e604190c47f801ef Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:26 +0530 Subject: [PATCH 264/864] arm64: dts: qcom: sdx75: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on sdx75 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-22-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index d1b61530b562..85cc9c6e6f83 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -1100,7 +1100,7 @@ usb_1_dwc3_ss: endpoint { pdc: interrupt-controller@b220000 { compatible = "qcom,sdx75-pdc", "qcom,pdc"; - reg = <0x0 0xb220000 0x0 0x30000>, + reg = <0x0 0xb220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>; qcom,pdc-ranges = <0 147 52>, <52 266 32>, From 008bf7c2b6ae7a5ff82089a45830bd73a980dcb4 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:27 +0530 Subject: [PATCH 265/864] arm64: dts: qcom: milos: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on milos spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-23-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index c6594c86e86e..435d878246fa 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -2250,7 +2250,7 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,milos-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x30000>, + reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>; interrupt-parent = <&intc>; From b10afe4618f36aff99f3495da44f6a05a2a3dbb2 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:28 +0530 Subject: [PATCH 266/864] arm64: dts: qcom: qdu1000: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on qdu1000 spans 0x10000 bytes. Reduce the size of the first reg entry from 0x30000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-24-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 952d4270d118..26cc86d12f72 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1054,7 +1054,7 @@ usb_1_dwc3_ss: endpoint { pdc: interrupt-controller@b220000 { compatible = "qcom,qdu1000-pdc", "qcom,pdc"; - reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + reg = <0x0 0xb220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, <94 609 31>, <125 63 1>; #interrupt-cells = <2>; From 9c10f67778541fef41a35374ac7f5ffe1b928561 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 27 May 2026 15:13:29 +0530 Subject: [PATCH 267/864] arm64: dts: qcom: eliza: Reduce OS PDC DRV span to 0x10000 The OS PDC DRV register window on eliza spans 0x10000 bytes. Reduce the size of the first reg entry from 0x40000 to 0x10000. Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260527094333.2311731-25-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 977de44b816e..2b73daea3592 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -2696,7 +2696,7 @@ lpass_ag_noc: interconnect@7e40000 { pdc: interrupt-controller@b220000 { compatible = "qcom,eliza-pdc", "qcom,pdc"; - reg = <0x0 0x0b220000 0x0 0x40000>, + reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x174000f0 0x0 0x64>; qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, From f662fca3dc872fed4c9ab92def19305ac5a7ad2d Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 9 Jun 2026 22:34:05 +0530 Subject: [PATCH 268/864] arm64: dts: qcom: ipq5332: Move PHYs and PERST# to Root Port node Follow the new binding style by defining PHYs and PERST# (now RESET#) under the Root Port node. Avoid mixing styles and move these properties to the RP node. Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260609-move_perst_to_rp-v2-1-6c731523d08c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 14 ++++++-------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 79ec77cfe552..7fcf632e289f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -36,9 +36,6 @@ &pcie0 { pinctrl-0 = <&pcie0_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -46,13 +43,15 @@ &pcie0_phy { status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; +}; + &pcie1 { pinctrl-0 = <&pcie1_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -60,6 +59,11 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; +}; + &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index fbc6c4d37fa3..74d9de8d7641 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -741,19 +741,18 @@ pcie1: pcie@18000000 { "aux", "ahb"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - interconnects = <&gcc MASTER_SNOC_PCIE3_2_M &gcc SLAVE_SNOC_PCIE3_2_M>, <&gcc MASTER_ANOC_PCIE3_2_S &gcc SLAVE_ANOC_PCIE3_2_S>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -845,19 +844,18 @@ pcie0: pcie@20000000 { "aux", "ahb"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - interconnects = <&gcc MASTER_SNOC_PCIE3_1_M &gcc SLAVE_SNOC_PCIE3_1_M>, <&gcc MASTER_ANOC_PCIE3_1_S &gcc SLAVE_ANOC_PCIE3_1_S>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From 29609eb2d96e86605e837b8be2787c8808561c07 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 9 Jun 2026 22:34:06 +0530 Subject: [PATCH 269/864] arm64: dts: qcom: ipq5424: Move PHYs and PERST# to Root Port node Follow the new binding style by defining PHYs and PERST# (now RESET#) under the Root Port node. Avoid mixing styles and move these properties to the RP node. Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260609-move_perst_to_rp-v2-2-6c731523d08c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 12 +++++++---- arch/arm64/boot/dts/qcom/ipq5424.dtsi | 24 ++++++++++----------- 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts index de71b72ae6dc..be8657239c46 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts @@ -86,8 +86,6 @@ &pcie2 { pinctrl-0 = <&pcie2_default_state>; pinctrl-names = "default"; - perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -95,12 +93,14 @@ &pcie2_phy { status = "okay"; }; +&pcie2_port0 { + reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; +}; + &pcie3 { pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; - perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -108,6 +108,10 @@ &pcie3_phy { status = "okay"; }; +&pcie3_port0 { + reset-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; +}; + &qusb_phy_0 { vdd-supply = <&vreg_misc_0p925>; vdda-pll-supply = <&vreg_misc_1p8>; diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi index 876bf6a8b8ff..702061e16a58 100644 --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi @@ -968,19 +968,19 @@ pcie3: pcie@40000000 { "aux", "ahb"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -1071,19 +1071,19 @@ pcie2: pcie@50000000 { "aux", "ahb"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie2_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -1174,19 +1174,19 @@ pcie1: pcie@60000000 { "aux", "ahb"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -1277,19 +1277,19 @@ pcie0: pcie@70000000 { "aux", "ahb"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From 71dd62dac8e2d03f952587f8985a859fce422815 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Mon, 1 Jun 2026 22:17:22 -0400 Subject: [PATCH 270/864] arm64: dts: qcom: sdm670-google: add lpi reserved gpios Add reserved GPIOs for the Pixel 3a, which blocks access to the sensor GPIOs. The hunk in the original patch was dropped in the commit because it depended on an unapplied patch, which is now commit fe9f4a46895d ("arm64: dts: qcom: sdm670-google: add common device tree include"). Fixes: c4b423835ee7 ("arm64: dts: qcom: sdm670: add lpi pinctrl") Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260602021722.30760-1-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi index 0f57b915186b..b4854801a5f5 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670-google-common.dtsi @@ -522,6 +522,11 @@ rmi4_f12: rmi4-f12@12 { }; }; +&lpi_tlmm { + /* sensor gpios are protected */ + gpio-reserved-ranges = <0 8>, <12 6>; +}; + &mdss { status = "okay"; }; From a10eafcfc6e481da6b62d78dbf408c6ef2b6b5c7 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 8 Jun 2026 17:51:49 +0530 Subject: [PATCH 271/864] dt-bindings: clock: qcom,rpmcc: Add Qualcomm Shikra SoC RPMCC Add bindings documentation for RPM clock controller on Qualcomm Shikra SoC. The Qualcomm Shikra RPMCC has the clocks same as Agatti (QCM2290) RPMCC. Hence, add support to use the QCM2290 RPMCC compatible as fallback for Shikra RPMCC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-1-94cefe092ee3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,rpmcc.yaml | 65 ++++++++++--------- 1 file changed, 36 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml index ab97d4b7dba8..af9fc5b14a81 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -21,35 +21,41 @@ description: | properties: compatible: - items: - - enum: - - qcom,rpmcc-apq8060 - - qcom,rpmcc-apq8064 - - qcom,rpmcc-ipq806x - - qcom,rpmcc-mdm9607 - - qcom,rpmcc-msm8226 - - qcom,rpmcc-msm8660 - - qcom,rpmcc-msm8909 - - qcom,rpmcc-msm8916 - - qcom,rpmcc-msm8917 - - qcom,rpmcc-msm8936 - - qcom,rpmcc-msm8937 - - qcom,rpmcc-msm8940 - - qcom,rpmcc-msm8953 - - qcom,rpmcc-msm8974 - - qcom,rpmcc-msm8976 - - qcom,rpmcc-msm8992 - - qcom,rpmcc-msm8994 - - qcom,rpmcc-msm8996 - - qcom,rpmcc-msm8998 - - qcom,rpmcc-qcm2290 - - qcom,rpmcc-qcs404 - - qcom,rpmcc-sdm429 - - qcom,rpmcc-sdm660 - - qcom,rpmcc-sm6115 - - qcom,rpmcc-sm6125 - - qcom,rpmcc-sm6375 - - const: qcom,rpmcc + oneOf: + - items: + - enum: + - qcom,rpmcc-apq8060 + - qcom,rpmcc-apq8064 + - qcom,rpmcc-ipq806x + - qcom,rpmcc-mdm9607 + - qcom,rpmcc-msm8226 + - qcom,rpmcc-msm8660 + - qcom,rpmcc-msm8909 + - qcom,rpmcc-msm8916 + - qcom,rpmcc-msm8917 + - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8937 + - qcom,rpmcc-msm8940 + - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8974 + - qcom,rpmcc-msm8976 + - qcom,rpmcc-msm8992 + - qcom,rpmcc-msm8994 + - qcom,rpmcc-msm8996 + - qcom,rpmcc-msm8998 + - qcom,rpmcc-qcm2290 + - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 + - qcom,rpmcc-sdm660 + - qcom,rpmcc-sm6115 + - qcom,rpmcc-sm6125 + - qcom,rpmcc-sm6375 + - const: qcom,rpmcc + - items: + - enum: + - qcom,rpmcc-shikra + - const: qcom,rpmcc-qcm2290 + - const: qcom,rpmcc '#clock-cells': const: 1 @@ -126,6 +132,7 @@ allOf: - qcom,rpmcc-qcs404 - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 + - qcom,rpmcc-shikra - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 From f390a1fac199b03d8971b84a531d1a978a2b20cc Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Mon, 8 Jun 2026 17:51:50 +0530 Subject: [PATCH 272/864] dt-bindings: clock: qcom: Add Qualcomm Shikra SoC Global Clock Controller Add device tree bindings for the global clock controller on Qualcomm Shikra SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,shikra-gcc.yaml | 70 +++++ include/dt-bindings/clock/qcom,shikra-gcc.h | 263 ++++++++++++++++++ 2 files changed, 333 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,shikra-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml new file mode 100644 index 000000000000..da6eebfa84c2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Clock & Reset Controller on Qualcomm Shikra SoC + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + Global clock control module provides the clocks, resets and power + domains on Qualcomm Shikra SoC platform. + + See also: include/dt-bindings/clock/qcom,shikra-gcc.h + +properties: + compatible: + const: qcom,shikra-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + + power-domains: + items: + - description: CX domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@1400000 { + compatible = "qcom,shikra-gcc"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, + <&pcie_pipe_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,shikra-gcc.h b/include/dt-bindings/clock/qcom,shikra-gcc.h new file mode 100644 index 000000000000..656c959c7e12 --- /dev/null +++ b/include/dt-bindings/clock/qcom,shikra-gcc.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SHIKRA_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_AUX2 1 +#define GPLL1 2 +#define GPLL10 3 +#define GPLL11 4 +#define GPLL12 5 +#define GPLL12_OUT_AUX2 6 +#define GPLL3 7 +#define GPLL3_OUT_MAIN 8 +#define GPLL4 9 +#define GPLL5 10 +#define GPLL6 11 +#define GPLL6_OUT_MAIN 12 +#define GPLL7 13 +#define GPLL8 14 +#define GPLL8_OUT_MAIN 15 +#define GPLL9 16 +#define GPLL9_OUT_MAIN 17 +#define GCC_AHB2PHY_CSI_CLK 18 +#define GCC_AHB2PHY_USB_CLK 19 +#define GCC_BOOT_ROM_AHB_CLK 20 +#define GCC_CAM_THROTTLE_NRT_CLK 21 +#define GCC_CAM_THROTTLE_RT_CLK 22 +#define GCC_CAMERA_AHB_CLK 23 +#define GCC_CAMERA_XO_CLK 24 +#define GCC_CAMSS_AXI_CLK 25 +#define GCC_CAMSS_AXI_CLK_SRC 26 +#define GCC_CAMSS_CAMNOC_ATB_CLK 27 +#define GCC_CAMSS_CAMNOC_DRAGONLINK_ATB_CLK 28 +#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 29 +#define GCC_CAMSS_CCI_0_CLK 30 +#define GCC_CAMSS_CCI_CLK_SRC 31 +#define GCC_CAMSS_CPHY_0_CLK 32 +#define GCC_CAMSS_CPHY_1_CLK 33 +#define GCC_CAMSS_CSI0PHYTIMER_CLK 34 +#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 35 +#define GCC_CAMSS_CSI1PHYTIMER_CLK 36 +#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 37 +#define GCC_CAMSS_MCLK0_CLK 38 +#define GCC_CAMSS_MCLK0_CLK_SRC 39 +#define GCC_CAMSS_MCLK1_CLK 40 +#define GCC_CAMSS_MCLK1_CLK_SRC 41 +#define GCC_CAMSS_MCLK2_CLK 42 +#define GCC_CAMSS_MCLK2_CLK_SRC 43 +#define GCC_CAMSS_MCLK3_CLK 44 +#define GCC_CAMSS_MCLK3_CLK_SRC 45 +#define GCC_CAMSS_NRT_AXI_CLK 46 +#define GCC_CAMSS_OPE_AHB_CLK 47 +#define GCC_CAMSS_OPE_AHB_CLK_SRC 48 +#define GCC_CAMSS_OPE_CLK 49 +#define GCC_CAMSS_OPE_CLK_SRC 50 +#define GCC_CAMSS_RT_AXI_CLK 51 +#define GCC_CAMSS_TFE_0_CLK 52 +#define GCC_CAMSS_TFE_0_CLK_SRC 53 +#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 54 +#define GCC_CAMSS_TFE_0_CSID_CLK 55 +#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 56 +#define GCC_CAMSS_TFE_1_CLK 57 +#define GCC_CAMSS_TFE_1_CLK_SRC 58 +#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 59 +#define GCC_CAMSS_TFE_1_CSID_CLK 60 +#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 61 +#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 62 +#define GCC_CAMSS_TOP_AHB_CLK 63 +#define GCC_CAMSS_TOP_AHB_CLK_SRC 64 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 65 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 66 +#define GCC_DDRSS_GPU_AXI_CLK 67 +#define GCC_DDRSS_MEMNOC_PCIE_SF_CLK 68 +#define GCC_DISP_AHB_CLK 69 +#define GCC_DISP_GPLL0_CLK_SRC 70 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 71 +#define GCC_DISP_HF_AXI_CLK 72 +#define GCC_DISP_THROTTLE_CORE_CLK 73 +#define GCC_DISP_XO_CLK 74 +#define GCC_EMAC0_AHB_CLK 75 +#define GCC_EMAC0_AXI_CLK 76 +#define GCC_EMAC0_AXI_CLK_SRC 77 +#define GCC_EMAC0_AXI_SYS_NOC_CLK 78 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 79 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 80 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 81 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 82 +#define GCC_EMAC0_PHY_AUX_CLK 83 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 84 +#define GCC_EMAC0_PTP_CLK 85 +#define GCC_EMAC0_PTP_CLK_SRC 86 +#define GCC_EMAC0_RGMII_CLK 87 +#define GCC_EMAC0_RGMII_CLK_SRC 88 +#define GCC_EMAC1_AHB_CLK 89 +#define GCC_EMAC1_AXI_CLK 90 +#define GCC_EMAC1_AXI_CLK_SRC 91 +#define GCC_EMAC1_AXI_SYS_NOC_CLK 92 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 93 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 94 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 95 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 96 +#define GCC_EMAC1_PHY_AUX_CLK 97 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 98 +#define GCC_EMAC1_PTP_CLK 99 +#define GCC_EMAC1_PTP_CLK_SRC 100 +#define GCC_EMAC1_RGMII_CLK 101 +#define GCC_EMAC1_RGMII_CLK_SRC 102 +#define GCC_GP1_CLK 103 +#define GCC_GP1_CLK_SRC 104 +#define GCC_GP2_CLK 105 +#define GCC_GP2_CLK_SRC 106 +#define GCC_GP3_CLK 107 +#define GCC_GP3_CLK_SRC 108 +#define GCC_GPU_CFG_AHB_CLK 109 +#define GCC_GPU_GPLL0_CLK_SRC 110 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 111 +#define GCC_GPU_IREF_CLK 112 +#define GCC_GPU_MEMNOC_GFX_CLK 113 +#define GCC_GPU_SMMU_VOTE_CLK 114 +#define GCC_GPU_SNOC_DVM_GFX_CLK 115 +#define GCC_GPU_THROTTLE_CORE_CLK 116 +#define GCC_LPASS_CONFIG_CLK 117 +#define GCC_LPASS_CORE_AXIM_CLK 118 +#define GCC_MMU_TCU_VOTE_CLK 119 +#define GCC_PCIE_AUX_CLK 120 +#define GCC_PCIE_AUX_CLK_SRC 121 +#define GCC_PCIE_AUX_PHY_CLK_SRC 122 +#define GCC_PCIE_CFG_AHB_CLK 123 +#define GCC_PCIE_CLKREF_EN 124 +#define GCC_PCIE_MSTR_AXI_CLK 125 +#define GCC_PCIE_PIPE_CLK 126 +#define GCC_PCIE_PIPE_CLK_SRC 127 +#define GCC_PCIE_RCHNG_PHY_CLK 128 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 129 +#define GCC_PCIE_SLEEP_CLK 130 +#define GCC_PCIE_SLV_AXI_CLK 131 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 132 +#define GCC_PCIE_TBU_CLK 133 +#define GCC_PCIE_THROTTLE_CORE_CLK 134 +#define GCC_PCIE_THROTTLE_XO_CLK 135 +#define GCC_PCIE_TILE_AXI_SYS_NOC_CLK 136 +#define GCC_PDM2_CLK 137 +#define GCC_PDM2_CLK_SRC 138 +#define GCC_PDM_AHB_CLK 139 +#define GCC_PDM_XO4_CLK 140 +#define GCC_PWM0_XO512_CLK 141 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 142 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 143 +#define GCC_QMIP_DISP_AHB_CLK 144 +#define GCC_QMIP_GPU_CFG_AHB_CLK 145 +#define GCC_QMIP_PCIE_CFG_AHB_CLK 146 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 147 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 148 +#define GCC_QUPV3_WRAP0_CORE_CLK 149 +#define GCC_QUPV3_WRAP0_S0_CLK 150 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 151 +#define GCC_QUPV3_WRAP0_S1_CLK 152 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 153 +#define GCC_QUPV3_WRAP0_S2_CLK 154 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 155 +#define GCC_QUPV3_WRAP0_S3_CLK 156 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 157 +#define GCC_QUPV3_WRAP0_S4_CLK 158 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 159 +#define GCC_QUPV3_WRAP0_S5_CLK 160 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 161 +#define GCC_QUPV3_WRAP0_S6_CLK 162 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 163 +#define GCC_QUPV3_WRAP0_S7_CLK 164 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 165 +#define GCC_QUPV3_WRAP0_S8_CLK 166 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 167 +#define GCC_QUPV3_WRAP0_S9_CLK 168 +#define GCC_QUPV3_WRAP0_S9_CLK_SRC 169 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 170 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 171 +#define GCC_SDCC1_AHB_CLK 172 +#define GCC_SDCC1_APPS_CLK 173 +#define GCC_SDCC1_APPS_CLK_SRC 174 +#define GCC_SDCC1_ICE_CORE_CLK 175 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 176 +#define GCC_SDCC2_AHB_CLK 177 +#define GCC_SDCC2_APPS_CLK 178 +#define GCC_SDCC2_APPS_CLK_SRC 179 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 180 +#define GCC_SYS_NOC_USB2_PRIM_AXI_CLK 181 +#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 182 +#define GCC_TSCSS_AHB_CLK 183 +#define GCC_TSCSS_CLK_SRC 184 +#define GCC_TSCSS_CNTR_CLK 185 +#define GCC_TSCSS_ETU_CLK 186 +#define GCC_UFS_CLKREF_EN 187 +#define GCC_USB20_MASTER_CLK 188 +#define GCC_USB20_MASTER_CLK_SRC 189 +#define GCC_USB20_MOCK_UTMI_CLK 190 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 191 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 192 +#define GCC_USB20_SLEEP_CLK 193 +#define GCC_USB30_PRIM_MASTER_CLK 194 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 195 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 196 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 197 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 198 +#define GCC_USB30_PRIM_SLEEP_CLK 199 +#define GCC_USB3_PRIM_CLKREF_EN 200 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 201 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 202 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 203 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 204 +#define GCC_VCODEC0_AXI_CLK 205 +#define GCC_VENUS_AHB_CLK 206 +#define GCC_VENUS_CTL_AXI_CLK 207 +#define GCC_VIDEO_AHB_CLK 208 +#define GCC_VIDEO_AXI0_CLK 209 +#define GCC_VIDEO_THROTTLE_CORE_CLK 210 +#define GCC_VIDEO_VCODEC0_SYS_CLK 211 +#define GCC_VIDEO_VENUS_CLK_SRC 212 +#define GCC_VIDEO_VENUS_CTL_CLK 213 +#define GCC_VIDEO_XO_CLK 214 + +/* GCC power domains */ +#define GCC_CAMSS_TOP_GDSC 0 +#define GCC_EMAC0_GDSC 1 +#define GCC_EMAC1_GDSC 2 +#define GCC_PCIE_GDSC 3 +#define GCC_USB20_GDSC 4 +#define GCC_USB30_PRIM_GDSC 5 +#define GCC_VCODEC0_GDSC 6 +#define GCC_VENUS_GDSC 7 + +/* GCC resets */ +#define GCC_CAMSS_OPE_BCR 0 +#define GCC_CAMSS_TFE_BCR 1 +#define GCC_CAMSS_TOP_BCR 2 +#define GCC_EMAC0_BCR 3 +#define GCC_EMAC1_BCR 4 +#define GCC_GPU_BCR 5 +#define GCC_MMSS_BCR 6 +#define GCC_PCIE_BCR 7 +#define GCC_PCIE_PHY_BCR 8 +#define GCC_PDM_BCR 9 +#define GCC_QUPV3_WRAPPER_0_BCR 10 +#define GCC_QUSB2PHY_PRIM_BCR 11 +#define GCC_QUSB2PHY_SEC_BCR 12 +#define GCC_SDCC1_BCR 13 +#define GCC_SDCC2_BCR 14 +#define GCC_TSCSS_BCR 15 +#define GCC_USB20_BCR 16 +#define GCC_USB30_PRIM_BCR 17 +#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_PHY_PRIM_SP0_BCR 20 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 21 +#define GCC_VCODEC0_BCR 22 +#define GCC_VENUS_BCR 23 +#define GCC_VIDEO_INTERFACE_BCR 24 + +#endif From 0b967a82e7b3c575af7f71df68d56e7786ab533e Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Wed, 10 Jun 2026 22:28:27 +0530 Subject: [PATCH 273/864] arm64: dts: qcom: ipq9574: Add missing PCIe global IRQs IPQ9574 also has the dedicated 'global' IRQ line for each PCIe controller. Add the same. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260610-ipq9574_pcie_global_irq-v1-1-6d6333b95c43@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 3f15c40f7841..451c2076f6a7 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -955,7 +955,8 @@ pcie1: pcie@10000000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -963,7 +964,8 @@ pcie1: pcie@10000000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1041,7 +1043,8 @@ pcie3: pcie@18000000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1049,7 +1052,8 @@ pcie3: pcie@18000000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1127,7 +1131,8 @@ pcie2: pcie@20000000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1135,7 +1140,8 @@ pcie2: pcie@20000000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1212,7 +1218,8 @@ pcie0: pcie@28000000 { , , , - ; + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1220,7 +1227,8 @@ pcie0: pcie@28000000 { "msi4", "msi5", "msi6", - "msi7"; + "msi7", + "global"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; From 83f13e07c5216058ccf53bfe08dd5c57e28e747a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 12 Jun 2026 14:52:43 +0200 Subject: [PATCH 274/864] arm64: dts: qcom: qcm6490-fairphone-fp5: Add AW88261 amplifiers Add nodes for the two AW88261 amplifiers, for the top and bottom speakers of this phone. Hook them up to the sound card. Reviewed-by: Konrad Dybcio Co-developed-by: Bharadwaj Raju Signed-off-by: Bharadwaj Raju Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260612-fp5-aw88261-v2-1-f7ef7d060170@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcm6490-fairphone-fp5.dts | 57 ++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 82b404510fed..f072bd96c7d4 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -866,8 +866,33 @@ vibrator@5a { &i2c2 { status = "okay"; - /* AW88261FCR amplifier @ 34 */ - /* AW88261FCR amplifier @ 35 */ + /* Top speaker / ear speaker */ + aw88261_l: audio-codec@34 { + compatible = "awinic,aw88261"; + reg = <0x34>; + + dvdd-supply = <&vreg_l18b>; + sound-name-prefix = "Amplifier L"; + firmware-name = "qcom/qcm6490/fairphone5/aw88261_acf.bin"; + + awinic,audio-channel = <0>; + + #sound-dai-cells = <0>; + }; + + /* Bottom speaker */ + aw88261_r: audio-codec@35 { + compatible = "awinic,aw88261"; + reg = <0x35>; + + dvdd-supply = <&vreg_l18b>; + sound-name-prefix = "Amplifier R"; + firmware-name = "qcom/qcm6490/fairphone5/aw88261_acf.bin"; + + awinic,audio-channel = <1>; + + #sound-dai-cells = <0>; + }; }; &i2c4 { @@ -1160,6 +1185,13 @@ &pon_resin { status = "okay"; }; +&q6afedai { + dai@127 { + reg = ; + qcom,sd-lines = <0>; + }; +}; + &qup_spi13_cs { drive-strength = <6>; bias-disable; @@ -1237,6 +1269,11 @@ &sound { compatible = "fairphone,fp5-sndcard"; model = "Fairphone 5"; + pinctrl-0 = <&lpass_i2s1_active>; + pinctrl-1 = <&lpass_i2s1_sleep>; + pinctrl-names = "default", + "sleep"; + mm1-dai-link { link-name = "MultiMedia1"; @@ -1245,6 +1282,22 @@ cpu { }; }; + i2s-dai-link { + link-name = "Quinary MI2S Playback"; + + codec { + sound-dai = <&aw88261_l>, <&aw88261_r>; + }; + + cpu { + sound-dai = <&q6afedai QUINARY_MI2S_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + }; + displayport-rx-dai-link { link-name = "DisplayPort Playback"; From bb016ddb9061a89c72448f4dbe356350f5cac0ea Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 15 Jun 2026 18:48:56 +0200 Subject: [PATCH 275/864] arm64: dts: qcom: sm8650: update the cpus capacity-dmips-mhz After some more advanced benchmarks with Integer, Floaring Point, Encryption, Compression, NEON, ... on the A520, A720 and X4 cpus, the median gain with the same frequency range is: - 281% of A720 over A520 - 126% of X4 over A720 When adjusted with the frequency delta, we get better values describing the difference in capacity, showing the weakness of the A520 designed for very small tasks while the A720 and X4 are much more powerful. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20260615-topic-sm8650-upstream-cpu-props-v3-1-eeb6e9fa7581@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index babf6638a24c..686dcad822d5 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -153,7 +153,7 @@ cpu2: cpu@200 { enable-method = "psci"; next-level-cache = <&l2_200>; - capacity-dmips-mhz = <1792>; + capacity-dmips-mhz = <2909>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; @@ -189,7 +189,7 @@ cpu3: cpu@300 { enable-method = "psci"; next-level-cache = <&l2_300>; - capacity-dmips-mhz = <1792>; + capacity-dmips-mhz = <2909>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; @@ -225,7 +225,7 @@ cpu4: cpu@400 { enable-method = "psci"; next-level-cache = <&l2_400>; - capacity-dmips-mhz = <1792>; + capacity-dmips-mhz = <2909>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 3>; @@ -261,7 +261,7 @@ cpu5: cpu@500 { enable-method = "psci"; next-level-cache = <&l2_500>; - capacity-dmips-mhz = <1792>; + capacity-dmips-mhz = <2909>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -297,7 +297,7 @@ cpu6: cpu@600 { enable-method = "psci"; next-level-cache = <&l2_600>; - capacity-dmips-mhz = <1792>; + capacity-dmips-mhz = <2909>; dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -333,7 +333,7 @@ cpu7: cpu@700 { enable-method = "psci"; next-level-cache = <&l2_700>; - capacity-dmips-mhz = <1894>; + capacity-dmips-mhz = <3591>; dynamic-power-coefficient = <588>; qcom,freq-domain = <&cpufreq_hw 2>; From 884ff1172a70f47697c5033701b4c86f23abdb57 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 15 Jun 2026 18:48:57 +0200 Subject: [PATCH 276/864] arm64: dts: qcom: sm8650: add CPU cache size properties Add the L1 cache size and its line size (cache-size and cache-line-size) with the corresponding L1-I cache and L1-D cache. L1 cache is unified, but clidr_el1 register (get_cache_type) tells that L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and d-cache-line-size and cache-line-size of L3 cache is specified. All cache line sizes were confirmed by checking ccsidr_el1. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20260615-topic-sm8650-upstream-cpu-props-v3-2-eeb6e9fa7581@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 686dcad822d5..e24c0c4bc788 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -75,6 +75,11 @@ cpu0: cpu@0 { compatible = "arm,cortex-a520"; reg = <0 0>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 0>; power-domains = <&cpu_pd0>; @@ -103,11 +108,15 @@ l2_0: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <524288>; + cache-line-size = <64>; l3_0: l3-cache { compatible = "cache"; cache-level = <3>; cache-unified; + cache-size = <12582912>; + cache-line-size = <64>; }; }; }; @@ -117,6 +126,11 @@ cpu1: cpu@100 { compatible = "arm,cortex-a520"; reg = <0 0x100>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 0>; power-domains = <&cpu_pd1>; @@ -146,6 +160,11 @@ cpu2: cpu@200 { compatible = "arm,cortex-a720"; reg = <0 0x200>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 3>; power-domains = <&cpu_pd2>; @@ -174,6 +193,8 @@ l2_200: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <524288>; + cache-line-size = <64>; }; }; @@ -182,6 +203,11 @@ cpu3: cpu@300 { compatible = "arm,cortex-a720"; reg = <0 0x300>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 3>; power-domains = <&cpu_pd3>; @@ -210,6 +236,8 @@ l2_300: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <524288>; + cache-line-size = <64>; }; }; @@ -218,6 +246,11 @@ cpu4: cpu@400 { compatible = "arm,cortex-a720"; reg = <0 0x400>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 3>; power-domains = <&cpu_pd4>; @@ -246,6 +279,8 @@ l2_400: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <524288>; + cache-line-size = <64>; }; }; @@ -254,6 +289,11 @@ cpu5: cpu@500 { compatible = "arm,cortex-a720"; reg = <0 0x500>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 1>; power-domains = <&cpu_pd5>; @@ -282,6 +322,8 @@ l2_500: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <524288>; + cache-line-size = <64>; }; }; @@ -290,6 +332,11 @@ cpu6: cpu@600 { compatible = "arm,cortex-a720"; reg = <0 0x600>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 1>; power-domains = <&cpu_pd6>; @@ -318,6 +365,8 @@ l2_600: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <524288>; + cache-line-size = <64>; }; }; @@ -326,6 +375,11 @@ cpu7: cpu@700 { compatible = "arm,cortex-x4"; reg = <0 0x700>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + clocks = <&cpufreq_hw 2>; power-domains = <&cpu_pd7>; @@ -354,6 +408,8 @@ l2_700: l2-cache { cache-level = <2>; cache-unified; next-level-cache = <&l3_0>; + cache-size = <2097152>; + cache-line-size = <64>; }; }; From c0bec4b58b8e740236d9ac338821f78dbf784546 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 15 Jun 2026 18:48:58 +0200 Subject: [PATCH 277/864] arm64: dts: qcom: sm8650: fix soundwire ports properties Since commit 9e53a66a2f2f ("soundwire: qcom: deprecate qcom,din/out-ports"), the ports are checked against the actul hardware configuration, leading to: qcom-soundwire 6ad0000.soundwire: din-ports (0) mismatch with controller (1) qcom-soundwire 6d30000.soundwire: dout-ports (0) mismatch with controller (1) Fix the ports count and properties of the corresponding soundwire controllers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20260615-topic-sm8650-upstream-cpu-props-v3-3-eeb6e9fa7581@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 40 ++++++++++++++-------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e24c0c4bc788..d9b2c88a130a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4737,18 +4737,18 @@ swr1: soundwire@6ad0000 { pinctrl-0 = <&rx_swr_active>; pinctrl-names = "default"; - qcom,din-ports = <0>; + qcom,din-ports = <1>; qcom,dout-ports = <11>; - qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; - qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff>; - qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff>; - qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff>; - qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff>; - qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; + qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff 0x31 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0x18 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff 0xff 0x01 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff 0xff>; #address-cells = <2>; #size-cells = <0>; @@ -4834,17 +4834,17 @@ swr2: soundwire@6d30000 { pinctrl-names = "default"; qcom,din-ports = <4>; - qcom,dout-ports = <0>; + qcom,dout-ports = <1>; - qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; + qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x00 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0x01 0x02 0x00 0x00>; #address-cells = <2>; #size-cells = <0>; From ae51d9396f9318189e91578878409d8ada152edb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 16 Jun 2026 11:08:49 +0200 Subject: [PATCH 278/864] arm64: dts: qcom: sc8180x-primus: Rename regulator nodes The nodes would be sorted correctly, if their names started with "regulator-" (which is the style used in the latest submissions). Touch that up. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260616-topic-8180_disp_power-v2-1-167785993231@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index aff398390eba..ffe7c45366ed 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -167,7 +167,7 @@ reserved-region@9a500000 { }; }; - vreg_nvme_0p9: nvme-0p9-regulator { + vreg_nvme_0p9: regulator-nvme-0p9 { compatible = "regulator-fixed"; regulator-name = "vreg_nvme_0p9"; @@ -177,7 +177,7 @@ vreg_nvme_0p9: nvme-0p9-regulator { regulator-always-on; }; - vreg_nvme_3p3: nvme-3p3-regulator { + vreg_nvme_3p3: regulator-nvme-3p3 { compatible = "regulator-fixed"; regulator-name = "vreg_nvme_3p3"; @@ -190,7 +190,7 @@ vreg_nvme_3p3: nvme-3p3-regulator { regulator-always-on; }; - vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator { + vdd_kb_tp_3v3: regulator-vdd-kb-tp-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_kb_tp_3v3"; regulator-min-microvolt = <3300000>; @@ -205,7 +205,7 @@ vdd_kb_tp_3v3: vdd-kb-tp-3v3-regulator { pinctrl-0 = <&kb_tp_3v3_en_active_state>; }; - vph_pwr: vph-pwr-regulator { + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; regulator-min-microvolt = <3700000>; From 80bf2eb87bfbf1b7bc7b12228cbcc710b0a26275 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 16 Jun 2026 11:08:50 +0200 Subject: [PATCH 279/864] arm64: dts: qcom: sc8180x-primus: Describe the display power net Describe and wire up the power supplies for the eDP panel and its backlight. Previously, this was only working because of settings inherited from the bootloader. Fixes: 2ce38cc1e8fe ("arm64: dts: qcom: sc8180x: Introduce Primus") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260616-topic-8180_disp_power-v2-2-167785993231@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 48 ++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index ffe7c45366ed..e34f4758ebe2 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -29,9 +29,10 @@ backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8180c_lpg 4 1000000>; enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply = <&vled_bl_pw>; - pinctrl-names = "default"; pinctrl-0 = <&bl_pwm_default>; + pinctrl-names = "default"; }; chosen { @@ -167,6 +168,38 @@ reserved-region@9a500000 { }; }; + vled_bl_pw: regulator-vled-bl-pw { + compatible = "regulator-fixed"; + + regulator-name = "VLED_BL_PW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8180_2_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&bl_pwr_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_lcm_3v3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_LCM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&lcm_3v3_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme_0p9: regulator-nvme-0p9 { compatible = "regulator-fixed"; regulator-name = "vreg_nvme_0p9"; @@ -540,6 +573,7 @@ &mdss_edp { aux-bus { panel { compatible = "edp-panel"; + power-supply = <&vreg_lcm_3v3>; backlight = <&backlight>; @@ -769,6 +803,12 @@ &wifi { }; /* PINCTRL */ +&pmc8180_2_gpios { + bl_pwr_en: bl-pwr-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; &pmc8180c_gpios { bl_pwm_default: bl-pwm-default-state { @@ -950,4 +990,10 @@ rx-pins { bias-pull-up; }; }; + + lcm_3v3_en: lcm-3v3-en-state { + pins = "gpio130"; + function = "gpio"; + bias-disable; + }; }; From 0b1c6d2a65fc41aa0d5f6617dd04043384678d61 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 16 Jun 2026 11:08:51 +0200 Subject: [PATCH 280/864] arm64: dts: qcom: sc8180x-lenovo-flex-5g: Rename regulator nodes Align with the contemporary way of naming regulator nodes (regulator- prefix) in preparation for adding more of them. Reorder the renamed entries to match the expectations of the DT coding style doc. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260616-topic-8180_disp_power-v2-3-167785993231@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index d86a31ddede2..0d2cfb830e83 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -157,14 +157,7 @@ cdsp_mem: cdsp-region@98900000 { }; }; - vph_pwr: vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "vph_pwr"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; - - vreg_s4a_1p8: pm8150-s4-regulator { + vreg_s4a_1p8: regulator-pm8150-s4 { compatible = "regulator-fixed"; regulator-name = "vreg_s4a_1p8"; @@ -177,6 +170,13 @@ vreg_s4a_1p8: pm8150-s4-regulator { vin-supply = <&vph_pwr>; }; + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + usbprim-sbu-mux { compatible = "pericom,pi3usb102", "gpio-sbu-mux"; From d5f5c089858f7accd1e4574c0c09d811e90eb51f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 16 Jun 2026 11:08:52 +0200 Subject: [PATCH 281/864] arm64: dts: qcom: sc8180x-lenovo-flex-5g: Describe the display power net Describe and wire up the power supplies for the eDP panel and its backlight. Previously, this was only working because of settings inherited from the bootloader. Fixes: 20dea72a393c ("arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260616-topic-8180_disp_power-v2-4-167785993231@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 0d2cfb830e83..7601afc3d7bf 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -26,6 +26,7 @@ backlight: backlight { compatible = "pwm-backlight"; pwms = <&pmc8180c_lpg 4 1000000>; enable-gpios = <&pmc8180c_gpios 8 GPIO_ACTIVE_HIGH>; + power-supply = <&vled_bl_pw>; pinctrl-0 = <&bl_pwm_default>; pinctrl-names = "default"; @@ -157,6 +158,38 @@ cdsp_mem: cdsp-region@98900000 { }; }; + vled_bl_pw: regulator-vled-bl-pw { + compatible = "regulator-fixed"; + + regulator-name = "VLED_BL_PW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8180_2_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&bl_pwr_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_lcm_3v3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_LCM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&lcm_3v3_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_s4a_1p8: regulator-pm8150-s4 { compatible = "regulator-fixed"; regulator-name = "vreg_s4a_1p8"; @@ -438,6 +471,7 @@ &mdss_edp { aux-bus { panel { compatible = "edp-panel"; + power-supply = <&vreg_lcm_3v3>; no-hpd; backlight = <&backlight>; @@ -472,6 +506,13 @@ &pcie3_phy { status = "okay"; }; +&pmc8180_2_gpios { + bl_pwr_en: bl-pwr-en-state { + pins = "gpio1"; + function = "normal"; + }; +}; + &pmc8180_pwrkey { status = "okay"; }; @@ -765,6 +806,12 @@ ts_int_default: ts-int-default-state { drive-strength = <2>; }; + lcm_3v3_en: lcm-3v3-en-state { + pins = "gpio130"; + function = "gpio"; + bias-disable; + }; + usbprim_sbu_default: usbprim-sbu-state { oe-n-pins { pins = "gpio152"; From 4614628bea862cbad0ec3323200900a1f34e98c5 Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Fri, 22 May 2026 16:20:20 +0530 Subject: [PATCH 282/864] arm64: dts: qcom: qcs615-ride: fix sdhc_2 vqmmc-supply for UHS-I mode SD card is detected as SDHS instead of UHS-I because sdhc_2 was configured with vreg_s4a as vqmmc-supply, which cannot switch between 1.8V and 3.3V. Switch vqmmc-supply to vreg_l2a and update its voltage range to 1800000-2960000 uV to enable proper UHS-I signaling. Signed-off-by: Monish Chunara Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260522105020.3588377-1-mchunara@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 51b13b492472..047b4efb04b9 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -232,8 +232,8 @@ vreg_l1a: ldo1 { vreg_l2a: ldo2 { regulator-name = "vreg_l2a"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <3100000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; regulator-initial-mode = ; regulator-allow-set-load; regulator-allowed-modes = ; vmmc-supply = <&vreg_l10a>; - vqmmc-supply = <&vreg_s4a>; + vqmmc-supply = <&vreg_l2a>; status = "okay"; }; From 50c0854e2703b4e446f83680d7eb0dc0bd5bb34d Mon Sep 17 00:00:00 2001 From: Teguh Sobirin Date: Fri, 5 Jun 2026 17:49:39 -0500 Subject: [PATCH 283/864] arm64: dts: qcom: sm8750: Add UART15 Add uart15 node for the UART bus present on the sm8750 SoC. Signed-off-by: Teguh Sobirin Signed-off-by: Aaron Kling Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260605-sm8750-uart15-v1-1-93e660722e61@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 8967b3817f55..7634d132f07f 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -1218,6 +1218,28 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, status = "disabled"; }; + + uart15: serial@89c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0089c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart15_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; }; i2c_master_hub_0: geniqup@9c0000 { @@ -4060,6 +4082,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state { bias-pull-down; }; + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins = "gpio30", "gpio31"; + function = "qup2_se7"; + drive-strength = <2>; + bias-pull-up; + }; + sdc2_sleep: sdc2-sleep-state { clk-pins { pins = "sdc2_clk"; From 9d7d847ff1c502802ac764120f9a1800b94ce497 Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Wed, 29 Apr 2026 15:34:43 +0800 Subject: [PATCH 284/864] arm64: dts: qcom: kodiak: avoid EFI overlap for ADSP remote heap On KODIAK platforms boot can fail when the DT "adsp-rpc-remote-heap" reserved-memory region overlaps with firmware allocations (UEFI/EFI runtime). The kernel then reports failure to reserve the region and subsequent EFI runtime activity may trigger aborts. The remote heap node was described as a fixed "no-map" region, which turns it into a hard carveout. Replace it with a "shared-dma-pool" reserved memory region with reusable CMA-backed allocation, specifying alignment and size. This avoids hard carveouts and reduces the chance of conflicting with firmware memory maps while keeping an explicit pool for ADSP remote heap usage. Fixes: 90a58ffa9c55 ("arm64: dts: qcom: kodiak: Add memory region for audiopd") Cc: stable@kernel.org Signed-off-by: Jianping Li Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260429073443.2027-1-jianping.li@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index ac048ec9aeb5..7e73348fe0d0 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -191,9 +191,12 @@ rmtfs_mem: rmtfs@9c900000 { qcom,vmid = ; }; - adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 { - reg = <0x0 0x9cb80000 0x0 0x800000>; - no-map; + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; }; }; From 650ca2ce6876e1d255a18f07a704ddcbbe50c0e7 Mon Sep 17 00:00:00 2001 From: Jie Zhang Date: Mon, 27 Apr 2026 23:56:05 +0530 Subject: [PATCH 285/864] arm64: dts: qcom: talos-evk-som: Enable Adreno 612 GPU Enable GPU for talos-evk-som platform and provide path for zap shader. Signed-off-by: Jie Zhang Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260427-talos-evt-gpu-v1-1-d40b6dffa108@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 294354c034c3..6d2cff3cf23c 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -317,6 +317,14 @@ &gpi_dma1 { status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; From dbf48f009161162147c8df3cb3a47e8e7a3a0442 Mon Sep 17 00:00:00 2001 From: Stanislav Zaikin Date: Mon, 8 Jun 2026 16:33:28 +0200 Subject: [PATCH 286/864] dt-bindings: arm: qcom: Add SM7325 Xiaomi 12 Lite 5G (taoyao) Xiaomi 12 Lite 5G (xiaomi,taoyao) is a smartphone based on the SM7325 SoC. Signed-off-by: Stanislav Zaikin Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260608143329.252033-2-zstaseg@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 3257a1e1f5f9..f2780007b795 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1055,6 +1055,7 @@ properties: - enum: - motorola,dubai - nothing,spacewar + - xiaomi,taoyao - const: qcom,sm7325 - items: From 28705df5d0df5f8ba34c7ca3fcc5b46e7799b7c2 Mon Sep 17 00:00:00 2001 From: Stanislav Zaikin Date: Mon, 8 Jun 2026 16:33:29 +0200 Subject: [PATCH 287/864] arm64: dts: qcom: sm7325: Add Xiaomi 12 Lite 5G (taoyao) DTS Xiaomi 12 Lite 5G is a handset released in 2022 This commit has the following features working: - Display (with simple fb) - Touchscreen - UFS - Power and volume buttons - Pinctrl - RPM Regulators - Remoteprocs - wifi, bluetooth - USB (Device Mode) Signed-off-by: Stanislav Zaikin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260608143329.252033-3-zstaseg@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm7325-xiaomi-taoyao.dts | 913 ++++++++++++++++++ 2 files changed, 914 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 5a1c56cf98f6..84d9ca96f248 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -350,6 +350,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-csot.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-motorola-dubai-tianma.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7325-nothing-spacewar.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm7325-xiaomi-taoyao.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts new file mode 100644 index 000000000000..6f8bc65bb99b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts @@ -0,0 +1,913 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2025, Stanislav Zaikin + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sm7325.dtsi" +#include "pm7325.dtsi" +#include "pm7250b.dtsi" /* PM7250B */ +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/* The following reserved memory regions have different addresses or sizes */ +/delete-node/ &adsp_mem; +/delete-node/ &adsp_rpc_remote_heap_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &rmtfs_mem; + +/ { + model = "Xiaomi 12 Lite 5G"; + compatible = "xiaomi,taoyao", "qcom,sm7325"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + serial1 = &uart7; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer { + compatible = "simple-framebuffer"; + memory-region = <&framebuffer_reserved>; + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&key_vol_up>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,sm7325-pmic-glink", + "qcom,qcm6490-pmic-glink", + "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; + }; + }; + }; + }; + }; + + vreg_oled_dvdd: regulator-oled-dvdd { + compatible = "regulator-fixed"; + regulator-name = "oled_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_s1b_1p856>; + regulator-boot-on; + }; + + /* S2B is really ebi.lvl but it's there for supply map completeness sake. */ + vreg_s2b_0p7: regulator-smpb2 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s2b_0p7"; + + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <700000>; + regulator-always-on; + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + reserved-memory { + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + cvp_mem: cvp@86200000 { + reg = <0x0 0x86200000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86700000 { + reg = <0x0 0x86700000 0x0 0x4000000>; + no-map; + }; + + camera_mem: camera@8ad00000 { + reg = <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8b710000 { + reg = <0x0 0x8b710000 0x0 0xa000>; + no-map; + }; + + cdsp_mem: cdsp@9c700000 { + reg = <0x0 0x9c700000 0x0 0x1e00000>; + no-map; + }; + + ramoops@a9000000 { + compatible = "ramoops"; + reg = <0x0 0xa9000000 0x0 0x200000>; + mem-type = <2>; + pmsg-size = <0x100000>; + record-size = <0x100000>; + }; + + removed_mem: removed@c0000000 { + reg = <0x0 0xc0000000 0x0 0x6800000>; + no-map; + }; + + pil_trustedvm_mem: pil-trustedvm-region@d0800000 { + reg = <0x0 0xd0800000 0x0 0x76f7000>; + no-map; + }; + + qrtr_shmem: qrtr-shmem@d7ef7000 { + reg = <0x0 0xd7ef7000 0x0 0x9000>; + no-map; + }; + + neuron_block_0_mem: neuron-block@d7f00000 { + reg = <0x0 0xd7f00000 0x0 0x80000>; + no-map; + }; + + neuron_block_1_mem: neuron-block@d7f80000 { + reg = <0x0 0xd7f80000 0x0 0x80000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@e0400000 { + reg = <0x0 0xe0400000 0x0 0x800000>; + no-map; + }; + + framebuffer_reserved: framebuffer@e1000000 { + reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; + no-map; + }; + + rmtfs_mem: rmtfs@e7d00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xe7d00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = , + ; + }; + }; + + wcn6750-pmu { + compatible = "qcom,wcn6750-pmu"; + pinctrl-0 = <&hst_bt_en>, + <&hst_sw_ctrl>; + pinctrl-names = "default"; + vddio-supply = <&vreg_l19b_1p8>; + vddaon-supply = <&vreg_s7b_0p952>; + vddasd-supply = <&vreg_l11c_2p8>; + vddpmu-supply = <&vreg_s7b_0p952>; + vddrfa0p8-supply = <&vreg_s7b_0p952>; + vddrfa1p2-supply = <&vreg_s8b_1p256>; + vddrfa1p7-supply = <&vreg_s1b_1p856>; + vddrfa2p2-supply = <&vreg_s1c_2p2>; + + bt-enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p7: ldo7 { + regulator-name = "vreg_pmu_rfa_1p7"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p952>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_s2b_0p7>; + vdd-l5-supply = <&vreg_s2b_0p7>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p256>; + vdd-l8-supply = <&vreg_s7b_0p952>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p856>; + vdd-l13-supply = <&vreg_s7b_0p952>; + vdd-l14-l16-supply = <&vreg_s8b_1p256>; + + /* + * S2, L4-L5 are ARCs: + * S2 - ebi.lvl, + * L4 - lmx.lvl, + * L5 - lcx.lvl. + * + * L10 are unused. + */ + + vreg_s1b_1p856: smps1 { + regulator-name = "vreg_s1b_1p856"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p952: smps7 { + regulator-name = "vreg_s7b_0p952"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p256: smps8 { + regulator-name = "vreg_s8b_1p256"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p6: ldo3 { + regulator-name = "vreg_l3b_0p6"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allowed-modes = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + /* Constrained for UFS VCC, at least until UFS driver scales voltage */ + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p776: ldo11 { + regulator-name = "vreg_l11b_1p776"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p8: ldo12 { + regulator-name = "vreg_l12b_0p8"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p8: ldo13 { + regulator-name = "vreg_l13b_0p8"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p2: ldo14 { + regulator-name = "vreg_l14b_1p2"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p88: ldo15 { + regulator-name = "vreg_l15b_0p88"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p2: ldo16 { + regulator-name = "vreg_l16b_1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name = "vreg_l17b_1p8"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_s1b_1p856>; + vdd-l2-l8-supply = <&vreg_s1b_1p856>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s7b_0p952>; + + vdd-bob-supply = <&vph_pwr>; + + /* + * S2, S5, S7, S10 are ARCs: + * S2 - cx.lvl, + * S5 - mss.lvl, + * S7 - gfx.lvl, + * S10 - mx.lvl. + */ + + vreg_s1c_2p2: smps1 { + regulator-name = "vreg_s1c_2p2"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s9c_0p676: smps9 { + regulator-name = "vreg_s9c_0p676"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-name = "vreg_l2c_1p8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8_3p0: ldo4 { + regulator-name = "vreg_l4c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8_3p0: ldo5 { + regulator-name = "vreg_l5c_1p8_3p0"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +&dispcc { + status = "disabled"; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sm7325/xiaomi/taoyao/a660_zap.mbn"; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + +&ipa { + firmware-name = "qcom/sm7325/xiaomi/taoyao/ipa_fws.mbn"; + + status = "okay"; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&pm7325_gpios { + key_vol_up: key-vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qup_spi13_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi13_data_clk { + drive-strength = <6>; + bias-disable; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm7325/xiaomi/taoyao/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm7325/xiaomi/taoyao/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm7325/xiaomi/taoyao/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/sm7325/xiaomi/taoyao/wpss.mbn"; + + status = "okay"; +}; + +&spi13 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupts-extended = <&tlmm 81 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l7c_3p0>; + vddio-supply = <&vreg_l2c_1p8>; + + spi-max-frequency = <5000000>; + + touchscreen-size-x = <10800>; + touchscreen-size-y = <24000>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + /* + * 48-51: presumably NFC SE + * 56-59: presumably fingerprint reader + */ + gpio-reserved-ranges = <48 4>, <56 4>; + + bt_uart_sleep_cts: bt-uart-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + bias-bus-hold; + }; + + bt_uart_sleep_rts: bt-uart-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + bias-pull-down; + }; + + bt_uart_sleep_txd: bt-uart-sleep-txd-state { + pins = "gpio30"; + function = "gpio"; + bias-pull-up; + }; + + bt_uart_sleep_rxd: bt-uart-sleep-rxd-state { + pins = "gpio31"; + function = "gpio"; + bias-pull-up; + }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_sleep: sde-dsi-sleep-state { + pins = "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active_sleep: sde-te-active-state { + pins = "gpio80"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins = "gpio81"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + hst_bt_en: hst-bt-en-state { + pins = "gpio85"; + function = "gpio"; + bias-disable; + }; + + hst_sw_ctrl: hst-sw-ctrl-state { + pins = "gpio86"; + function = "gpio"; + bias-pull-down; + }; + + ts_reset: ts-reset-state { + pins = "gpio105"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&uart5 { + status = "okay"; +}; + +&uart7 { + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-1 = <&bt_uart_sleep_cts>, + <&bt_uart_sleep_rts>, + <&bt_uart_sleep_txd>, + <&bt_uart_sleep_rxd>; + pinctrl-names = "default", "sleep"; + + status = "okay"; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + /* + * Technically l9b enables an eLDO (supplied by s1b) which then powers + * VCCQ2 of the UFS. + */ + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&usb_1 { + /* USB 2.0 only */ + qcom,select-utmi-as-pipe-clk; + + maximum-speed = "high-speed"; + /* Remove USB3 phy */ + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p072>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sm7325/xiaomi/taoyao/vpu20_1v.mbn"; + + status = "okay"; +}; + +&wifi { + qcom,calibration-variant = "Xiaomi_taoyao"; + + status = "okay"; +}; From 81a1e944d3b8322468e95549a9c5aed4fc3465d2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 17 Jun 2026 12:20:26 +0200 Subject: [PATCH 288/864] arm64: dts: qcom: monaco-arduino-monza: Remove duplicate includes monaco-arduino-monza.dts includes monaco-monza-som.dtsi, which aleady includes monaco.dtsi and monaco-pmics.dtsi. Remove the duplicates. The resulting DTB file is identical. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260617-topic-monza_includes-v1-1-fcef9ce489fb@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 46ce0722f98f..7d75a5466950 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -10,8 +10,6 @@ #include #include -#include "monaco.dtsi" -#include "monaco-pmics.dtsi" #include "monaco-monza-som.dtsi" / { From 447f8053b1849b22bbf6f71a2cbb1a81fb931d48 Mon Sep 17 00:00:00 2001 From: Harrison Vanderbyl Date: Wed, 10 Jun 2026 00:59:05 +1000 Subject: [PATCH 289/864] arm64: dts: qcom: purwa: Add Microsoft Surface Pro 12in Initial device tree for Microsoft Surface Pro 12in Currently supported: - UFS - Touchscreen - Pen - USB 3.2 x2 (DP Alt Mode) - Audio - Wifi - Bluetooth - CDSP - ADSP - GPU Not currently supported: - Accelerometer - Front, Back and IR cameras - IRIS video decoder Tested on Surface_Pro_12in_1st_Ed_with_Snapdragon_2110 Signed-off-by: Harrison Vanderbyl Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260609145906.40854-2-harrison.vanderbyl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../dts/qcom/x1p42100-microsoft-sp12in.dts | 1194 +++++++++++++++++ 2 files changed, 1196 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 84d9ca96f248..00a75626e303 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -463,3 +463,5 @@ x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2 dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb +x1p42100-microsoft-sp12in-el2-dtbs := x1p42100-microsoft-sp12in.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p42100-microsoft-sp12in.dtb x1p42100-microsoft-sp12in-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts b/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts new file mode 100644 index 000000000000..0314b2246cdb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p42100-microsoft-sp12in.dts @@ -0,0 +1,1194 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024, Linaro Limited + * Copyright (c) 2025, Jens Glathe + * Copyright (c) 2025, Harrison Vanderbyl + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include + +#include "purwa.dtsi" +#include "hamoa-pmics.dtsi" + +/delete-node/ &pmc8380_6; +/delete-node/ &pmc8380_6_thermal; + +/ { + model = "Surface Pro 12in 1st Edition"; + compatible = "microsoft,surface-pro-12in", "qcom,x1p42100"; + chassis-type = "tablet"; + + aliases { + serial0 = &uart2; + serial1 = &uart14; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + + power-supply = <&vreg_edp_3p3>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>, <&vol_up_n_default>, <&vol_down_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + + key-vol-up { + gpios = <&pm8550_gpios 8 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-vol-down { + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + /* Right-side upper port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_sbu: endpoint { + remote-endpoint = <&usb_1_ss0_sbu_mux>; + }; + }; + }; + }; + + /* Right-side lower port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_sbu: endpoint { + remote-endpoint = <&usb_1_ss1_sbu_mux>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x20000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + vin-supply = <&vreg_panel_en>; + }; + + vreg_panel_en: regulator-panel-en { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PANEL_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-enable-ramp-delay = <150000>; + + pinctrl-0 = <&panel_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1P42100-Microsoft-Surface-Pro-12in"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; + + usb-1-ss0-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 168 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 167 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss0_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss0_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss0_sbu>; + }; + }; + }; + + usb-1-ss1-sbu-mux { + compatible = "onnn,fsusb42", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 179 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 178 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_1_ss1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb_1_ss1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_ss1_sbu>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/x1p42100/Microsoft/Surface12/qcdxkmsucpurwa.mbn"; +}; + +&i2c8 { + clock-frequency = <1000000>; + + status = "okay"; + + touchscreen@16 { + compatible = "hid-over-i2c"; + reg = <0x16>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 38 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + vddl-supply = <&vreg_l15b_1p8>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + + status = "okay"; + + /* MAX34417 @12 */ + /* MAX34417 @14 */ + /* MAX34417 @16 */ + /* MAX34417 @18 */ + /* MAX34417 @1a */ +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + /* NFC @28 Business 2109 sku only */ +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + qcom,dmic-sample-rate = <4800000>; + + vdd-micb-supply = <&vreg_l1b_1p8>; + + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + + backlight = <&backlight>; + + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pm8550_gpios { + vol_up_n_default: vol-up-n-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; + + vol_down_n_default: vol-down-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1p42100/Microsoft/Surface12/qcadsp8380.mbn", + "qcom/x1p42100/Microsoft/Surface12/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1p42100/Microsoft/Surface12/qccdsp8380.mbn", + "qcom/x1p42100/Microsoft/Surface12/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&swr0 { + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Left speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>; /* SPI (TPM) */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio2"; + function = "gpio"; + bias-disable; + }; + + panel_en: panel-en-state { + pins = "gpio29"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ssam_state: ssam-state-state { + pins = "gpio91"; + function = "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins = "gpio38"; + function = "gpio"; + bias-disable; + }; + + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + output-high; + drive-strength = <16>; + }; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb_1_ss0_sbu_default: usb-1-ss0-sbu-state { + oe-n-pins { + pins = "gpio168"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio167"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; + + usb_1_ss1_sbu_default: usb-1-ss1-sbu-state { + oe-n-pins { + pins = "gpio179"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + sel-pins { + pins = "gpio178"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + }; +}; + +&uart2 { + status = "okay"; + + embedded-controller { + compatible = "microsoft,surface-sam"; + + interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + current-speed = <4000000>; + + pinctrl-0 = <&ssam_state>; + pinctrl-names = "default"; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <900000>; + + vdd-hba-supply = <&vreg_l3j_0p8>; + + status = "okay"; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; From 765234f19964cc2ba704b76d117491ca5c7e0899 Mon Sep 17 00:00:00 2001 From: Haritha S K Date: Tue, 5 May 2026 16:56:17 +0530 Subject: [PATCH 290/864] arm64: dts: qcom: talos: Add passive polling-delay for gpu-thermal zone Introduce a passive polling delay to ensure more than one "passive" thermal point is considered when throttling the GPU thermal zone. Signed-off-by: Haritha S K Acked-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260505-qcs615_gpu_cooling-v2-1-1ba42260b29d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index d23d2325f5ff..6bd1118167e9 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -5460,6 +5460,7 @@ cpu-critical { gpu-thermal { thermal-sensors = <&tsens0 9>; + polling-delay-passive = <200>; trips { gpu_alert0: trip-point0 { From b881149621b235b8bd556c407d7cd76f0eeb3954 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:05 +0200 Subject: [PATCH 291/864] arm64: dts: xilinx: zynqmp-sck: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Radhey Shyam Pandey Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 44834bf1c19c..52954761c9f3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -218,23 +218,23 @@ &pinctrl0 { status = "okay"; pinctrl_gpio0_default: gpio0-default { - conf { - groups = "gpio0_38_grp"; - bias-pull-up; - power-source = ; - }; + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; - mux { - groups = "gpio0_38_grp"; - function = "gpio0"; - }; + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; - conf-tx { - pins = "MIO38"; - bias-disable; - output-enable; - }; - }; + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; pinctrl_uart1_default: uart1-default { conf { @@ -392,9 +392,9 @@ mux { }; &gpio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; }; &uart1 { From 531ce288b6dd43c1ce90e0b501c209783f0e0ab2 Mon Sep 17 00:00:00 2001 From: Vinayak Katoch Date: Fri, 19 Jun 2026 15:20:08 +0530 Subject: [PATCH 292/864] arm64: dts: qcom: sm8250: Add memory-region for audio PD Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Signed-off-by: Vinayak Katoch Link: https://lore.kernel.org/r/20260619-sm8250-audio-v1-1-8a76e033e209@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 271778f16895..afdd3378f0ab 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -863,6 +864,14 @@ cdsp_secure_heap: memory@8bf00000 { reg = <0x0 0x8bf00000 0x0 0x4600000>; no-map; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; }; smem { @@ -6084,6 +6093,9 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; qcom,non-secure-domain; #address-cells = <1>; #size-cells = <0>; From dee885034faf7c9b265987407ab303b464ed0058 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:20:21 +0200 Subject: [PATCH 293/864] arm64: dts: mediatek: tungsten-smarc: Remove unnecessary cells Remove unnecessary address and size cells from both the disp_dsi0 and the xhci2's ethernet usb device subnode to fix a dtbs_check warning for avoid_unnecessary_addr_size. Fixes: 9fda4a8a479f ("arm64: dts: mediatek: add device tree for Tungsten 510 board") Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi index 9f5a0ec563e8..8256279c5629 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -265,8 +265,6 @@ &disp_pwm0 { }; &disp_dsi0 { - #address-cells = <1>; - #size-cells = <0>; status = "okay"; ports { @@ -1049,8 +1047,6 @@ &xhci2 { ethernet@1 { compatible = "usb424,7850"; reg = <1>; - #address-cells = <1>; - #size-cells = <0>; mdio { #address-cells = <1>; From b6db6e4b4bfb339c0e3db87d23545af53ac2eaeb Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:18 +0200 Subject: [PATCH 294/864] arm64: dts: mediatek: mt6795: Remove deprecated UART DMA property Remove the mediatek,dma-33bits property as it is now deprecated and, while at it, also remove the fallback compatible as it was not entirely right to use anyway, because this IP is not fully compatible with the one found in MT6577 and would create more issues than the ones it could resolve (as in - it's better to not probe the controller than to probe it and manage it in some incorrect way). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 134cfa77e3b1..6dd706b27830 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -547,8 +547,7 @@ uart1: serial@11003000 { }; apdma: dma-controller@11000380 { - compatible = "mediatek,mt6795-uart-dma", - "mediatek,mt6577-uart-dma"; + compatible = "mediatek,mt6795-uart-dma"; reg = <0 0x11000380 0 0x60>, <0 0x11000400 0 0x60>, <0 0x11000480 0 0x60>, @@ -568,7 +567,6 @@ apdma: dma-controller@11000380 { dma-requests = <8>; clocks = <&pericfg CLK_PERI_AP_DMA>; clock-names = "apdma"; - mediatek,dma-33bits; #dma-cells = <1>; }; From 5551862f57e5b673fe4d9f3542b7037dbc95ddc9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:20 +0200 Subject: [PATCH 295/864] arm64: dts: mediatek: mt8183: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each of the three UART controllers. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 95cc06799533..8b0992548431 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1071,6 +1071,22 @@ gce: mailbox@10238000 { clock-names = "gce"; }; + apdma: dma-controller@11000780 { + compatible = "mediatek,mt8183-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000780 0 0x80>, <0 0x11000800 0 0x80>, + <0 0x11000880 0 0x80>, <0 0x11000900 0 0x80>, + <0 0x11000980 0 0x80>, <0 0x11000a00 0 0x80>; + interrupts = , + , + , + , + , + ; + clocks = <&infracfg CLK_INFRA_AP_DMA>; + #dma-cells = <1>; + dma-requests = <6>; + }; + auxadc: auxadc@11001000 { compatible = "mediatek,mt8183-auxadc", "mediatek,mt8173-auxadc"; @@ -1088,6 +1104,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1098,6 +1116,8 @@ uart1: serial@11003000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1108,6 +1128,8 @@ uart2: serial@11004000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; From e3999d8e4cfeb84ac67d8dbe185943304e54c1f9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:21 +0200 Subject: [PATCH 296/864] arm64: dts: mediatek: mt8186: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each of the three UART controllers. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index fded6345d422..621408439ffa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1142,6 +1142,22 @@ systimer: timer@10017000 { clocks = <&clk13m>; }; + apdma: dma-controller@10200d80 { + compatible = "mediatek,mt8186-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10200d80 0 0x80>, <0 0x10200e00 0 0x80>, + <0 0x10200e80 0 0x80>, <0 0x10200f00 0 0x80>, + <0 0x10200f80 0 0x80>, <0 0x10201000 0 0x80>; + interrupts = , + , + , + , + , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_AP_DMA>; + #dma-cells = <1>; + dma-requests = <6>; + }; + gce: mailbox@1022c000 { compatible = "mediatek,mt8186-gce"; reg = <0 0X1022c000 0 0x4000>; @@ -1218,6 +1234,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1228,6 +1246,8 @@ uart1: serial@11003000 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1482,6 +1502,8 @@ uart2: serial@11018000 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; From f58f96921848f4037c71c48ddda0a408fed0a879 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:22 +0200 Subject: [PATCH 297/864] arm64: dts: mediatek: mt8188: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each of the four UART controllers that are declared. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 75133794cec3..14a320f0c70c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1360,6 +1360,31 @@ spmi: spmi@10027000 { clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; }; + apdma: dma-controller@10220880 { + compatible = "mediatek,mt8188-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>, + <0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>, + <0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>, + <0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>, + <0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>, + <0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_BCLK>; + #dma-cells = <1>; + dma-requests = <12>; + }; + infra_iommu: iommu@10315000 { compatible = "mediatek,mt8188-iommu-infra"; reg = <0 0x10315000 0 0x1000>; @@ -1512,6 +1537,8 @@ uart0: serial@11001100 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1521,6 +1548,8 @@ uart1: serial@11001200 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1530,6 +1559,8 @@ uart2: serial@11001300 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1539,6 +1570,8 @@ uart3: serial@11001400 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; From f0c918fe2469c35390def236ea1da32686461100 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:23 +0200 Subject: [PATCH 298/864] arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to its two uart controllers. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9f8f115edd4c..898953acdb61 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -741,6 +741,19 @@ spmi: spmi@10027000 { assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; }; + apdma: dma-controller@10217a80 { + compatible = "mediatek,mt8192-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10217a80 0 0x80>, <0 0x10217b00 0 0x80>, + <0 0x10217b80 0 0x80>, <0 0x10217c00 0 0x80>; + interrupts = , + , + , + ; + clocks = <&infracfg CLK_INFRA_AP_DMA>; + #dma-cells = <1>; + dma-requests = <4>; + }; + gce: mailbox@10228000 { compatible = "mediatek,mt8192-gce"; reg = <0 0x10228000 0 0x4000>; @@ -765,6 +778,8 @@ uart0: serial@11002000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -775,6 +790,8 @@ uart1: serial@11003000 { interrupts = ; clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; From d8461fe07c1e4defee981da778eaeec43d4cbba0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Jul 2026 11:09:24 +0200 Subject: [PATCH 299/864] arm64: dts: mediatek: mt8195: Add and use UART AP_DMA controller This SoC has a DMA controller (AP_DMA) that provides one channel for each data direction (transmit and receive) for all of the UART controllers in the SoC. In order to increase the efficiency of data TX/RX over the UART controllers, add the UART DMA controller and assign the right channels to each uart controller. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c72e34c57629..9aaf8b6edcb5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -904,6 +904,31 @@ spmi: spmi@10027000 { assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; }; + apdma: dma-controller@10220880 { + compatible = "mediatek,mt8195-uart-dma", "mediatek,mt6835-uart-dma"; + reg = <0 0x10220880 0 0x80>, <0 0x10220900 0 0x80>, + <0 0x10220980 0 0x80>, <0 0x10220a00 0 0x80>, + <0 0x10220a80 0 0x80>, <0 0x10220b00 0 0x80>, + <0 0x10220b80 0 0x80>, <0 0x10220c00 0 0x80>, + <0 0x10220c80 0 0x80>, <0 0x10220d00 0 0x80>, + <0 0x10220d80 0 0x80>, <0 0x10220e00 0 0x80>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + #dma-cells = <1>; + dma-requests = <12>; + }; + iommu_infra: infra-iommu@10315000 { compatible = "mediatek,mt8195-iommu-infra"; reg = <0 0x10315000 0 0x5000>; @@ -1040,6 +1065,8 @@ uart0: serial@11001100 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1050,6 +1077,8 @@ uart1: serial@11001200 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1060,6 +1089,8 @@ uart2: serial@11001300 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1070,6 +1101,8 @@ uart3: serial@11001400 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; clock-names = "baud", "bus"; + dmas = <&apdma 6>, <&apdma 7>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1080,6 +1113,8 @@ uart4: serial@11001500 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; clock-names = "baud", "bus"; + dmas = <&apdma 8>, <&apdma 9>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1090,6 +1125,8 @@ uart5: serial@11001600 { interrupts = ; clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; clock-names = "baud", "bus"; + dmas = <&apdma 10>, <&apdma 11>; + dma-names = "tx", "rx"; status = "disabled"; }; From b8e1c0a7a19712b93895a5d418888852860230f7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:24 +0200 Subject: [PATCH 300/864] ARM: dts: st: spear: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20260706101823.341230-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/st/spear1340-evb.dts | 2 +- arch/arm/boot/dts/st/spear320.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/spear1340-evb.dts b/arch/arm/boot/dts/st/spear1340-evb.dts index 9e7c356b1d9e..133015a5dd46 100644 --- a/arch/arm/boot/dts/st/spear1340-evb.dts +++ b/arch/arm/boot/dts/st/spear1340-evb.dts @@ -259,7 +259,7 @@ sound { stream_name = "spdif-cap", "spdif-play", "i2s-play", "i2s-cap"; dai_name = "spdifin-pcm", "spdifout-pcm", "i2s0-pcm", "i2s1-pcm"; nr_controllers = <4>; - status = "okay"; + status = "okay"; }; spdif0: spdif-in@d0100000 { diff --git a/arch/arm/boot/dts/st/spear320.dtsi b/arch/arm/boot/dts/st/spear320.dtsi index 56f141297ea3..cbf494419f43 100644 --- a/arch/arm/boot/dts/st/spear320.dtsi +++ b/arch/arm/boot/dts/st/spear320.dtsi @@ -82,7 +82,7 @@ pwm: pwm@a8000000 { reg = <0xa8000000 0x1000>; #pwm-cells = <2>; status = "disabled"; - }; + }; apb { #address-cells = <1>; From 4830d793ebdb21b32771ac6724b8e2ff04497332 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:25 +0200 Subject: [PATCH 301/864] ARM: dts: st: ste: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260706101823.341230-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/st/ste-dbx5x0.dtsi | 2 +- arch/arm/boot/dts/st/ste-href.dtsi | 2 +- arch/arm/boot/dts/st/ste-snowball.dts | 2 +- arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts | 2 +- arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts | 2 +- arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts | 2 +- arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi index 0f87abeddc33..25a20fafc6b9 100644 --- a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi @@ -1119,7 +1119,7 @@ msp2: msp@80117000 { dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev - HighPrio - Fixed */ + HighPrio - Fixed */ dma-names = "rx", "tx"; clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>; diff --git a/arch/arm/boot/dts/st/ste-href.dtsi b/arch/arm/boot/dts/st/ste-href.dtsi index fbf0309e108f..a85d87665610 100644 --- a/arch/arm/boot/dts/st/ste-href.dtsi +++ b/arch/arm/boot/dts/st/ste-href.dtsi @@ -207,7 +207,7 @@ mmc@80005000 { // On-board eMMC mmc@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; + max-frequency = <100000000>; bus-width = <8>; cap-mmc-highspeed; non-removable; diff --git a/arch/arm/boot/dts/st/ste-snowball.dts b/arch/arm/boot/dts/st/ste-snowball.dts index 1322abfc7acf..14ed1079ff6c 100644 --- a/arch/arm/boot/dts/st/ste-snowball.dts +++ b/arch/arm/boot/dts/st/ste-snowball.dts @@ -295,7 +295,7 @@ mmc@80005000 { // On-board eMMC mmc@80114000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; + max-frequency = <100000000>; bus-width = <8>; cap-mmc-highspeed; no-sdio; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts index ad9a20ccaaeb..0c3eef7a294a 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-gavini.dts @@ -402,7 +402,7 @@ wifi@1 { /* eMMC */ mmc@80005000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <50000000>; bus-width = <8>; non-removable; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts index 64562a3a262c..18fb7263058e 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-janice.dts @@ -452,7 +452,7 @@ wifi@1 { /* eMMC */ mmc@80005000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <50000000>; + max-frequency = <50000000>; bus-width = <8>; non-removable; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts index cdb147dcc1db..c34d43a2b750 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-kyle.dts @@ -274,7 +274,7 @@ wifi@1 { */ mmc@80005000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; + max-frequency = <100000000>; bus-width = <8>; non-removable; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts index 064d6fee8821..7bf4287f6e13 100644 --- a/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/st/ste-ux500-samsung-skomer.dts @@ -253,7 +253,7 @@ wifi@1 { */ mmc@80005000 { arm,primecell-periphid = <0x10480180>; - max-frequency = <100000000>; + max-frequency = <100000000>; bus-width = <8>; non-removable; cap-mmc-highspeed; From 03f906d8f5541e8bb741035981304feceed5993d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 25 Jun 2026 11:13:56 +0200 Subject: [PATCH 302/864] ARM: dts: st: spear13xx: Drop unused/incorrect usbh0_id and usbh1_id "usbh0_id" and "usbh1_id" properties were never documented and never used by Linux drivers, thus should be safe to drop to fix dtbs_check warnings like: st/spear1310-evb.dtb: usb@e4800000 (st,spear600-ehci): Unevaluated properties are not allowed ('usbh0_id' was unexpected) st/spear1310-evb.dtb: usb@e5800000 (st,spear600-ehci): Unevaluated properties are not allowed ('usbh1_id' was unexpected) Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20260625091355.107054-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/st/spear13xx.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/st/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi index 0bb88f2d4ef5..cf98160ba268 100644 --- a/arch/arm/boot/dts/st/spear13xx.dtsi +++ b/arch/arm/boot/dts/st/spear13xx.dtsi @@ -178,7 +178,6 @@ usb@e4800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe4800000 0x1000>; interrupts = <0 64 0x4>; - usbh0_id = <0>; status = "disabled"; }; @@ -186,7 +185,6 @@ usb@e5800000 { compatible = "st,spear600-ehci", "usb-ehci"; reg = <0xe5800000 0x1000>; interrupts = <0 66 0x4>; - usbh1_id = <1>; status = "disabled"; }; @@ -194,7 +192,6 @@ usb@e4000000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe4000000 0x1000>; interrupts = <0 65 0x4>; - usbh0_id = <0>; status = "disabled"; }; @@ -202,7 +199,6 @@ usb@e5000000 { compatible = "st,spear600-ohci", "usb-ohci"; reg = <0xe5000000 0x1000>; interrupts = <0 67 0x4>; - usbh1_id = <1>; status = "disabled"; }; From 055044260e7a603ff587537651e12c8fbfbed851 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 10 Jun 2026 12:34:32 +0000 Subject: [PATCH 303/864] riscv: dts: spacemit: k3: Enable SD card support Add the device tree node of SDHCI-0 controller which found on CoM260-IFX board, it's currenty used for Micro SD card slot, and one GPIO pin is configured as card insertion/removal detection pin, the slot use 4-bit data bus, and up support to SDR104 speed mode. Link: https://patch.msgid.link/20260610-07-k3-enable-sd-v1-1-196ae29bd091@kernel.org Signed-off-by: Yixun Lan --- .../riscv/boot/dts/spacemit/k3-com260-ifx.dts | 18 ++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 44 +++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 13 ++++++ 3 files changed, 75 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts index 238bb03d0e9e..e7f76cd24b90 100644 --- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts @@ -19,3 +19,21 @@ chosen { stdout-path = "serial0:115200n8"; }; }; + +&sdhci0 { + pinctrl-names = "default","uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K3_GPIO(4) GPIO_ACTIVE_HIGH>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&aldo4>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 3ee1471f3798..6b808f890a28 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -689,4 +689,48 @@ uart0-0-pins { drive-strength = <25>; }; }; + + mmc1_cfg: mmc1-cfg { + mmc1-data-cmd-pins { + pinmux = , /* mmc1 dat3 */ + , /* mmc1 dat2 */ + , /* mmc1 dat1 */ + , /* mmc1 dat0 */ + ; /* mmc1 cmd */ + + bias-pull-up = <0>; + drive-strength = <25>; + power-source = <3300>; + }; + + mmc1-clk-pins { + pinmux = ; /* mmc1 clk */ + + bias-pull-down; + drive-strength = <25>; + power-source = <3300>; + }; + }; + + mmc1_uhs_cfg: mmc1-uhs-cfg { + mmc1-uhs-data-cmd-pins { + pinmux = , /* mmc1 dat3 */ + , /* mmc1 dat2 */ + , /* mmc1 dat1 */ + , /* mmc1 dat0 */ + ; /* mmc1 cmd */ + + bias-pull-up = <0>; + drive-strength = <21>; + power-source = <1800>; + }; + + mmc1-uhs-clk-pins { + pinmux = ; /* mmc1 clk */ + + bias-pull-down; + drive-strength = <21>; + power-source = <1800>; + }; + }; }; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 19fc9b49668e..dabb0d5e6bad 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1099,6 +1099,19 @@ pll: clock-controller@d4090000 { #clock-cells = <1>; }; + sdhci0: mmc@d4280000 { + compatible = "spacemit,k3-sdhci"; + reg = <0x0 0xd4280000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_SDH_AXI>, + <&syscon_apmu CLK_APMU_SDH0>; + clock-names = "core", "io"; + resets = <&syscon_apmu RESET_APMU_SDH_AXI>, + <&syscon_apmu RESET_APMU_SDH0>; + reset-names = "axi", "sdh"; + interrupts = <99 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + syscon_apmu: system-controller@d4282800 { compatible = "spacemit,k3-syscon-apmu"; reg = <0x0 0xd4282800 0x0 0x400>; From 618949bb99d72561e36e1373d504d891d0117cd7 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 Jun 2026 20:20:29 +0530 Subject: [PATCH 304/864] dt-bindings: clock: qcom: Add Glymur camera clock controller Add device tree bindings for the camera clock controller on Qualcomm Glymur SoC. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Vladimir Zapolskiy Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260624-glymur_camcc-v5-1-a321df74b1a1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,x1e80100-camcc.yaml | 3 + include/dt-bindings/clock/qcom,glymur-camcc.h | 122 ++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,glymur-camcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index b28614186cc0..e7cb8cfa957a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -8,12 +8,14 @@ title: Qualcomm Camera Clock & Reset Controller on x1e80100 maintainers: - Bryan O'Donoghue + - Jagadeesh Kona description: | Qualcomm camera clock control module provides the clocks, resets and power domains on x1e80100. See also: + include/dt-bindings/clock/qcom,glymur-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -22,6 +24,7 @@ allOf: properties: compatible: enum: + - qcom,glymur-camcc - qcom,x1e80100-camcc - qcom,x1p42100-camcc diff --git a/include/dt-bindings/clock/qcom,glymur-camcc.h b/include/dt-bindings/clock/qcom,glymur-camcc.h new file mode 100644 index 000000000000..0c93fc77ef26 --- /dev/null +++ b/include/dt-bindings/clock/qcom,glymur-camcc.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_GLYMUR_H + +/* CAM_CC clocks */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_CLK 1 +#define CAM_CC_BPS_CLK_SRC 2 +#define CAM_CC_BPS_FAST_AHB_CLK 3 +#define CAM_CC_CAMNOC_AXI_NRT_CLK 4 +#define CAM_CC_CAMNOC_AXI_RT_CLK 5 +#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6 +#define CAM_CC_CAMNOC_DCD_XO_CLK 7 +#define CAM_CC_CAMNOC_XO_CLK 8 +#define CAM_CC_CCI_0_CLK 9 +#define CAM_CC_CCI_0_CLK_SRC 10 +#define CAM_CC_CCI_1_CLK 11 +#define CAM_CC_CCI_1_CLK_SRC 12 +#define CAM_CC_CORE_AHB_CLK 13 +#define CAM_CC_CPAS_AHB_CLK 14 +#define CAM_CC_CPAS_BPS_CLK 15 +#define CAM_CC_CPAS_FAST_AHB_CLK 16 +#define CAM_CC_CPAS_IFE_0_CLK 17 +#define CAM_CC_CPAS_IFE_1_CLK 18 +#define CAM_CC_CPAS_IFE_LITE_CLK 19 +#define CAM_CC_CPAS_IPE_NPS_CLK 20 +#define CAM_CC_CPHY_RX_CLK_SRC 21 +#define CAM_CC_CSI0PHYTIMER_CLK 22 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 23 +#define CAM_CC_CSI1PHYTIMER_CLK 24 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 25 +#define CAM_CC_CSI4PHYTIMER_CLK 26 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 27 +#define CAM_CC_CSID_CLK 28 +#define CAM_CC_CSID_CLK_SRC 29 +#define CAM_CC_CSID_CSIPHY_RX_CLK 30 +#define CAM_CC_CSIPHY0_CLK 31 +#define CAM_CC_CSIPHY1_CLK 32 +#define CAM_CC_CSIPHY4_CLK 33 +#define CAM_CC_FAST_AHB_CLK_SRC 34 +#define CAM_CC_GDSC_CLK 35 +#define CAM_CC_ICP_AHB_CLK 36 +#define CAM_CC_ICP_CLK 37 +#define CAM_CC_ICP_CLK_SRC 38 +#define CAM_CC_IFE_0_CLK 39 +#define CAM_CC_IFE_0_CLK_SRC 40 +#define CAM_CC_IFE_0_DSP_CLK 41 +#define CAM_CC_IFE_0_FAST_AHB_CLK 42 +#define CAM_CC_IFE_1_CLK 43 +#define CAM_CC_IFE_1_CLK_SRC 44 +#define CAM_CC_IFE_1_DSP_CLK 45 +#define CAM_CC_IFE_1_FAST_AHB_CLK 46 +#define CAM_CC_IFE_LITE_AHB_CLK 47 +#define CAM_CC_IFE_LITE_CLK 48 +#define CAM_CC_IFE_LITE_CLK_SRC 49 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 50 +#define CAM_CC_IFE_LITE_CSID_CLK 51 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 52 +#define CAM_CC_IPE_NPS_AHB_CLK 53 +#define CAM_CC_IPE_NPS_CLK 54 +#define CAM_CC_IPE_NPS_CLK_SRC 55 +#define CAM_CC_IPE_NPS_FAST_AHB_CLK 56 +#define CAM_CC_IPE_PPS_CLK 57 +#define CAM_CC_IPE_PPS_FAST_AHB_CLK 58 +#define CAM_CC_JPEG_CLK 59 +#define CAM_CC_JPEG_CLK_SRC 60 +#define CAM_CC_MCLK0_CLK 61 +#define CAM_CC_MCLK0_CLK_SRC 62 +#define CAM_CC_MCLK1_CLK 63 +#define CAM_CC_MCLK1_CLK_SRC 64 +#define CAM_CC_MCLK2_CLK 65 +#define CAM_CC_MCLK2_CLK_SRC 66 +#define CAM_CC_MCLK3_CLK 67 +#define CAM_CC_MCLK3_CLK_SRC 68 +#define CAM_CC_MCLK4_CLK 69 +#define CAM_CC_MCLK4_CLK_SRC 70 +#define CAM_CC_MCLK5_CLK 71 +#define CAM_CC_MCLK5_CLK_SRC 72 +#define CAM_CC_MCLK6_CLK 73 +#define CAM_CC_MCLK6_CLK_SRC 74 +#define CAM_CC_MCLK7_CLK 75 +#define CAM_CC_MCLK7_CLK_SRC 76 +#define CAM_CC_PLL0 77 +#define CAM_CC_PLL0_OUT_EVEN 78 +#define CAM_CC_PLL0_OUT_ODD 79 +#define CAM_CC_PLL1 80 +#define CAM_CC_PLL1_OUT_EVEN 81 +#define CAM_CC_PLL2 82 +#define CAM_CC_PLL3 83 +#define CAM_CC_PLL3_OUT_EVEN 84 +#define CAM_CC_PLL4 85 +#define CAM_CC_PLL4_OUT_EVEN 86 +#define CAM_CC_PLL5 87 +#define CAM_CC_PLL5_OUT_EVEN 88 +#define CAM_CC_QDSS_DEBUG_CLK 89 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 90 +#define CAM_CC_QDSS_DEBUG_XO_CLK 91 +#define CAM_CC_SLEEP_CLK 92 +#define CAM_CC_SLEEP_CLK_SRC 93 +#define CAM_CC_SLOW_AHB_CLK_SRC 94 +#define CAM_CC_XO_CLK_SRC 95 + +/* CAM_CC power domains */ +#define CAM_CC_BPS_GDSC 0 +#define CAM_CC_IFE_0_GDSC 1 +#define CAM_CC_IFE_1_GDSC 2 +#define CAM_CC_IPE_0_GDSC 3 +#define CAM_CC_TITAN_TOP_GDSC 4 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IPE_0_BCR 4 +#define CAM_CC_QDSS_DEBUG_BCR 5 + +#endif From 1c436bca83bef0f7ca8d106a878a89af17048270 Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Wed, 10 Jun 2026 14:38:58 +0300 Subject: [PATCH 305/864] ARM: dts: qcom: msm8926-sony-xperia-yukon-eagle: add initial device tree Add device tree for Sony Xperia M2 (sony-eagle) smartphone based on the Qualcomm MSM8926 SoC. Initial features: - Framebuffer - GPIO buttons (Volume Down and Camera) - Regulators - Internal storage - SD card - Accelerometer - Ambient Light/Proximity sensor - NFC - pm8226_resin (Volume Up) - Vibrator - USB/Charger Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Erikas Bitovtas Link: https://lore.kernel.org/r/20260610-yukon-eagle-v4-2-763d5698bd2c@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/Makefile | 1 + .../qcom/msm8926-sony-xperia-yukon-eagle.dts | 407 ++++++++++++++++++ 2 files changed, 408 insertions(+) create mode 100644 arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index 4ffc03122784..026d5b682b2b 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ msm8226-motorola-falcon.dtb \ msm8226-motorola-titan.dtb \ + msm8926-sony-xperia-yukon-eagle.dtb \ qcom-apq8016-sbc.dtb \ qcom-apq8026-asus-sparrow.dtb \ qcom-apq8026-huawei-sturgeon.dtb \ diff --git a/arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts b/arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts new file mode 100644 index 000000000000..b3ef39726b86 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msm8926-sony-xperia-yukon-eagle.dts @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Erikas Bitovtas + */ + +/dts-v1/; + +#include "msm8926.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &adsp_region; +/delete-node/ &mba_region; +/delete-node/ &mpss_region; +/delete-node/ &smem_region; + +/ { + model = "Sony Xperia M2"; + compatible = "sony,eagle", "qcom,msm8926", "qcom,msm8226"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + display0 = &framebuffer0; + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3201000 { + compatible = "simple-framebuffer"; + reg = <0x03201000 0x800000>; + width = <540>; + height = <960>; + stride = <(540 * 3)>; + format = "r8g8b8"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + power-domains = <&mmcc MDSS_GDSC>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-camera-focus { + label = "Camera Focus"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + button-camera-snapshot { + label = "Camera Snapshot"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + + button-volume-down { + label = "Volume Down"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + reserved-memory { + framebuffer@3201000 { + reg = <0x03201000 0x800000>; + no-map; + }; + + mpss_region: mpss@8000000 { + reg = <0x08000000 0x4d00000>; + no-map; + }; + + reserved@cd00000 { + reg = <0x0cd00000 0x200000>; + no-map; + }; + + mba_region: mba@d100000 { + reg = <0x0d100000 0x3a000>; + no-map; + }; + + reserved@d13a000 { + reg = <0x0d13a000 0xc6000>; + no-map; + }; + + wcnss_region: wcnss@d200000 { + reg = <0x0d200000 0x5ae000>; + no-map; + }; + + reserved@d850000 { + reg = <0x0d850000 0x3b0000>; + no-map; + }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1400000>; + no-map; + }; + + reserved@f000000 { + reg = <0x0f000000 0x500000>; + no-map; + }; + + venus_region: venus@f500000 { + reg = <0x0f500000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x280000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + accelerometer@f { + compatible = "kionix,kxtj21009"; + reg = <0x0f>; + + interrupts-extended = <&tlmm 49 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; + + light-sensor@48 { + compatible = "sensortek,stk3310"; + reg = <0x48>; + + interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; + + proximity-near-level = <1700>; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + nfc@28 { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupts-extended = <&tlmm 21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 20 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>; + }; +}; + +&pm8226_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8226_vib { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1287500>; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&smbb { + qcom,fast-charge-current-limit = <1500000>; + qcom,fast-charge-safe-voltage = <4250000>; + qcom,minimum-input-voltage = <4200000>; + + status = "okay"; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio106", "gpio107", "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&smbb>; + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; From bd504200195c0bcb26706f363814d3426ef3baa7 Mon Sep 17 00:00:00 2001 From: Marius Dinu Date: Fri, 3 Jul 2026 11:44:53 +0300 Subject: [PATCH 306/864] ARM: dts: rockchip: add eeprom node to rk3288-tinker This board contains an EEPROM that holds the CPU serial number and ethernet MAC. It is used by U-boot when configuring the device tree for the Linux kernel. Signed-off-by: Marius Dinu Link: https://patch.msgid.link/20260703084645.7001-1-m95d+git@psihoexpert.ro Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi index 8e27a20f2845..7e16022c7d9e 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-tinker.dtsi @@ -344,6 +344,11 @@ regulator-state-mem { &i2c2 { status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; }; &i2c5 { From 068a6bd57167cb97058b08f22db0584fabdaab95 Mon Sep 17 00:00:00 2001 From: Yanan He Date: Mon, 6 Jul 2026 17:14:41 +0800 Subject: [PATCH 307/864] dt-bindings: vendor-prefixes: add alientek Add a vendor prefix for Alientek, a board and module vendor used by the ATK-DLRV1126 board. Link: https://en.alientek.com Signed-off-by: Yanan He Acked-by: Conor Dooley Link: https://patch.msgid.link/20260706-rv1126-alientek-dlrv1126-v2-1-ff3176ca362b@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..914d5a8fd628 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -88,6 +88,8 @@ patternProperties: description: ALFA Network Inc. "^algoltek,.*": description: AlgolTek, Inc. + "^alientek,.*": + description: Guangzhou Xingyi Intelligent Technology Co., Ltd. "^allegro,.*": description: Allegro DVT "^allegromicro,.*": From f1522feb72aa5231532c9f69e7f5cc91972697e1 Mon Sep 17 00:00:00 2001 From: Yanan He Date: Mon, 6 Jul 2026 17:14:42 +0800 Subject: [PATCH 308/864] dt-bindings: arm: rockchip: Add Alientek DLRV1126 The board consists of a DLRV1126 carrier board and a CLRV1126F core module based on the Rockchip RV1126 SoC. Signed-off-by: Yanan He Acked-by: Conor Dooley Link: https://patch.msgid.link/20260706-rv1126-alientek-dlrv1126-v2-2-ff3176ca362b@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..9058f2a461d5 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -162,6 +162,13 @@ properties: - const: coolpi,pi-4b - const: rockchip,rk3588s + - description: Alientek CLRV1126F SoM based boards + items: + - enum: + - alientek,dlrv1126 + - const: alientek,clrv1126f + - const: rockchip,rv1126 + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards items: - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board From 17bee9ee734e56d512ec7803eb7948adb56d1d9c Mon Sep 17 00:00:00 2001 From: Yanan He Date: Mon, 6 Jul 2026 17:14:44 +0800 Subject: [PATCH 309/864] ARM: dts: rockchip: Add RV1126 I2C5 The controller is present in the SoC and can be used by boards for external peripherals, such as an RTC on the Alientek DLRV1126 carrier board. Signed-off-by: Yanan He Link: https://patch.msgid.link/20260706-rv1126-alientek-dlrv1126-v2-4-ff3176ca362b@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi | 10 ++++++++++ arch/arm/boot/dts/rockchip/rv1126.dtsi | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index 35ef6732281f..1d883b80aed4 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -123,6 +123,16 @@ i2c3m2_xfer: i2c3m2-xfer { <1 RK_PD7 3 &pcfg_pull_none>; }; }; + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>, + /* i2c5_sda_m0 */ + <2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>; + }; + }; i2s0 { i2s0m0_lrck_tx: i2s0m0-lrck-tx { rockchip,pins = diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index d6e8b63daa42..d0cdc5f74212 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -23,6 +23,7 @@ aliases { i2c0 = &i2c0; i2c2 = &i2c2; i2c3 = &i2c3; + i2c5 = &i2c5; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -400,6 +401,20 @@ i2c3: i2c@ff520000 { status = "disabled"; }; + i2c5: i2c@ff540000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff540000 0x1000>; + interrupts = ; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + rockchip,grf = <&pmugrf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm8: pwm@ff550000 { compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; reg = <0xff550000 0x10>; From 44045aa7a9a9e6484617f44f77a3efb2d8e78565 Mon Sep 17 00:00:00 2001 From: Yanan He Date: Mon, 6 Jul 2026 17:14:45 +0800 Subject: [PATCH 310/864] ARM: dts: rockchip: Add Alientek DLRV1126 The board consists of a CLRV1126F core module and a DLRV1126 carrier board. The core module contains the RV1126 SoC, eMMC and RK809 PMIC, while the carrier board provides Ethernet, SD card, AP6212 WiFi and Bluetooth, PCF8563 RTC, ADC keys, GPIO LEDs and audio connectors. The board has been tested with Ethernet/NFS boot, eMMC, SD card, SDIO WiFi enumeration, Bluetooth LE scanning, RTC, ADC keys, GPIO LEDs and RK809 audio card registration. Signed-off-by: Yanan He Reviewed-by: Andrew Lunn #gmac and mdio nodes Link: https://patch.msgid.link/20260706-rv1126-alientek-dlrv1126-v2-5-ff3176ca362b@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/Makefile | 1 + .../rockchip/rv1126-alientek-clrv1126f.dtsi | 291 ++++++++++++++++++ .../dts/rockchip/rv1126-alientek-dlrv1126.dts | 256 +++++++++++++++ 3 files changed, 548 insertions(+) create mode 100644 arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi create mode 100644 arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts diff --git a/arch/arm/boot/dts/rockchip/Makefile b/arch/arm/boot/dts/rockchip/Makefile index d0154fd7ff24..e9f9e0ac3bfd 100644 --- a/arch/arm/boot/dts/rockchip/Makefile +++ b/arch/arm/boot/dts/rockchip/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-evb.dtb \ rv1109-relfor-saib.dtb \ rv1109-sonoff-ihost.dtb \ + rv1126-alientek-dlrv1126.dtb \ rv1126-edgeble-neu2-io.dtb \ rv1126-sonoff-ihost.dtb \ rk3036-evb.dtb \ diff --git a/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi b/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi new file mode 100644 index 000000000000..d7c4230a06dc --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-alientek-clrv1126f.dtsi @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Yanan He + */ + +#include "rv1126.dtsi" + +/ { + compatible = "alientek,clrv1126f", "rockchip,rv1126"; + + aliases { + mmc0 = &emmc; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + #sound-dai-cells = <0>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + clock-names = "mclk"; + clocks = <&cru MCLK_I2S0_TX_OUT2IO>; + assigned-clocks = <&cru MCLK_I2S0_TX_OUT2IO>; + assigned-clock-parents = <&cru MCLK_I2S0_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc3v3_sys>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vcc_1v8>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_1v8>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts b/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts new file mode 100644 index 000000000000..0234b93ceb59 --- /dev/null +++ b/arch/arm/boot/dts/rockchip/rv1126-alientek-dlrv1126.dts @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Yanan He + */ + +/dts-v1/; +#include +#include "rv1126-alientek-clrv1126f.dtsi" + +/ { + model = "Alientek ATK-DLRV1126"; + compatible = "alientek,dlrv1126", "alientek,clrv1126f", "rockchip,rv1126"; + + aliases { + ethernet0 = &gmac; + mmc1 = &sdio; + mmc2 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-esc { + label = "esc"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + + button-left { + label = "left"; + linux,code = ; + press-threshold-microvolt = <801562>; + }; + + button-menu { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <1198828>; + }; + + button-right { + label = "right"; + linux,code = ; + press-threshold-microvolt = <400781>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "sys-led"; + gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led-1 { + label = "user-led"; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "on"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Speaker", "Speaker", + "Headphone", "Headphones", + "Microphone", "Mic Jack"; + simple-audio-card,routing = + "Speaker", "SPKO", + "Headphones", "HPOL", + "Headphones", "HPOR", + "MICL", "Mic Jack"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <20000>; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, + <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim &rgmiim1_bus2 &rgmiim1_bus4 + &clk_out_ethernetm1_pins>; + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio1>; + interrupts = ; + }; +}; + +&i2s0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_sclk_tx>, + <&i2s0m0_mclk>, + <&i2s0m0_lrck_tx>, + <&i2s0m0_sdo0>, + <&i2s0m0_sdo1_sdi3>; + rockchip,trcm-sync-tx-only; + rockchip,i2s-rx-route = <3 1 2 0>; + rockchip,i2s-tx-route = <0 1 2 3>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETHERNET_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + }; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio { + bus-width = <4>; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <25000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43430a1-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wakeup"; + max-speed = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>; + shutdown-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; From 4b4a2ce19af5badef165c109d0d6d9f7c102914a Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 27 Jun 2026 22:42:23 +0530 Subject: [PATCH 311/864] dt-binding: ARM: samsung: Add Samsung Exynos8855 Add Samsung Exynos8855 smdk board to documentation Signed-off-by: Alim Akhtar Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260627171228.2687857-2-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 753b3ba1b607..273464400477 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -235,6 +235,12 @@ properties: - winlink,e850-96 # WinLink E850-96 - const: samsung,exynos850 + - description: Exynos8855 based boards + items: + - enum: + - samsung,exynos8855-smdk # Samsung SMDK + - const: samsung,exynos8855 + - description: Exynos8895 based boards items: - enum: From f03058d3768c3ec4af0fab7a36d0631423cb3cf5 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 27 Jun 2026 22:42:27 +0530 Subject: [PATCH 312/864] arm64: dts: exynos: add initial support for Samsung Exynos8855 smdk Add initial devicetree support for Samsung smdk board using Exynos8855 SoC. This SoC has Octa-core CPU with tri cluster architecture, a custom GPU and a NPU supporting up to 14.7 TOPS apart from other supporting peripheral and IPs. Commercially this SoC is also known as Exynos1580 [1] [1] https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/ Signed-off-by: Alim Akhtar Link: https://semiconductor.samsung.com/processor/mobile-processor/exynos-1580/ Link: https://patch.msgid.link/20260627171228.2687857-6-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/exynos8855-pinctrl.dtsi | 574 ++++++++++++++++++ .../arm64/boot/dts/exynos/exynos8855-smdk.dts | 31 + arch/arm64/boot/dts/exynos/exynos8855.dtsi | 204 +++++++ 4 files changed, 810 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos8855-smdk.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos8855.dtsi diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index 76cc23acb9b2..8c48ce2e02e5 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \ exynos7870-on7xelte.dtb \ exynos7885-jackpotlte.dtb \ exynos850-e850-96.dtb \ + exynos8855-smdk.dtb \ exynos8895-dreamlte.dtb \ exynos9810-starlte.dtb \ exynos990-c1s.dtb \ diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi new file mode 100644 index 000000000000..b65f1698cd74 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's S5E8855 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2023 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's S5E8855 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include "exynos-pinctrl.h" + +&pinctrl_alive { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + ; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpq1: gpq1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc3: gpc3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc4: gpc4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc5: gpc5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc6: gpc6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc7: gpc7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc8: gpc8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc9: gpc9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc10: gpc10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc11: gpc11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc12: gpc12-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc13: gpc13-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpc14: gpc14-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpj0: gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpj1: gpj1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpj2: gpj2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm6: gpm6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm7: gpm7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm8: gpm8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm9: gpm9-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm10: gpm10-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm11: gpm11-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm12: gpm12-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm13: gpm13-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm14: gpm14-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm15: gpm15-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm16: gpm16-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm17: gpm17-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm18: gpm18-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm19: gpm19-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm20: gpm20-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm21: gpm21-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; + +&pinctrl_hsi_ufs { + gpf3: gpf3-gpio-bank{ + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_peric { + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_pericmmc { + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_usi { + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts new file mode 100644 index 000000000000..e74ff8a1bbcf --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos8855-smdk.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos8855 SMDK board device tree source + * + * Copyright (C) 2023 Samsung Electronics Co., Ltd. + * + * Device tree source file for Samsung SMDK board which is based on + * Exynos8855 SoC. + */ + +/dts-v1/; + +#include "exynos8855.dtsi" + +/ { + model = "Samsung Exynos8855 SMDK board"; + compatible = "samsung,exynos8855-smdk","samsung,exynos8855"; + + chosen { + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x80000000>; + }; + +}; + +&oscclk { + clock-frequency = <76800000>; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi new file mode 100644 index 000000000000..9d82fceb5130 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos8855 SoC device tree source + * + * Copyright (C) 2023 Samsung Electronics Co., Ltd. + * + * Samsung Exynos8855 SoC device nodes are listed in this file. + * Exynos8855 based board files can include this file and provide + * values for board specific bindings. + */ + +#include + +/ { + compatible = "samsung,exynos8855"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_hsi_ufs; + pinctrl3 = &pinctrl_peric; + pinctrl4 = &pinctrl_pericmmc; + pinctrl5 = &pinctrl_usi; + }; + + oscclk: clock-oscclk { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x300>; + enable-method = "psci"; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x400>; + enable-method = "psci"; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x500>; + enable-method = "psci"; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x600>; + enable-method = "psci"; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x700>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + gic: interrupt-controller@10200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10200000 0x10000>, + <0x10240000 0x140000>; + interrupts = ; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos8855-pinctrl"; + reg = <0x11850000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos8855-wakeup-eint", + "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@12030000 { + compatible = "samsung,exynos8855-pinctrl"; + reg = <0x12030000 0x1000>; + interrupts = ; + }; + + pinctrl_usi: pinctrl@15030000 { + compatible = "samsung,exynos8855-pinctrl"; + reg = <0x15030000 0x1000>; + interrupts = ; + }; + + pinctrl_peric: pinctrl@15440000 { + compatible = "samsung,exynos8855-pinctrl"; + reg = <0x15440000 0x1000>; + interrupts = ; + }; + + pinctrl_pericmmc: pinctrl@154f0000 { + compatible = "samsung,exynos8855-pinctrl"; + reg = <0x154f0000 0x1000>; + interrupts = ; + }; + + pinctrl_hsi_ufs: pinctrl@17040000 { + compatible = "samsung,exynos8855-pinctrl"; + reg = <0x17040000 0x1000>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = + , + , + , + ; + }; +}; + +#include "exynos8855-pinctrl.dtsi" From a87d503a0ab077b0d9892290ab7dbec29f922eb1 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Sat, 27 Jun 2026 22:42:28 +0530 Subject: [PATCH 313/864] MAINTAINERS: Add entry for Samsung Exynos8855 SoC Add maintainers entry for the Samsung Exynos8855 SoC based platforms Signed-off-by: Alim Akhtar Reviewed-by: Peter Griffin Link: https://patch.msgid.link/20260627171228.2687857-7-alim.akhtar@samsung.com Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 15011f5752a9..be843bf82036 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23993,6 +23993,13 @@ F: arch/arm64/boot/dts/exynos/exynos850* F: drivers/clk/samsung/clk-exynos850.c F: include/dt-bindings/clock/exynos850.h +SAMSUNG EXYNOS8855 SoC SUPPORT +M: Alim Akhtar +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: arch/arm64/boot/dts/exynos/exynos8855* + SAMSUNG EXYNOS ACPM MAILBOX PROTOCOL M: Tudor Ambarus L: linux-kernel@vger.kernel.org From 50a8e96a1513760418e7f2e5bc51a7e48fc2b82e Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 7 Jul 2026 10:32:09 +0200 Subject: [PATCH 314/864] dt-bindings: xilinx: Remove EDK/Ethernet references The latest EDK version was 14.7 released in 2013 that's why remove description for it. Also remove generic description for Ethernet which doesn't bring any value. Reviewed-by: Radhey Shyam Pandey Acked-by: Conor Dooley Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/xilinx.txt | 98 +------------------- 1 file changed, 1 insertion(+), 97 deletions(-) diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt index 0ee9de99b3ae..a1a2cde7b7d8 100644 --- a/Documentation/devicetree/bindings/xilinx.txt +++ b/Documentation/devicetree/bindings/xilinx.txt @@ -1,93 +1,4 @@ - d) Xilinx IP cores - - The Xilinx EDK toolchain ships with a set of IP cores (devices) for use - in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range - of standard device types (network, serial, etc.) and miscellaneous - devices (gpio, LCD, spi, etc). Also, since these devices are - implemented within the fpga fabric every instance of the device can be - synthesised with different options that change the behaviour. - - Each IP-core has a set of parameters which the FPGA designer can use to - control how the core is synthesized. Historically, the EDK tool would - extract the device parameters relevant to device drivers and copy them - into an 'xparameters.h' in the form of #define symbols. This tells the - device drivers how the IP cores are configured, but it requires the kernel - to be recompiled every time the FPGA bitstream is resynthesized. - - The new approach is to export the parameters into the device tree and - generate a new device tree each time the FPGA bitstream changes. The - parameters which used to be exported as #defines will now become - properties of the device node. In general, device nodes for IP-cores - will take the following form: - - (name): (generic-name)@(base-address) { - compatible = "xlnx,(ip-core-name)-(HW_VER)" - [, (list of compatible devices), ...]; - reg = <(baseaddr) (size)>; - interrupt-parent = <&interrupt-controller-phandle>; - interrupts = < ... >; - xlnx,(parameter1) = "(string-value)"; - xlnx,(parameter2) = <(int-value)>; - }; - - (generic-name): an open firmware-style name that describes the - generic class of device. Preferably, this is one word, such - as 'serial' or 'ethernet'. - (ip-core-name): the name of the ip block (given after the BEGIN - directive in system.mhs). Should be in lowercase - and all underscores '_' converted to dashes '-'. - (name): is derived from the "PARAMETER INSTANCE" value. - (parameter#): C_* parameters from system.mhs. The C_ prefix is - dropped from the parameter name, the name is converted - to lowercase and all underscore '_' characters are - converted to dashes '-'. - (baseaddr): the baseaddr parameter value (often named C_BASEADDR). - (HW_VER): from the HW_VER parameter. - (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). - - Typically, the compatible list will include the exact IP core version - followed by an older IP core version which implements the same - interface or any other device with the same interface. - - 'reg' and 'interrupts' are all optional properties. - - For example, the following block from system.mhs: - - BEGIN opb_uartlite - PARAMETER INSTANCE = opb_uartlite_0 - PARAMETER HW_VER = 1.00.b - PARAMETER C_BAUDRATE = 115200 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_CLK_FREQ = 50000000 - PARAMETER C_BASEADDR = 0xEC100000 - PARAMETER C_HIGHADDR = 0xEC10FFFF - BUS_INTERFACE SOPB = opb_7 - PORT OPB_Clk = CLK_50MHz - PORT Interrupt = opb_uartlite_0_Interrupt - PORT RX = opb_uartlite_0_RX - PORT TX = opb_uartlite_0_TX - PORT OPB_Rst = sys_bus_reset_0 - END - - becomes the following device tree node: - - opb_uartlite_0: serial@ec100000 { - device_type = "serial"; - compatible = "xlnx,opb-uartlite-1.00.b"; - reg = ; - interrupt-parent = <&opb_intc_0>; - interrupts = <1 0>; // got this from the opb_intc parameters - current-speed = ; // standard serial device prop - clock-frequency = ; // standard serial device prop - xlnx,data-bits = <8>; - xlnx,odd-parity = <0>; - xlnx,use-parity = <0>; - }; - - That covers the general approach to binding xilinx IP cores into the - device tree. The following are bindings for specific devices: + Bindings for specific devices: i) Xilinx ML300 Framebuffer @@ -102,13 +13,6 @@ Default is . - rotate-display (empty) : rotate display 180 degrees. - iii) Xilinx EMAC and Xilinx TEMAC - - Xilinx Ethernet devices. In addition to general xilinx properties - listed above, nodes for these devices should include a phy-handle - property, and may include other common network device properties - like local-mac-address. - v) Xilinx hwicap Xilinx hwicap devices provide access to the configuration logic From e2393ed6275732036d8f7c2b05de1319c5c691d6 Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Wed, 3 Jun 2026 14:23:03 -0500 Subject: [PATCH 315/864] dt-bindings: arm: ti: Add am62l3-beaglebadge This board is based on ti,am62l3. https://www.beagleboard.org/boards/beaglebadge Signed-off-by: Judith Mendez Acked-by: Conor Dooley Link: https://patch.msgid.link/20260603192305.1347908-2-jm@ti.com Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 69b5441cbf1a..060e879bc104 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -40,6 +40,7 @@ properties: - description: K3 AM62L3 SoC and Boards items: - enum: + - beagle,am62l3-beaglebadge - ti,am62l3-evm - const: ti,am62l3 From 0c78b72362f4bd90f8a46ea7be385fe05137e06d Mon Sep 17 00:00:00 2001 From: Judith Mendez Date: Wed, 3 Jun 2026 14:23:04 -0500 Subject: [PATCH 316/864] arm64: dts: ti: Add k3-am62l3-beaglebadge BeagleBoard.org BeagleBadge is a compact, affordable open source hardware single board computer based on the Texas Instruments AM62L3 SoC designed for IoT and embedded applications with low power consumption. Expansion is provided over open standards based headers including QWIIC and GPIO interfaces. https://www.beagleboard.org/boards/beaglebadge Co-developed-by: Andrew Davis Signed-off-by: Andrew Davis Signed-off-by: Judith Mendez Link: https://patch.msgid.link/20260603192305.1347908-3-jm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am62l3-beaglebadge.dts | 657 ++++++++++++++++++ 2 files changed, 658 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62l3-beaglebadge.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 371f9a043fe5..913f51ebee38 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62d2-evm.dtb # Boards with AM62Lx SoCs +dtb-$(CONFIG_ARCH_K3) += k3-am62l3-beaglebadge.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb # Boards with AM62Px SoC diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-beaglebadge.dts b/arch/arm64/boot/dts/ti/k3-am62l3-beaglebadge.dts new file mode 100644 index 000000000000..ee2d562baf51 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62l3-beaglebadge.dts @@ -0,0 +1,657 @@ +// SPDX-License-Identifier: GPL-2.0-only or MIT +/* + * https://www.beagleboard.org/boards/beaglebadge + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am62l3.dtsi" +#include "k3-pinctrl.h" + +/ { + compatible = "beagle,am62l3-beaglebadge", "ti,am62l3"; + model = "BeagleBoard.org BeagleBadge"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c4 = &wkup_i2c0; + mmc1 = &sdhci1; + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + /* 256MB */ + reg = <0x00000000 0x80000000 0x00000000 0x10000000>; + device_type = "memory"; + bootph-all; + }; + + thermal-zones { + wkup0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&vtm0 0>; + + trips { + crit0 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-select { + label = "SELECT"; + linux,code = ; + gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + }; + + button-back { + label = "BACK"; + linux,code = ; + gpios = <&gpio0 104 GPIO_ACTIVE_LOW>; + }; + + button-up { + label = "UP"; + linux,code = ; + gpios = <&gpio0 32 GPIO_ACTIVE_LOW>; + }; + + button-down { + label = "DOWN"; + linux,code = ; + gpios = <&gpio0 42 GPIO_ACTIVE_LOW>; + }; + + button-left { + label = "LEFT"; + linux,code = ; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + }; + + button-right { + label = "RIGHT"; + linux,code = ; + gpios = <&gpio0 95 GPIO_ACTIVE_LOW>; + }; + }; + + multicolor-led { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + max-brightness = <255>; + + led-red { + pwms = <&ecap2 0 10000000 0>; + color = ; + }; + + led-green { + pwms = <&ecap1 0 10000000 0>; + color = ; + }; + + led-blue { + pwms = <&epwm1 1 10000000 0>; + color = ; + }; + }; + }; + + seven-segment-left { + compatible = "gpio-7-segment"; + segment-gpios = <&mcp23s18 0 GPIO_ACTIVE_LOW>, + <&mcp23s18 1 GPIO_ACTIVE_LOW>, + <&mcp23s18 2 GPIO_ACTIVE_LOW>, + <&mcp23s18 3 GPIO_ACTIVE_LOW>, + <&mcp23s18 4 GPIO_ACTIVE_LOW>, + <&mcp23s18 5 GPIO_ACTIVE_LOW>, + <&mcp23s18 6 GPIO_ACTIVE_LOW>, + <&mcp23s18 7 GPIO_ACTIVE_LOW>; + }; + + seven-segment-right { + compatible = "gpio-7-segment"; + segment-gpios = <&mcp23s18 8 GPIO_ACTIVE_LOW>, + <&mcp23s18 9 GPIO_ACTIVE_LOW>, + <&mcp23s18 10 GPIO_ACTIVE_LOW>, + <&mcp23s18 11 GPIO_ACTIVE_LOW>, + <&mcp23s18 12 GPIO_ACTIVE_LOW>, + <&mcp23s18 13 GPIO_ACTIVE_LOW>, + <&mcp23s18 14 GPIO_ACTIVE_LOW>, + <&mcp23s18 15 GPIO_ACTIVE_LOW>; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&epwm0 1 1000000 0>; + amp-supply = <&sensor_3v3>; + }; + + vsys_out: regulator-0 { + /* output of BQ24070 */ + compatible = "regulator-fixed"; + regulator-name = "VSYS_OUT"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3v3_main: regulator-1 { + /* output of TPS62A06 */ + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MAIN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_out>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_3v3: regulator-2 { + /* output of TPS22965 */ + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_main>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vdd_3v3_sd: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-boot-on; + enable-active-high; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_3v3_sd_ena_pins_default>; + bootph-all; + }; + + sensor_3v3: regulator-4 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "Sensor_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3>; + regulator-boot-on; + enable-active-high; + gpios = <&wkup_gpio0 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_3v3_ena_pins_default>; + bootph-all; + }; +}; + +&pmx0 { + uart0_pins_default: uart0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */ + >; + bootph-all; + }; + + uart0_pins_wakeup: uart0-wakeup-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */ + AM62LX_IOPAD(0x01b4, PIN_INPUT | PIN_WKUP_EN, 0) /* (D13) UART0_RXD */ + >; + bootph-all; + }; + + uart1_pins_default: uart1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x019c, PIN_OUTPUT, 2) /* (A12) MCASP0_ACLKR.UART1_TXD */ + AM62LX_IOPAD(0x0198, PIN_INPUT, 2) /* (C11) MCASP0_AFSR.UART1_RXD */ + AM62LX_IOPAD(0x0180, PIN_INPUT, 2) /* (A8) MCASP0_AXR3.UART1_CTSn */ + AM62LX_IOPAD(0x0184, PIN_OUTPUT, 2) /* (B10) MCASP0_AXR2.UART1_RTSn */ + >; + bootph-all; + }; + + usr_button_pins_default: usr-button-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00a4, PIN_INPUT, 7) /* (H18) GPMC0_AD11.GPIO0_26 */ + AM62LX_IOPAD(0x01e4, PIN_INPUT, 7) /* (D16) EXT_REFCLK1.GPIO0_104 */ + AM62LX_IOPAD(0x00c0, PIN_INPUT, 7) /* (N19) GPMC0_ADVn_ALE.GPIO0_32 */ + AM62LX_IOPAD(0x00e8, PIN_INPUT, 7) /* (L19) GPMC0_CSn1.GPIO0_42 */ + AM62LX_IOPAD(0x00b8, PIN_INPUT, 7) /* (L21) GPMC0_CLK.GPIO0_31 */ + AM62LX_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) UART0_RTSn.GPIO0_95 */ + >; + bootph-all; + }; + + i2c0_pins_default: i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */ + AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */ + >; + bootph-all; + }; + + i2c1_pins_default: i2c1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */ + AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */ + >; + bootph-all; + }; + + i2c2_qwiic_pins_default: i2c2-qwiic-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01dc, PIN_INPUT_PULLUP, 0) /* (B8) I2C2_SCL */ + AM62LX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D8) I2C2_SDA */ + >; + bootph-all; + }; + + vdd_3v3_sd_ena_pins_default: vdd-3v3-sd-ena-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x07c, PIN_OUTPUT, 7) /* (L23) GPMC0_AD1.GPIO0_16 */ + >; + bootph-all; + }; + + sensor_3v3_ena_pins_default: sensor-3v3-ena-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x004, PIN_OUTPUT, 7) /* (AA23) WKUP_UART0_TXD.WKUP_GPIO0_1 */ + >; + bootph-all; + }; + + mmc1_pins_default: mmc1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */ + AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */ + AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */ + AM62LX_IOPAD(0x0220, PIN_INPUT, 0) /* (Y4) MMC1_DAT1 */ + AM62LX_IOPAD(0x021c, PIN_INPUT, 0) /* (AA2) MMC1_DAT2 */ + AM62LX_IOPAD(0x0218, PIN_INPUT, 0) /* (AB2) MMC1_DAT3 */ + AM62LX_IOPAD(0x0234, PIN_INPUT, 7) /* (B6) MMC1_SDCD.GPIO0_122 */ + >; + bootph-all; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | + PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */ + >; + bootph-all; + }; + + pwm_beeper_pins_default: pwm-beeper-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00b0, PIN_OUTPUT, 4) /* (F22) GPMC0_AD14.EHRPWM0_B */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x01e8, PIN_INPUT, 0) /* (C8) EXTINTn */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0010, PIN_INPUT_PULLUP, 0) /* (AB22) WKUP_I2C0_SCL */ + AM62LX_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (AA22) WKUP_I2C0_SDA */ + >; + bootph-all; + }; + + rgb_led_ecap2_pins_default: rgb-led-ecap2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0190, PIN_OUTPUT, 2) /* (A11) MCASP0_ACLKX.ECAP2_IN_APWM_OUT */ + >; + }; + + rgb_led_ecap1_pins_default: rgb-led-ecap1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0188, PIN_OUTPUT, 2) /* (A9) MCASP0_AXR1.ECAP1_IN_APWM_OUT */ + >; + }; + + rgb_led_epwm1_pins_default: rgb-led-epwm1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x018c, PIN_OUTPUT, 5) /* (B9) MCASP0_AXR0.EHRPWM1_B */ + >; + }; + + spi1_pins_default: spi1-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x008c, PIN_OUTPUT, 4) /* (H22) GPMC0_AD5.SPI1_CLK */ + AM62LX_IOPAD(0x0088, PIN_OUTPUT, 4) /* (K23) GPMC0_AD4.SPI1_CS0 */ + AM62LX_IOPAD(0x0080, PIN_INPUT, 4) /* (K22) GPMC0_AD2.SPI1_D0 */ + AM62LX_IOPAD(0x0084, PIN_OUTPUT, 4) /* (J23) GPMC0_AD3.SPI1_D1 */ + >; + bootph-all; + }; + + spi3_pins_default: spi3-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00d0, PIN_OUTPUT, 5) /* (P22) GPMC0_BE1n.SPI3_CLK */ + AM62LX_IOPAD(0x00cc, PIN_OUTPUT, 5) /* (P23) GPMC0_BE0n_CLE.SPI3_CS0 */ + AM62LX_IOPAD(0x00d4, PIN_INPUT, 5) /* (N23) GPMC0_WAIT0.SPI3_D0 */ + AM62LX_IOPAD(0x00d8, PIN_OUTPUT, 5) /* (N22) GPMC0_WAIT1.SPI3_D1 */ + >; + }; + + mcp23s18_reset_pins_default: mcp23s18-reset-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00a0, PIN_OUTPUT, 7) /* (H21) GPMC0_AD10.GPIO0_25 */ + >; + }; + + epwm2_pins_default: epwm2-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00c4, PIN_OUTPUT, 4) /* (N20) GPMC0_OEn_REn.EHRPWM2_A */ + >; + }; + + lora_control_pins_default: lora-control-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (M19) GPMC0_WEn.GPIO0_34 */ + AM62LX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (L20) GPMC0_CSn0.GPIO0_41 */ + AM62LX_IOPAD(0x01a4, PIN_INPUT, 7) /* (D11) SPI0_CS1.GPIO0_88 */ + AM62LX_IOPAD(0x01bc, PIN_INPUT, 7) /* (B14) UART0_CTSn.GPIO0_94 */ + >; + bootph-all; + }; + + gpio0_pins_default: gpio0-default-pins { + pinctrl-single,pins = < + AM62LX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (L22) GPMC0_AD0.GPIO0_15 */ + AM62LX_IOPAD(0x00e0, PIN_INPUT, 7) /* (M21) GPMC0_DIR.GPIO0_40 */ + AM62LX_IOPAD(0x00ec, PIN_OUTPUT, 7) /* (M23) GPMC0_CSn2.GPIO0_43 */ + AM62LX_IOPAD(0x00f0, PIN_INPUT, 7) /* (M22) GPMC0_CSn3.GPIO0_44 */ + AM62LX_IOPAD(0x0194, PIN_OUTPUT, 7) /* (B11) MCASP0_AFSX.GPIO0_84 */ + >; + bootph-all; + }; +}; + +&uart0 { + wakeup-source; + pinctrl-0 = <&uart0_pins_default>; + pinctrl-1 = <&uart0_pins_wakeup>; + pinctrl-names = "default", "wakeup"; + bootph-all; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_default>; + bootph-all; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + bootph-all; + status = "okay"; + + /* T&H Sensor */ + th-sensor@44 { + compatible = "sensirion,sht4x"; + reg = <0x44>; + }; + + /* EEPROM */ + eeprom@50 { + /* FT24C32A-ELRT */ + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + /* Fuel Gauge */ + fuel-gauge@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; + + /* IMU Sensor */ + accelerometer@6a { + compatible = "st,lsm6ds3tr-c"; + reg = <0x6a>; + vdd-supply = <&vcc_3v3_main>; + vddio-supply = <&vcc_3v3_main>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + bootph-all; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_qwiic_pins_default>; + bootph-all; + status = "okay"; +}; + +&wkup_i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + bootph-all; + status = "okay"; + + tps65214: pmic@30 { + compatible = "ti,tps65214"; + reg = <0x30>; + interrupt-parent = <&gic500>; + interrupts = ; + buck1-supply = <&vcc_3v3_main>; + buck2-supply = <&vcc_3v3_main>; + buck3-supply = <&vcc_3v3_main>; + ldo1-supply = <&vcc_3v3_main>; + ldo2-supply = <&vcc_3v3_main>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + ti,power-button; + bootph-all; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "PMIC_VDD_RTC"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&gpio0 { + gpio-line-names = "","","","","","","","","","", /* 0-9 */ + "","","","","","BOOST_5V_ENA","VDD_3V3_SD_ENA","","","", /* 10-19 */ + "","","","","","MCP23S18_RESET","BTN_SELECT","","","", /* 20-29 */ + "","BTN_LEFT","BTN_UP","","LORA_RESET","","","","","", /* 30-39 */ + "GAUGE_BATLOW","LORA_RFSW","BTN_DOWN","USB_RST","MBUS_INT","","","","","", /* 40-49 */ + "","WLAN_EN","","","","","","","","", /* 50-59 */ + "","","","","","","","","","", /* 60-69 */ + "","","","","","","","","","", /* 70-79 */ + "","","","","MBUS_RST","","","","LORA_BUSY","", /* 80-89 */ + "","","","","LORA_DIO","BTN_RIGHT","","","","", /* 90-99 */ + "","","","","BTN_BACK","","","","","", /* 100-109 */ + "","","","","","","","","","", /* 110-119 */ + "","","SD_CD","","",""; /* 120-125 */ + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins_default>, <&usr_button_pins_default>, <&lora_control_pins_default>; + bootph-all; + status = "okay"; +}; + +&wkup_gpio0 { + gpio-line-names = "","SENSOR_3V3_ENA","","","","","",""; /* 0-7 */ + bootph-all; + status = "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_3v3_sd>; + disable-wp; + cd-gpios = <&gpio0 122 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + ti,fails-without-test-cd; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + bootph-all; + status = "okay"; +}; + +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_beeper_pins_default>; + status = "okay"; +}; + +&epwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_epwm1_pins_default>; + status = "okay"; +}; + +&epwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&epwm2_pins_default>; + status = "okay"; +}; + +&ecap1 { + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_ecap1_pins_default>; + status = "okay"; +}; + +&ecap2 { + pinctrl-names = "default"; + pinctrl-0 = <&rgb_led_ecap2_pins_default>; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + usb-role-switch; + bootph-all; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + bootph-all; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; + bootph-all; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_default>; + status = "okay"; + + mcp23s18: gpio@0 { + compatible = "microchip,mcp23s18"; + reg = <0>; + spi-max-frequency = <10000000>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23s18_reset_pins_default>; + microchip,spi-present-mask = /bits/ 8 <0x01>; + }; +}; + +&spi3 { + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins_default>; + status = "okay"; +}; From d7a395b7df55d1029e01879ea9e7da1d6e7fdb72 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Wed, 1 Jul 2026 11:09:44 +0200 Subject: [PATCH 317/864] ARM: dts: imx6ul-tqma6ul: add nvmem-layout TQMa6UL has board-information located in EEPROM at offset 0x20. Add necessary nodes and properties for nvmem cell. Signed-off-by: Max Merchel Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi index 4fa98e6a66d7..9b70e58868b0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -126,6 +126,16 @@ m24c64_50: eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; pagesize = <32>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; }; m24c02_52: eeprom@52 { From aec8004c5478371d49e9be238d4d87abebb4c1b6 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Wed, 1 Jul 2026 11:45:18 +0200 Subject: [PATCH 318/864] ARM: dts: imx6qdl-tqma6: add nvmem-layout TQMa6x has board-information located in EEPROM at offset 0x20. Add necessary nodes and properties for nvmem cell. Signed-off-by: Max Merchel Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi | 10 ++++++++++ arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi index 67f8f59aff5a..2fa116e1ca9a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -39,6 +39,16 @@ m24c64_50: eeprom@50 { reg = <0x50>; pagesize = <32>; vcc-supply = <&sw4_reg>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi index db552802554d..4361c7efb9d7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -32,6 +32,16 @@ m24c64_50: eeprom@50 { reg = <0x50>; pagesize = <32>; vcc-supply = <&sw4_reg>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; }; }; From 43c17d862977492ea7c4a21e4c8f22582c603508 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 3 Jul 2026 17:27:31 +0200 Subject: [PATCH 319/864] arm64: dts: freescale: imx9-var-dart-sonata: fix Ethernet PHY configuration Fix the Ethernet PHY description on the DART-MX9 Sonata boards. The GPIO previously described as the PHY reset line is actually a board-level enable signal required by the PHY. Model it accordingly and remove the incorrect reset GPIO description from the PHY nodes. On i.MX91 and i.MX93 the signal is described as a fixed regulator, whereas the existing regulator description on i.MX95 is reused. Keeping the PHY enable asserted during boot ensures that Ethernet initialization completes successfully. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-var-dart-sonata.dts | 14 +++++++++++--- .../boot/dts/freescale/imx93-var-dart-sonata.dts | 14 +++++++++++--- .../boot/dts/freescale/imx95-var-dart-sonata.dts | 3 --- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts index 3f0fd321d95f..f7e32f9375f5 100644 --- a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts @@ -97,6 +97,17 @@ reg_rgb_sel: regulator-rgb-enable { enable-active-high; }; + reg_phy1_supply: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "SUPPLY_PHY1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -139,9 +150,6 @@ mdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <15000>; - reset-deassert-us = <100000>; leds { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts index 5513d3b148a2..1ca3ec8330d0 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-dart-sonata.dts @@ -103,6 +103,17 @@ reg_vref_1v8: regulator-adc-vref { regulator-min-microvolt = <1800000>; }; + reg_phy1_supply: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "SUPPLY_PHY1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VDD_SD2_3V3"; @@ -180,9 +191,6 @@ mdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-assert-us = <15000>; - reset-deassert-us = <100000>; - reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; leds { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index 7a58ad38ffb4..ccf7e77016e4 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -346,9 +346,6 @@ &netc_emdio { ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <100000>; leds { #address-cells = <1>; From c8cb123cde467117f69ae57f83bf02d374f81609 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:31 +0200 Subject: [PATCH 320/864] arm64: dts: imx8: Correct indentation and whitespace Correct spaces or mix of tabs+spaces into proper tab-indented lines and remove other whitespace violations. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Acked-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 2 +- .../dts/freescale/imx8mm-emtop-baseboard.dts | 301 +++++++++--------- .../dts/freescale/imx8mp-evk-flexcan2.dtso | 4 +- .../freescale/imx8mp-nitrogen-smarc-som.dtsi | 82 ++--- .../dts/freescale/imx8mq-librem5-devkit.dts | 4 +- 5 files changed, 196 insertions(+), 197 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 6fc82b5eb58c..681f24810d52 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -423,7 +423,7 @@ usb-hub@8 { refclk-frequency = <25000000>; reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; }; - + /* On Module Audio Codec */ sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts index 87fe3ebedb8d..b031a9308dda 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts @@ -35,9 +35,9 @@ leds { pinctrl-0 = <&pinctrl_gpio_led>; led-1 { - label = "buzzer"; - gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; - default-state = "off"; + label = "buzzer"; + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; }; }; @@ -49,11 +49,11 @@ osc_can: clock-osc-can { }; reg_audio: regulator-audio { - compatible = "regulator-fixed"; - regulator-name = "wm8904_supply"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; + compatible = "regulator-fixed"; + regulator-name = "wm8904_supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; }; reg_wifi_vmmc: regulator-wifi-vmmc { @@ -68,13 +68,13 @@ reg_wifi_vmmc: regulator-wifi-vmmc { }; sound-wm8904 { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "wm8904-audio"; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,routing = + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", @@ -82,45 +82,44 @@ sound-wm8904 { "Headphone Jack", "MICBIAS", "IN1L", "Headphone Jack"; - simple-audio-card,widgets = - "Microphone","Headphone Jack", - "Headphone", "Headphone Jack", - "Line", "Line In Jack"; + simple-audio-card,widgets = "Microphone","Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; - dailink_master: simple-audio-card,codec { - sound-dai = <&wm8904>; - }; + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; - simple-audio-card,cpu { - sound-dai = <&sai3>; - }; + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; }; sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "imx-spdif"; - spdif-controller = <&spdif1>; - spdif-out; - spdif-in; + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif1>; + spdif-out; + spdif-in; }; }; /* CAN BUS */ &ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; - can: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_canbus>; - clocks = <&osc_can>; - interrupt-parent = <&gpio1>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; - spi-max-frequency = <10000000>; - }; + can: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_canbus>; + clocks = <&osc_can>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <10000000>; + }; }; &fec1 { @@ -177,29 +176,29 @@ rtc@32 { /* AUDIO */ &sai3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MM_CLK_SAI3>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + status = "okay"; }; &spdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spdif1>; - assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; - assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, - <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, - <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; - clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", - "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "okay"; }; /* USBOTG */ @@ -216,8 +215,8 @@ usb_hs_ep: endpoint { }; &usbotg2 { - dr_mode = "host"; - status = "okay"; + dr_mode = "host"; + status = "okay"; }; /* Wifi */ @@ -246,26 +245,26 @@ wifi: wifi@1 { /* SD-card */ &usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - bus-width = <4>; - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; }; &iomuxc { pinctrl_canbus: canbusgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14 + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14 >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 @@ -274,125 +273,125 @@ MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 pinctrl_usb_otg: usbotggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */ - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */ >; }; pinctrl_fec1: fec1grp { fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 >; }; pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; }; pinctrl_sai3: sai3grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 - MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 - MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 - MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 - MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 - >; + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + >; }; pinctrl_spdif1: spdif1grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 - >; + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc1_gpio: usdhc1-gpiogrp { fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */ - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */ - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */ >; }; pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - >; + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - >; + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - >; + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso index f7d2674c45f7..d87119842027 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk-flexcan2.dtso @@ -7,9 +7,9 @@ /plugin/; &flexcan2 { - status = "okay"; /* can2 pin conflict with pdm */ + status = "okay"; /* can2 pin conflict with pdm */ }; &micfil { - status = "disabled"; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi index 5da0f1b3ed8a..347e1bc13b3a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi @@ -32,29 +32,29 @@ led-0 { }; reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; &A53_0 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &A53_1 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &A53_2 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &A53_3 { - cpu-supply = <&buck2>; + cpu-supply = <&buck2>; }; &i2c1 { @@ -220,7 +220,7 @@ &wdog1 { &iomuxc { pinctrl_gpio_led: gpioledgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19 >; }; @@ -233,15 +233,15 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 pinctrl_i2c6: i2c6grp { fsl,pins = < - MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 - MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 + MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3 + MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3 >; }; pinctrl_mcp23018: mcp23018grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 - MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0 + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100 >; }; @@ -253,15 +253,15 @@ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0 pinctrl_uart2: uart2grp { fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150 @@ -277,8 +277,8 @@ MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154 @@ -293,8 +293,8 @@ MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 - MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152 @@ -309,34 +309,34 @@ MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12 pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 >; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 >; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index aadaeef928bd..0c3f1b20b3d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -215,7 +215,7 @@ vibrator { compatible = "gpio-vibrator"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_haptic>; - enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; vcc-supply = <®_3v3_p>; }; @@ -856,7 +856,7 @@ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = < - MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x06 >; }; From 972e858b01fbc724947f8ec825e0897e545b380f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:32 +0200 Subject: [PATCH 321/864] arm64: dts: s32g3: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Ghennadi Procopciuc Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g3.dtsi | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 129d6ad8e5c6..24fa3057e929 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -553,22 +553,22 @@ usbmisc: usbmisc@44064200 { reg = <0x44064200 0x200>; }; - usbotg: usb@44064000 { - compatible = "nxp,s32g3-usb", "nxp,s32g2-usb"; - reg = <0x44064000 0x200>; - interrupt-parent = <&gic>; - interrupts = , /* OTG Core */ - ; /* OTG Wakeup */ - clocks = <&clks 94>, <&clks 95>; - fsl,usbmisc = <&usbmisc 0>; - ahb-burst-config = <0x3>; - tx-burst-size-dword = <0x10>; - rx-burst-size-dword = <0x10>; - phy_type = "ulpi"; - dr_mode = "host"; - maximum-speed = "high-speed"; - status = "disabled"; - }; + usbotg: usb@44064000 { + compatible = "nxp,s32g3-usb", "nxp,s32g2-usb"; + reg = <0x44064000 0x200>; + interrupt-parent = <&gic>; + interrupts = , /* OTG Core */ + ; /* OTG Wakeup */ + clocks = <&clks 94>, <&clks 95>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x3>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + phy_type = "ulpi"; + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "disabled"; + }; spi0: spi@401d4000 { compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi"; From 018e75238a5fad4dc502c5028edf220651ba9da8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 20:03:34 +0200 Subject: [PATCH 322/864] ARM: dts: marvell: armada: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-370.dtsi | 8 ++++---- arch/arm/boot/dts/marvell/armada-xp-gp.dts | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/marvell/armada-370.dtsi b/arch/arm/boot/dts/marvell/armada-370.dtsi index 2013a5ccecd3..cf73287501da 100644 --- a/arch/arm/boot/dts/marvell/armada-370.dtsi +++ b/arch/arm/boot/dts/marvell/armada-370.dtsi @@ -63,8 +63,8 @@ pcie0: pcie@1,0 { interrupt-names = "intx"; interrupts-extended = <&mpic 58>; #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie0_intc 0>, @@ -91,8 +91,8 @@ pcie2: pcie@2,0 { interrupt-names = "intx"; interrupts-extended = <&mpic 62>; #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie2_intc 0>, diff --git a/arch/arm/boot/dts/marvell/armada-xp-gp.dts b/arch/arm/boot/dts/marvell/armada-xp-gp.dts index d1d348b91c0a..65cc0373fe04 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-gp.dts +++ b/arch/arm/boot/dts/marvell/armada-xp-gp.dts @@ -34,13 +34,13 @@ chosen { memory@0 { device_type = "memory"; /* - * 8 GB of plug-in RAM modules by default.The amount - * of memory available can be changed by the - * bootloader according the size of the module - * actually plugged. However, memory between - * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is - * the address range used for I/O (internal registers, - * MBus windows). + * 8 GB of plug-in RAM modules by default.The amount + * of memory available can be changed by the + * bootloader according the size of the module + * actually plugged. However, memory between + * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is + * the address range used for I/O (internal registers, + * MBus windows). */ reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, <0x00000001 0x00000000 0x00000001 0x00000000>; From 932f7dc9269adfd84e8f9af3cf1640b5fc8903bc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 20:03:35 +0200 Subject: [PATCH 323/864] ARM: dts: marvell: kirkwood: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/kirkwood-b3.dts | 4 ++-- .../arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi | 2 +- arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/marvell/kirkwood-b3.dts b/arch/arm/boot/dts/marvell/kirkwood-b3.dts index 681343c1357a..9d5cc1689864 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-b3.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-b3.dts @@ -94,10 +94,10 @@ i2c@11000 { serial@12000 { /* Internal on test pins, 3.3v TTL - * UART0_RX = Testpoint 65 + * UART0_RX = Testpoint 65 * UART0_TX = Testpoint 66 * See the Excito Wiki for more details. - */ + */ status = "okay"; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts index cb564c3bcdc4..a9adb777c7a0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-netgear_readynas_duo_v2.dts @@ -239,7 +239,7 @@ ethernet0-port@0 { }; &pciec { - status = "okay"; + status = "okay"; }; &pcie0 { diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi index d6b615cf6390..121d84609f20 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi @@ -83,7 +83,7 @@ &mdio { status = "okay"; ethphy0: ethernet-phy@X { - /* overwrite reg property in board file */ + /* overwrite reg property in board file */ }; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts index 20c6290d2037..82ccc6feaf3c 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts @@ -109,7 +109,7 @@ led-yellow { label = "obsa6:yellow:stat"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - }; + }; gpio_keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts index 2bc4b68bd723..ff08b01434bf 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts @@ -130,7 +130,7 @@ led-yellow { label = "obsa7:yellow:stat"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - }; + }; gpio_keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi index f136059607b7..6c15e9257de3 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi @@ -57,7 +57,7 @@ &mdio { ethphy1: ethernet-phy@1 { device_type = "ethernet-phy"; - /* overwrite reg property in board file */ + /* overwrite reg property in board file */ }; }; From c517ff045dae04c5aa8e74f017bcf6710c3d742d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 20:03:36 +0200 Subject: [PATCH 324/864] ARM: dts: marvell: orion5x: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts | 2 +- arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts index 12a4aac2633e..9757c3b57de6 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts @@ -109,7 +109,7 @@ flash@0 { compatible = "cfi-flash"; reg = <0 0x80000>; bank-width = <1>; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <1>; partition@0 { diff --git a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts index cb1bd24b7ae3..b2b3309ed1df 100644 --- a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts @@ -69,7 +69,7 @@ flash@0 { compatible = "cfi-flash"; reg = <0 0x40000>; bank-width = <1>; - #address-cells = <1>; + #address-cells = <1>; #size-cells = <1>; }; }; From 3d04a8aa8e7a274b2ec2218d4e863b3befcdc64e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jul 2026 08:51:47 +0200 Subject: [PATCH 325/864] arm64: dts: imx93-tqma9352-mba93xxla: Add LVDS overlay Add the overlay for the Tianma TM070JVHG33 LVDS display. Reviewed-by: Frank Li Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + ...3-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso | 38 +++++++++++++++++++ .../freescale/imx93-tqma9352-mba93xxla.dts | 21 ++++++++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 01d4ddfde098..6f1dbd7dbab6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -642,8 +642,10 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb +imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..4cb2d08b671e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtso @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds { + status = "okay"; +}; + +&display { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; + +&lcdif { + assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-rates = <477400000>; + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; +}; + +&media_blk_ctrl { + status = "okay"; +}; + +&tpm5 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index a78bbc46c59b..914efa9b1c22 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -73,6 +73,23 @@ clk_dp: clk-dp { clock-frequency = <26000000>; }; + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -534,6 +551,10 @@ &lpuart8 { status = "okay"; }; +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + &pcf85063 { /* RTC_EVENT# from SoM is connected on mainboard */ pinctrl-names = "default"; From 2b73b844564e4099fc43c4bbdea0c7abd65fae5c Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jul 2026 08:51:48 +0200 Subject: [PATCH 326/864] arm64: dts: imx93-tqma9352-mba93xxca: Add LVDS overlay Add the overlay for the Tianma TM070JVHG33 LVDS display. Reviewed-by: Frank Li Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ .../freescale/imx93-tqma9352-mba93xxca.dts | 21 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6f1dbd7dbab6..cf802b6f0611 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -642,9 +642,11 @@ imx93-tqma9352-mba91xxca-rgb-cdtech-dc44-dtbs := imx93-tqma9352-mba91xxca.dtb im dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb +imx93-tqma9352-mba93xxca-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxca.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts index 9108181e6592..39a8742de1da 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -67,6 +67,23 @@ backlight_lvds: backlight { status = "disabled"; }; + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + power-supply = <®_3v3>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + fan0: pwm-fan { compatible = "pwm-fan"; pinctrl-names = "default"; @@ -571,6 +588,10 @@ &lpuart8 { status = "okay"; }; +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + &pcf85063 { /* RTC_EVENT# from SoM is connected on mainboard */ pinctrl-names = "default"; From fcf306c5f504e5dc4e25a0e81beccf29a58af261 Mon Sep 17 00:00:00 2001 From: Martin Schmiedel Date: Tue, 7 Jul 2026 08:51:49 +0200 Subject: [PATCH 327/864] arm64: dts: imx93-tqma9352-mba93xxla-mini: Add LVDS overlay Add the overlay for the Tianma TM070JVHG33 LVDS display. Signed-off-by: Martin Schmiedel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../imx93-tqma9352-mba93xxla-mini.dts | 45 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index cf802b6f0611..842c98a91bb7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -645,10 +645,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtb imx93-tqma9352-mba93xxca-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxca.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo imx93-tqma9352-mba93xxla-mini-ezurio-wlan-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtbo +imx93-tqma9352-mba93xxla-mini-lvds-tm070jvhg33-dtbs += imx93-tqma9352-mba93xxla-mini.dtb imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtbo dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-ezurio-wlan.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla-mini-lvds-tm070jvhg33.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx93w-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts index 4afd6b650d9d..0d553a8da713 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla-mini.dts @@ -58,6 +58,37 @@ aliases { spi5 = &lpspi6; }; + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm5 0 5000000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + display: display { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display>; + power-supply = <®_3v3>; + enable-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + backlight = <&backlight_lvds>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; + iio-hwmon { compatible = "iio-hwmon"; io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; @@ -311,6 +342,10 @@ &lpuart8 { status = "okay"; }; +&ldb_lvds_ch0 { + remote-endpoint = <&panel_in_lvds0>; +}; + &pcf85063 { /* RTC_EVENT# from SoM is connected on mainboard */ pinctrl-names = "default"; @@ -375,6 +410,16 @@ &usdhc3 { }; &iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + + pinctrl_display: displaygrp { + fsl,pins = /* HYS | PD | FSEL_2 | DSE X4 */ + ; + }; + pinctrl_eqos: eqosgrp { fsl,pins = /* PD | FSEL_2 | DSE X4 */ , From 4b407eaff92dbac9f31a61040e40ef05a82eb3a5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 7 Jul 2026 11:41:25 +0200 Subject: [PATCH 328/864] arm64: dts: imx8mp: add missing #sound-dai-cells to xcvr This device is used for 'sound-dai' and needs #sound-dai-cells. dtbs_check raises a warning regarding sound_dai_property. Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5ce2825182fd..9cf9f6f08654 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1599,6 +1599,7 @@ xcvr: xcvr@30cc0000 { <0x30cc0e00 0x080>; reg-names = "ram", "regs", "rxfifo", "txfifo"; + #sound-dai-cells = <0>; interrupts = /* XCVR IRQ 0 */ , /* XCVR IRQ 1 */ From b463d4de9d365690d44fac9b8136190332639de1 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 7 Jul 2026 10:55:42 +0200 Subject: [PATCH 329/864] arm64: dts: imx91-tqma9131-mba91xxca: USB phy adjustments Add samsung,picophy-pre-emp-curr-control and samsung,picophy-dc-vol-level-adjust using the same values as other TQ-Systems GmbH mainboards. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts index 5c430e6fca65..60d11a4573e3 100644 --- a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts @@ -518,6 +518,8 @@ &usbotg1 { adp-disable; usb-role-switch; disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; port { @@ -532,6 +534,8 @@ &usbotg2 { #address-cells = <1>; #size-cells = <0>; disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; hub_2_0: hub@1 { From 96927ebe2610849ebdd78635b2e63a7af7a94eae Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Tue, 7 Jul 2026 10:55:43 +0200 Subject: [PATCH 330/864] arm64: dts: imx91-tqma9131: move ele-reserved memory into 512MB range TQMa91 has a 512MiB RAM variant for which the edgelock memory location exceeds the valid memory area. Signed-off-by: Alexander Feilke Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi index c99d7bc16848..a8c79731eace 100644 --- a/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi @@ -33,9 +33,9 @@ linux,cma { }; /* EdgeLock secure enclave */ - ele_reserved: ele-reserved@a4120000 { + ele_reserved: ele-reserved@94120000 { compatible = "shared-dma-pool"; - reg = <0 0xa4120000 0 0x100000>; + reg = <0 0x94120000 0 0x100000>; no-map; }; }; From e5f7c88d3ad8c617db4c8bc381001d272b02ca21 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 13 Jul 2026 11:22:46 +0900 Subject: [PATCH 331/864] arm64: dts: imx91-9x9-qsb: Add audio-related board muxes The board uses GPIO-controlled muxes to route shared signals between different functions. Add the audio-related mux states for: - selecting PDM or CAN1 - selecting SAI1 or M.2 - enabling the SAI1 audio path or not Signed-off-by: Chancel Liu Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-9x9-qsb.dts | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index ea8cf14e0bc6..4821ac312ab2 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -30,6 +30,55 @@ chosen { stdout-path = &lpuart1; }; + can_mux: mux-controller-0 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pcal6524 17 GPIO_ACTIVE_HIGH>; + }; + + sai1_mux: mux-controller-1 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pcal6524 18 GPIO_ACTIVE_HIGH>; + }; + + sai1_en_mux: mux-controller-2 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + #mux-state-cells = <1>; + mux-gpios = <&pcal6524 9 GPIO_ACTIVE_HIGH>; + }; + + pinctrl-gpiomux { + compatible = "pinctrl-multiplexer"; + + can_fun: can-grp { + mux-states = <&can_mux 1>; + }; + + m2_fun: m2-grp { + mux-states = <&sai1_mux 1>; + }; + + pdm_fun: pdm-grp { + mux-states = <&can_mux 0>; + }; + + sai1_disable: sai1-disable-grp { + mux-states = <&sai1_en_mux 1>; + }; + + sai1_enable: sai1-enable-grp { + mux-states = <&sai1_en_mux 0>; + }; + + sai1_fun: sai1-grp { + mux-states = <&sai1_mux 0>; + }; + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; From de6ed1fd9b97ed143b10de7064c6d30a9b545379 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 13 Jul 2026 11:22:47 +0900 Subject: [PATCH 332/864] arm64: dts: imx91-9x9-qsb: Add WM8524 sound card support Add WM8524 sound card support which connects to SAI1. Signed-off-by: Chancel Liu Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-9x9-qsb.dts | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 4821ac312ab2..089d999196d6 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -30,6 +30,18 @@ chosen { stdout-path = &lpuart1; }; + wm8524: audio-codec { + compatible = "wlf,wm8524"; + #sound-dai-cells = <0>; + wlf,mute-gpios = <&pcal6524 2 GPIO_ACTIVE_LOW>; + + port { + codec_ep: endpoint { + remote-endpoint = <&sai1_ep1>; + }; + }; + }; + can_mux: mux-controller-0 { compatible = "gpio-mux"; #mux-control-cells = <0>; @@ -110,6 +122,16 @@ linux,cma { linux,cma-default; }; }; + + sound-wm8524 { + compatible = "audio-graph-card2"; + label = "wm8524-audio"; + links = <&sai1_port1>; + widgets = "Line", "Line Out Jack"; + routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; + }; }; &adc1 { @@ -186,6 +208,15 @@ MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x31e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX91_PAD_UART1_RXD__LPUART1_RX 0x31e @@ -433,6 +464,42 @@ &lpuart1 { status = "okay"; }; +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>, <&sai1_fun>, <&sai1_enable>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + fsl,sai-mclk-direction-output; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sai1_port1: port@1 { + reg = <1>; + playback-only; + + sai1_ep1: endpoint { + dai-format = "i2s"; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + bitclock-master; + frame-master; + mclk-fs = <256>; + system-clock-direction-out; + remote-endpoint = <&codec_ep>; + }; + }; + }; +}; + &usbotg1 { adp-disable; disable-over-current; From 25f7d6026e2549a73e529bef85c80579528ebb33 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 13 Jul 2026 11:22:48 +0900 Subject: [PATCH 333/864] arm64: dts: imx91-9x9-qsb: Add PDM microphone sound card support Add PDM microphone sound card support, configure the pinmux. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Chancel Liu Signed-off-by: Frank Li --- .../boot/dts/freescale/imx91-9x9-qsb.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts index 089d999196d6..044b37fcc0ba 100644 --- a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts @@ -42,6 +42,18 @@ codec_ep: endpoint { }; }; + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <4>; + + port { + dmic_ep: endpoint { + remote-endpoint = <&micfil_ep>; + }; + }; + }; + can_mux: mux-controller-0 { compatible = "gpio-mux"; #mux-control-cells = <0>; @@ -123,6 +135,12 @@ linux,cma { }; }; + sound-micfil { + compatible = "audio-graph-card2"; + label = "micfil-audio"; + links = <&micfil_port>; + }; + sound-wm8524 { compatible = "audio-graph-card2"; label = "wm8524-audio"; @@ -202,6 +220,14 @@ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e @@ -464,6 +490,24 @@ &lpuart1 { status = "okay"; }; +&micfil { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>, <&pdm_fun>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; + + micfil_port: port { + capture-only; + + micfil_ep: endpoint { + remote-endpoint = <&dmic_ep>; + }; + }; +}; + &sai1 { #sound-dai-cells = <0>; pinctrl-names = "default"; From ed93dafad1121ad5c8e48185789e4eee551a0434 Mon Sep 17 00:00:00 2001 From: Esben Haabendal Date: Sat, 11 Jul 2026 12:18:42 +0200 Subject: [PATCH 334/864] arm64: dts: imx8mq: Add DCSS node Add node for iMX8MQ Display Controller Subsystem. Reviewed-by: Lucas Stach Signed-off-by: Esben Haabendal Acked-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index e60872aeeb49..d75710cdb5b4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1598,6 +1598,29 @@ aips4: bus@32c00000 { /* AIPS4 */ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + dcss: display-controller@32e00000 { + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctxld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; From 35cf35e239477cb28e5f6ccd987933d70c21061f Mon Sep 17 00:00:00 2001 From: John Madieu Date: Mon, 25 May 2026 11:05:58 +0000 Subject: [PATCH 335/864] arm64: dts: renesas: rzv2h: Add audio clock inputs Model the optional external audio clock inputs as CPG input clocks for RZ/V2H family SoCs (RZ/V2H, RZ/V2N, RZ/G3E), allowing the Audio Clock Generator (ADG) to derive internal audio clocks from these external sources. The clock frequencies are board-specific and must be overridden in the board DTS files. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260525110603.4018170-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 20 ++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 20 ++++++++++++++++++-- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 20 ++++++++++++++++++-- 3 files changed, 54 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index b48da8534a3d..be11cdde3cfe 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -21,6 +21,20 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -271,8 +285,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g047-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index d6c8c39df2a4..3a308dbf733c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -39,6 +39,20 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -294,8 +308,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g056-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 1e94366bb7ee..8af0f0f2f2f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -21,6 +21,20 @@ audio_extal_clk: audio-clk { clock-frequency = <0>; }; + audio_clkb: audio-b-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + audio_clkc: audio-c-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + /* * The default cluster table is based on the assumption that the PLLCA55 clock * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to @@ -276,8 +290,10 @@ pinctrl: pinctrl@10410000 { cpg: clock-controller@10420000 { compatible = "renesas,r9a09g057-cpg"; reg = <0 0x10420000 0 0x10000>; - clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; - clock-names = "audio_extal", "rtxin", "qextal"; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>, + <&audio_clkb>, <&audio_clkc>; + clock-names = "audio_extal", "rtxin", "qextal", + "audio_clkb", "audio_clkc"; #clock-cells = <2>; #reset-cells = <1>; #power-domain-cells = <0>; From 4e66920563d718732b743ae418860cde13265242 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Mon, 25 May 2026 11:06:01 +0000 Subject: [PATCH 336/864] arm64: dts: renesas: rzg3e-smarc-som: Add I2C1 support Add and enable I2C1 controller support with pin configuration. The I2C1 bus is routed to the carrier board and used for peripherals such as the audio codec. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260525110603.4018170-7-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 2e1d9686df88..15c22dbf0ad3 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -32,6 +32,7 @@ / { aliases { ethernet0 = ð0; ethernet1 = ð1; + i2c1 = &i2c1; i2c2 = &i2c2; mmc0 = &sdhi0; mmc2 = &sdhi2; @@ -112,6 +113,12 @@ &gpu { mali-supply = <®_vdd0p8v_others>; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -234,6 +241,11 @@ ctrl { }; }; + i2c1_pins: i2c1 { + pinmux = , /* SCL1 */ + ; /* SDA1 */ + }; + i2c2_pins: i2c { pinmux = , /* SCL2 */ ; /* SDA2 */ From c49ad13019771d5161290dc0eacb3ff6186c0953 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 28 May 2026 14:47:50 +0100 Subject: [PATCH 337/864] arm64: dts: renesas: rzt2h-n2h-evk: Remove unused MII/GMII pins Remove the unused TXER, RXER, CRS, and COL pinmux configurations from the gmac1 (ETH3) and gmac2 (ETH2) pin groups. The Ethernet interfaces on both the RZ/T2H and RZ/N2H EVK boards operate in RGMII mode, which does not utilize these extra MII/GMII sideband signal pins. Update the board switch configuration comments to accurately reflect the pin ranges that are actually in use. Fixes: b272b94fd2239 ("arm64: dts: renesas: rzt2h-n2h-evk: Enable Ethernet support") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528134752.79813-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts | 14 ++------------ .../boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts | 15 ++------------- 2 files changed, 4 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index e9ed2de128f6..987e44d0bf95 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -256,8 +256,7 @@ can0_pins: can0-pins { /* * GMAC1 Pin Configuration: * - * SW2[8] ON - use pins P33_2-P33_7, P34_0-P34_5, P34_7 and - * P35_0-P35_2 for Ethernet port 3 + * SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet port 3 */ gmac1_pins: gmac1-pins { pinmux = , /* ETH3_TXCLK */ @@ -272,10 +271,6 @@ gmac1_pins: gmac1-pins { , /* ETH3_RXD2 */ , /* ETH3_RXD3 */ , /* ETH3_RXDV */ - , /* ETH3_TXER */ - , /* ETH3_RXER */ - , /* ETH3_CRS */ - , /* ETH3_COL */ , /* GMAC1_MDC */ , /* GMAC1_MDIO */ , /* ETH3_REFCLK */ @@ -286,8 +281,7 @@ gmac1_pins: gmac1-pins { * GMAC2 Pin Configuration: * * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 - * SW2[7] ON - use pins P29_1-P29_7, P30_0-P30_4, and P31_2-P31_5 - * for Ethernet port 2 + * SW2[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 */ gmac2_pins: gmac2-pins { pinmux = , /* ETH2_TXCLK */ @@ -302,10 +296,6 @@ gmac2_pins: gmac2-pins { , /* ETH2_RXD2 */ , /* ETH2_RXD3 */ , /* ETH2_RXDV */ - , /* ETH2_TXER */ - , /* ETH2_RXER */ - , /* ETH2_CRS */ - , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ , /* ETH2_REFCLK */ diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index ef6cc7497c2c..a66502d8d82b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -339,9 +339,7 @@ can1_pins: can1-pins { /* * GMAC1 Pin Configuration: * - * DSW5[8] ON - use pins P00_0-P00_2, P33_2-P33_7, P34_0-P34_6 - * for Ethernet port 3 - * DSW12[1] OFF; DSW12[2] ON - use pin P00_3 for Ethernet port 3 + * DSW5[8] ON - use pins P33_2-P33_7 and P34_0-P34_6 for Ethernet port 3 */ gmac1_pins: gmac1-pins { pinmux = , /* ETH3_TXCLK */ @@ -356,10 +354,6 @@ gmac1_pins: gmac1-pins { , /* ETH3_RXD2 */ , /* ETH3_RXD3 */ , /* ETH3_RXDV */ - , /* ETH3_TXER */ - , /* ETH3_RXER */ - , /* ETH3_CRS */ - , /* ETH3_COL */ , /* GMAC1_MDC */ , /* GMAC1_MDIO */ , /* ETH3_REFCLK */ @@ -370,8 +364,7 @@ gmac1_pins: gmac1-pins { * GMAC2 Pin Configuration: * * DSW5[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 - * DSW5[7] ON - use pins P29_1-P29_7, P30_0-P30_4, P30_7, - * P31_2, P31_4 and P31_5 are used for Ethernet port 2 + * DSW5[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14 */ gmac2_pins: gmac2-pins { @@ -387,10 +380,6 @@ gmac2_pins: gmac2-pins { , /* ETH2_RXD2 */ , /* ETH2_RXD3 */ , /* ETH2_RXDV */ - , /* ETH2_TXER */ - , /* ETH2_RXER */ - , /* ETH2_CRS */ - , /* ETH2_COL */ , /* GMAC2_MDC */ , /* GMAC2_MDIO */ , /* ETH2_REFCLK */ From 1f90a38214d52f773edd02bf02805aa905164ee0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 28 May 2026 14:47:51 +0100 Subject: [PATCH 338/864] arm64: dts: renesas: rzt2h-n2h-evk: Configure ETH pins Update the gmac1 (ETH3) and gmac2 (ETH2) pin configurations on the RZ/T2H and RZ/N2H EVK boards to comply with the electrical specifications defined in Table 58.11 of the hardware user manual. While restructuring the nodes into pin groups, fix a copy-paste comment typo in the RZ/N2H device tree where the ETH3_TXD1 pin mux configuration was mistakenly labeled as ETH3_TXD0. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528134752.79813-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 130 +++++++++++++----- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 129 ++++++++++++----- 2 files changed, 191 insertions(+), 68 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index 987e44d0bf95..572be8aa6d7e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -258,23 +258,54 @@ can0_pins: can0-pins { * * SW2[8] ON - use pins P33_2-P33_7 and P34_0-P34_5 for Ethernet port 3 */ - gmac1_pins: gmac1-pins { - pinmux = , /* ETH3_TXCLK */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD1 */ - , /* ETH3_TXD2 */ - , /* ETH3_TXD3 */ - , /* ETH3_TXEN */ - , /* ETH3_RXCLK */ - , /* ETH3_RXD0 */ - , /* ETH3_RXD1 */ - , /* ETH3_RXD2 */ - , /* ETH3_RXD3 */ - , /* ETH3_RXDV */ - , /* GMAC1_MDC */ - , /* GMAC1_MDIO */ - , /* ETH3_REFCLK */ - ; /* IRQ3 */ + gmac1_pins: gmac1-group { + irq-pins { + pinmux = ; /* IRQ3 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + md-pins { + pinmux = , /* GMAC1_MDC */ + ; /* GMAC1_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH3_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + ; /* ETH3_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH3_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + ; /* ETH3_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* @@ -283,23 +314,54 @@ gmac1_pins: gmac1-pins { * SW2[6] OFF - connect MDC/MDIO of Ethernet port 2 to GMAC2 * SW2[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 */ - gmac2_pins: gmac2-pins { - pinmux = , /* ETH2_TXCLK */ - , /* ETH2_TXD0 */ - , /* ETH2_TXD1 */ - , /* ETH2_TXD2 */ - , /* ETH2_TXD3 */ - , /* ETH2_TXEN */ - , /* ETH2_RXCLK */ - , /* ETH2_RXD0 */ - , /* ETH2_RXD1 */ - , /* ETH2_RXD2 */ - , /* ETH2_RXD3 */ - , /* ETH2_RXDV */ - , /* GMAC2_MDC */ - , /* GMAC2_MDIO */ - , /* ETH2_REFCLK */ - ; /* IRQ13 */ + gmac2_pins: gmac2-group { + irq-pins { + pinmux = ; /* IRQ13 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + md-pins { + pinmux = , /* GMAC2_MDC */ + ; /* GMAC2_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH2_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + ; /* ETH2_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH2_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + ; /* ETH2_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index a66502d8d82b..4e57d4fe195c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -341,23 +341,54 @@ can1_pins: can1-pins { * * DSW5[8] ON - use pins P33_2-P33_7 and P34_0-P34_6 for Ethernet port 3 */ - gmac1_pins: gmac1-pins { - pinmux = , /* ETH3_TXCLK */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD0 */ - , /* ETH3_TXD2 */ - , /* ETH3_TXD3 */ - , /* ETH3_TXEN */ - , /* ETH3_RXCLK */ - , /* ETH3_RXD0 */ - , /* ETH3_RXD1 */ - , /* ETH3_RXD2 */ - , /* ETH3_RXD3 */ - , /* ETH3_RXDV */ - , /* GMAC1_MDC */ - , /* GMAC1_MDIO */ - , /* ETH3_REFCLK */ - ; /* IRQ15 */ + gmac1_pins: gmac1-group { + irq-pins { + pinmux = ; /* IRQ15 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + md-pins { + pinmux = , /* GMAC1_MDC */ + ; /* GMAC1_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH3_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH3_RXCLK */ + , /* ETH3_RXD0 */ + , /* ETH3_RXD1 */ + , /* ETH3_RXD2 */ + , /* ETH3_RXD3 */ + ; /* ETH3_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH3_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH3_TXD0 */ + , /* ETH3_TXD1 */ + , /* ETH3_TXD2 */ + , /* ETH3_TXD3 */ + ; /* ETH3_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* @@ -367,24 +398,54 @@ gmac1_pins: gmac1-pins { * DSW5[7] ON - use pins P29_1-P29_7 and P30_0-P30_4 for Ethernet port 2 * DSW13[7] OFF; DSW13[8] ON - use pin P13_7 for IRQ14 */ - gmac2_pins: gmac2-pins { - pinmux = , /* ETH2_TXCLK */ - , /* ETH2_TXD0 */ - , /* ETH2_TXD1 */ - , /* ETH2_TXD2 */ - , /* ETH2_TXD3 */ - , /* ETH2_TXEN */ - , /* ETH2_RXCLK */ - , /* ETH2_RXD0 */ - , /* ETH2_RXD1 */ - , /* ETH2_RXD2 */ - , /* ETH2_RXD3 */ - , /* ETH2_RXDV */ - , /* GMAC2_MDC */ - , /* GMAC2_MDIO */ - , /* ETH2_REFCLK */ - ; /* IRQ14 */ + gmac2_pins: gmac2-group { + irq-pins { + pinmux = ; /* IRQ14 */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + md-pins { + pinmux = , /* GMAC2_MDC */ + ; /* GMAC2_MDIO */ + drive-strength-microamp = <5000>; + slew-rate = <0>; + input-schmitt-disable; + }; + + refclk-pins { + pinmux = ; /* ETH2_REFCLK */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + + rx-pins { + pinmux = , /* ETH2_RXCLK */ + , /* ETH2_RXD0 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD2 */ + , /* ETH2_RXD3 */ + ; /* ETH2_RXDV */ + input-schmitt-disable; + }; + + txclk-pins { + pinmux = ; /* ETH2_TXCLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + input-schmitt-disable; + }; + + txd-en-pins { + pinmux = , /* ETH2_TXD0 */ + , /* ETH2_TXD1 */ + , /* ETH2_TXD2 */ + , /* ETH2_TXD3 */ + ; /* ETH2_TXEN */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; }; /* From 1417a63d16ba5681fe137e546aaa9c5b2828c5d5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 28 May 2026 14:47:52 +0100 Subject: [PATCH 339/864] arm64: dts: renesas: rzt2h-n2h-evk: Configure SCI0 pins Configure the drive strength, slew rate, and Schmitt trigger settings for the sci0 pin group shared by the RZ/T2H and RZ/N2H EVK boards. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260528134752.79813-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index e86e6d3aa8a3..ceccddb92d40 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -257,6 +257,9 @@ &pinctrl { sci0_pins: sci0-pins { pinmux = , ; + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; }; #if SD0_EMMC From 4fb32d9e4836c33ea9861f7c3e57beab6f546eb1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 May 2026 13:54:40 +0100 Subject: [PATCH 340/864] arm64: dts: renesas: r9a08g046l48-smarc: Enable rsci{1,2,3} nodes Enable rsci{1,2,3} device nodes for the RZ/G3L SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260529125442.327290-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 32d3b08a3cf3..3ce24b66cb8d 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -13,6 +13,7 @@ #define SW_DPI_EN 0 #define SW_GPIO4 1 #define SW_I3C_EN 0 +#define SW_SER0_PMOD 1 #define PMOD_GPIO4 0 #define PMOD_GPIO6 0 @@ -37,6 +38,9 @@ / { aliases { i2c2 = &i2c2; i2c3 = &i2c3; + serial0 = &rsci2; + serial1 = &rsci3; + serial2 = &rsci1; serial3 = &scif0; }; @@ -134,6 +138,30 @@ i2c3_pins: i2c3 { ; /* RIIC3_SDA */ }; + rsci1_pins: rsci1 { + pinmux = , /* RSCI1_RXD_MISO_SCL */ + , /* RSCI1_TXD_MOSI_SDA */ + , /* RSCI1_CTS */ + ; /* RSCI1_SS_CTS#_RTS# */ + bias-pull-up; + }; + + rsci2_pins: rsci2 { + pinmux = , /* RSCI2_RXD_MISO_SCL */ + , /* RSCI2_TXD_MOSI_SDA */ + , /* RSCI2_CTS */ + ; /* RSCI2_SS_CTS#_RTS# */ + bias-pull-up; + power-source = <1800>; + }; + + rsci3_pins: rsci3 { + pinmux = , /* RSCI3_RXD_MISO_SCL */ + ; /* RSCI3_TXD_MOSI_SDA */ + bias-pull-up; + power-source = <1800>; + }; + scif0_pins: scif0 { pins = "SCIF0_TXD", "SCIF0_RXD"; power-source = <1800>; @@ -147,6 +175,37 @@ ssi0_pins: ssi0 { }; }; +#if SW_SER0_PMOD +&rsci1 { + pinctrl-0 = <&rsci1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if !SW_DPI_EN +&rsci2 { + pinctrl-0 = <&rsci2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_DPI_EN) +&rsci3 { + pinctrl-0 = <&rsci3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; From ba82a7f75e8a33963354c1be109793f2bccccb79 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 May 2026 14:07:00 +0100 Subject: [PATCH 341/864] arm64: dts: renesas: r9a08g046: Add RSPI{0..2} nodes Add device tree nodes for the three RSPI channels on the RZ/G3L (R9A08G046) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260529130704.327505-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi index 03bdee870528..c63a857f0e5b 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi @@ -358,6 +358,75 @@ i2c3: i2c@10090c00 { status = "disabled"; }; + rspi0: spi@100b0000 { + compatible = "renesas,r9a08g046-rspi"; + reg = <0 0x100b0000 0 0x1000>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A08G046_RSPI0_PCLK>, + <&cpg CPG_MOD R9A08G046_RSPI0_TCLK>; + clock-names = "pclk", "tclk"; + resets = <&cpg R9A08G046_RSPI0_PRESETN>, + <&cpg R9A08G046_RSPI0_TRESETN>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac 0x26f2>, <&dmac 0x26f1>; + dma-names = "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@100e9000 { + compatible = "renesas,r9a08g046-rspi"; + reg = <0 0x100e9000 0 0x1000>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A08G046_RSPI1_PCLK>, + <&cpg CPG_MOD R9A08G046_RSPI1_TCLK>; + clock-names = "pclk", "tclk"; + resets = <&cpg R9A08G046_RSPI1_PRESETN>, + <&cpg R9A08G046_RSPI1_TRESETN>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac 0x26f6>, <&dmac 0x26f5>; + dma-names = "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@100ea000 { + compatible = "renesas,r9a08g046-rspi"; + reg = <0 0x100ea000 0 0x1000>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A08G046_RSPI2_PCLK>, + <&cpg CPG_MOD R9A08G046_RSPI2_TCLK>; + clock-names = "pclk", "tclk"; + resets = <&cpg R9A08G046_RSPI2_PRESETN>, + <&cpg R9A08G046_RSPI2_TRESETN>; + reset-names = "presetn", "tresetn"; + dmas = <&dmac 0x26fa>, <&dmac 0x26f9>; + dma-names = "rx", "tx"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + rsci0: serial@100b8000 { compatible = "renesas,r9a08g046-rsci"; reg = <0 0x100b8000 0 0x1000>; From db60b8a6154af4221954065c695a0b35cee34b72 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 May 2026 14:07:01 +0100 Subject: [PATCH 342/864] arm64: dts: renesas: r9a08g046l48-smarc: Enable RSPI2 Enable RSPI2 on the RZ/G3L SMARC EVK board by adding pin control configuration and activating the rspi2 node. The RSPI2 pins are shared with the DPI display interface and the two cannot be used simultaneously. This is controlled by switch SW_DPI_EN. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260529130704.327505-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a08g046l48-smarc.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts index 3ce24b66cb8d..5289efd1a430 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts @@ -162,6 +162,14 @@ rsci3_pins: rsci3 { power-source = <1800>; }; + rspi2_pins: rspi2 { + pinmux = , /* RSPI2_MISO */ + , /* RSPI2_MOSI */ + , /* RSPI2_SCK */ + ; /* RSPI2_SSLA */ + power-source = <1800>; + }; + scif0_pins: scif0 { pins = "SCIF0_TXD", "SCIF0_RXD"; power-source = <1800>; @@ -206,6 +214,17 @@ &rsci3 { }; #endif +#if !SW_DPI_EN +&rspi2 { + pinctrl-0 = <&rspi2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; From 9f115f9c3133294dfe149fe2e8376a854b0124a5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 1 Jun 2026 13:38:51 +0200 Subject: [PATCH 343/864] arm64: dts: renesas: r8a78000: Enable application CPU cores via PSCI Add PSCI "enable-method" DT properties to all application CPU cores. This allows the OS to bring application CPU cores up and down. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260601113919.8327-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 7780fb4e8351..fb71974ef390 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -143,6 +143,7 @@ a720_0: cpu@0 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x0>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_0>; }; @@ -150,6 +151,7 @@ a720_1: cpu@100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_1>; }; @@ -157,6 +159,7 @@ a720_2: cpu@200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_2>; }; @@ -164,6 +167,7 @@ a720_3: cpu@300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_3>; }; @@ -171,6 +175,7 @@ a720_4: cpu@10000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_4>; }; @@ -178,6 +183,7 @@ a720_5: cpu@10100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_5>; }; @@ -185,6 +191,7 @@ a720_6: cpu@10200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_6>; }; @@ -192,6 +199,7 @@ a720_7: cpu@10300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x10300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_7>; }; @@ -199,6 +207,7 @@ a720_8: cpu@20000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_8>; }; @@ -206,6 +215,7 @@ a720_9: cpu@20100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_9>; }; @@ -213,6 +223,7 @@ a720_10: cpu@20200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_10>; }; @@ -220,6 +231,7 @@ a720_11: cpu@20300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x20300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_11>; }; @@ -227,6 +239,7 @@ a720_12: cpu@30000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_12>; }; @@ -234,6 +247,7 @@ a720_13: cpu@30100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_13>; }; @@ -241,6 +255,7 @@ a720_14: cpu@30200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_14>; }; @@ -248,6 +263,7 @@ a720_15: cpu@30300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x30300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_15>; }; @@ -255,6 +271,7 @@ a720_16: cpu@40000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_16>; }; @@ -262,6 +279,7 @@ a720_17: cpu@40100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_17>; }; @@ -269,6 +287,7 @@ a720_18: cpu@40200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_18>; }; @@ -276,6 +295,7 @@ a720_19: cpu@40300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x40300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_19>; }; @@ -283,6 +303,7 @@ a720_20: cpu@50000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_20>; }; @@ -290,6 +311,7 @@ a720_21: cpu@50100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_21>; }; @@ -297,6 +319,7 @@ a720_22: cpu@50200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_22>; }; @@ -304,6 +327,7 @@ a720_23: cpu@50300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x50300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_23>; }; @@ -311,6 +335,7 @@ a720_24: cpu@60000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_24>; }; @@ -318,6 +343,7 @@ a720_25: cpu@60100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_25>; }; @@ -325,6 +351,7 @@ a720_26: cpu@60200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_26>; }; @@ -332,6 +359,7 @@ a720_27: cpu@60300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x60300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_27>; }; @@ -339,6 +367,7 @@ a720_28: cpu@70000 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70000>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_28>; }; @@ -346,6 +375,7 @@ a720_29: cpu@70100 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70100>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_29>; }; @@ -353,6 +383,7 @@ a720_30: cpu@70200 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70200>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_30>; }; @@ -360,6 +391,7 @@ a720_31: cpu@70300 { compatible = "arm,cortex-a720ae"; reg = <0x0 0x70300>; device_type = "cpu"; + enable-method = "psci"; next-level-cache = <&L2_CA720_31>; }; From f0de09f7de324b2deed7ebdb26d775a0abe9e10d Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 2 Jun 2026 20:21:09 +0200 Subject: [PATCH 344/864] arm64: dts: renesas: r8a779g0: Add MFIS node Describe the MFIS core which is used for various tasks including inter-processor communication. Interrupt numbers look irregular but they all work as expected on a Renesas R-Car V4H SparrowHawk board. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260602182157.304964-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 82a7278836e5..8a291447b904 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -589,6 +589,23 @@ tmu4: timer@ffc00000 { status = "disabled"; }; + mfis: system-controller@e6260000 { + compatible = "renesas,r8a779g0-mfis"; + reg = <0 0xe6260000 0 0x10000>; + reg-names = "common"; + interrupts = , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0e", "ch1e", "ch2e", "ch3e", "ch4e", "ch5e", + "ch6e", "ch7e", "ch8e", "ch9e", "ch10e", "ch11e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + status = "disabled"; + }; + tsn0: ethernet@e6460000 { compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn"; reg = <0 0xe6460000 0 0x7000>, From 31fd71751e699117d71ed998c58fc7fe9ec471fa Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 3 Jun 2026 15:33:35 +0100 Subject: [PATCH 345/864] arm64: dts: renesas: r9a09g047e57-smarc: Drop SW_SER0_PMOD condition for rsci4 Rsci4 is routed to either the PMOD connector or the M.2 connector, depending on the SW_SER0_PMOD switch state. In both cases, rsci4 is available for use, so there is no need to guard it with SW_SER0_PMOD. Drop the SW_SER0_PMOD condition and retain only the SW_LCD_EN check, as rsci4 is unavailable only when the LCD is enabled. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260603143340.162457-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 6372f582a7c4..07db9e434521 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -237,7 +237,7 @@ &rsci2 { }; #endif -#if (!SW_LCD_EN) && (SW_SER0_PMOD) +#if !SW_LCD_EN &rsci4 { pinctrl-0 = <&rsci4_pins>; pinctrl-names = "default"; From e3203a81238d59833adfe551ccad929245a1ea92 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 3 Jun 2026 15:33:36 +0100 Subject: [PATCH 346/864] arm64: dts: renesas: r9a09g047: Add max-frequency to SDHI nodes Add max-frequency properties of 200MHz to the sdhi0, sdhi1, and sdhi2 MMC controllers in the R9A09G047 SoC DTSI to define the maximum supported bus frequency. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260603143340.162457-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index be11cdde3cfe..cf3f77e5551a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1281,6 +1281,7 @@ sdhi0: mmc@15c00000 { clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa7>; power-domains = <&cpg>; status = "disabled"; @@ -1301,6 +1302,7 @@ sdhi1: mmc@15c10000 { clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa8>; power-domains = <&cpg>; status = "disabled"; @@ -1321,6 +1323,7 @@ sdhi2: mmc@15c20000 { clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; clock-names = "core", "clkh", "cd", "aclk"; + max-frequency = <200000000>; resets = <&cpg 0xa9>; power-domains = <&cpg>; status = "disabled"; From 2cc5ac6e859bcf3ec5d4c8725909918f8bb907a2 Mon Sep 17 00:00:00 2001 From: bui duc phuc Date: Tue, 9 Jun 2026 18:38:27 +0700 Subject: [PATCH 347/864] ARM: dts: renesas: r8a7740: Add FSI clocks Add the SPU bus clock, icka/b functional clocks, and xcka/b external clock inputs to the FSI device node. This prepares for subsequent driver changes that explicitly manage the SPU clock required for FSI register access on R-Mobile A1. Signed-off-by: bui duc phuc Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260609113836.45079-3-phucduc.bui@gmail.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index c7056b96ec0b..d4776a7877ff 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -501,7 +501,11 @@ sh_fsi2: sound@fe1f0000 { compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = ; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsib_clk>, <&fsiack_clk>, + <&fsibck_clk>; + clock-names = "fck", "spu", "icka", "ickb", "xcka", + "xckb"; power-domains = <&pd_a4mp>; status = "disabled"; }; @@ -722,6 +726,12 @@ vou_clk: vou@e6150088 { <0>; #clock-cells = <0>; }; + fsib_clk: fsib@e6150090 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150090 4>; + clocks = <&pllc1_div2_clk>, <&fsibck_clk>, <0>, <0>; + #clock-cells = <0>; + }; stpro_clk: stpro@e615009c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; From e2b5bacc8e2056ca81b08a59529ae182cd80e3ff Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 02:57:29 +0200 Subject: [PATCH 348/864] arm64: dts: renesas: r8a77965-salvator-x: Enable GPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable GPU on Salvator-X with R-Car M3-N. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20260611005952.146825-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts index f84c64ed4df7..af8cfdccd210 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-x.dts @@ -30,3 +30,7 @@ &du { clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&gpu { + status = "okay"; +}; From 0d501c2fbcd931815380dc3db07f1dd77d151422 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 02:57:30 +0200 Subject: [PATCH 349/864] arm64: dts: renesas: r8a77965-salvator-xs: Enable GPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable GPU on Salvator-X 2nd version with R-Car M3-N. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20260611005952.146825-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts index a1d3c8d531cf..f0d9c0124f69 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts @@ -30,3 +30,7 @@ &du { clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&gpu { + status = "okay"; +}; From e7f8013a1306ac9af01e43f1e05f13d235b566a7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 Jun 2026 02:57:31 +0200 Subject: [PATCH 350/864] arm64: dts: renesas: r8a77965-ulcb: Enable GPU support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable GPU on M3NULCB with R-Car M3-N. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://patch.msgid.link/20260611005952.146825-3-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts index 71704b67a20e..127eb2ea3c92 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a77965-ulcb.dts @@ -31,3 +31,7 @@ &du { clock-names = "du.0", "du.1", "du.3", "dclkin.0", "dclkin.1", "dclkin.3"; }; + +&gpu { + status = "okay"; +}; From 7cb769eb22d1f6b0536b2979b92c50cb5873e07a Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:48 +0000 Subject: [PATCH 351/864] arm64: dts: renesas: r9a09g047: Add RZ/G3E Sound support Add the snd_rzg3e node for the RZ/G3E SoC with all sub-components: - SSI (Serial Sound Interface) units 0-9, - SSIU (Serial Sound Interface Unit) units 0-27, - SRC (Sample Rate Converter) units 0-9, - CTU (Channel Transfer Unit) units 0-7, - DVC (Digital Volume Control) units 0-1, - MIX (Mixer) units 0-1. Sub-node names follow the new RZ/G3E sound binding: unprefixed 'ssi', 'ssiu', 'src', 'dvc', 'mix', 'ctu' wrapper nodes instead of the legacy 'rcar_sound,xxx' R-Car prefix. Wire up all 5 DMA controllers (dmac0-dmac4) for each audio sub-node with repeated channel names, so that the DMA core can pick the first available controller. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260619083951.3777556-2-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 500 +++++++++++++++++++++ 1 file changed, 500 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index cf3f77e5551a..310f988a63c4 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -912,6 +912,506 @@ rsci9: serial@12803000 { status = "disabled"; }; + snd_rzg3e: sound@13c00000 { + compatible = "renesas,r9a09g047-sound"; + reg = <0 0x13c00000 0 0x20000>, /* SCU */ + <0 0x13c20000 0 0x10000>, /* ADG */ + <0 0x13c30000 0 0x1000>, /* SSIU */ + <0 0x13c31000 0 0x1f000>, /* SSI */ + <0 0x13c50000 0 0x10000>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&cpg CPG_MOD 0xf5>, + <&cpg CPG_MOD 0x181>, <&cpg CPG_MOD 0x182>, + <&cpg CPG_MOD 0x183>, <&cpg CPG_MOD 0x184>, + <&cpg CPG_MOD 0x185>, <&cpg CPG_MOD 0x186>, + <&cpg CPG_MOD 0x187>, <&cpg CPG_MOD 0x188>, + <&cpg CPG_MOD 0x189>, <&cpg CPG_MOD 0x18a>, + <&cpg CPG_MOD 0x174>, <&cpg CPG_MOD 0x175>, + <&cpg CPG_MOD 0x176>, <&cpg CPG_MOD 0x177>, + <&cpg CPG_MOD 0x178>, <&cpg CPG_MOD 0x179>, + <&cpg CPG_MOD 0x17a>, <&cpg CPG_MOD 0x17b>, + <&cpg CPG_MOD 0x17c>, <&cpg CPG_MOD 0x17d>, + <&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>, + <&cpg CPG_MOD 0x172>, <&cpg CPG_MOD 0x173>, + <&cpg CPG_MOD 0x170>, <&cpg CPG_MOD 0x171>, + <&cpg CPG_MOD 0xfb>, <&cpg CPG_MOD 0xfc>, + <&cpg CPG_MOD 0xfd>, <&cpg CPG_MOD 0xfa>, + <&cpg CPG_MOD 0x180>, + <&cpg CPG_MOD 0xf6>, <&cpg CPG_MOD 0xf7>, + <&cpg CPG_MOD 0x17e>, + <&cpg CPG_MOD 0x160>, <&cpg CPG_MOD 0x161>, + <&cpg CPG_MOD 0x162>, <&cpg CPG_MOD 0x163>, + <&cpg CPG_MOD 0x164>, <&cpg CPG_MOD 0x165>, + <&cpg CPG_MOD 0x166>, <&cpg CPG_MOD 0x167>, + <&cpg CPG_MOD 0x168>, <&cpg CPG_MOD 0x169>, + <&cpg CPG_MOD 0xf8>, <&cpg CPG_MOD 0xf9>; + clock-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "src-0", "src-1", + "src-2", "src-3", + "src-4", "src-5", + "src-6", "src-7", + "src-8", "src-9", + "mix-0", "mix-1", + "ctu-0", "ctu-1", + "dvc-0", "dvc-1", + "audio-clka", "audio-clkb", + "audio-clkc", "audio-clki", + "ssif_supply", + "scu", "scu_x2", + "scu_supply", + "adg-ssi-0", "adg-ssi-1", + "adg-ssi-2", "adg-ssi-3", + "adg-ssi-4", "adg-ssi-5", + "adg-ssi-6", "adg-ssi-7", + "adg-ssi-8", "adg-ssi-9", + "audmapp", "adg"; + power-domains = <&cpg>; + resets = <&cpg 0xe1>, + <&cpg 0xe2>, <&cpg 0xe3>, + <&cpg 0xe4>, <&cpg 0xe5>, + <&cpg 0xe6>, <&cpg 0xe7>, + <&cpg 0xe8>, <&cpg 0xe9>, + <&cpg 0xea>, <&cpg 0xeb>, + <&cpg 0xec>, <&cpg 0xee>, + <&cpg 0xed>; + reset-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "scu", "adg", + "audmapp"; + status = "disabled"; + + ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + dvc { + dvc0: dvc-0 { + dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>, + <&dmac2 0x1db3>, <&dmac3 0x1db3>, + <&dmac4 0x1db3>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + dvc1: dvc-1 { + dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>, + <&dmac2 0x1db4>, <&dmac3 0x1db4>, + <&dmac4 0x1db4>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + }; + + mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + src { + src0: src-0 { + interrupts = ; + dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>, + <&dmac1 0x1d9f>, <&dmac1 0x1da9>, + <&dmac2 0x1d9f>, <&dmac2 0x1da9>, + <&dmac3 0x1d9f>, <&dmac3 0x1da9>, + <&dmac4 0x1d9f>, <&dmac4 0x1da9>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>, + <&dmac1 0x1da0>, <&dmac1 0x1daa>, + <&dmac2 0x1da0>, <&dmac2 0x1daa>, + <&dmac3 0x1da0>, <&dmac3 0x1daa>, + <&dmac4 0x1da0>, <&dmac4 0x1daa>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>, + <&dmac1 0x1da1>, <&dmac1 0x1dab>, + <&dmac2 0x1da1>, <&dmac2 0x1dab>, + <&dmac3 0x1da1>, <&dmac3 0x1dab>, + <&dmac4 0x1da1>, <&dmac4 0x1dab>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>, + <&dmac1 0x1da2>, <&dmac1 0x1dac>, + <&dmac2 0x1da2>, <&dmac2 0x1dac>, + <&dmac3 0x1da2>, <&dmac3 0x1dac>, + <&dmac4 0x1da2>, <&dmac4 0x1dac>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>, + <&dmac1 0x1da3>, <&dmac1 0x1dad>, + <&dmac2 0x1da3>, <&dmac2 0x1dad>, + <&dmac3 0x1da3>, <&dmac3 0x1dad>, + <&dmac4 0x1da3>, <&dmac4 0x1dad>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>, + <&dmac1 0x1da4>, <&dmac1 0x1dae>, + <&dmac2 0x1da4>, <&dmac2 0x1dae>, + <&dmac3 0x1da4>, <&dmac3 0x1dae>, + <&dmac4 0x1da4>, <&dmac4 0x1dae>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>, + <&dmac1 0x1da5>, <&dmac1 0x1daf>, + <&dmac2 0x1da5>, <&dmac2 0x1daf>, + <&dmac3 0x1da5>, <&dmac3 0x1daf>, + <&dmac4 0x1da5>, <&dmac4 0x1daf>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>, + <&dmac1 0x1da6>, <&dmac1 0x1db0>, + <&dmac2 0x1da6>, <&dmac2 0x1db0>, + <&dmac3 0x1da6>, <&dmac3 0x1db0>, + <&dmac4 0x1da6>, <&dmac4 0x1db0>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>, + <&dmac1 0x1da7>, <&dmac1 0x1db1>, + <&dmac2 0x1da7>, <&dmac2 0x1db1>, + <&dmac3 0x1da7>, <&dmac3 0x1db1>, + <&dmac4 0x1da7>, <&dmac4 0x1db1>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>, + <&dmac1 0x1da8>, <&dmac1 0x1db2>, + <&dmac2 0x1da8>, <&dmac2 0x1db2>, + <&dmac3 0x1da8>, <&dmac3 0x1db2>, + <&dmac4 0x1da8>, <&dmac4 0x1db2>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx"; + }; + }; + + ssi { + ssi0: ssi-0 { + interrupts = ; + }; + ssi1: ssi-1 { + interrupts = ; + }; + ssi2: ssi-2 { + interrupts = ; + }; + ssi3: ssi-3 { + interrupts = ; + }; + ssi4: ssi-4 { + interrupts = ; + }; + ssi5: ssi-5 { + interrupts = ; + }; + ssi6: ssi-6 { + interrupts = ; + }; + ssi7: ssi-7 { + interrupts = ; + }; + ssi8: ssi-8 { + interrupts = ; + }; + ssi9: ssi-9 { + interrupts = ; + }; + }; + + ssiu { + ssiu00: ssiu-0 { + dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>, + <&dmac1 0x1d61>, <&dmac1 0x1d62>, + <&dmac2 0x1d61>, <&dmac2 0x1d62>, + <&dmac3 0x1d61>, <&dmac3 0x1d62>, + <&dmac4 0x1d61>, <&dmac4 0x1d62>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu01: ssiu-1 { + dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>, + <&dmac1 0x1d63>, <&dmac1 0x1d64>, + <&dmac2 0x1d63>, <&dmac2 0x1d64>, + <&dmac3 0x1d63>, <&dmac3 0x1d64>, + <&dmac4 0x1d63>, <&dmac4 0x1d64>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu02: ssiu-2 { + dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>, + <&dmac1 0x1d65>, <&dmac1 0x1d66>, + <&dmac2 0x1d65>, <&dmac2 0x1d66>, + <&dmac3 0x1d65>, <&dmac3 0x1d66>, + <&dmac4 0x1d65>, <&dmac4 0x1d66>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu03: ssiu-3 { + dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>, + <&dmac1 0x1d67>, <&dmac1 0x1d68>, + <&dmac2 0x1d67>, <&dmac2 0x1d68>, + <&dmac3 0x1d67>, <&dmac3 0x1d68>, + <&dmac4 0x1d67>, <&dmac4 0x1d68>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu10: ssiu-4 { + dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>, + <&dmac1 0x1d69>, <&dmac1 0x1d6a>, + <&dmac2 0x1d69>, <&dmac2 0x1d6a>, + <&dmac3 0x1d69>, <&dmac3 0x1d6a>, + <&dmac4 0x1d69>, <&dmac4 0x1d6a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu11: ssiu-5 { + dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>, + <&dmac1 0x1d6b>, <&dmac1 0x1d6c>, + <&dmac2 0x1d6b>, <&dmac2 0x1d6c>, + <&dmac3 0x1d6b>, <&dmac3 0x1d6c>, + <&dmac4 0x1d6b>, <&dmac4 0x1d6c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu12: ssiu-6 { + dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>, + <&dmac1 0x1d6d>, <&dmac1 0x1d6e>, + <&dmac2 0x1d6d>, <&dmac2 0x1d6e>, + <&dmac3 0x1d6d>, <&dmac3 0x1d6e>, + <&dmac4 0x1d6d>, <&dmac4 0x1d6e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu13: ssiu-7 { + dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>, + <&dmac1 0x1d6f>, <&dmac1 0x1d70>, + <&dmac2 0x1d6f>, <&dmac2 0x1d70>, + <&dmac3 0x1d6f>, <&dmac3 0x1d70>, + <&dmac4 0x1d6f>, <&dmac4 0x1d70>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu20: ssiu-8 { + dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>, + <&dmac1 0x1d71>, <&dmac1 0x1d72>, + <&dmac2 0x1d71>, <&dmac2 0x1d72>, + <&dmac3 0x1d71>, <&dmac3 0x1d72>, + <&dmac4 0x1d71>, <&dmac4 0x1d72>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu21: ssiu-9 { + dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>, + <&dmac1 0x1d73>, <&dmac1 0x1d74>, + <&dmac2 0x1d73>, <&dmac2 0x1d74>, + <&dmac3 0x1d73>, <&dmac3 0x1d74>, + <&dmac4 0x1d73>, <&dmac4 0x1d74>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu22: ssiu-10 { + dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>, + <&dmac1 0x1d75>, <&dmac1 0x1d76>, + <&dmac2 0x1d75>, <&dmac2 0x1d76>, + <&dmac3 0x1d75>, <&dmac3 0x1d76>, + <&dmac4 0x1d75>, <&dmac4 0x1d76>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu23: ssiu-11 { + dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>, + <&dmac1 0x1d77>, <&dmac1 0x1d78>, + <&dmac2 0x1d77>, <&dmac2 0x1d78>, + <&dmac3 0x1d77>, <&dmac3 0x1d78>, + <&dmac4 0x1d77>, <&dmac4 0x1d78>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu30: ssiu-12 { + dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>, + <&dmac1 0x1d79>, <&dmac1 0x1d7a>, + <&dmac2 0x1d79>, <&dmac2 0x1d7a>, + <&dmac3 0x1d79>, <&dmac3 0x1d7a>, + <&dmac4 0x1d79>, <&dmac4 0x1d7a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu31: ssiu-13 { + dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>, + <&dmac1 0x1d7b>, <&dmac1 0x1d7c>, + <&dmac2 0x1d7b>, <&dmac2 0x1d7c>, + <&dmac3 0x1d7b>, <&dmac3 0x1d7c>, + <&dmac4 0x1d7b>, <&dmac4 0x1d7c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu32: ssiu-14 { + dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>, + <&dmac1 0x1d7d>, <&dmac1 0x1d7e>, + <&dmac2 0x1d7d>, <&dmac2 0x1d7e>, + <&dmac3 0x1d7d>, <&dmac3 0x1d7e>, + <&dmac4 0x1d7d>, <&dmac4 0x1d7e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu33: ssiu-15 { + dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>, + <&dmac1 0x1d7f>, <&dmac1 0x1d80>, + <&dmac2 0x1d7f>, <&dmac2 0x1d80>, + <&dmac3 0x1d7f>, <&dmac3 0x1d80>, + <&dmac4 0x1d7f>, <&dmac4 0x1d80>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu40: ssiu-16 { + dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>, + <&dmac1 0x1d81>, <&dmac1 0x1d82>, + <&dmac2 0x1d81>, <&dmac2 0x1d82>, + <&dmac3 0x1d81>, <&dmac3 0x1d82>, + <&dmac4 0x1d81>, <&dmac4 0x1d82>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu41: ssiu-17 { + dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>, + <&dmac1 0x1d83>, <&dmac1 0x1d84>, + <&dmac2 0x1d83>, <&dmac2 0x1d84>, + <&dmac3 0x1d83>, <&dmac3 0x1d84>, + <&dmac4 0x1d83>, <&dmac4 0x1d84>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu42: ssiu-18 { + dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>, + <&dmac1 0x1d85>, <&dmac1 0x1d86>, + <&dmac2 0x1d85>, <&dmac2 0x1d86>, + <&dmac3 0x1d85>, <&dmac3 0x1d86>, + <&dmac4 0x1d85>, <&dmac4 0x1d86>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu43: ssiu-19 { + dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>, + <&dmac1 0x1d87>, <&dmac1 0x1d88>, + <&dmac2 0x1d87>, <&dmac2 0x1d88>, + <&dmac3 0x1d87>, <&dmac3 0x1d88>, + <&dmac4 0x1d87>, <&dmac4 0x1d88>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu50: ssiu-20 { + dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>, + <&dmac1 0x1d89>, <&dmac1 0x1d8a>, + <&dmac2 0x1d89>, <&dmac2 0x1d8a>, + <&dmac3 0x1d89>, <&dmac3 0x1d8a>, + <&dmac4 0x1d89>, <&dmac4 0x1d8a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu60: ssiu-21 { + dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>, + <&dmac1 0x1d8b>, <&dmac1 0x1d8c>, + <&dmac2 0x1d8b>, <&dmac2 0x1d8c>, + <&dmac3 0x1d8b>, <&dmac3 0x1d8c>, + <&dmac4 0x1d8b>, <&dmac4 0x1d8c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu70: ssiu-22 { + dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>, + <&dmac1 0x1d8d>, <&dmac1 0x1d8e>, + <&dmac2 0x1d8d>, <&dmac2 0x1d8e>, + <&dmac3 0x1d8d>, <&dmac3 0x1d8e>, + <&dmac4 0x1d8d>, <&dmac4 0x1d8e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu80: ssiu-23 { + dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>, + <&dmac1 0x1d8f>, <&dmac1 0x1d90>, + <&dmac2 0x1d8f>, <&dmac2 0x1d90>, + <&dmac3 0x1d8f>, <&dmac3 0x1d90>, + <&dmac4 0x1d8f>, <&dmac4 0x1d90>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu90: ssiu-24 { + dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>, + <&dmac1 0x1d91>, <&dmac1 0x1d92>, + <&dmac2 0x1d91>, <&dmac2 0x1d92>, + <&dmac3 0x1d91>, <&dmac3 0x1d92>, + <&dmac4 0x1d91>, <&dmac4 0x1d92>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu91: ssiu-25 { + dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>, + <&dmac1 0x1d93>, <&dmac1 0x1d94>, + <&dmac2 0x1d93>, <&dmac2 0x1d94>, + <&dmac3 0x1d93>, <&dmac3 0x1d94>, + <&dmac4 0x1d93>, <&dmac4 0x1d94>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu92: ssiu-26 { + dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>, + <&dmac1 0x1d95>, <&dmac1 0x1d96>, + <&dmac2 0x1d95>, <&dmac2 0x1d96>, + <&dmac3 0x1d95>, <&dmac3 0x1d96>, + <&dmac4 0x1d95>, <&dmac4 0x1d96>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + ssiu93: ssiu-27 { + dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>, + <&dmac1 0x1d97>, <&dmac1 0x1d98>, + <&dmac2 0x1d97>, <&dmac2 0x1d98>, + <&dmac3 0x1d97>, <&dmac3 0x1d98>, + <&dmac4 0x1d97>, <&dmac4 0x1d98>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", + "tx", "rx"; + }; + }; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; From c42be528a5a4da70eefa7d2e531dc719a8d103a4 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:49 +0000 Subject: [PATCH 352/864] arm64: dts: renesas: rzg3e-smarc-som: Add Versa3 clock generator Add the Renesas 5P35023 (Versa3) programmable clock generator on the I2C2 bus along with its 24MHz input clock (x2 oscillator) to feed the audio subsystem. The Versa3 provides the following clock outputs: - Output 0: 24MHz (reference), - Output 1: 12.288MHz (audio, 48kHz family), - Output 2: 11.2896MHz (audio, 44.1kHz family), - Output 3: 12.288MHz (audio), - Output 4: 25MHz (DIFF1, Ethernet). These clocks are required for the audio codec and the Ethernet controller found on the RZ/G3E SMARC EVK. Output 5 (DIFF2) is left out, as it is not connected on this board. Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260619083951.3777556-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 15c22dbf0ad3..455ed35ae5d3 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -78,6 +78,12 @@ reg_vdd0p8v_others: regulator-vdd0p8v-others { regulator-always-on; }; + x2: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + /* 32.768kHz crystal */ x3: x3-clock { compatible = "fixed-clock"; @@ -137,6 +143,20 @@ raa215300: pmic@12 { interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>; }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x2>; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>; + assigned-clock-rates = <24000000>, <12288000>, + <11289600>, <12288000>, + <25000000>; + }; }; &i3c { From 14d21efe16dc5b92774a987ada0868e0bcf3dd91 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:50 +0000 Subject: [PATCH 353/864] arm64: dts: renesas: rzg3e-smarc-som: Add audio pinmux definitions Add pinmux definitions for SSI3/SSI4 audio interface on RZ/G3E SMARC SoM: - sound_clk_pins: AUDIO_CLKB and AUDIO_CLKC clock outputs, - sound_pins: SSI3_SCK, SSI3_WS, SSI3_SDATA (playback) and SSI4_SDATA (capture). Signed-off-by: John Madieu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260619083951.3777556-4-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 455ed35ae5d3..0e6dc84e0199 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -352,6 +352,18 @@ sd2-pwen { }; }; + sound_clk_pins: sound-clk { + pinmux = , /* AUDIO_CLKB */ + ; /* AUDIO_CLKC */ + }; + + sound_pins: sound { + pinmux = , /* SSI3_SDATA */ + , /* SSI3_SCK */ + , /* SSI3_WS */ + ; /* SSI4_SDATA */ + }; + xspi_pins: xspi0 { pinmux = , /* XSPI0_IO0 */ , /* XSPI0_IO1 */ From 3e23d2548ddb2d73b26b85c990a77925a9cf7f86 Mon Sep 17 00:00:00 2001 From: John Madieu Date: Fri, 19 Jun 2026 08:39:51 +0000 Subject: [PATCH 354/864] arm64: dts: renesas: r9a09g047e57-smarc: Add DA7212 audio codec support RZ/G3E SMARC board has a DA7212 audio codec connected via I2C1 for sound input/output using SSI3/SSI4 where: - The codec receives its master clock from the Versa3 clock generator present on the SoM, - SSI4 shares clock pins with SSI3 to provide a separate data line for full-duplex audio capture. Enable audio support on RZ/G3E SMARC2 EVK boards with a DA7212 audio codec. Reviewed-by: Geert Uytterhoeven Signed-off-by: John Madieu Link: https://patch.msgid.link/20260619083951.3777556-5-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 112 ++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 07db9e434521..4eed095b683b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -32,6 +32,37 @@ #include "rzg3e-smarc-som.dtsi" #include "renesas-smarc2.dtsi" +/* + * SSI-DA7212 + * + * These commands are required when Playback/Capture + * + * amixer -q cset name='Aux Switch' on + * amixer -q cset name='Mixin Left Aux Left Switch' on + * amixer -q cset name='Mixin Right Aux Right Switch' on + * amixer -q cset name='ADC Switch' on + * amixer -q cset name='Mixout Right Mixin Right Switch' off + * amixer -q cset name='Mixout Left Mixin Left Switch' off + * amixer -q cset name='Headphone Volume' 70% + * amixer -q cset name='Headphone Switch' on + * amixer -q cset name='Mixout Left DAC Left Switch' on + * amixer -q cset name='Mixout Right DAC Right Switch' on + * amixer -q cset name='DAC Left Source MUX' 'DAI Input Left' + * amixer -q cset name='DAC Right Source MUX' 'DAI Input Right' + * amixer -q sset 'Mic 1 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mic 2 Amp Source MUX' 'MIC_P' + * amixer -q sset 'Mixin Left Mic 1' on + * amixer -q sset 'Mixin Right Mic 2' on + * amixer -q sset 'Mic 1' 90% on + * amixer -q sset 'Mic 2' 90% on + * amixer -q sset 'Lineout' 80% on + * amixer -q set "Headphone" 100% on + * + * When Capture chained with DVC, use this command to amplify sound + * amixer set 'DVC In',0 80% + * For playback, use: amixer set 'DVC Out',0 80% + */ + / { model = "Renesas SMARC EVK version 2 based on r9a09g047e57"; compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", @@ -55,6 +86,22 @@ vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { gpios-states = <0>; states = <3300000 0>, <1800000 1>; }; + + sound_card: sound { + compatible = "audio-graph-card"; + + label = "snd-rzg3e"; + + dais = <&rsnd_port0>; /* DA7212 */ + }; +}; + +&audio_clkb { + clock-frequency = <11289600>; +}; + +&audio_clkc { + clock-frequency = <12288000>; }; &canfd { @@ -99,6 +146,35 @@ &i2c0 { pinctrl-names = "default"; }; +&i2c1 { + da7212: codec@1a { + compatible = "dlg,da7212"; + #sound-dai-cells = <0>; + reg = <0x1a>; + + clocks = <&versa3 1>; + clock-names = "mclk"; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDSP-supply = <®_3p3v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_1p8v>; + + port { + da7212_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint0>; + mclk-fs = <256>; + }; + }; + }; +}; + &keys { pinctrl-0 = <&nmi_pins>; pinctrl-names = "default"; @@ -280,6 +356,42 @@ &sdhi1 { vqmmc-supply = <&vqmmc_sd1_pvdd>; }; +&snd_rzg3e { + pinctrl-0 = <&sound_clk_pins &sound_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* audio_clkout */ + #clock-cells = <0>; + clock-frequency = <11289600>; + + /* Multi DAI */ + #sound-dai-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + rsnd_port0: port@0 { + reg = <0>; + rsnd_endpoint0: endpoint { + remote-endpoint = <&da7212_endpoint>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + + playback = <&ssi3>, <&src1>, <&dvc1>; + capture = <&ssi4>, <&src0>, <&dvc0>; + }; + }; + }; +}; + +&ssi4 { + shared-pin; +}; + &usb3_phy { status = "okay"; }; From 92b4465b221e4e1b38d56b6ce8290949555b72bd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 21 Jun 2026 04:50:21 +0200 Subject: [PATCH 355/864] arm64: dts: renesas: Add soc: labels to soc nodes Add soc: labels to the /soc {} nodes to align DTS with r8a77951.dtsi which already has that soc: label. The soc: label is useful in U-Boot where it is used in U-Boot extras DT fragments. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260621025052.406507-1-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-2-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-3-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-4-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-5-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-6-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-7-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-8-marek.vasut+renesas@mailbox.org Link: https://patch.msgid.link/20260621025052.406507-9-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 36675f5bcdea..e66d86db6e6c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -262,7 +262,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index ceef0104f75e..62c6703917db 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -146,7 +146,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 9df5f1a42400..0ae9bb72d2dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -326,7 +326,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ad36aa8e7543..4f9989b5e77a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -311,7 +311,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9d76e39eab72..ad4491ba948f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -311,7 +311,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 611a9335c63a..70708f5cf746 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -182,7 +182,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1f6676e2795a..f7f1f280fa0b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -91,7 +91,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 86b7792d68fa..514dafe34478 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -120,7 +120,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 5f3fcef7560c..522a49db0258 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -85,7 +85,7 @@ scif_clk: scif { clock-frequency = <0>; }; - soc { + soc: soc { compatible = "simple-bus"; bootph-all; From 7589467672a86ae29f2f62715166f88a054f4b54 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Jun 2026 18:07:33 +0100 Subject: [PATCH 356/864] arm64: dts: renesas: rzt2h-n2h-evk-common: Add memory nodes Add memory nodes for the RZ/T2H and RZ/N2H EVK boards. These boards populate 8GiB of DDR memory, which is exposed through two address ranges. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260622170733.1703585-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index ceccddb92d40..ffcc0960903b 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -29,6 +29,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + memory@c8000000 { + device_type = "memory"; + /* first 128MiB is reserved for secure area. */ + reg = <0x0 0xc8000000 0x0 0x38000000>; + }; + + memory@240000000 { + device_type = "memory"; + reg = <0x2 0x40000000 0x1 0xc0000000>; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; From a91b23a9d0ea08ed20df34bf2d9e9b10eb8da4c1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 26 Jun 2026 20:03:24 +0200 Subject: [PATCH 357/864] ARM: dts: renesas: r9a06g032: Describe SPI controllers Add nodes for the 6 SPI controllers of the Renesas RZ/N1D SoC. The first 4 can only be controllers, the latter 2 can only be targets. DMA nodes are not added yet because DMA needs some extra code in the drivers and cannot be tested yet. Basic FIFO mode works reliably, though. Signed-off-by: Wolfram Sang Tested-by: Herve Codina Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260626180326.9593-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 442ea26b40f5..19c9bce0a26d 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -563,6 +563,90 @@ gic: interrupt-controller@44101000 { ; }; + /* Controller only */ + spi1: spi@50005000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50005000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Controller only */ + spi2: spi@50006000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50006000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI1>, <&sysctrl R9A06G032_HCLK_SPI1>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Controller only */ + spi3: spi@50007000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50007000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI2>, <&sysctrl R9A06G032_HCLK_SPI2>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Controller only */ + spi4: spi@50008000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50008000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI3>, <&sysctrl R9A06G032_HCLK_SPI3>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + num-cs = <4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Target only */ + spi5: spi@50009000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x50009000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-slave; + #address-cells = <0>; + #size-cells = <0>; + status = "disabled"; + }; + + /* Target only */ + spi6: spi@5000a000 { + compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi"; + reg = <0x5000a000 0x200>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>; + clock-names = "ssi_clk", "pclk"; + power-domains = <&sysctrl>; + spi-slave; + #address-cells = <0>; + #size-cells = <0>; + status = "disabled"; + }; + /* * The GPIO mapping to the corresponding pins is not obvious. * See the hardware documentation for details. From f4f9b372a8a6aeb9b95e9ca4d9542b384ebb983c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Fri, 26 Jun 2026 20:03:25 +0200 Subject: [PATCH 358/864] ARM: dts: renesas: r9a06g032-rzn1d400-eb: Enable SPI-FRAM Activate the FRAM and the SPI bus which it is attached to. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260626180326.9593-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a06g032-rzn1d400-eb.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts index 97a339b30d76..ead379988fb1 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts @@ -53,6 +53,10 @@ led@1 { }; }; +&gpio2 { + status = "okay"; +}; + &i2c2 { /* Sensors are different across revisions. All are LM75B compatible */ sensor@49 { @@ -152,6 +156,13 @@ pins_sdio1_clk: pins-sdio1-clk { drive-strength = <12>; }; + pins_spi1: pins-spi1 { + pinmux = , + , + , + ; + }; + pins_uart2: pins-uart2 { pinmux = , , @@ -168,6 +179,20 @@ &sdio1 { status = "okay"; }; +&spi1 { + pinctrl-0 = <&pins_spi1>; + pinctrl-names = "default"; + status = "okay"; + + cs-gpios = <&gpio2a 31 GPIO_ACTIVE_LOW>; + + fram: fram@0 { + compatible = "cypress,fm25", "atmel,at25"; + reg = <0>; + spi-max-frequency = <12500000>; + }; +}; + &switch { pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>; From c73b080d1d1bf89775d69f2e249820e3e242814b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 17:33:10 +0100 Subject: [PATCH 359/864] arm64: dts: renesas: r9a09g057: Add PCIe nodes Add PCIe nodes to Renesas RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708163311.222176-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 140 +++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 8af0f0f2f2f7..639693d464a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1041,6 +1041,146 @@ rsci9: serial@12803000 { status = "disabled"; }; + pcie0: pcie@13400000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13400000 0 0x10000>; + ranges = <0x02000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0x43000000 0x4 0x40000000 0x4 0x40000000 0x6 0x00000000>; + dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie0 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie0 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie0 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 0>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + + pcie1: pcie@13410000 { + compatible = "renesas,r9a09g057-pcie"; + reg = <0 0x13410000 0 0x10000>; + ranges = <0x02000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0x43000000 0xa 0x40000000 0xa 0x40000000 0x5 0xc0000000>; + dma-ranges = <0x43000000 0x0 0x40000000 0x0 0x40000000 0x4 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all", + "link_equalization_request", + "turn_off_event", "pmu_poweroff", + "d3_event_f0", "d3_event_f1", + "cfg_pmcsr_writeclear_f0", + "cfg_pmcsr_writeclear_f1"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie1 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie1 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie1 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD 0xc4>, <&cpg CPG_MOD 0xc5>; + clock-names = "aclk", "pmu"; + resets = <&cpg 0xb2>; + reset-names = "aresetn"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + num-lanes = <2>; + renesas,sysc = <&sys 1>; + status = "disabled"; + + pcie_port1: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x003b>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 90a9d595f36ba11d95568acfda641a7e371f627d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 17:33:11 +0100 Subject: [PATCH 360/864] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable PCIe Enable the PCIE1 slot which is connected to PCIe0 channel. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708163311.222176-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 3c1ddacc0944..637fc92dcc26 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -384,6 +384,18 @@ &ostm7 { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + num-lanes = <4>; + status = "okay"; +}; + +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + &pinctrl { eth0_pins: eth0 { pins = "ET0_TXC_TXCLK"; @@ -430,6 +442,12 @@ i2c8_pins: i2c8 { ; /* I2C8_SCL */ }; + pcie0_pins: pcie0 { + pins = "PCIE0_RSTOUTB"; + slew-rate = <0>; + renesas,output-impedance = <2>; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; From 3e7259fb8a31c8b784628cfc417998447b0e5629 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 18:28:48 +0100 Subject: [PATCH 361/864] arm64: dts: renesas: r9a09g056: Fix PCIe dma-ranges memory space code The RZ/V2N SoC supports up to 8 GiB of memory. Update the PCIe dma-ranges property to use the 64-bit prefetchable memory space code. Fixes: 4c443296ff17 ("arm64: dts: renesas: r9a09g056: Add PCIe node") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708172849.227915-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 3a308dbf733c..76fa34ff3d07 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -1065,7 +1065,7 @@ pcie: pcie@13400000 { reg = <0 0x13400000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>; + dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>; bus-range = <0x0 0xff>; interrupts = , , From 24afcb87e6aca1ff3face276223eeea0012f8e2b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 8 Jul 2026 18:28:49 +0100 Subject: [PATCH 362/864] arm64: dts: renesas: r9a09g047: Fix PCIe dma-ranges memory space code The RZ/G3E SoC supports up to 8 GiB of memory. Update the PCIe dma-ranges property to use the 64-bit prefetchable memory space code. Fixes: 1ac57c9830cb ("arm64: dts: renesas: r9a09g047: Add PCIe node") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260708172849.227915-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 310f988a63c4..73757e8e2197 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -1447,7 +1447,7 @@ pcie: pcie@13400000 { reg = <0 0x13400000 0 0x10000>; ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, <0x43000000 4 0x40000000 4 0x40000000 6 0x00000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 2 0x00000000>; + dma-ranges = <0x43000000 0 0x40000000 0 0x40000000 2 0x00000000>; bus-range = <0x0 0xff>; interrupts = , , From 11c3fc9e3db80adb129e78c296cf2bd9ea6daca7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Jul 2026 14:20:38 +0200 Subject: [PATCH 363/864] dt-bindings: soc: mediatek: mutex: Improve title and description Improve both the title and the description of this hardware to disambiguate its functionality from a hardware mutex and/or from a hwspinlock. Though in datasheets this is called "DISP_MUTEX", the meaning is is "Mute-X" (where "X" means "any hardware trigger signal") really as this is what this piece of hardware does: muting or unmuting of signals in each sub-IP of the display or other multimedia related controllers. Based on that, also clarify the description text, as to make sure that the information is actually accurate. While at it, also avoid forcing literal blocks in the description as there is nothing in there needing that (no ascii graph or other stuff that needs a literal block anyway), and add myself in the list of maintainers. Acked-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- .../bindings/soc/mediatek/mediatek,mutex.yaml | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 5267cfe92572..1ba086ad749d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -4,18 +4,21 @@ $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek mutex +title: MediaTek Mute-X maintainers: + - AngeloGioacchino Del Regno - Chun-Kuang Hu - Philipp Zabel -description: | - Mediatek mutex, namely MUTEX, is used to send the triggers signals called - Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display - data path or MDP data path. - In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects - the shadow register. +description: + MediaTek Mute-X, namely MUTEX, is used to "mute" or "unmute" trigger signals + like Start Of Frame (SOF), End Of Frame (EOF), Tearing Effect (TE / VSYNC) + and others to each hardware sub-modules in the Display Controller IP or in + the Media Data Path (MDP) IP. + In some SoCs like MT2701, this hardware module may feature functionality + to, for example, protect shadow registers by blocking auto write triggers + upon operation (usually frame push) completion. MUTEX device node must be siblings to the central MMSYS_CONFIG node. For a description of the MMSYS_CONFIG binding, see Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml From df9b9d59586f3d8bdeba5b3c7b7ea68cb0302fb7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Oct 2025 16:01:28 -0400 Subject: [PATCH 364/864] dt-bindings: input: fsl,scu-key: Add compatible string fsl,imx8qm-sc-key Add compatible string fsl,imx8qm-sc-key for i.MX8QM and fallback to fsl,imx-sc-key. Acked-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/input/fsl,scu-key.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml index 29921aab9d97..2566cffc252d 100644 --- a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml +++ b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml @@ -18,7 +18,9 @@ allOf: properties: compatible: items: - - const: fsl,imx8qxp-sc-key + - enum: + - fsl,imx8qm-sc-key + - fsl,imx8qxp-sc-key - const: fsl,imx-sc-key linux,keycodes: From f9c8aaffc782cae682d3606037f2d02fb4e0035a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 28 Oct 2025 16:01:29 -0400 Subject: [PATCH 365/864] arm64: dts: imx8qm: add scu power key support Add scu power key node. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index ae7de9f99055..9f9b34153ad5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -330,6 +331,12 @@ clk: clock-controller { #clock-cells = <2>; }; + scu_key: keys { + compatible = "fsl,imx8qm-sc-key", "fsl,imx-sc-key"; + linux,keycodes = ; + wakeup-source; + }; + iomuxc: pinctrl { compatible = "fsl,imx8qm-iomuxc"; }; From d92d8c9ddfecb9124ef006b6195a0d954499857d Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein Date: Sun, 5 Jul 2026 10:16:32 +0200 Subject: [PATCH 366/864] arm64: dts: apple: Add pmgr-misc nodes to t60xx Adds the PMGR misc control nodes for M1/2 Pro/Max/Ultra series devices. Reviewed-by: Sven Peter Signed-off-by: Sasha Finkelstein Reviewed-by: Joshua Peisach Link: https://patch.msgid.link/20260705-pmgr-misc-v3-3-51b75fed6f73@chaosmail.tech Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 7 +++++++ arch/arm64/boot/dts/apple/t602x-die0.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index f715b19efd16..3271d234b483 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -24,6 +24,13 @@ aic: interrupt-controller@28e100000 { power-domains = <&ps_aic>; }; + pmgr_misc: power-management@28e20c000 { + compatible = "apple,t6000-pmgr-misc"; + reg = <0x2 0x8e20c000 0 0x400>, + <0x2 0x8e20c800 0 0x400>; + reg-names = "fabric-ps", "dcs-ps"; + }; + smc: smc@290400000 { compatible = "apple,t6000-smc", "apple,smc"; reg = <0x2 0x90400000 0x0 0x4000>, diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi index 8622ddea7b44..121f2cf75915 100644 --- a/arch/arm64/boot/dts/apple/t602x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -23,6 +23,13 @@ aic: interrupt-controller@28e100000 { power-domains = <&ps_aic>; }; + pmgr_misc: power-management@28e20c000 { + compatible = "apple,t6020-pmgr-misc"; + reg = <0x2 0x8e20c000 0 0x400>, + <0x2 0x8e20c400 0 0x400>; + reg-names = "fabric-ps", "dcs-ps"; + }; + nub_spmi0: spmi@29e114000 { compatible = "apple,t6020-spmi", "apple,t8103-spmi"; reg = <0x2 0x9e114000 0x0 0x100>; From 949e5a6a8f349ff3098f4dc2aa3483723e4209c1 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 14 Jul 2026 18:33:51 +0200 Subject: [PATCH 367/864] dt-bindings: arm: fsl: add Variscite DART-MX8M-MINI Boards Add DT compatible strings for Variscite DART-MX8MM SoM and Variscite development carrier Board. Acked-by: Krzysztof Kozlowski Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f96f3d31dac1..7b57a6ee1b50 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1064,6 +1064,12 @@ properties: - const: solidrun,imx8mm-sr-som - const: fsl,imx8mm + - description: Variscite DART-MX8MM based boards + items: + - const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board + - const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony From 5297deef08bc3ddc1a27b3518b770dbc3a14da81 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 14 Jul 2026 18:33:52 +0200 Subject: [PATCH 368/864] arm64: dts: freescale: Add support for Variscite DART-MX8M-MINI Add device tree support for the Variscite DART-MX8MM system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8M Mini MPU processor - Up to 4GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-var-dart.dtsi | 558 ++++++++++++++++++ 1 file changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi new file mode 100644 index 000000000000..2324063f8fd9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX8M-MINI + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8m-mini/dart-mx8m-mini/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "Variscite DART-MX8M-MINI Module"; + compatible = "variscite,var-dart-mx8mm", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth_phy>; + regulator-name = "eth_phy_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <20000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + phy-supply = <®_eth_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio2>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&mu { + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +/* BT module */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc1 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_fec1_sleep: fec1sleepgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16 0x120 + MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120 + MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18 0x120 + MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19 0x120 + MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20 0x120 + MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21 0x120 + MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29 0x120 + MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28 0x120 + MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27 0x120 + MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26 0x120 + MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23 0x120 + MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25 0x120 + MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120 + MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x100 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x140 + >; + }; + + pinctrl_reg_eth_phy: regeth-phygrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140 + MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 + MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x140 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 + >; + }; +}; From 770aba46ea0fad62631848d4cf2c0c8a5fac7ba5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Tue, 14 Jul 2026 18:33:53 +0200 Subject: [PATCH 369/864] arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board Add device tree support for the Variscite Sonata carrier board with the DART-MX8M-MINI system on module. The Sonata board includes - uSD Card support - USB ports and OTG - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals Link: https://variscite.com/carrier-boards/sonata-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-var-dart-sonata.dts | 516 ++++++++++++++++++ 2 files changed, 517 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 842c98a91bb7..be3c858f1eeb 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-iv-306-d.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tx8m-1610-moduline-mini-111.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts new file mode 100644 index 000000000000..57d29a5c3821 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Sonata carrier board for DART-MX8M-MINI + * + * Link: https://variscite.com/carrier-boards/sonata-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8mm-var-dart.dtsi" + +/ { + model = "Variscite DART-MX8M-MINI on Sonata-Board"; + compatible = "variscite,var-dart-mx8mm-sonata", + "variscite,var-dart-mx8mm", + "fsl,imx8mm"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-up { + label = "Up"; + linux,code = ; + gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-down { + label = "Down"; + linux,code = ; + gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-emmc { + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + label = "eMMC"; + linux,default-trigger = "mmc2"; + }; + }; + + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vmmc_usdhc2>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio1 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; + + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&clk40m>; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9534: gpio@22 { + compatible = "nxp,pca9534"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + extcon_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca6408_1: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6408>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + pca6408_2: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + reset-gpios = <&pca6408_2 3 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +/* Console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + wakeup-source; + status = "okay"; +}; + +/* Header */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* Header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + disable-over-current; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 + >; + }; + + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x13 + >; + }; + + pinctrl_extcon: extcongrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c6 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 + >; + }; + + pinctrl_pca6408: pca6408grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c6 + >; + }; + + pinctrl_pwm: pwmgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; + + pinctrl_vmmc_usdhc2: regvmmc-usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0xc1 + >; + }; + + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc1 + >; + }; +}; From 67f06acfca6cd79c75aa89df334968348fb611fd Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Mon, 22 Jun 2026 12:11:56 +0530 Subject: [PATCH 370/864] arm64: dts: qcom: lemans: Add compatible to the PCIe Root Port Add 'compatible = "pciclass,0604"' to the pcieport0 node in lemans.dtsi to allow the PCI subsystem to associate the DT node with the PCI-to-PCI bridge device. This is required for downstream DT nodes (such as M.2 connectors described as graph endpoints of the Root Port) to be matched to PCI devices. Reviewed-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Signed-off-by: Wei Deng Link: https://lore.kernel.org/r/20260622-v3-lemans-split-v3-1-d26bb22594e3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 4b706b1da4d6..23af6777cf53 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2761,6 +2761,7 @@ pcie0: pcie@1c00000 { status = "disabled"; pcieport0: pcie@0 { + compatible = "pciclass,0604"; device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; From a6d4bb0a6aced2bdffd606d3a9d5df73ea0d19a1 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Mon, 22 Jun 2026 12:11:57 +0530 Subject: [PATCH 371/864] arm64: dts: qcom: lemans-evk: Describe the PCIe M.2 Key E connector The lemans EVK has the PCIe M.2 Mechanical Key E connector to connect wireless connectivity cards over PCIe and UART interfaces. Hence, describe the connector node and link it with the PCIe 0 Root Port and UART17 nodes through graph port/endpoint. The M.2 Key E connector is powered by a 3.3V fixed regulator (vreg_wcn_3p3) which is sourced from the board's 12V DC input rail (vreg_dcin_12v). Both regulators are always-on and are required by the pcie-m2-e-connector binding. Also add the serial1 = &uart17 alias, which is required for the Bluetooth serdev device to be enumerated on the UART17 interface. Reviewed-by: Bartosz Golaszewski Reviewed-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam Signed-off-by: Wei Deng Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260622-v3-lemans-split-v3-2-d26bb22594e3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 75 +++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 0b01be78a737..0c53640c42a6 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -21,6 +21,7 @@ aliases { ethernet0 = ðernet0; mmc1 = &sdhc; serial0 = &uart10; + serial1 = &uart17; serial2 = &uart0; }; @@ -119,6 +120,38 @@ usb2_con_hs_ep: endpoint { }; }; + connector-3 { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcieport0_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart17_ep>; + }; + }; + }; + }; + edp0-connector { compatible = "dp-connector"; label = "EDP0"; @@ -218,6 +251,17 @@ vmmc_sdc: regulator-vmmc-sdc { regulator-max-microvolt = <2950000>; }; + vreg_dcin_12v: regulator-dcin-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_DCIN_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + regulator-always-on; + regulator-boot-on; + }; + vreg_sdc: regulator-vreg-sdc { compatible = "regulator-gpio"; @@ -231,6 +275,19 @@ vreg_sdc: regulator-vreg-sdc { startup-delay-us = <100>; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vreg_dcin_12v>; + + regulator-always-on; + regulator-boot-on; + }; }; &apps_rsc { @@ -815,6 +872,14 @@ &pcie1_phy { status = "okay"; }; +&pcieport0 { + port { + pcieport0_ep: endpoint { + remote-endpoint = <&m2_e_pcie_ep>; + }; + }; +}; + &pmm8654au_0_pon_resin { linux,code = ; status = "okay"; @@ -1057,6 +1122,16 @@ &uart10 { status = "okay"; }; +&uart17 { + status = "okay"; + + port { + uart17_ep: endpoint { + remote-endpoint = <&m2_e_uart_ep>; + }; + }; +}; + &ufs_mem_hc { reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; vcc-supply = <&vreg_l8a>; From 569413a98a1761782a0770aa85d20a2c78893279 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 25 Jun 2026 10:42:43 +0200 Subject: [PATCH 372/864] arm64: dts: qcom: msm8996-xiaomi-gemini: Fix up ti,drv2604 enable GPIO Update the 'enable-gpio' property name to 'enable-gpios' to conform to the bindings for the TI DRV2604 haptics module. While at it, use the GPIO_ACTIVE_HIGH define instead of the raw literal. Fixes: 4ac46b3682c5 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5") Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260625-topic-ti_drv2604_dtwarn-v1-1-76e91fcafbe8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index fd3a2121465b..ca22e2f9d20a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -39,7 +39,7 @@ &blsp2_i2c3 { haptics: drv2604@5a { compatible = "ti,drv2604"; reg = <0x5a>; - enable-gpio = <&tlmm 93 0x00>; + enable-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>; mode = ; library-sel = ; pinctrl-names = "default","sleep"; From c4f26a1987f84a904880dc25598d26b178b829ec Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 24 Jun 2026 20:38:12 +0800 Subject: [PATCH 373/864] arm64: dts: qcom: glymur: Add label properties to CoreSight devices Add label properties to TPDM and CTI nodes in the glymur device tree to provide human-readable identifiers for each CoreSight device. These labels allow userspace tools and the CoreSight framework to identify devices by name rather than by base address. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260624-add-label-node-for-glymur-v2-1-e8420fd7025f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index dcedd7a98651..de616cc2929e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -6303,6 +6303,7 @@ tpdm@1000f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_spdm"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -6367,6 +6368,7 @@ tpdm@1102c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_gcc"; qcom,dsb-msrs-num = <32>; @@ -6385,6 +6387,7 @@ tpdm@11180000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; @@ -6404,6 +6407,7 @@ tpdm@11185000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_dpm_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -6423,6 +6427,7 @@ tpdm@11186000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_cdsp_dpm_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -6543,6 +6548,7 @@ cti@11193000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_cdsp"; }; cti_wpss: cti@111ab000 { @@ -6551,6 +6557,7 @@ cti_wpss: cti@111ab000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "cti_wpss"; }; tpdm@111d0000 { @@ -6559,6 +6566,7 @@ tpdm@111d0000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qm"; qcom,dsb-msrs-num = <32>; @@ -6734,6 +6742,7 @@ tpdm@11207000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_mm_dsb"; qcom,dsb-msrs-num = <32>; @@ -6752,6 +6761,7 @@ tpdm@1120b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_east_dsb"; qcom,dsb-msrs-num = <32>; @@ -6770,6 +6780,7 @@ tpdm@11213000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_west_dsb"; qcom,dsb-msrs-num = <32>; @@ -6788,6 +6799,7 @@ tpdm@11219000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_center_dsb"; qcom,dsb-msrs-num = <32>; @@ -6806,6 +6818,7 @@ tpdm@1121a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_ipcc"; qcom,cmb-msrs-num = <32>; @@ -6824,6 +6837,7 @@ tpdm@1121b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_qrng"; qcom,cmb-msrs-num = <32>; @@ -6842,6 +6856,7 @@ tpdm@1121c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pmu"; qcom,dsb-msrs-num = <32>; @@ -6860,6 +6875,7 @@ tpdm@1121d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_cx"; qcom,cmb-msrs-num = <32>; @@ -6878,6 +6894,7 @@ tpdm@1121e000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_mxc"; qcom,cmb-msrs-num = <32>; @@ -6896,6 +6913,7 @@ tpdm@1121f000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_rdpm_mxa"; qcom,cmb-msrs-num = <32>; @@ -6914,6 +6932,7 @@ tpdm@11220000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_center_dsb_1"; qcom,dsb-msrs-num = <32>; @@ -6932,6 +6951,7 @@ tpdm@11224000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_south2_dsb"; qcom,dsb-msrs-num = <32>; @@ -6950,6 +6970,7 @@ tpdm@11228000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_south_dsb"; qcom,dsb-msrs-num = <32>; @@ -6968,6 +6989,7 @@ tpdm@11470000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_pcie_rscc"; qcom,cmb-element-bits = <32>; qcom,cmb-msrs-num = <32>; @@ -7011,6 +7033,7 @@ tpdm@11c03000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_4"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7189,6 +7212,7 @@ tpdm@11c09000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_0"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7208,6 +7232,7 @@ tpdm@11c0a000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_1"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7227,6 +7252,7 @@ tpdm@11c0b000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_2"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7246,6 +7272,7 @@ tpdm@11c0c000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao_prio_3"; qcom,cmb-element-bits = <64>; qcom,cmb-msrs-num = <32>; @@ -7265,6 +7292,7 @@ tpdm@11c0d000 { clocks = <&aoss_qmp>; clock-names = "apb_pclk"; + label = "tpdm_swao"; qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <32>; From b0b51a5f1911fd812004eb6b16d178468fece237 Mon Sep 17 00:00:00 2001 From: Ekansh Gupta Date: Mon, 29 Jun 2026 12:04:38 +0530 Subject: [PATCH 374/864] arm64: dts: qcom: talos: Add memory-region for audio PD Reserve memory region for audio PD dynamic loading and remote heap requirements. Add the required VMID list for memory ownership transfers. Reviewed-by: Konrad Dybcio Signed-off-by: Ekansh Gupta Link: https://lore.kernel.org/r/20260629-talos-remoteheap-v3-1-4e23366c9196@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 6bd1118167e9..c8d877a6b472 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -677,6 +678,14 @@ pil_gpu_mem: pil-gpu@97715000 { reg = <0x0 0x97715000 0x0 0x2000>; no-map; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x800000>; + }; }; soc: soc@0 { @@ -5254,6 +5263,9 @@ fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; #address-cells = <1>; #size-cells = <0>; From 09531bb8e0de5081fdbe215877dd7f2ec8b2f0e1 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Mon, 29 Jun 2026 14:59:03 +0800 Subject: [PATCH 375/864] arm64: dts: qcom: sc8280xp-x13s: Fix the drive-strength of mclk pin The value can be retrieve via windbg on Windows. lkd> !dd f111000 L8 ctl_reg => 0x284 in drivers/pinctrl/qcom/pinctrl-msm.c function msm_gpio_dbg_show_one() ... drive = (ctl_reg >> g->drv_bit) & 7; // (0x284 >> 6) & 7 == 2 ... seq_printf(s, " %dmA", msm_regval_to_drive(drive)); // (drive + 1) * 2 == 6; ... So the value is 6, not 16, it matches Windows now. Fixes: 21927e94caa5 ("arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor") Signed-off-by: Pengyu Luo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260629065905.15651-2-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 91ba02d28bc3..8b576d85f8e4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1565,7 +1565,7 @@ cam_rgb_default: cam-rgb-default-state { mclk-pins { pins = "gpio17"; function = "cam_mclk"; - drive-strength = <16>; + drive-strength = <6>; bias-disable; }; From a83d9707310a1193c9ed953e974bdb70707a23a6 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Mon, 29 Jun 2026 14:59:04 +0800 Subject: [PATCH 376/864] arm64: dts: qcom: sc8280xp: Add camera MCLK pinctrl Define pinctrl definitions to enable camera master clocks on sc8280xp. Suggested-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Signed-off-by: Pengyu Luo Link: https://lore.kernel.org/r/20260629065905.15651-3-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 56 ++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index f02795c8b31c..899506007d0e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5599,6 +5599,62 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 230>; wakeup-parent = <&pdc>; + cam_mclk0_default: cam-mclk0-default-state { + pins = "gpio119"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk1_default: cam-mclk1-default-state { + pins = "gpio120"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk2_default: cam-mclk2-default-state { + pins = "gpio16"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk3_default: cam-mclk3-default-state { + pins = "gpio17"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk4_default: cam-mclk4-default-state { + pins = "gpio6"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk5_default: cam-mclk5-default-state { + pins = "gpio7"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk6_default: cam-mclk6-default-state { + pins = "gpio33"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + + cam_mclk7_default: cam-mclk7-default-state { + pins = "gpio34"; + function = "cam_mclk"; + drive-strength = <6>; + bias-disable; + }; + cci0_default: cci0-default-state { cci0_i2c0_default: cci0-i2c0-default-pins { /* cci_i2c_sda0, cci_i2c_scl0 */ From 4ebc5ca0a3d4c4b89e7d0115bf2a7e33c5fbe931 Mon Sep 17 00:00:00 2001 From: Pengyu Luo Date: Mon, 29 Jun 2026 14:59:05 +0800 Subject: [PATCH 377/864] arm64: dts: qcom: sc8280xp-x13s: Use predefined MCLK pinctrl Now that the predefined MCLK pinctrl configuration is available in the sc8280xp SoC DTSI, switch the ThinkPad X13s to use it. Drop the local, duplicate MCLK pin definition from the camera pinctrl node. Signed-off-by: Pengyu Luo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260629065905.15651-4-mitltlatltl@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 8b576d85f8e4..218573a97785 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -674,8 +674,9 @@ camera@10 { reg = <0x10>; reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&cam_rgb_default>, <&cam_mclk3_default>; pinctrl-names = "default"; - pinctrl-0 = <&cam_rgb_default>; leds = <&privacy_led>; led-names = "privacy"; @@ -1562,13 +1563,6 @@ cam_indicator_en: cam-indicator-en-state { }; cam_rgb_default: cam-rgb-default-state { - mclk-pins { - pins = "gpio17"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - sc-rgb-xshut-n-pins { pins = "gpio15"; function = "gpio"; From be9222a4f92c74a50b83055e0063ab68e5760596 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 30 Jun 2026 10:22:40 +0300 Subject: [PATCH 378/864] dt-bindings: arm: qcom: Document Eliza CQS SoM and its EVK board Document the compatible strings for the Qualcomm Eliza CQS System-on-Module (SoM) and its EVK board. The SoM is populated with a CQ7790S Eliza variant, PMICs, LPDDR and eMMC. The SoM is then connected to the EVK base board, which provides a multitude of connectors for peripherals. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-1-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f2780007b795..0dd64c97e5c2 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -55,6 +55,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - const: qcom,eliza-cqs-evk + - const: qcom,eliza-cqs-som + - const: qcom,eliza + - items: - enum: - sony,karin_windy From 85a1eb421dfa3b69fc3028c48597ee3aa90a5393 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 30 Jun 2026 10:22:41 +0300 Subject: [PATCH 379/864] arm64: dts: qcom: eliza: Add Eliza CQS SoM platform The Eliza CQS (CQ7790S) System-on-Module is designed to be connected to an Eliza EVK base board. The SoM provides the SoC, PMICs, LPDDR and eMMC, while the EVK base board provides connectors for a multitude of peripherals. Add the Eliza CQS SoM DTSI so it can be included by the EVK board DTS. Describe the regulators and board clocks, enable eMMC support through SDHC1, specify the ADSP firmware and enable the ADSP remoteproc. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-2-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi | 394 ++++++++++++++++++++ 1 file changed, 394 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi new file mode 100644 index 000000000000..33f4cd282272 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include + +#include "eliza.dtsi" +#include "pm7550ba-eliza.dtsi" + +/ { + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3b>; + vdd-l2-l3-supply = <&vreg_s3b>; + vdd-l4-l5-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s2b>; + vdd-l7-supply = <&vreg_s1b>; + vdd-l8-supply = <&vreg_s1b>; + vdd-l9-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s1b>; + vdd-l12-l14-supply = <&vreg_bob>; + vdd-l13-l16-supply = <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-bob-supply = <&vph_pwr>; + + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s2b: smps2 { + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <2744000>; + regulator-initial-mode = ; + }; + + vreg_s3b: smps3 { + regulator-name = "vreg_s3b"; + regulator-min-microvolt = <375000>; + regulator-max-microvolt = <2744000>; + regulator-initial-mode = ; + }; + + vreg_s4b: smps4 { + regulator-name = "vreg_s4b"; + regulator-min-microvolt = <2156000>; + regulator-max-microvolt = <2400000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l6b: ldo6 { + regulator-name = "vreg_l6b"; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10b: ldo10 { + regulator-name = "vreg_l10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20b: ldo20 { + regulator-name = "vreg_l20b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l21b: ldo21 { + regulator-name = "vreg_l21b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l22b: ldo22 { + regulator-name = "vreg_l22b"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l23b: ldo23 { + regulator-name = "vreg_l23b"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1b>; + + qcom,pmic-id = "d"; + + vreg_l1d: ldo1 { + regulator-name = "vreg_l1d"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s2b>; + vdd-l3-supply = <&vreg_s2b>; + + qcom,pmic-id = "g"; + + vreg_l1g: ldo1 { + regulator-name = "vreg_l1g"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l3g: ldo3 { + regulator-name = "vreg_l3g"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + }; + + regulators-3 { + compatible = "qcom,pmr735d-rpmh-regulators"; + + vdd-l1-l2-l5-supply = <&vreg_s3b>; + vdd-l3-l4-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s1b>; + vdd-l7-supply = <&vreg_s3b>; + + qcom,pmic-id = "k"; + + vreg_l1k: ldo1 { + regulator-name = "vreg_l1k"; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2k: ldo2 { + regulator-name = "vreg_l2k"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <969000>; + regulator-initial-mode = ; + }; + + vreg_l3k: ldo3 { + regulator-name = "vreg_l3k"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + }; + + vreg_l4k: ldo4 { + regulator-name = "vreg_l4k"; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l5k: ldo5 { + regulator-name = "vreg_l5k"; + regulator-min-microvolt = <866000>; + regulator-max-microvolt = <931000>; + regulator-initial-mode = ; + }; + + vreg_l6k: ldo6 { + regulator-name = "vreg_l6k"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l7k: ldo7 { + regulator-name = "vreg_l7k"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + }; + }; +}; + +&remoteproc_adsp { + firmware-name = "qcom/eliza/adsp.mbn", + "qcom/eliza/adsp_dtb.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l12b>; + vqmmc-supply = <&vreg_l1d>; + pinctrl-0 = <&sdc1_default>; + pinctrl-1 = <&sdc1_sleep>; + pinctrl-names = "default", "sleep"; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <20 4>, /* NFC SPI */ + <111 2>, /* WCN UART1 */ + <118 1>; /* NFC Secure I/O */ +}; From 49902982de9bef2c6e76041ee317fdb1c38dcea6 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 30 Jun 2026 10:22:42 +0300 Subject: [PATCH 380/864] arm64: dts: qcom: eliza: Add Eliza CQS EVK board The Eliza CQS EVK board combines the CQ7790S-based (Eliza) SoM with the common Eliza EVK base board, which provides connectors for different peripherals. Add a common Eliza EVK dtsi for the base board bits that can be reused alongside other Eliza SoM variants. Then, add the final Eliza CQS EVK dts, including the CQS SoM and common EVK dtsi. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260630-eliza-dts-qcs-evk-v4-3-18cbbdba6e7e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 20 ++++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts create mode 100644 arch/arm64/boot/dts/qcom/eliza-evk.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 00a75626e303..8e5b72ab9035 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts new file mode 100644 index 000000000000..43d428a4ed2d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "eliza-cqs-som.dtsi" +#include "eliza-evk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Eliza CQS EVK"; + compatible = "qcom,eliza-cqs-evk", "qcom,eliza-cqs-som", "qcom,eliza"; +}; diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi new file mode 100644 index 000000000000..e47b24f8b827 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/ { + aliases { + serial0 = &uart13; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart13 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; From 7f98ca4bf5330bfa8e8f7de5d749af4961323279 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 30 Jun 2026 10:50:20 +0300 Subject: [PATCH 381/864] arm64: dts: qcom: eliza: Add PMIC nodes for CQS SoM and MTP Both the CQS SoM and the MTP have the following array of PMICs: PMK8550, PM7550, 2x PM8550VS, PMIV0102 and PMR735D. Since on Eliza there is already support for SPMI multi-master, it is necessary to duplicate the devicetree description for each of these PMICs, due to the SPMI bus index and address. So add a new Elize specific dtsi for each of these PMICs and include all of them in both the CQS SoM and MTP board dts. Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260630-dts-qcom-eliza-mtp-evk-add-pmics-v1-1-f4f320f7c88b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi | 5 ++ arch/arm64/boot/dts/qcom/eliza-mtp.dts | 5 ++ arch/arm64/boot/dts/qcom/pm7550-eliza.dtsi | 61 +++++++++++++ .../arm64/boot/dts/qcom/pm8550vs-d-eliza.dtsi | 63 ++++++++++++++ .../arm64/boot/dts/qcom/pm8550vs-g-eliza.dtsi | 63 ++++++++++++++ arch/arm64/boot/dts/qcom/pmk8550-eliza.dtsi | 87 +++++++++++++++++++ arch/arm64/boot/dts/qcom/pmr735d-eliza.dtsi | 63 ++++++++++++++ 7 files changed, 347 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm7550-eliza.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm8550vs-d-eliza.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pm8550vs-g-eliza.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmk8550-eliza.dtsi create mode 100644 arch/arm64/boot/dts/qcom/pmr735d-eliza.dtsi diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi index 33f4cd282272..318ae3c22351 100644 --- a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi @@ -9,6 +9,11 @@ #include "eliza.dtsi" #include "pm7550ba-eliza.dtsi" +#include "pm7550-eliza.dtsi" +#include "pm8550vs-d-eliza.dtsi" +#include "pm8550vs-g-eliza.dtsi" +#include "pmr735d-eliza.dtsi" +#include "pmk8550-eliza.dtsi" / { clocks { diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 1374afd9d14e..a7d6f9d52ef3 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -11,6 +11,11 @@ #include "eliza.dtsi" #include "pm7550ba-eliza.dtsi" +#include "pm7550-eliza.dtsi" +#include "pm8550vs-d-eliza.dtsi" +#include "pm8550vs-g-eliza.dtsi" +#include "pmr735d-eliza.dtsi" +#include "pmk8550-eliza.dtsi" / { model = "Qualcomm Technologies, Inc. Eliza MTP"; diff --git a/arch/arm64/boot/dts/qcom/pm7550-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm7550-eliza.dtsi new file mode 100644 index 000000000000..9b907f69264b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550-eliza.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pm7550-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm7550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + /* + * Current Linux driver currently only supports up to + * 125°C, should be updated to 145°C once available. + */ + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pm7550: pmic@1 { + compatible = "qcom,pm7550", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550_gpios: gpio@8800 { + compatible = "qcom,pm7550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs-d-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs-d-eliza.dtsi new file mode 100644 index 000000000000..548d2aa83962 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550vs-d-eliza.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pm8550vs-d-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550vs_d_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pm8550vs_d: pmic@3 { + compatible = "qcom,pm8550vs", "qcom,spmi-pmic"; + reg = <3 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_d_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_d_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_d_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8550vs-g-eliza.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs-g-eliza.dtsi new file mode 100644 index 000000000000..4ad2cd189a6c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8550vs-g-eliza.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pm8550vs-g-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm8550vs_g_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pm8550vs_g: pmic@6 { + compatible = "qcom,pm8550vs", "qcom,spmi-pmic"; + reg = <6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8550vs_g_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8550vs_g_gpios: gpio@8800 { + compatible = "qcom,pm8550vs-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8550vs_g_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmk8550-eliza.dtsi b/arch/arm64/boot/dts/qcom/pmk8550-eliza.dtsi new file mode 100644 index 000000000000..e0ff4ff9c469 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8550-eliza.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +/ { + reboot-mode { + compatible = "nvmem-reboot-mode"; + nvmem-cells = <&reboot_reason>; + nvmem-cell-names = "reboot-mode"; + mode-recovery = <0x01>; + mode-bootloader = <0x02>; + }; +}; + +&spmi_bus0 { + pmk8550: pmic@0 { + compatible = "qcom,pm8550", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8550_pon: pon@1300 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8550_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pmk8550_sdam_2: nvram@7100 { + compatible = "qcom,spmi-sdam"; + reg = <0x7100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x7100 0x100>; + + reboot_reason: reboot-reason@48 { + reg = <0x48 0x1>; + bits = <1 7>; + }; + }; + + pmk8550_gpios: gpio@b800 { + compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; + reg = <0xb800>; + gpio-controller; + gpio-ranges = <&pmk8550_gpios 0 0 6>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmk8550_pwm: pwm { + compatible = "qcom,pmk8550-pwm"; + + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <2>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pmr735d-eliza.dtsi b/arch/arm64/boot/dts/qcom/pmr735d-eliza.dtsi new file mode 100644 index 000000000000..1c29d8ddea65 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmr735d-eliza.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pmr735d-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmr735d_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus0 { + pmr735d: pmic@a { + compatible = "qcom,pmr735d", "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmr735d_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmr735d_gpios: gpio@8800 { + compatible = "qcom,pmr735d-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmr735d_gpios 0 0 2>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From 46956cefab5bb7bf9602d49eca8c112d9cb6362b Mon Sep 17 00:00:00 2001 From: Konstantin Shabanov Date: Mon, 29 Jun 2026 22:48:09 +0700 Subject: [PATCH 382/864] dt-bindings: vendor-prefixes: Add HONOR Add vendor prefix for Honor Device Co., Ltd. Link: https://www.honor.com/ Signed-off-by: Konstantin Shabanov Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260629154812.9066-2-mail@etehtsea.me Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..9ca2508f531f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -735,6 +735,8 @@ patternProperties: description: Honestar Technologies Co., Ltd. "^honeywell,.*": description: Honeywell + "^honor,.*": + description: Honor Device Co., Ltd. "^hoperf,.*": description: Shenzhen Hope Microelectronics Co., Ltd. "^hoperun,.*": From 2f0a5092a22ceae468289ac9511af7df2266ca13 Mon Sep 17 00:00:00 2001 From: Konstantin Shabanov Date: Mon, 29 Jun 2026 22:48:10 +0700 Subject: [PATCH 383/864] dt-bindings: arm: qcom: Add HONOR MagicBook Art 14 Document the X1E-80-100 variant of the HONOR MagicBook Art 14. Signed-off-by: Konstantin Shabanov Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260629154812.9066-3-mail@etehtsea.me Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0dd64c97e5c2..f24ba443209b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1173,6 +1173,7 @@ properties: - dell,inspiron-14-plus-7441 - dell,latitude-7455 - dell,xps13-9345 + - honor,magicbook-art-14-snapdragon - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,ideacentre-mini-01q8x10 From 21b15fa5f8f4c2515c67b53cf9641dc19cf0c94b Mon Sep 17 00:00:00 2001 From: Konstantin Shabanov Date: Mon, 29 Jun 2026 22:48:11 +0700 Subject: [PATCH 384/864] arm64: dts: qcom: Add HONOR MagicBook Art 14 device tree Introduce support for the HONOR MagicBook Art 14 laptop. This version is based on the initial work by Kirill A. Korinsky [1] and Valentin Manea [2]. Supported: - Sound (with alsa-ucm-conf config [3]) - Speakers - Headphone jack - Bluetooth - Battery - HDMI - Touchpad - Keyboard (with backlight) - Touchscreen - WiFi - USB-C ports - USB-A port - UFS - H/W accel - DP over USB-C Untested: - Camera - Fingerprint reader - Sleep/Suspend Broken: - eDP [1]: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/ [2]: https://github.com/vamanea/linux-magicbook/blob/x1e80100-magicbook-6.19/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts [3]: https://github.com/alsa-project/alsa-ucm-conf/pull/755 Signed-off-by: Konstantin Shabanov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/all/871px910m1.wl-kirill@korins.ky/ Link: https://github.com/vamanea/linux-magicbook/blob/x1e80100-magicbook-6.19/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts Link: https://github.com/alsa-project/alsa-ucm-conf/pull/755 Link: https://lore.kernel.org/r/20260629154812.9066-4-mail@etehtsea.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/x1e80100-honor-magicbook-art-14.dts | 1341 +++++++++++++++++ 2 files changed, 1343 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 8e5b72ab9035..ff5e9b41397a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -438,6 +438,8 @@ x1e80100-hp-elitebook-ultra-g1q-el2-dtbs := x1e80100-hp-elitebook-ultra-g1q.dtb dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-elitebook-ultra-g1q.dtb x1e80100-hp-elitebook-ultra-g1q-el2.dtb x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb +x1e80100-honor-magicbook-art-14-el2-dtbs := x1e80100-honor-magicbook-art-14.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-honor-magicbook-art-14.dtb x1e80100-honor-magicbook-art-14-el2.dtb x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts b/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts new file mode 100644 index 000000000000..b70c1e094bbf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-honor-magicbook-art-14.dts @@ -0,0 +1,1341 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Kirill A. Korinsky + * Copyright (c) 2025 Valentin Manea + * Copyright (c) 2026 Konstantin Shabanov + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" + +/ { + model = "HONOR MagicBook Art 14 Snapdragon"; + compatible = "honor,magicbook-art-14-snapdragon", "qcom,x1e80100"; + chassis-type = "laptop"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + hdmi-bridge { + compatible = "realtek,rtd2171"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Left-side port, closer to the screen */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side port, farther from the screen */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-HONOR-MagicBook-Art-14-Snapdragon"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550ve_8_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name = "vreg_l5b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name = "vreg_l16b_2p9"; + regulator-min-microvolt = <2912000>; + regulator-max-microvolt = <2912000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name = "vreg_l1f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name = "vreg_l2f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name = "vreg_l3f_1p0"; + regulator-min-microvolt = <1024000>; + regulator-max-microvolt = <1024000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/HONOR/MRO-XXX/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@5d { + compatible = "hid-over-i2c"; + reg = <0x5d>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd3v3-supply = <&vreg_l13b_3p0>; + vdd1v8-supply = <&vreg_l4b_1p8>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@38 { + compatible = "hid-over-i2c"; + reg = <0x38>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + + pinctrl-0 = <&ts0_default>; + pinctrl-names = "default"; + }; +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_l12b_1p2>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/HONOR/MRO-XXX/qcvss8380.mbn"; + + status = "okay"; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pm8550ve_8_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/HONOR/MRO-XXX/qcadsp8380.mbn", + "qcom/x1e80100/HONOR/MRO-XXX/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/HONOR/MRO-XXX/qccdsp8380.mbn", + "qcom/x1e80100/HONOR/MRO-XXX/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <34 2>, /* Unused */ + <44 4>; /* SPI (TPM) */ + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + ts0_default: ts0-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + drive-strength = <16>; + }; + + int-n-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + }; +}; + +&uart21 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <600000>; + vccq-supply = <&vreg_l2i_1p2>; + vccq-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1_ss0 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + +/* usb_2 is for camera, USB port on top of the screen */ +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +/* MP0 goes to the USB-A port (USB3) and FPC */ +&usb_mp { + status = "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p8>; + + status = "okay"; +}; From ef50987f031344bbf6190eba257511138ff2953f Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 12 Jun 2026 22:57:37 +0530 Subject: [PATCH 385/864] dt-bindings: arm: qcom: Document Shikra and its EVK boards Shikra is a Qualcomm IoT SoC available in a System-on-Module (SoM) form factor. The SoM integrates the Shikra SoC, PMICs, and essential passives, and is designed to be mounted on carrier boards. Three eSoM variant are introduced: - CQM: retail variant with integrated modem (PM4125 and PM8005 PMIC) - CQS: retail variant without modem (PM4125 and PM8005 PMIC) - IQS: industrial-grade variant without modem (PM8150 PMIC) Each SoM variant pairs with a common EVK carrier board provides debug UART, USB, and other peripheral interfaces. Add compatible strings for the CQ2390M, CQ2390S, IQ2390S SoM variant and its corresponding EVK boards. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-1-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/arm/qcom.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f24ba443209b..c92b8ed297e5 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -971,6 +971,24 @@ properties: - xiaomi,polaris - const: qcom,sdm845 + - items: + - enum: + - qcom,shikra-cqm-evk + - const: qcom,shikra-cqm-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-cqs-evk + - const: qcom,shikra-cqs-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-iqs-evk + - const: qcom,shikra-iqs-som + - const: qcom,shikra + - items: - enum: - qcom,sdx55-mtp From 66664b5701da0e1cd96e60b602e0d6ffab267776 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 12 Jun 2026 22:57:38 +0530 Subject: [PATCH 386/864] arm64: dts: qcom: Introduce Shikra SoC base dtsi Add initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform built around a heterogeneous CPU cluster (Cortex-A55 + Cortex-A78C) with RPM-based power and clock management. Enable support for the following peripherals: - CPU nodes - Global Clock Controller (GCC) - RPM-based clock controller (RPMCC) and power domains (RPMPD) - Interrupt controller - Top Level Mode Multiplexer (TLMM) - Debug UART - eMMC host controller - System timer and watchdog Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Monish Chunara Signed-off-by: Monish Chunara Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Co-developed-by: Vishnu Santhosh Signed-off-by: Vishnu Santhosh Co-developed-by: Xueyao An Signed-off-by: Xueyao An Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-2-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 842 +++++++++++++++++++++++++++ 1 file changed, 842 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra.dtsi diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi new file mode 100644 index 000000000000..4e5bc9e17c8e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -0,0 +1,842 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78c"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&l2_3>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <489>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + cache-size = <0x40000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu3>; + }; + }; + }; + + l3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x80000>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-shikra", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + qcom,dload-mode = <&tcsr_regs 0x13000>; + #reset-cells = <1>; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a78c { + compatible = "arm,cortex-a78-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-shikra", "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,shikra-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = ; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + #power-domain-cells = <0>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ + <12 422>, /* DWC3 ss_phy_irq */ + <58 272>, /* QUSB2_PHY dmse_hv_vddmx */ + <59 273>, /* QUSB2_PHY dpse_hv_vddmx */ + <86 183>, /* MPM wake, SPMI */ + <90 157>, /* QUSB2_PHY DM */ + <91 158>; /* QUSB2_PHY DP */ + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x1600000>; + no-map; + }; + + xblboot_mem: xblboot@85e00000 { + reg = <0x0 0x85e00000 0x0 0x100000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@85fff000 { + reg = <0x0 0x85fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + + audio_heap_mem: audio-heap@86200000 { + reg = <0x0 0x86200000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@a0000000 { + reg = <0x0 0xa0000000 0x0 0x100000>; + no-map; + }; + + qtee_mem: qtee@a1300000 { + reg = <0x0 0xa1300000 0x0 0x500000>; + no-map; + }; + + tz_apps_mem: tz-apps@a1800000 { + reg = <0x0 0xa1800000 0x0 0x2100000>; + no-map; + }; + + mpss_wlan_mem: mpss-wlan@ab000000 { + reg = <0x0 0xab000000 0x0 0x6e00000>; + no-map; + }; + + wlan_mem: wlan@b2300000 { + reg = <0x0 0xb2300000 0x0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@b2400000 { + reg = <0x0 0xb2400000 0x0 0x1900000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@b3d00000 { + reg = <0x0 0xb3d00000 0x0 0x2000>; + no-map; + }; + + video_mem: video@b3d02000 { + reg = <0x0 0xb3d02000 0x0 0x700000>; + no-map; + }; + + lmcu_mem: lmcu@b4402000 { + reg = <0x0 0xb4402000 0x0 0x300000>; + no-map; + }; + + lmcu_dtb_mem: lmcu-dtb@b4702000 { + reg = <0x0 0xb4702000 0x0 0x40000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + tcsr_mutex: syscon@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs: syscon@3c0000 { + compatible = "qcom,shikra-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x0 0x00500000 0x0 0x700000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 165>; + wakeup-parent = <&mpm>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se0"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <6>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <6>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; + }; + + mem_noc: interconnect@d00000 { + compatible = "qcom,shikra-mem-noc-core"; + reg = <0x0 0x00d00000 0x0 0x43080>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; + clock-names = "gpu_axi"; + #interconnect-cells = <2>; + }; + + llcc: system-cache-controller@e00000 { + compatible = "qcom,shikra-llcc"; + reg = <0x0 0x00e00000 0x0 0x80000>, + <0x0 0x00f00000 0x0 0x80000>, + <0x0 0x01000000 0x0 0x80000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc_broadcast_base"; + interrupts = ; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,shikra-gcc"; + reg = <0x0 0x01400000 0x0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + system_noc: interconnect@1880000 { + compatible = "qcom,shikra-sys-noc"; + reg = <0x0 0x01880000 0x0 0x6a080>; + clocks = <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, + <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, + <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; + clock-names = "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + #interconnect-cells = <2>; + + clk_virt: interconnect-clk { + compatible = "qcom,shikra-clk-virt"; + #interconnect-cells = <2>; + }; + + mc_virt: interconnect-mc { + compatible = "qcom,shikra-mc-virt"; + #interconnect-cells = <2>; + }; + + mmrt_virt: interconnect-mmrt { + compatible = "qcom,shikra-mmrt-virt"; + #interconnect-cells = <2>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible = "qcom,shikra-mmnrt-virt"; + #interconnect-cells = <2>; + }; + }; + + config_noc: interconnect@1900000 { + compatible = "qcom,shikra-config-noc"; + reg = <0x0 0x01900000 0x0 0x8080>; + #interconnect-cells = <2>; + }; + + qfprom: efuse@1b44000 { + compatible = "qcom,shikra-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim_1: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; + bits = <5 8>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&mpm 86 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram", "mmio-sram"; + reg = <0x0 0x045f0000 0x0 0x7000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x045f0000 0x7000>; + + apss_mpm: sram@1b8 { + reg = <0x1b8 0x48>; + }; + }; + + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x0 0x04690000 0x0 0x14000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; + + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + iommus = <&apps_smmu 0xc0 0x0>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmpd RPMPD_VDDCX>; + operating-points-v2 = <&sdhc1_opp_table>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + + bus-width = <8>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + resets = <&gcc GCC_SDCC1_BCR>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <400000 0>; + }; + }; + }; + + qupv3_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@4a80000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x04a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + sram@c11e000 { + compatible = "qcom,shikra-imem", "mmio-sram"; + reg = <0x0 0x0c11e000 0x0 0x1000>; + ranges = <0x0 0x0 0x0c11e000 0x1000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xf200000 0x0 0x10000>, + <0x0 0xf240000 0x0 0x80000>; + + interrupts = ; + + #interrupt-cells = <4>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu3>; + }; + }; + }; + + apcs_glb: mailbox@f400000 { + compatible = "qcom,shikra-apss-shared", "qcom,sdm845-apss-shared"; + reg = <0x0 0x0f400000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + watchdog@f410000 { + compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt"; + reg = <0x0 0x0f410000 0x0 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f420000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x10000000>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@f423000 { + reg = <0x0f423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; From c337a718f7286fec0ab751aa0dffa013a65d030a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 12 Jun 2026 22:57:39 +0530 Subject: [PATCH 387/864] arm64: dts: qcom: Add Shikra CQ2390M SoM platform Add device tree include for the CQ2390M variant of the Shikra System-on-Module, a compact compute module integrating the Shikra SoC and PMIC for IoT applications, designed to mount on carrier boards. - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 and PM8005 PMIC) The DTSI includes the common shikra.dtsi, adds PM4125 and PM8005 PMIC peripheral definitions specific to this variant. Since PM8005 regulators are controlled by rpmpd, so disabling the pm8005 regulators. Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-3-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 156 +++++++++++++++++++ 1 file changed, 156 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi new file mode 100644 index 000000000000..dc3861489f64 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "shikra.dtsi" +#include "pm4125.dtsi" +#include "pm8005.dtsi" + +/ { + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm4125_gpios 9 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm4125_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + +&pm4125_resin { + linux,code = ; + + status = "okay"; +}; + +&pm8005_regulators { + status = "disabled"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + + pm4125_s2: s2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm4125_l3: l3 { + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <650000>; + }; + + pm4125_l4: l4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + pm4125_l5: l5 { + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l6: l6 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + pm4125_l7: l7 { + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <664000>; + }; + + pm4125_l8: l8 { + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l9: l9 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l10: l10 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l12: l12 { + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <975000>; + }; + + pm4125_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l17: l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l18: l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + pm4125_l19: l19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + pm4125_l20: l20 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + }; + + pm4125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3056000>; + }; + + pm4125_l22: l22 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + }; + }; +}; From 1e39b7b11d8a0715a5152a78b5b5283e7a63887d Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 12 Jun 2026 22:57:40 +0530 Subject: [PATCH 388/864] arm64: dts: qcom: Add Shikra IQ2390S SoM platform Add device tree include for the IQ2390S variant of the Shikra System-on-Module, an industrial compute module integrating the Shikra SoC and PMIC for industrial IoT applications, designed to mount on carrier boards. - shikra-iqs-som.dtsi: Industrial SoM without modem (PM8150 PMIC) The DTSI includes the common shikra.dtsi and adds PM8150 PMIC regulator definitions specific to this variant. Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-4-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 170 +++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi new file mode 100644 index 000000000000..73945bf42112 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "shikra.dtsi" +#include "pm8150.dtsi" + +/ { + gpio-key { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_n>; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + +&pm8150_gpios { + vol_up_n: vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source = <0>; + }; + +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8150-regulators"; + + pm8150_s4: s4 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <2040000>; + }; + + pm8150_s5: s5 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + pm8150_s6: s6 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1352000>; + }; + + pm8150_s7: s7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm8150_s8: s8 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pm8150_l1: l1 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l2: l2 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3300000>; + }; + + pm8150_l3: l3 { + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l4: l4 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + }; + + pm8150_l5: l5 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + pm8150_l6: l6 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm8150_l7: l7 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm8150_l8: l8 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l9: l9 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm8150_l10: l10 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + pm8150_l11: l11 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm8150_l12: l12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + }; + + pm8150_l13: l13 { + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3230000>; + }; + + pm8150_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1910000>; + }; + + pm8150_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + + pm8150_l16: l16 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <3544000>; + }; + + pm8150_l17: l17 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + pm8150_l18: l18 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + }; +}; From eaac964e84ace6a65fd38e7388dd43cca581b52f Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 12 Jun 2026 22:57:41 +0530 Subject: [PATCH 389/864] arm64: dts: qcom: Add Shikra EVK boards Add device trees for the Shikra EVK platform, which combines each of Shikra SoM variant with a common carrier board. Three EVK boards are introduced: - shikra-cqm-evk.dts: pairs with CQ2390M SoM (retail, with modem) - shikra-cqs-evk.dts: pairs with CQ2390S SoM (retail, without modem) - shikra-iqs-evk.dts: pairs with IQ2390S SoM (industrial, without modem) Also add shikra-evk.dtsi, it represents the common carrier-board and daughter-card configuration shared across all Shikra EVK variants. Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Monish Chunara Signed-off-by: Monish Chunara Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Co-developed-by: Vishnu Santhosh Signed-off-by: Vishnu Santhosh Co-developed-by: Xueyao An Signed-off-by: Xueyao An Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260612-shikra-dt-v6-5-6b6cb58db477@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 3 ++ arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 40 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 40 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 14 ++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 40 +++++++++++++++++++++ 5 files changed, 137 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts create mode 100644 arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts create mode 100644 arch/arm64/boot/dts/qcom/shikra-evk.dtsi create mode 100644 arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ff5e9b41397a..33e9199511aa 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -334,6 +334,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-huawei-matebook-e-2019.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-iqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts new file mode 100644 index 000000000000..0a52ab9b7a4c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra CQM EVK"; + compatible = "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts new file mode 100644 index 000000000000..b3f19a64d7ae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra CQS EVK"; + compatible = "qcom,shikra-cqs-evk", "qcom,shikra-cqs-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi new file mode 100644 index 000000000000..6eb4184f7642 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&qupv3_0 { + firmware-name = "qcom/shikra/qupv3fw.elf"; + + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts new file mode 100644 index 000000000000..3003a47bd759 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-iqs-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra IQS EVK"; + compatible = "qcom,shikra-iqs-evk", "qcom,shikra-iqs-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8150_l17>; + vqmmc-supply = <&pm8150_s4>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; From ddecda0cddbb797714987a893c356046d3ebb4dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:39:44 +0200 Subject: [PATCH 390/864] arm64: dts: qcom: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-1-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts | 2 +- arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso | 2 +- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi | 8 ++++---- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi index e53de709e9d1..e95da761234b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -87,7 +87,7 @@ gsbi7_uart_2pins: gsbi7-uart-2pins-state { function = "gsbi7"; }; - gsbi7_uart_4pins: gsbi7_uart_4pins-state { + gsbi7_uart_4pins: gsbi7-uart-4pins-state { pins = "gpio82", "gpio83", "gpio84", "gpio85"; function = "gsbi7"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 95be1d2e214f..06c0af0aa317 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1866,7 +1866,7 @@ cci_i2c1_sleep: cci-i2c1-sleep-pins { }; }; - spi8_default: spi8_default-state { + spi8_default: spi8-default-state { mosi-pins { pins = "gpio45"; function = "blsp_spi8"; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts index 07c10c84eefa..2c0590617ac4 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts @@ -55,7 +55,7 @@ vph_pwr: vph-pwr-regulator { regulator-max-microvolt = <3700000>; }; - vreg_bob_3p3: pmx65_bob { + vreg_bob_3p3: pmx65-bob-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_bob_3p3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso index 4600d5441cce..a4c6d39cf777 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-camera.dtso @@ -14,7 +14,7 @@ #include &{/} { - vreg_cam1_1p8: vreg_cam1_1p8 { + vreg_cam1_1p8: cam1-1p8-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_cam1_1p8"; startup-delay-us = <10000>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 40f88498999b..cefb8ff00806 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -63,7 +63,7 @@ vreg_3p3: vreg-3p3-regulator { regulator-max-microvolt = <3300000>; }; - vreg_conn_1p8: vreg_conn_1p8 { + vreg_conn_1p8: vreg-conn-1p8-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_conn_1p8"; startup-delay-us = <4000>; @@ -71,7 +71,7 @@ vreg_conn_1p8: vreg_conn_1p8 { gpio = <&pmm8654au_1_gpios 4 GPIO_ACTIVE_HIGH>; }; - vreg_conn_pa: vreg_conn_pa { + vreg_conn_pa: vreg-conn-pa-regulator { compatible = "regulator-fixed"; regulator-name = "vreg_conn_pa"; startup-delay-us = <4000>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 23af6777cf53..3b0539e27b51 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1023,7 +1023,7 @@ qfprom: efuse@784000 { #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@240c { + gpu_speed_bin: gpu-speed-bin@240c { reg = <0x240c 0x1>; bits = <0 8>; }; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index acf41e869305..efe1e74fe509 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2907,7 +2907,7 @@ ws-pins { }; }; - lpi_i2s4_active: lpi_i2s4-active-state { + lpi_i2s4_active: lpi-i2s4-active-state { data0-pins { pins = "gpio17"; function = "i2s4_data"; diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi index 7d8481173171..a5458ab41629 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -47,22 +47,22 @@ framebuffer { }; reserved-memory { - adsp_pil_mem: adsp_pil_mem@55300000 { + adsp_pil_mem: adsp-pil-mem@55300000 { reg = <0x0 0x55300000 0x0 0x2200000>; no-map; }; - ipa_fw_mem: ipa_fw_mem@57500000 { + ipa_fw_mem: ipa-fw-mem@57500000 { reg = <0x0 0x57500000 0x0 0x10000>; no-map; }; - ipa_gsi_mem: ipa_gsi_mem@57510000 { + ipa_gsi_mem: ipa-gsi-mem@57510000 { reg = <0x0 0x57510000 0x0 0x5000>; no-map; }; - gpu_mem: gpu_mem@57515000 { + gpu_mem: gpu-mem@57515000 { reg = <0x0 0x57515000 0x0 0x2000>; no-map; }; From 841c620c76f213d048fb1c3fc879b92102a0eb9f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:39:45 +0200 Subject: [PATCH 391/864] arm64: dts: qcom: Use tab for indentation Correct mix of tabs+spaces into proper tab indented lines. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-2-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/apq8016-sbc-usb-host.dtso | 2 +- .../qcom/qrb2210-rb1-vision-mezzanine.dtso | 4 +- arch/arm64/boot/dts/qcom/sm8750.dtsi | 12 ++-- arch/arm64/boot/dts/qcom/talos.dtsi | 64 +++++++++---------- 4 files changed, 41 insertions(+), 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso b/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso index a82c26b7eae8..9872d5cb83bd 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-usb-host.dtso @@ -4,5 +4,5 @@ /plugin/; &usb { - dr_mode = "host"; + dr_mode = "host"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso index c314cd6dd484..f5e6021a3354 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso @@ -60,7 +60,7 @@ ov9282_ep: endpoint { link-frequencies = /bits/ 64 <400000000>; data-lanes = <1 2>; remote-endpoint = <&csiphy0_ep>; - }; - }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 7634d132f07f..c462168e3b2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2107,12 +2107,12 @@ aggre2_noc: interconnect@1700000 { }; cambistmclkcc: clock-controller@1760000 { - compatible = "qcom,sm8750-cambistmclkcc"; - reg = <0x0 0x1760000 0x0 0x6000>; - clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, - <&bi_tcxo_div2>, - <&bi_tcxo_ao_div2>, - <&sleep_clk>; + compatible = "qcom,sm8750-cambistmclkcc"; + reg = <0x0 0x1760000 0x0 0x6000>; + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MMCX>, <&rpmhpd RPMHPD_MX>; required-opps = <&rpmhpd_opp_low_svs>, diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index c8d877a6b472..bdfb70ca9740 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -51,10 +51,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_0: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -76,10 +76,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_100: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -101,10 +101,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_200: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -126,10 +126,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_300: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -151,10 +151,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_400: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -176,10 +176,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_500: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -202,10 +202,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_600: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; @@ -227,10 +227,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; l2_700: l2-cache { - compatible = "cache"; - cache-level = <2>; - cache-unified; - next-level-cache = <&l3_0>; + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; }; }; From a62a64f6d0707a6a8e36d634d9a5aaf27b3c4c94 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:39:46 +0200 Subject: [PATCH 392/864] arm64: dts: qcom: Use lowercase hex for unit addresses and values DTS coding style prefers lowercase hex. No functional change. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-3-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 4 ++-- arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index adedcc6da1da..1a278503d340 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -591,7 +591,7 @@ saw1: power-manager@2099000 { nss_common: syscon@3000000 { compatible = "syscon"; - reg = <0x03000000 0x0000FFFF>; + reg = <0x03000000 0x0000ffff>; }; usb3_0: usb@100f8800 { @@ -1241,7 +1241,7 @@ pcie@0 { qsgmii_csr: syscon@1bb00000 { compatible = "syscon"; - reg = <0x1bb00000 0x000001FF>; + reg = <0x1bb00000 0x000001ff>; }; lcc: clock-controller@28000000 { diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi index 0dd52cac0e2e..7206a33da279 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615-wp8548.dtsi @@ -15,7 +15,7 @@ / { memory@48000000 { device_type = "memory"; - reg = <0x48000000 0x7F00000>; + reg = <0x48000000 0x7f00000>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index b2dc0327dff8..9368fd6b8751 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -66,8 +66,8 @@ venus_mem: venus@97800000 { no-map; }; - cdsp_mem: cdsp-mem@97D00000 { - reg = <0 0x97D00000 0 0x800000>; + cdsp_mem: cdsp-mem@97d00000 { + reg = <0 0x97d00000 0 0x800000>; no-map; }; @@ -81,8 +81,8 @@ slpi_mem: slpi@98700000 { no-map; }; - spss_mem: spss@99B00000 { - reg = <0 0x99B00000 0 0x100000>; + spss_mem: spss@99b00000 { + reg = <0 0x99b00000 0 0x100000>; no-map; }; From f0c4a40ebf64d4dfd8c6d023c89e521992b6e145 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:39:47 +0200 Subject: [PATCH 393/864] arm64: dts: qcom: Correct whitespace around '=' Coding convention asks that equal character '=' in property assignment is preceded and followed by a space. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260706-dts-qcom-style-checker-v2-4-90c781ae0417@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/milos-fairphone-fp6.dts | 20 +++++++++---------- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts index 2fc93e64b520..bb3b67e2fd01 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -449,16 +449,16 @@ vreg_l2c: ldo2 { regulators-2 { compatible = "qcom,pmr735b-rpmh-regulators"; - vdd-l1-l2-supply= <&vreg_s3b>; - vdd-l3-supply= <&vreg_s3b>; - vdd-l4-supply= <&vreg_s1b>; - vdd-l5-supply= <&vreg_s2b>; - vdd-l6-supply= <&vreg_s2b>; - vdd-l7-l8-supply= <&vreg_s2b>; - vdd-l9-supply= <&vreg_s3b>; - vdd-l10-supply= <&vreg_s1b>; - vdd-l11-supply= <&vreg_s3b>; - vdd-l12-supply= <&vreg_s3b>; + vdd-l1-l2-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + vdd-l4-supply = <&vreg_s1b>; + vdd-l5-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s2b>; + vdd-l7-l8-supply = <&vreg_s2b>; + vdd-l9-supply = <&vreg_s3b>; + vdd-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s3b>; + vdd-l12-supply = <&vreg_s3b>; qcom,pmic-id = "f"; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index c462168e3b2d..4a48cc4771b0 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4992,7 +4992,7 @@ port@4 { reg = <4>; tpda_aoss_in4: endpoint { - remote-endpoint =<&tpdm_swao_out>; + remote-endpoint = <&tpdm_swao_out>; }; }; }; From 29019077c414391ff3662710fe7d91740d3d5613 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Jul 2026 15:29:23 +0300 Subject: [PATCH 394/864] arm64: dts: qcom: eliza: Add CPU and LLCC BWMONs Describe the CPU and LLCC bandwidth monitor nodes for Eliza, together with the corresponding OPP tables. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260708-dts-qcom-eliza-add-bwmon-v1-1-602a409f550f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 96 +++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 2b73daea3592..bea4a9351bd7 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -3616,6 +3616,102 @@ cpufreq_hw: cpufreq@17d91000 { #clock-cells = <1>; }; + pmu@24091000 { + compatible = "qcom,eliza-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x24091000 0x0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2188800>; + }; + + opp-1 { + opp-peak-kBps = <5414400>; + }; + + opp-2 { + opp-peak-kBps = <6220800>; + }; + + opp-3 { + opp-peak-kBps = <6835200>; + }; + + opp-4 { + opp-peak-kBps = <8371200>; + }; + + opp-5 { + opp-peak-kBps = <10944000>; + }; + + opp-6 { + opp-peak-kBps = <12748800>; + }; + + opp-7 { + opp-peak-kBps = <14745600>; + }; + + opp-8 { + opp-peak-kBps = <16896000>; + }; + }; + }; + + pmu@240b7400 { + compatible = "qcom,eliza-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x240b7400 0x0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <307200>; + }; + + opp-1 { + opp-peak-kBps = <5600000>; + }; + + opp-2 { + opp-peak-kBps = <8528000>; + }; + + opp-3 { + opp-peak-kBps = <11120000>; + }; + + opp-4 { + opp-peak-kBps = <14000000>; + }; + + opp-5 { + opp-peak-kBps = <14928000>; + }; + + opp-6 { + opp-peak-kBps = <17056000>; + }; + }; + }; + gem_noc: interconnect@24100000 { compatible = "qcom,eliza-gem-noc"; reg = <0x0 0x24100000 0x0 0x163080>; From e78c2cf207c1ebf4558b709308199ee21de478ac Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Thu, 9 Jul 2026 12:12:11 +0300 Subject: [PATCH 395/864] arm64: dts: qcom: eliza: Enable first QUPv3 wrapper by default Since each serial engine will be enabled as needed in each board dts, there is no point of disabling the first QUPv3 wrapper in SoC dtsi. So enable it by default. This is also now in line with the other SoCs, and also with the second QUPv3 wrapper. Fixes: 844807e1f89d ("arm64: dts: qcom: eliza: Add QUPv3, GPI DMA, SDHCI and LLCC nodes") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260709-dts-qcom-eliza-enable-qupv3-1st-v1-1-e9a6904d0dea@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index bea4a9351bd7..357e8066c176 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -1232,8 +1232,6 @@ qupv3_1: geniqup@ac0000 { #size-cells = <2>; ranges; - status = "disabled"; - i2c0: i2c@a80000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x00a80000 0x0 0x4000>; From d638dbd1ef46394ef10f7660c8781f58640d143d Mon Sep 17 00:00:00 2001 From: Ajit Singh Date: Wed, 24 Jun 2026 18:24:41 +0530 Subject: [PATCH 396/864] dt-bindings: vendor-prefixes: Add prefix for Vicharak Vicharak develops computing platforms and manufactures single-board computers, including FPGA-integrated SBCs. Add a vendor prefix for them. Link: https://vicharak.in/ Acked-by: Krzysztof Kozlowski Signed-off-by: Ajit Singh Link: https://lore.kernel.org/r/20260624125443.18729-2-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 9ca2508f531f..7b0d79ebf9bd 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1803,6 +1803,8 @@ patternProperties: description: VIA Technologies, Inc. "^vialab,.*": description: VIA Labs, Inc. + "^vicharak,.*": + description: Vicharak Computers Pvt. Ltd. "^vicor,.*": description: Vicor Corporation "^videostrong,.*": From 49c41e85a95fc85bc1fd6b69bd9ac3a88d607380 Mon Sep 17 00:00:00 2001 From: Ajit Singh Date: Wed, 24 Jun 2026 18:24:42 +0530 Subject: [PATCH 397/864] dt-bindings: arm: qcom: Add Vicharak Axon Mini The Vicharak Axon Mini is a single-board computer based on the Qualcomm QCM6490 platform. Add the top-level compatible string for this board. Acked-by: Krzysztof Kozlowski Signed-off-by: Ajit Singh Link: https://lore.kernel.org/r/20260624125443.18729-3-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c92b8ed297e5..3bfe1b750dc7 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -413,6 +413,7 @@ properties: - shift,otter - thundercomm,minipc-g1iot - thundercomm,rubikpi3 + - vicharak,axon-mini - const: qcom,qcm6490 - items: From e4bb1e8370378203ae77c02955226a96101fb240 Mon Sep 17 00:00:00 2001 From: Ajit Singh Date: Wed, 24 Jun 2026 18:24:43 +0530 Subject: [PATCH 398/864] arm64: dts: qcom: qcs6490: Add Vicharak Axon Mini Add DTS for the Vicharak Axon Mini board based on the Qualcomm QCS6490 SoC. This adds debug UART, eMMC, UFS, SDIO WLAN, USB 2.0 host, PCIe support along with regulators. The UFS ICE block is kept disabled because enabling it currently causes an SError during qcom_ice_create() on this board. UFS works without ICE. Reviewed-by: Dmitry Baryshkov Signed-off-by: Ajit Singh Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260624125443.18729-4-blfizzyy@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcs6490-vicharak-axon-mini.dts | 1014 +++++++++++++++++ 2 files changed, 1015 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 33e9199511aa..e05414290d8e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -185,6 +185,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-minipc-g1iot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-vicharak-axon-mini.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts new file mode 100644 index 000000000000..4f2e0109f49b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-vicharak-axon-mini.dts @@ -0,0 +1,1014 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026 Vicharak Computers Pvt. Ltd. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include + +#include "kodiak.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Vicharak Axon Mini"; + compatible = "vicharak,axon-mini", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&user_leds>; + pinctrl-names = "default"; + + user-led { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&tlmm 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + default-state = "on"; + panic-indicator; + retain-state-suspended; + }; + + status-led { + color = ; + function = LED_FUNCTION_INDICATOR; + gpios = <&tlmm 55 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + retain-state-suspended; + }; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + wpss_mem: wpss@84800000 { + reg = <0x0 0x84800000 0x0 0x1900000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86100000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88900000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@8a700000 { + reg = <0x0 0x8a700000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@8ae00000 { + reg = <0x0 0x8ae00000 0x0 0x500000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@8b300000 { + reg = <0x0 0x8b300000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@8b310000 { + reg = <0x0 0x8b310000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@8b31a000 { + reg = <0x0 0x8b31a000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + chg-skin-thermal { + polling-delay-passive = <0>; + + thermal-sensors = <&pm7250b_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + conn-thermal { + polling-delay-passive = <0>; + + thermal-sensors = <&pm7250b_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + quiet-thermal { + polling-delay-passive = <0>; + + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + polling-delay-passive = <0>; + + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + + vcc_5v0: regulator-vcc-5v-peri { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vph_pwr>; + + regulator-boot-on; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_5v0_usb2_0: regulator-vcc-5v0-usb2-0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_usb2_0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vcc_5v0>; + + gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&vcc5v0_usb2_0_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_pcie1_3v3: regulator-vcc-pcie1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_pcie1_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v0>; + + gpio = <&tlmm 115 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&vcc_pcie1_3v3_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_pcie0_dsi_3v3: regulator-vcc-pcie0-dsi-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_pcie0_dsi_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_5v0>; + + gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&vcc_pcie0_dsi_3v3_en>; + pinctrl-names = "default"; + + regulator-boot-on; + regulator-always-on; + }; + + wlan_pwrseq: wlan-pwrseq { + compatible = "mmc-pwrseq-simple"; + + pinctrl-0 = <&wl_enable_h>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <20000>; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name = "vreg_l7b_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2208000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1976000>; + regulator-initial-mode = ; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + + /* + * VREG_L12C_1P8 supplies the Ampak WLAN/BT module + * VDDIO and the external 32.768 kHz oscillator. + */ + regulator-always-on; + regulator-boot-on; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3300000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +&ice { + status = "disabled"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pm7250b_adc { + channel@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "charger_skin_therm"; + }; + + channel@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "conn_therm"; + }; +}; + +&pm7250b_adc_tm { + status = "okay"; + + charger-skin-therm@0 { + reg = <0>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + conn-therm@1 { + reg = <1>; + io-channels = <&pm7250b_adc ADC5_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@3 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "pmk8350_die_therm"; + }; + + channel@44 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pmk8350_xo_therm"; + }; + + channel@103 { + reg = ; + qcom,pre-scaling = <1 1>; + label = "pm7325_die_therm"; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcs6490/qupv3fw.elf"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + + status = "okay"; +}; + +&sdhc_1 { + vqmmc-supply = <&vreg_l19b_1p8>; + vmmc-supply = <&vreg_bob_3p296>; + + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + +&sdhc_2 { + vqmmc-supply = <&vreg_l2c_1p62>; + vmmc-supply = <&vreg_l6c_2p96>; + + mmc-pwrseq = <&wlan_pwrseq>; + + bus-width = <4>; + non-removable; + no-sd; + no-mmc; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <48 4>; /* NFC */ + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + user_leds: user-led-state { + pins = "gpio19", "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + vcc5v0_usb2_0_en: vcc-5v0-usb2-0-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + vcc_pcie0_dsi_3v3_en: vcc-pcie0-dsi-3v3-en-state { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + vcc_pcie1_3v3_en: vcc-pcie1-3v3-en-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wl_enable_h: wl-enable-h-state { + pins = "gpio84"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; + +&uart5 { + status = "okay"; +}; + +&ufs_mem_hc { + /delete-property/ qcom,ice; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p96>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&usb_2 { + /* Routed to an onboard USB hub for two USB-A host ports. */ + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; + +/* pinctrl */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; From db3c61fa8bc174af66429db33445c1e141552fa2 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 24 Jun 2026 20:20:31 +0530 Subject: [PATCH 399/864] arm64: dts: qcom: glymur: Add camera clock controller support Add support for camera clock controller for camera clients to be able to request for camera clocks on Glymur SoC's. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dmitry Baryshkov Reviewed-by: Vladimir Zapolskiy Signed-off-by: Jagadeesh Kona Link: https://lore.kernel.org/r/20260624-glymur_camcc-v5-3-a321df74b1a1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index de616cc2929e..c557ce942782 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include @@ -4878,6 +4879,22 @@ usb_mp: usb@a400000 { status = "disabled"; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,glymur-camcc"; + reg = <0x0 0x0ade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: display-subsystem@ae00000 { compatible = "qcom,glymur-mdss"; reg = <0x0 0x0ae00000 0x0 0x1000>; From 63b9c63716d452a71d4c5346e0dba4212b94c6a1 Mon Sep 17 00:00:00 2001 From: Gopikrishna Garmidi Date: Tue, 2 Jun 2026 02:48:20 -0700 Subject: [PATCH 400/864] arm64: dts: qcom: glymur-crd: merge duplicate &pmh0101_gpios node extensions The &pmh0101_gpios node is extended twice in glymur-crd.dtsi. The first extension defines the nvme_reg_en pinctrl state for the NVMe regulator enable GPIO (gpio14), and the second adds key_vol_up_default for the volume-up key (gpio6). Merge both pinctrl states into a single &pmh0101_gpios block to avoid the duplicate node extension. No functional change intended. Fixes: a5ad8a8e473c ("arm64: dts: qcom: Commonize Glymur CRD DTSI") Signed-off-by: Gopikrishna Garmidi Reviewed-by: Pankaj Patil Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260602-merge-duplicate-pmh0101-gpios-node-v2-1-251107b3d9fe@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 23297b0ff216..b314c6dd423c 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -836,14 +836,6 @@ &pcie6_port0 { wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; }; -&pmh0101_gpios { - nvme_reg_en: nvme-reg-en-state { - pins = "gpio14"; - function = "normal"; - bias-disable; - }; -}; - &pmh0110_f_e1_gpios { nvme_sec_reg_en: nvme-reg-en-state { pins = "gpio14"; @@ -859,6 +851,12 @@ key_vol_up_default: key-vol-up-default-state { output-disable; bias-pull-up; }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; }; &pmh0110_f_e0_gpios { From f1bdfd7167aa454f435bc1e9dac4b3a89812d77e Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 4 Feb 2026 10:22:01 +0800 Subject: [PATCH 401/864] dt-binding: document QCOM platforms for CTCU device Document the platforms that fallback to using the qcom,sa8775p-ctcu compatible for probing. Signed-off-by: Jie Gan Reviewed-by: Krzysztof Kozlowski Acked-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-1-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index e002f87361ad..f3f3feac4ce2 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -29,7 +29,11 @@ properties: oneOf: - items: - enum: + - qcom,glymur-ctcu + - qcom,kaanapali-ctcu - qcom,qcs8300-ctcu + - qcom,sm8750-ctcu + - qcom,x1e80100-ctcu - const: qcom,sa8775p-ctcu - enum: - qcom,sa8775p-ctcu From 8017f8fa34672a6e81badb944b0570f11b3ffe83 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 4 Feb 2026 10:22:02 +0800 Subject: [PATCH 402/864] arm64: dts: qcom: hamoa: enable ETR and CTCU devices Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device. The CTCU serves as the control unit for the ETR device, managing its behavior to determine how trace data is collected. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Reviewed-by: Abel Vesa Acked-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-2-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++- 1 file changed, 159 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index b672a763047a..09527dcf9576 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -6772,6 +6772,35 @@ data-pins { }; }; + ctcu@10001000 { + compatible = "qcom,x1e80100-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm@10002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x10002000 0x0 0x1000>, @@ -6988,6 +7017,122 @@ qdss_funnel_out: endpoint { }; }; + replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc_etr: tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04e0 0x0>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x0500 0x0>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@10800000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x10800000 0x0 0x1000>; @@ -7309,7 +7454,20 @@ swao_rep_in: endpoint { }; out-ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + + port@1 { + reg = <1>; + swao_rep_out1: endpoint { remote-endpoint = <&eud_in>; }; From 73d469b4f5273fc91802bad772de58bc213fe6c3 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Wed, 4 Feb 2026 10:22:03 +0800 Subject: [PATCH 403/864] arm64: dts: qcom: sm8750: enable ETR and CTCU devices Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Reviewed-by: Abel Vesa Acked-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260204-enable-ctcu-and-etr-v3-3-0bb95c590ae1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 177 +++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 4a48cc4771b0..3496f00ac4f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -4141,6 +4141,35 @@ tcsrcc: clock-controller@f204008 { #reset-cells = <1>; }; + ctcu@10001000 { + compatible = "qcom,sm8750-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm@10002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x10002000 0x0 0x1000>, @@ -4255,6 +4284,122 @@ funnel_in0_out: endpoint { }; }; + replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x04e0 0x0>; + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc_etr1: tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0500 0x0>; + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@10800000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x10800000 0x0 0x1000>; @@ -4943,6 +5088,38 @@ tmc_etf_in: endpoint { }; }; }; + + out-ports { + port { + tmc_etf_out: endpoint { + remote-endpoint = <&swao_rep_in>; + }; + }; + }; + }; + + replicator@10b06000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10b06000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + swao_rep_in: endpoint { + remote-endpoint = <&tmc_etf_out>; + }; + }; + }; + + out-ports { + port { + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + }; }; tpda@10b08000 { From 5cd325bf0f59d7cee9d7912b37f053c7e6884fd6 Mon Sep 17 00:00:00 2001 From: Esteban Urrutia Date: Mon, 22 Jun 2026 20:54:25 -0400 Subject: [PATCH 404/864] arm64: dts: qcom: sm8450: Add missing PCM_OUT port An error in dmesg shows there is a mismatch between controller and DT dout-ports. Add PCM_OUT port to fix this. Signed-off-by: Esteban Urrutia Link: https://lore.kernel.org/r/20260622-sm8450-qol-v1-4-37e2ee8df9da@proton.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7ddd0f5f539c..3797abcc1a58 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2944,20 +2944,20 @@ swr1: soundwire@3210000 { clock-names = "iface"; label = "RX"; qcom,din-ports = <0>; - qcom,dout-ports = <5>; + qcom,dout-ports = <6>; pinctrl-0 = <&rx_swr_active>; pinctrl-names = "default"; - qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; - qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; - qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; - qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; - qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; - qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; - qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00>; #address-cells = <2>; #size-cells = <0>; From cab6d9627ef4bb72c5d6ec3f216028e4271b9abe Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Mon, 6 Jul 2026 18:01:08 +0530 Subject: [PATCH 405/864] arm64: dts: qcom: Fix pm4125 vbus regulator compatible and constraints Remove pm8150b fallback compatible from pm4125_vbus and fix regulator constraints in qrb2210 DTS files to use microvolt instead of microamp. Signed-off-by: Rakesh Kota Reviewed-by: Bryan O'Donoghue Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260706-add_pm4125-vbus-reg-v3-4-999d78a87b81@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm4125.dtsi | 2 +- arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts | 4 ++-- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm4125.dtsi b/arch/arm64/boot/dts/qcom/pm4125.dtsi index 542e8fe030da..3dc8d667d091 100644 --- a/arch/arm64/boot/dts/qcom/pm4125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm4125.dtsi @@ -37,7 +37,7 @@ pm4125_resin: resin { }; pm4125_vbus: usb-vbus-regulator@1100 { - compatible = "qcom,pm4125-vbus-reg", "qcom,pm8150b-vbus-reg"; + compatible = "qcom,pm4125-vbus-reg"; reg = <0x1100>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts index bf088fa9807f..c472e13fceca 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts @@ -235,8 +235,8 @@ &mdss_dsi0_phy { }; &pm4125_vbus { - regulator-min-microamp = <500000>; - regulator-max-microamp = <500000>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 4ace2d6c06ce..bf6fb12ad990 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -433,8 +433,8 @@ pm4125_ss_in: endpoint { }; &pm4125_vbus { - regulator-min-microamp = <500000>; - regulator-max-microamp = <500000>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; status = "okay"; }; From 5e92312a1d7542be9a0e588467bfbb2ca123eaac Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Thu, 21 May 2026 11:55:58 +0400 Subject: [PATCH 406/864] arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz. The CMN PLL driver did not account for the ref clock divider which is 2 for IPQ5018. Therefore, the computed rate was twice the actual output. With the driver now accounting for the CMN PLL reference clock divider (commit: 88c543fff756), set the correct reference clock rate. Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node") Signed-off-by: George Moussalem Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260521-ipq5018-cmn-pll-rate-fix-v2-1-04b28a92e0f2@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index edff89257468..c7a1fa5c9774 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -256,7 +256,7 @@ cmn_pll: clock-controller@9b000 { "sys"; #clock-cells = <1>; assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>; - assigned-clock-rates-u64 = /bits/ 64 <9600000000>; + assigned-clock-rates-u64 = /bits/ 64 <4800000000>; }; qfprom: qfprom@a0000 { From 26673879ee24b497f39afe4748e6a8bb7dfdd999 Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Wed, 10 Jun 2026 14:38:57 +0300 Subject: [PATCH 407/864] dt-bindings: arm: qcom: Add Sony Xperia M2 Document the Sony Xperia M2, which is a smartphone based on the Qualcomm MSM8926 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Erikas Bitovtas Link: https://lore.kernel.org/r/20260610-yukon-eagle-v4-1-763d5698bd2c@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 3bfe1b750dc7..0b4c17419d88 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -204,6 +204,7 @@ properties: - microsoft,tesla - motorola,peregrine - samsung,matisselte + - sony,eagle - const: qcom,msm8926 - const: qcom,msm8226 From 742dc058588bf1233647dcd95738c0afc621435d Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 8 Jun 2026 09:09:18 +0400 Subject: [PATCH 408/864] arm64: qcom: ipq5018: Add GEPHY RX and TX clocks Add RX and TX clocks for the IPQ5018 GEPHY to enable the datapath. Fixes: f5f2b835e316 ("arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus") Reviewed-by: Dmitry Baryshkov Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20260608-ipq5018-gephy-clocks-v4-3-fb2ccd56894b@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index c7a1fa5c9774..b5bfd5dcabad 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -229,6 +229,9 @@ ge_phy: ethernet-phy@7 { compatible = "ethernet-phy-id004d.d0c0"; reg = <7>; + clocks = <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + clock-names = "rx", "tx"; resets = <&gcc GCC_GEPHY_MISC_ARES>; }; }; From d5c8efda722eb1f67cfe299b71f13dab93746934 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Jun 2026 19:22:23 +0300 Subject: [PATCH 409/864] arm64: dts: qcom: sm8250: sort out Iris power domains On SM8250 Iris core requires two power rails to function, MX (for PLLs) and MMCX (for everything else). The commit fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") added only MX power rail, but omitted MMCX voltage levels. Add MMCX domain to the Iris device node. Fixes: fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") Reported-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Link: https://lore.kernel.org/r/20260604-iris-venus-fix-sm8250-v7-1-7bd2f0e5bae8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index afdd3378f0ab..e2af5cff4ff1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4335,8 +4335,12 @@ venus: video-codec@aa00000 { interrupts = ; power-domains = <&videocc MVS0C_GDSC>, <&videocc MVS0_GDSC>, - <&rpmhpd RPMHPD_MX>; - power-domain-names = "venus", "vcodec0", "mx"; + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mx", + "mmcx"; operating-points-v2 = <&venus_opp_table>; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, @@ -4362,22 +4366,26 @@ venus_opp_table: opp-table { opp-720000000 { opp-hz = /bits/ 64 <720000000>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; }; opp-1014000000 { opp-hz = /bits/ 64 <1014000000>; - required-opps = <&rpmhpd_opp_svs>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; }; opp-1098000000 { opp-hz = /bits/ 64 <1098000000>; - required-opps = <&rpmhpd_opp_svs_l1>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; }; opp-1332000000 { opp-hz = /bits/ 64 <1332000000>; - required-opps = <&rpmhpd_opp_nom>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; }; }; }; From 68ea007df9293fcb29d38219d73094bbf4b59673 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 4 Jun 2026 19:22:24 +0300 Subject: [PATCH 410/864] arm64: dts: qcom: sm8250: correct frequencies in the Iris OPP table The OPP table for the Iris core is wrong, it copies the VDD table from the downstream kernel, but that table is written for the video_cc_mvs0_clk_src, while the upstream uses video_cc_mvs0_clk for OPP rate setting (which is clk_src divided by 3). Specify correct frequencies in the OPP table. Fixes: fa245b3f06cd ("arm64: dts: qcom: sm8250: Add venus DT node") Reported-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov Reviewed-by: Vishnu Reddy Link: https://lore.kernel.org/r/20260604-iris-venus-fix-sm8250-v7-2-7bd2f0e5bae8@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e2af5cff4ff1..f11da2ca4181 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4364,26 +4364,26 @@ venus: video-codec@aa00000 { venus_opp_table: opp-table { compatible = "operating-points-v2"; - opp-720000000 { - opp-hz = /bits/ 64 <720000000>; + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_low_svs>; }; - opp-1014000000 { - opp-hz = /bits/ 64 <1014000000>; + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; required-opps = <&rpmhpd_opp_svs>, <&rpmhpd_opp_svs>; }; - opp-1098000000 { - opp-hz = /bits/ 64 <1098000000>; + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_svs_l1>; }; - opp-1332000000 { - opp-hz = /bits/ 64 <1332000000>; + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; required-opps = <&rpmhpd_opp_svs_l1>, <&rpmhpd_opp_nom>; }; From 06c8fc3e132ce8659bc9f0877b5c6daaf41aadbd Mon Sep 17 00:00:00 2001 From: Michael Scott Date: Wed, 20 May 2026 18:09:34 -0700 Subject: [PATCH 411/864] arm64: dts: qcom: x1-dell-thena: mark l12b and l15b always-on The l12b and l15b supplies are used by components that are not (fully) described (and some never will be) and must never be disabled. Mark the regulators as always-on to prevent them from being disabled, for example, when consumers probe defer or suspend. Note that these supplies currently have no consumers described in mainline for dell-thena beyond the audio codec (vdd-buck/vdd-rxtx/ vdd-io on wcd938x), which can release them when the codec goes idle. The board-level gpio-fixed regulators that feed the Type-C retimer's VDDIO and other rails are not described with a vin-supply link, so the kernel cannot keep their parent LDOs alive on its own. This mirrors the same change Johan Hovold applied to every other X1E80100 board in a March 2025 series; commit 63169c07d740 ("arm64: dts: qcom: x1e80100-dell-xps13-9345: mark l12b and l15b always-on") is representative. The dell-thena board file was introduced four months later and did not inherit that change; this patch closes the gap. Fixes: e7733b42111c ("arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455") Cc: stable@vger.kernel.org Signed-off-by: Michael Scott Reviewed-by: Konrad Dybcio Acked-by: Val Packett Link: https://lore.kernel.org/r/20260521010935.1333494-4-mike.scott@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index db291730130c..d6de4da02dcd 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -589,6 +589,7 @@ vreg_l12b_1p2: ldo12 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-always-on; }; vreg_l13b_3p0: ldo13 { @@ -610,6 +611,7 @@ vreg_l15b_1p8: ldo15 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; }; }; From f2a11bf61bb28f7c1aba4e5c986d56e0e6fade8f Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 11 Jun 2026 16:05:26 +0200 Subject: [PATCH 412/864] arm64: dts: qcom: monaco-arduino-monza: add ina232 power sensor The Arduino Monza board has a TI INA232 current/power monitor connected on I2C12 at address 0x40. It is used to measure the board supply current through a 2 milliohms shunt resistor. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260611-monza-ina232-v2-3-e4375ce652d0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index 7d75a5466950..d1346ca5dd4e 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -366,6 +366,12 @@ adv7535_out: endpoint { }; }; }; + + power-sensor@40 { + compatible = "ti,ina232"; + reg = <0x40>; + shunt-resistor = <2000>; + }; }; &mdss { From c3eceb0627605564f102dc0f5ca4a6060ca57fd4 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 10 Jul 2026 11:53:57 +0200 Subject: [PATCH 413/864] arm64: dts: qcom: milos: Add reset for sdhc_2 Add the missing reset (BCR) for sdhc_2. Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260710-milos-sdhc2-reset-v1-1-c7a155a517ba@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index 435d878246fa..e91c0cf5e093 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1769,6 +1769,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, iommus = <&apps_smmu 0x540 0>; + resets = <&gcc GCC_SDCC2_BCR>; + bus-width = <4>; qcom,dll-config = <0x0007442c>; From ed80cd88c5ad7909cc2fc9c3cdd1496ebaaed36d Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Jul 2026 01:14:23 -0700 Subject: [PATCH 414/864] arm64: dts: qcom: kaanapali: Add SoCCP for Kaanapali SoC Add remoteproc PAS loader for SoCCP with its SMP2P. On Kaanapali, it is brought up by bootloader. Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260709-knp-soccp-dt-v2-1-6e2bfca96088@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 70 +++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 0518488f358b..ec5330297c7e 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -512,6 +512,32 @@ smp2p_cdsp_in: slave-kernel { }; }; + smp2p-soccp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <617>, <616>; + qcom,local-pid = <0>; + qcom,remote-pid = <19>; + + soccp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + soccp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -1521,6 +1547,50 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + remoteproc_soccp: remoteproc@d00000 { + compatible = "qcom,kaanapali-soccp-pas"; + reg = <0x0 0x00d00000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&soccp_mem>, + <&soccp_dtb_mem>; + + qcom,smem-states = <&soccp_smp2p_out 0>, + <&soccp_smp2p_out 8>; + qcom,smem-state-names = "stop", + "ping"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <19>; + label = "soccp"; + }; + }; + rng: rng@10c3000 { compatible = "qcom,kaanapali-trng", "qcom,trng"; reg = <0x0 0x010c3000 0x0 0x1000>; From 7d8b8b55f4271e6d2ae3fbccbe2ea0b3615ff79f Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Jul 2026 01:14:24 -0700 Subject: [PATCH 415/864] arm64: dts: qcom: kaanapali-qrd: Add SoCCP node Add SoCCP node on Kaanapali QRD board. Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260709-knp-soccp-dt-v2-2-6e2bfca96088@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 55d02219ef4e..8ac1c664a7fd 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -786,6 +786,11 @@ &remoteproc_cdsp { status = "okay"; }; +&remoteproc_soccp { + firmware-name = "qcom/kaanapali/soccp.mbn", + "qcom/kaanapali/soccp_dtb.mbn"; +}; + &tlmm { gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ <74 1>, /* eSE */ From 70cd0b807ded233d206e2b95011578a2ed44542c Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Thu, 9 Jul 2026 01:14:25 -0700 Subject: [PATCH 416/864] arm64: dts: qcom: kaanapali-mtp: Add SoCCP node Add SoCCP node on Kaanapali MTP board. Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260709-knp-soccp-dt-v2-3-6e2bfca96088@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index f9b5b5718b90..b8d70623dc10 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -1076,6 +1076,11 @@ &remoteproc_cdsp { status = "okay"; }; +&remoteproc_soccp { + firmware-name = "qcom/kaanapali/soccp.mbn", + "qcom/kaanapali/soccp_dtb.mbn"; +}; + &sdhc_2 { cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; From e9f00c3cf7fd1840690692a27994fd2db4ce140d Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 7 Jul 2026 10:37:17 +0530 Subject: [PATCH 417/864] arm64: dts: qcom: kaanapali-mtp: Add PMIC Glink node Add PMIC Glink node on Kaanapali MTP Platform and add remote-endpoint linkages to DWC3 controller and QMP phy respectively. Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20260707-kaanapali-pmic-glink-v1-1-3f7d476672d9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 53 +++++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index b8d70623dc10..7ccff3d03b78 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -163,6 +163,49 @@ platform { }; }; + pmic-glink { + compatible = "qcom,kaanapali-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + }; + }; + }; + wcd939x: audio-codec { compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec"; @@ -1333,8 +1376,6 @@ &ufs_mem_phy { }; &usb { - dr_mode = "peripheral"; - status = "okay"; }; @@ -1353,3 +1394,11 @@ &usb_dp_qmpphy { status = "okay"; }; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; From bda7c136a03154f984edf2a5fc63f2a7d91c43e0 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 7 Jul 2026 10:37:18 +0530 Subject: [PATCH 418/864] arm64: dts: qcom: kaanapali-qrd: Add PMIC Glink node Add PMIC Glink node on Kaanapali QRD Platform and add remote-endpoint linkages to DWC3 controller and QMP phy respectively. Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/20260707-kaanapali-pmic-glink-v1-2-3f7d476672d9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 53 +++++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 8ac1c664a7fd..6efbe45605a0 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -80,6 +80,49 @@ key-volume-up { wakeup-source; }; }; + + pmic-glink { + compatible = "qcom,kaanapali-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + }; + }; + }; + }; + }; }; &apps_rsc { @@ -828,8 +871,6 @@ &ufs_mem_phy { }; &usb { - dr_mode = "peripheral"; - status = "okay"; }; @@ -848,3 +889,11 @@ &usb_dp_qmpphy { status = "okay"; }; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; From b8d47a9d22d22631c66877a686404ce4ae53dfbb Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 8 May 2026 13:57:28 +0530 Subject: [PATCH 419/864] arm64: dts: qcom: kaanapali: Switch SCMI perf protocol to use power-domain-cells The SCMI protocol@13 (Performance Domain Management) node was using performance/power domain, not a clock. This was using the older mechanism for passing the SCMI performance domain index to scmi-cpufreq, which predates the #power-domain-cells support added in commit 92b2028b00ff ("cpufreq: scmi: Add support to parse domain-id using #power-domain-cells"). Switch to #power-domain-cells to match all other Qualcomm platforms (sm8750, glymur, hamoa) and align with the semantically correct representation. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260508082729.37674-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 44 ++++++++++--------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index ec5330297c7e..74699bc3eadb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -45,9 +45,8 @@ cpu0: cpu@0 { reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd0>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd0>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; l2_0: l2-cache { @@ -63,9 +62,8 @@ cpu1: cpu@100 { reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd1>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd1>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -75,9 +73,8 @@ cpu2: cpu@200 { reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd2>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd2>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -87,9 +84,8 @@ cpu3: cpu@300 { reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd3>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd3>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -99,9 +95,8 @@ cpu4: cpu@400 { reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd4>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd4>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -111,9 +106,8 @@ cpu5: cpu@500 { reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd5>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 0>; + power-domains = <&cpu_pd5>, <&scmi_perf 0>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -123,9 +117,8 @@ cpu6: cpu@10000 { reg = <0x0 0x10000>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd6>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 1>; + power-domains = <&cpu_pd6>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; l2_1: l2-cache { @@ -141,9 +134,8 @@ cpu7: cpu@10100 { reg = <0x0 0x10100>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd7>; - power-domain-names = "psci"; - clocks = <&pdp_scmi_perf 1>; + power-domains = <&cpu_pd7>, <&scmi_perf 1>; + power-domain-names = "psci", "perf"; #cooling-cells = <2>; }; @@ -243,9 +235,9 @@ scmi: scmi { #address-cells = <1>; #size-cells = <0>; - pdp_scmi_perf: protocol@13 { + scmi_perf: protocol@13 { reg = <0x13>; - #clock-cells = <1>; + #power-domain-cells = <1>; }; }; }; From ff24f055eb3e1f617e5790bf07c4c71aeef10b0d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 17 Jun 2026 20:46:02 +0530 Subject: [PATCH 420/864] dt-bindings: arm: qcom: Document Hawi SoC and its reference boards Add Hawi SoC and its reference boards to the Qualcomm binding. Signed-off-by: Mukesh Ojha Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260617151602.2018579-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 0b4c17419d88..f8c37096df46 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -163,6 +163,11 @@ properties: - qcom,ipq9650-rdp488 - const: qcom,ipq9650 + - items: + - enum: + - qcom,hawi-mtp + - const: qcom,hawi + - items: - enum: - qcom,kaanapali-mtp From 0ed8261e0ebdac5f1f08dcbfc209efe36937ed2d Mon Sep 17 00:00:00 2001 From: Esteban Urrutia Date: Sat, 11 Jul 2026 23:12:27 -0400 Subject: [PATCH 421/864] arm64: dts: qcom: sm8450: Remove unneeded reserved memory nodes These nodes are not present on downstream device trees and only take memory away from the AP. No crashes occur without these nodes, so remove them. Reviewed-by: Dmitry Baryshkov Signed-off-by: Esteban Urrutia Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260711-sm8450-qol-dts-v2-1-5eb2e86468c5@proton.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 3797abcc1a58..7a2fb96bd2d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -752,11 +752,6 @@ oem_vm_mem: memory@bb000000 { no-map; }; - mte_mem: memory@c0000000 { - reg = <0x0 0xc0000000 0x0 0x20000000>; - no-map; - }; - qheebsp_reserved_mem: memory@e0000000 { reg = <0x0 0xe0000000 0x0 0x600000>; no-map; @@ -806,16 +801,6 @@ qtee_mem: memory@e9b00000 { reg = <0x0 0xe9b00000 0x0 0x500000>; no-map; }; - - trusted_apps_mem: memory@ea000000 { - reg = <0x0 0xea000000 0x0 0x3900000>; - no-map; - }; - - trusted_apps_ext_mem: memory@ed900000 { - reg = <0x0 0xed900000 0x0 0x3b00000>; - no-map; - }; }; smp2p-adsp { From 8a2b4481b66c802af293e55eee07406971d5aa7b Mon Sep 17 00:00:00 2001 From: Esteban Urrutia Date: Sat, 11 Jul 2026 23:12:28 -0400 Subject: [PATCH 422/864] arm64: dts: qcom: sm8450: Add mode-switch property to qmpphy USB QMP PHY is a possible handler of altmode switching, so add this property. Signed-off-by: Esteban Urrutia Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260711-sm8450-qol-dts-v2-2-5eb2e86468c5@proton.me Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7a2fb96bd2d9..2488928656d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2654,6 +2654,7 @@ usb_1_qmpphy: phy@88e8000 { #clock-cells = <1>; #phy-cells = <1>; + mode-switch; orientation-switch; status = "disabled"; From 43899c55d79baef54652ec3310683da304706fd5 Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Mon, 13 Jul 2026 18:17:26 +0800 Subject: [PATCH 423/864] arm64: dts: qcom: purwa: Override Iris clocks and operating points The Iris block on X1P differs from SM8550/X1E in its clock configuration and requires a dedicated OPP table. The node inherited from the X1E cannot be reused directly, and the fallback compatible "qcom,sm8550-iris" cannot be applied. Override the inherited clocks, clock-names, and operating points, and replaces them with the X1P42100-specific definitions. A new OPP table is provided to support the correct performance levels on this platform. Reviewed-by: Konrad Dybcio Reviewed-by: Dikshita Agarwal Reviewed-by: Dmitry Baryshkov Signed-off-by: Wangao Wang Link: https://lore.kernel.org/r/20260713-enable_iris_on_purwa-v9-1-633d7b87f0c9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/purwa.dtsi | 50 +++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa.dtsi b/arch/arm64/boot/dts/qcom/purwa.dtsi index 25cd547caab8..e54a606c8670 100644 --- a/arch/arm64/boot/dts/qcom/purwa.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa.dtsi @@ -21,6 +21,7 @@ /delete-node/ &cpu_pd11; /delete-node/ &gpu_opp_table; /delete-node/ &gpu_speed_bin; +/delete-node/ &iris_opp_table; /delete-node/ &pcie3_phy; /delete-node/ &thermal_aoss3; /delete-node/ &thermal_cpu2_0_btm; @@ -163,6 +164,55 @@ &gpucc { compatible = "qcom,x1p42100-gpucc"; }; +&iris { + compatible = "qcom,x1p42100-iris"; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&videocc VIDEO_CC_MVS0_BSE_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "vcodec0_bse"; + + operating-points-v2 = <&iris_opp_table_x1p42100>; + + iris_opp_table_x1p42100: opp-table { + compatible = "operating-points-v2"; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000 105000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000 150000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_svs>; + }; + + opp-335000000 { + opp-hz = /bits/ 64 <335000000 167500000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-424000000 { + opp-hz = /bits/ 64 <424000000 212000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_nom>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000 250000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_turbo>; + }; + }; +}; + /* PCIe3 has half the lanes compared to X1E80100 */ &pcie3 { num-lanes = <4>; From b66ca23dd964f78eb9ed0207ed0909fd9e8c27e1 Mon Sep 17 00:00:00 2001 From: Wangao Wang Date: Mon, 13 Jul 2026 18:17:27 +0800 Subject: [PATCH 424/864] arm64: dts: qcom: purwa-iot-som: enable video Enable video nodes on the purwa-iot-som board. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dikshita Agarwal Signed-off-by: Wangao Wang Link: https://lore.kernel.org/r/20260713-enable_iris_on_purwa-v9-2-633d7b87f0c9@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index 394e65518ac5..ff8621f87505 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -389,6 +389,10 @@ &gpu_zap_shader { firmware-name = "qcom/x1p42100/gen71500_zap.mbn"; }; +&iris { + status = "okay"; +}; + &pcie3 { pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; From f61fdd70f112ec5226f7adde3c29cf7aa55c6a42 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Jul 2026 13:18:26 +0300 Subject: [PATCH 425/864] arm64: dts: qcom: eliza-mtp: Enable touchscreen The Eliza MTP uses a Goodix GT9916 touchscreen controller connected over SPI. Describe the controller, its power supply, interrupt and reset GPIOs to enable touchscreen support. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260708-dts-qcom-eliza-mtp-enable-ts-v1-1-372020a7a86b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index a7d6f9d52ef3..5abc23b9b676 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -484,6 +484,30 @@ &remoteproc_adsp { status = "okay"; }; +&spi8 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l22b>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + &tlmm { gpio-reserved-ranges = <20 4>, /* NFC SPI */ <111 2>, /* WCN UART1 */ @@ -509,6 +533,21 @@ mdp_vsync: mdp-vsync-state { drive-strength = <2>; bias-pull-down; }; + + ts_irq: ts-irq-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; }; &uart13 { From 6f0b46832eda0d142c5d2a7450cf57f3f1a30aba Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 23 May 2026 15:02:39 +0100 Subject: [PATCH 426/864] arm64: dts: realtek: Add EL2 virtual timer interrupt The ARMv8.2 based CPUs used in a number of Realtek SoCs are missing the EL2 virtual timer interrupt. Add it. Furthermore, the "kent" platform appears to assign PPI9 to both the EL2 virtual timer and the GIC Maintenance Interrupt, which can't be right. Attempt a fix by setting the former to PPI12, as PPI9 is traditionally wired to the GIC itself. Signed-off-by: Marc Zyngier Signed-off-by: Yu-Chun Lin --- arch/arm64/boot/dts/realtek/kent.dtsi | 2 +- arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi index 8d4293cd4c03..02aca12d5ba9 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -23,7 +23,7 @@ timer { , , , - ; + ; }; cpus { diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index 3a7f6e35b7f7..43b13d133c32 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -105,7 +105,8 @@ timer { interrupts = , , , - ; + , + ; }; arm_pmu: pmu { From 3c778f0c9fa36b6b9a26bd2146df24ed4e830ba4 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Thu, 5 Mar 2026 13:58:38 +0800 Subject: [PATCH 427/864] arm64: dts: realtek: Add GPIO support for RTD1625 Add the GPIO node for the Realtek RTD1625 SoC. Reviewed-by: Bartosz Golaszewski Signed-off-by: Yu-Chun Lin --- arch/arm64/boot/dts/realtek/kent.dtsi | 39 +++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi index 02aca12d5ba9..df0d5ee3b1b9 100644 --- a/arch/arm64/boot/dts/realtek/kent.dtsi +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -151,6 +151,37 @@ uart0: serial@7800 { status = "disabled"; }; + gpio: gpio@31000 { + compatible = "realtek,rtd1625-iso-gpio"; + reg = <0x31000 0x398>; + gpio-controller; + gpio-ranges = <&isom_pinctrl 0 0 2>, + <&ve4_pinctrl 2 0 6>, + <&iso_pinctrl 8 0 4>, + <&ve4_pinctrl 12 6 2>, + <&main2_pinctrl 14 0 2>, + <&ve4_pinctrl 16 8 4>, + <&main2_pinctrl 20 2 3>, + <&ve4_pinctrl 23 12 3>, + <&iso_pinctrl 26 4 2>, + <&isom_pinctrl 28 2 2>, + <&ve4_pinctrl 30 15 6>, + <&main2_pinctrl 36 5 6>, + <&ve4_pinctrl 42 21 3>, + <&iso_pinctrl 45 6 6>, + <&ve4_pinctrl 51 24 1>, + <&iso_pinctrl 52 12 1>, + <&ve4_pinctrl 53 25 11>, + <&main2_pinctrl 64 11 28>, + <&ve4_pinctrl 92 36 2>, + <&iso_pinctrl 94 13 19>, + <&iso_pinctrl 128 32 4>, + <&ve4_pinctrl 132 38 13>, + <&iso_pinctrl 145 36 19>, + <&ve4_pinctrl 164 51 2>; + #gpio-cells = <2>; + }; + iso_pinctrl: pinctrl@4e000 { compatible = "realtek,rtd1625-iso-pinctrl"; reg = <0x4e000 0x1a4>; @@ -161,6 +192,14 @@ main2_pinctrl: pinctrl@4f200 { reg = <0x4f200 0x50>; }; + iso_m_gpio: gpio@89100 { + compatible = "realtek,rtd1625-isom-gpio"; + reg = <0x89100 0x30>; + gpio-controller; + gpio-ranges = <&isom_pinctrl 0 0 4>; + #gpio-cells = <2>; + }; + isom_pinctrl: pinctrl@146200 { compatible = "realtek,rtd1625-isom-pinctrl"; reg = <0x146200 0x34>; From 0a28bd927b543195be51e3279f659c8c9c53f29c Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Mon, 6 Jul 2026 16:43:58 +0200 Subject: [PATCH 428/864] arm64: dts: ti: k3-am642-tqma64xxl: add ospi0 vcc-supply Add missing vcc-supply to ospi0 flash. Signed-off-by: Alexander Feilke Signed-off-by: Nora Schiffer Link: https://patch.msgid.link/aaec2ddf7cecb58ca0af37d4f03afec571804757.1783348781.git.nora.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi index dde19d0784e3..fe4cb49934be 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -106,6 +106,7 @@ flash@0 { spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; spi-max-frequency = <84000000>; + vcc-supply = <®_1v8>; bootph-all; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; From fbc32d0ea1d60de471eae5608cf9bc0671d16f0f Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Mon, 6 Jul 2026 16:43:59 +0200 Subject: [PATCH 429/864] arm64: dts: ti: k3-am642-tqma64xxl-mbax4xxl: add icssg1 ti,pa-stats Add missing ti,pa-stats syscon phandle. In addition to providing additional ethtool stats, this avoids a "icssg-prueth icssg1-eth: couldn't get ti,pa-stats syscon regmap" error message. Signed-off-by: Alexander Feilke [Nora Schiffer: edited commit description] Signed-off-by: Nora Schiffer Link: https://patch.msgid.link/a03189aa138f74955a03b9fe6018a17bf7e2ce8c.1783348781.git.nora.schiffer@ew.tq-group.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts index 46be6824dd16..b9e52d8bc852 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -110,6 +110,7 @@ icssg1_eth: icssg1-eth { ti,mii-g-rt = <&icssg1_mii_g_rt>; ti,mii-rt = <&icssg1_mii_rt>; ti,iep = <&icssg1_iep0>, <&icssg1_iep1>; + ti,pa-stats = <&icssg1_pa_stats>; ethernet-ports { #address-cells = <1>; From 9199488ead533541b8720d340c3887f33902e650 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:24 +0100 Subject: [PATCH 430/864] arm64: dts: ti: k3-am69-aquila: Add Toradex DSI to HDMI Adapter Add a device tree overlay for the Toradex DSI to HDMI Adapter on the Aquila AM69 DSI_1 interface. Used on Aquila Development Board (J44), where DSI_1 is exposed via a Samtec LSS-130 connector. The adapter is based on the Lontium LT8912B DSI-to-HDMI bridge. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-10-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../dts/ti/k3-am69-aquila-dsi-to-hdmi.dtso | 115 ++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-hdmi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 913f51ebee38..fccd96354464 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -191,8 +191,12 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo # Boards with J784s4 SoC +k3-am69-aquila-dev-dsi-to-hdmi-dtbs := k3-am69-aquila-dev.dtb \ + k3-am69-aquila-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-hdmi.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-hdmi.dtso new file mode 100644 index 000000000000..d8e4dd69599e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-hdmi.dtso @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to HDMI Adapter on Aquila AM69 DSI_1. + * Used on Development Board (J44), DSI_1 is exposed via a Samtec LSS-130 connector. + * + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + hdmi-connector { + compatible = "hdmi-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi_gpio>; + ddc-i2c-bus = <&i2c_dsi_1>; + /* Aquila PWM_3_DSI (AQUILA B46) */ + hpd-gpios = <&main_gpio0 33 GPIO_ACTIVE_HIGH>; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&dsi_hdmi_bridge_out>; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dsi_hdmi_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +/* Aquila PWM_3_DSI (AQUILA B46) repurposed as HDMI HPD GPIO */ +&main_ehrpwm5 { + status = "disabled"; +}; + +&i2c_dsi_0 { + #address-cells = <1>; + #size-cells = <0>; + + hdmi@48 { + compatible = "lontium,lt8912b"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_20_dsi_1>; + /* Aquila GPIO_20_DSI_1 (AQUILA B45) */ + reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_hdmi_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + + dsi_hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; From c428a42a0caea3b6c17e460ba32dedb707f264f6 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:25 +0100 Subject: [PATCH 431/864] arm64: dts: ti: k3-am69-aquila: Add DSI to LVDS adapter with 10.1" display Add a device tree overlay for the Toradex DSI to LVDS Adapter with the Toradex Capacitive Touch Display 10.1" LVDS. Used on Development Board (J44), where DSI_1 is exposed via a Samtec LSS-130 connector. The adapter is based on the Texas Instruments SN65DSI84 DSI-to-LVDS bridge and drives a LogicTechno LT170410-2WHC 10.1" WXGA LVDS panel. Touch input is provided by an Atmel MaxTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-11-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...la-dsi-to-lvds-panel-cap-touch-10inch.dtso | 142 ++++++++++++++++++ 2 files changed, 147 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index fccd96354464..9619d033301e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -197,6 +197,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb @@ -311,6 +312,9 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ k3-am68-sk-base-board-pcie1-ep.dtbo +k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ + k3-am69-aquila-dev.dtb \ + k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \ @@ -394,6 +398,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ + k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-am69-sk-pcie0-ep.dtb \ k3-j7200-evm-pcie1-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtso new file mode 100644 index 000000000000..0cb662e023d4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtso @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to LVDS Adapter on Aquila DSI_1 with Capacitive Touch Display 10.1" + * Used on Development Board (J44), DSI_1 is exposed via a Samtec LSS-130 connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter + * https://www.toradex.com/accessories/verdin-dsi-to-lvds-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_19_dsi_1>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Aquila GPIO_19_DSI_1 (AQUILA B44) */ + enable-gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; + /* Aquila PWM_3_DSI (AQUILA B46) */ + pwms = <&main_ehrpwm5 0 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-bridge { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight_pwm3>; + power-supply = <®_3v3_dsi>; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; + + reg_3v3_dsi: regulator-3v3-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_DSI"; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +&i2c_dsi_0 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_20_dsi_1>; + /* Aquila GPIO_20_DSI_1 (AQUILA B45) */ + enable-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_17_dsi_1>, <&pinctrl_gpio_18_dsi_1>; + /* Aquila GPIO_17_DSI_1 (AQUILA B42) */ + interrupt-parent = <&main_gpio0>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + /* Aquila GPIO_18_DSI_1 (AQUILA B43) */ + reset-gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + }; +}; From e1df722d2b56101ec8f54ab99f3edccce631d2ea Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:26 +0100 Subject: [PATCH 432/864] arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 10.1" DSI with adapter Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" DSI used with the Toradex DSI Display Adapter on the Aquila Development Board. On this board, DSI_1 is exposed on connector J44 through a Samtec LSS-130 connector, and the adapter converts it to an FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-12-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...la-adapter-panel-cap-touch-10inch-dsi.dtso | 155 ++++++++++++++++++ 2 files changed, 160 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 9619d033301e..c38a3831bf4b 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -193,6 +193,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo # Boards with J784s4 SoC k3-am69-aquila-dev-dsi-to-hdmi-dtbs := k3-am69-aquila-dev.dtb \ k3-am69-aquila-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb @@ -312,6 +313,9 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ k3-am68-sk-base-board-pcie1-ep.dtbo +k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi-dtbs := \ + k3-am69-aquila-dev.dtb \ + k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am69-aquila-dev.dtb \ k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -398,6 +402,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ + k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi.dtb \ k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-am69-sk-pcie0-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtso new file mode 100644 index 000000000000..a5ee6c867fb1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtso @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" on Aquila DSI_1. + * Used on Development Board (J44), DSI_1 is exposed via a Samtec LSS-130 + * connector, and requires the Toradex DSI Display Adapter to convert to + * FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Aquila PWM_3_DSI (AQUILA B46) */ + pwms = <&main_ehrpwm5 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt101hvlnwc00", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <72400000>; + de-active = <1>; + hactive = <1280>; + hback-porch = <83 83 83>; + hfront-porch = <12 72 132>; + hsync-active = <0>; + hsync-len = <1 5 40>; + pixelclk-active = <1>; + vactive = <800>; + vback-porch = <13 13 13>; + vfront-porch = <1 15 49>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +/* I2C on DSI Connector Pin #52 and #54 */ +&i2c_dsi_1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_20_dsi_1>; + /* Aquila GPIO_20_DSI_1 (AQUILA B45) */ + enable-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_17_dsi_1>, <&pinctrl_gpio_18_dsi_1>; + /* Aquila GPIO_17_DSI_1 (AQUILA B42) */ + interrupt-parent = <&main_gpio0>; + /* + * Data-ready pulse is ~200 us; either edge can be used, + * use the rising edge because the falling edge is noisy. + */ + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + /* Aquila GPIO_18_DSI_1 (AQUILA B43) */ + reset-gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + }; +}; From 8490a1d1918dbe2e571649ed0d62244367867278 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:27 +0100 Subject: [PATCH 433/864] arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 7" DSI with adapter Add a device tree overlay for the Toradex Capacitive Touch Display 7" DSI used with the Toradex DSI Display Adapter on the Aquila Development Board. On this board, DSI_1 is exposed on connector J44 through a Samtec LSS-130 connector, and the adapter converts it to an FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-13-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...ila-adapter-panel-cap-touch-7inch-dsi.dtso | 155 ++++++++++++++++++ 2 files changed, 160 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c38a3831bf4b..be2f0588cf36 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -194,6 +194,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo k3-am69-aquila-dev-dsi-to-hdmi-dtbs := k3-am69-aquila-dev.dtb \ k3-am69-aquila-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb @@ -316,6 +317,9 @@ k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi-dtbs := \ k3-am69-aquila-dev.dtb \ k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo +k3-am69-aquila-dev-adapter-panel-cap-touch-7inch-dsi-dtbs := \ + k3-am69-aquila-dev.dtb \ + k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtbo k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am69-aquila-dev.dtb \ k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -403,6 +407,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi.dtb \ + k3-am69-aquila-dev-adapter-panel-cap-touch-7inch-dsi.dtb \ k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-am69-sk-pcie0-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtso new file mode 100644 index 000000000000..36d3746c8bd0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtso @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 7" on Aquila DSI_1. + * Used on Development Board (J44), DSI_1 is exposed via a Samtec LSS-130 + * connector, and requires the Toradex DSI Display Adapter to convert to + * FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-7-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Aquila PWM_3_DSI (AQUILA B46) */ + pwms = <&main_ehrpwm5 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt70hslnwca0", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <100 100 100>; + hfront-porch = <16 160 216>; + hsync-active = <0>; + hsync-len = <1 60 140>; + pixelclk-active = <1>; + vactive = <600>; + vback-porch = <13 13 13>; + vfront-porch = <1 12 127>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +/* I2C on DSI Connector Pin #52 and #54 */ +&i2c_dsi_1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_20_dsi_1>; + /* Aquila GPIO_20_DSI_1 (AQUILA B45) */ + enable-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_17_dsi_1>, <&pinctrl_gpio_18_dsi_1>; + /* Aquila GPIO_17_DSI_1 (AQUILA B42) */ + interrupt-parent = <&main_gpio0>; + /* + * Data-ready pulse is ~200 us; either edge can be used, + * use the rising edge because the falling edge is noisy. + */ + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + /* Aquila GPIO_18_DSI_1 (AQUILA B43) */ + reset-gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + }; +}; From b1bd0652f6fef8821128dce05aac70c5066ef7eb Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:28 +0100 Subject: [PATCH 434/864] arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 10.1" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" DSI on the Aquila DSI_1 interface. Used on the Clover Board (J12), where DSI_1 is exposed via a FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. The overlay is also combined with the Aquila AM69 Clover carrier board device tree to provide a ready-to-use DTB. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-14-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...m69-aquila-panel-cap-touch-10inch-dsi.dtso | 158 ++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-10inch-dsi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index be2f0588cf36..ddc1d8897c07 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -191,15 +191,20 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo # Boards with J784s4 SoC +k3-am69-aquila-clover-panel-cap-touch-10inch-dsi-dtbs := \ + k3-am69-aquila-clover.dtb \ + k3-am69-aquila-panel-cap-touch-10inch-dsi.dtbo k3-am69-aquila-dev-dsi-to-hdmi-dtbs := k3-am69-aquila-dev.dtb \ k3-am69-aquila-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-10inch-dsi.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-10inch-dsi.dtso new file mode 100644 index 000000000000..c5d597873440 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-10inch-dsi.dtso @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" on Aquila DSI_1. + * Used on Clover Board (J12), DSI_1 is exposed via a FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-dsi + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Aquila PWM_3_DSI (AQUILA B46) */ + pwms = <&main_ehrpwm5 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt101hvlnwc00", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <72400000>; + de-active = <1>; + hactive = <1280>; + hback-porch = <83 83 83>; + hfront-porch = <12 72 132>; + hsync-active = <0>; + hsync-len = <1 5 40>; + pixelclk-active = <1>; + vactive = <800>; + vback-porch = <13 13 13>; + vfront-porch = <1 15 49>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +/* Aquila PWM_3_DSI */ +&main_ehrpwm5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1 */ +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_20_dsi_1>; + /* Aquila GPIO_20_DSI_1 (AQUILA B45) */ + enable-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_17_dsi_1>, <&pinctrl_gpio_18_dsi_1>; + /* Aquila GPIO_17_DSI_1 (AQUILA B42) */ + interrupt-parent = <&main_gpio0>; + /* + * Data-ready pulse is ~200 us; either edge can be used, + * use the rising edge because the falling edge is noisy. + */ + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + /* Aquila GPIO_18_DSI_1 (AQUILA B43) */ + reset-gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + }; +}; From 9adea5f8411d447d386315297886e323764f7c28 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:29 +0100 Subject: [PATCH 435/864] arm64: dts: ti: k3-am69-aquila: Add Toradex Capacitive Touch Display 7" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 7" DSI on the Aquila DSI_1 interface. Used on the Clover Board (J12), where DSI_1 is exposed via a FFC/FPC connector. The display includes an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. Touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-15-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...am69-aquila-panel-cap-touch-7inch-dsi.dtso | 158 ++++++++++++++++++ 2 files changed, 163 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-7inch-dsi.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index ddc1d8897c07..d474ee530bbf 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -205,6 +205,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-panel-cap-touch-10inch-dsi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb @@ -319,6 +320,9 @@ k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ k3-am68-sk-base-board-pcie1-ep.dtbo +k3-am69-aquila-clover-panel-cap-touch-7inch-dsi-dtbs := \ + k3-am69-aquila-clover.dtb \ + k3-am69-aquila-panel-cap-touch-7inch-dsi.dtbo k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi-dtbs := \ k3-am69-aquila-dev.dtb \ k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo @@ -411,6 +415,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ + k3-am69-aquila-clover-panel-cap-touch-7inch-dsi.dtb \ k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi.dtb \ k3-am69-aquila-dev-adapter-panel-cap-touch-7inch-dsi.dtb \ k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-7inch-dsi.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-7inch-dsi.dtso new file mode 100644 index 000000000000..ce8490837c76 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-panel-cap-touch-7inch-dsi.dtso @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 7" on Aquila DSI_1. + * Used on Clover Board (J12), DSI_1 is exposed via a FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-7-inch-dsi + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Aquila PWM_3_DSI (AQUILA B46) */ + pwms = <&main_ehrpwm5 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt70hslnwca0", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <100 100 100>; + hfront-porch = <16 160 216>; + hsync-active = <0>; + hsync-len = <1 60 140>; + pixelclk-active = <1>; + vactive = <600>; + vback-porch = <13 13 13>; + vfront-porch = <1 12 127>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dphy_tx0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; + + port@1 { + reg = <1>; + + dsi0_in: endpoint { + remote-endpoint = <&dpi2_out>; + }; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + + dpi2_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; +}; + +/* Aquila PWM_3_DSI */ +&main_ehrpwm5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1 */ +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_20_dsi_1>; + /* Aquila GPIO_20_DSI_1 (AQUILA B45) */ + enable-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_17_dsi_1>, <&pinctrl_gpio_18_dsi_1>; + /* Aquila GPIO_17_DSI_1 (AQUILA B42) */ + interrupt-parent = <&main_gpio0>; + /* + * Data-ready pulse is ~200 us; either edge can be used, + * use the rising edge because the falling edge is noisy. + */ + interrupts = <12 IRQ_TYPE_EDGE_RISING>; + /* Aquila GPIO_18_DSI_1 (AQUILA B43) */ + reset-gpios = <&main_gpio0 31 GPIO_ACTIVE_LOW>; + }; +}; From c43c1b16c61cba5020424acdff38d5816a1e0801 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Tue, 2 Jun 2026 12:51:30 +0100 Subject: [PATCH 436/864] arm64: dts: ti: k3-am69-aquila: Add Toradex OV5640 CSI cameras Add device tree overlays for the Toradex OV5640 CSI cameras on Aquila CSI_1 and CSI_2. Two variants are supported for each interface: the current CSI Camera Set 5MP OV5640 with a 27 MHz oscillator and the legacy CSI Module 5MP OV5640 with a 24 MHz oscillator. On the Aquila AM69 Development Board, CSI_1 is exposed on connector J70 and CSI_2 is exposed on connector J71. Link: https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam Link: https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260602115123.1324474-16-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 14 ++++ .../ti/k3-am69-aquila-csi1-ov5640-24mhz.dtso | 18 +++++ .../dts/ti/k3-am69-aquila-csi1-ov5640.dtsi | 76 +++++++++++++++++++ .../dts/ti/k3-am69-aquila-csi1-ov5640.dtso | 19 +++++ .../ti/k3-am69-aquila-csi2-ov5640-24mhz.dtso | 18 +++++ .../dts/ti/k3-am69-aquila-csi2-ov5640.dtsi | 76 +++++++++++++++++++ .../dts/ti/k3-am69-aquila-csi2-ov5640.dtso | 19 +++++ 7 files changed, 240 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640-24mhz.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640-24mhz.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index d474ee530bbf..8dfb46af79b0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -200,6 +200,10 @@ dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-clover.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-csi1-ov5640-24mhz.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-csi1-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-csi2-ov5640-24mhz.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am69-aquila-dsi-to-hdmi.dtbo @@ -329,6 +333,14 @@ k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi-dtbs := \ k3-am69-aquila-dev-adapter-panel-cap-touch-7inch-dsi-dtbs := \ k3-am69-aquila-dev.dtb \ k3-am69-aquila-adapter-panel-cap-touch-7inch-dsi.dtbo +k3-am69-aquila-dev-csi-ov5640-24mhz-dtbs := \ + k3-am69-aquila-dev.dtb \ + k3-am69-aquila-csi1-ov5640-24mhz.dtbo \ + k3-am69-aquila-csi2-ov5640-24mhz.dtbo +k3-am69-aquila-dev-csi-ov5640-dtbs := \ + k3-am69-aquila-dev.dtb \ + k3-am69-aquila-csi1-ov5640.dtbo \ + k3-am69-aquila-csi2-ov5640.dtbo k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am69-aquila-dev.dtb \ k3-am69-aquila-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -418,6 +430,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am69-aquila-clover-panel-cap-touch-7inch-dsi.dtb \ k3-am69-aquila-dev-adapter-panel-cap-touch-10inch-dsi.dtb \ k3-am69-aquila-dev-adapter-panel-cap-touch-7inch-dsi.dtb \ + k3-am69-aquila-dev-csi-ov5640-24mhz.dtb \ + k3-am69-aquila-dev-csi-ov5640.dtb \ k3-am69-aquila-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am69-sk-csi2-dual-imx219.dtb \ k3-am69-sk-pcie0-ep.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640-24mhz.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640-24mhz.dtso new file mode 100644 index 000000000000..e7d238da8bef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640-24mhz.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Module 5MP OV5640 on Aquila CSI_1. + * Used on Development Board (J70). Uses a 24 MHz oscillator. + * + * https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-am69-aquila-csi1-ov5640.dtsi" + +&clock_camera_csi_1 { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtsi b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtsi new file mode 100644 index 000000000000..668658d32111 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common device tree include for Toradex OV5640 CSI Camera on Aquila CSI_1. + * Used on Development Board (J70). + */ + +#include + +&{/} { + clock_camera_csi_1: clock-camera-csi-1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + regulator_camera_csi_1: regulator-camera-csi-1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_12_csi_1>; + /* Aquila GPIO_12_CSI_1 - Camera Connector 24 */ + gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "V_CSI_1"; + startup-delay-us = <5000>; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi0_port0_in: endpoint { + remote-endpoint = <&csi0_port0_cam_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&dphy0 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_09_csi_1>, <&pinctrl_gpio_10_csi_1>; + clocks = <&clock_camera_csi_1>; + clock-names = "xclk"; + AVDD-supply = <®ulator_camera_csi_1>; + DOVDD-supply = <®ulator_camera_csi_1>; + DVDD-supply = <®ulator_camera_csi_1>; + /* Aquila GPIO_10_CSI_1 - Camera Connector 22 */ + powerdown-gpios = <&main_gpio0 2 GPIO_ACTIVE_HIGH>; + /* Aquila GPIO_09_CSI_1 - Camera Connector 11 */ + reset-gpios = <&main_gpio0 1 GPIO_ACTIVE_LOW>; + + port { + csi0_port0_cam_out: endpoint { + remote-endpoint = <&csi0_port0_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtso new file mode 100644 index 000000000000..76807176e288 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi1-ov5640.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Set 5MP OV5640 on Aquila CSI_1. + * Used on Development Board (J70). Uses a 27 MHz oscillator. + * + * https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam + * https://www.toradex.com/accessories/csi-camera-ov5640 + */ + +/dts-v1/; +/plugin/; + +#include "k3-am69-aquila-csi1-ov5640.dtsi" + +&clock_camera_csi_1 { + clock-frequency = <27000000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640-24mhz.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640-24mhz.dtso new file mode 100644 index 000000000000..607e1c76c86d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640-24mhz.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Module 5MP OV5640 on Aquila CSI_2. + * Used on Development Board (J71). Uses a 24 MHz oscillator. + * + * https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-am69-aquila-csi2-ov5640.dtsi" + +&clock_camera_csi_2 { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtsi b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtsi new file mode 100644 index 000000000000..454ac120337c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common device tree include for Toradex OV5640 CSI Camera on Aquila CSI_2. + * Used on Development Board (J71). + */ + +#include + +&{/} { + clock_camera_csi_2: clock-camera-csi-2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + regulator_camera_csi_2: regulator-camera-csi-2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_16_csi_2>; + /* Aquila GPIO_16_CSI_2 - Camera Connector 24 */ + gpio = <&wkup_gpio0 39 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "V_CSI_2"; + startup-delay-us = <5000>; + }; +}; + +&csi1_port0 { + status = "okay"; + + csi1_port0_in: endpoint { + remote-endpoint = <&csi1_port0_cam_out>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&dphy1 { + status = "okay"; +}; + +/* Aquila I2C_5_CSI2 */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_13_csi_2>, <&pinctrl_gpio_14_csi_2>; + clocks = <&clock_camera_csi_2>; + clock-names = "xclk"; + AVDD-supply = <®ulator_camera_csi_2>; + DOVDD-supply = <®ulator_camera_csi_2>; + DVDD-supply = <®ulator_camera_csi_2>; + /* Aquila GPIO_14_CSI_2 - Camera Connector 22 */ + powerdown-gpios = <&wkup_gpio0 33 GPIO_ACTIVE_HIGH>; + /* Aquila GPIO_13_CSI_2 - Camera Connector 11 */ + reset-gpios = <&wkup_gpio0 32 GPIO_ACTIVE_LOW>; + + port { + csi1_port0_cam_out: endpoint { + remote-endpoint = <&csi1_port0_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtso new file mode 100644 index 000000000000..d3279f373d32 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-csi2-ov5640.dtso @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Set 5MP OV5640 on Aquila CSI_2. + * Used on Development Board (J71). Uses a 27 MHz oscillator. + * + * https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam + * https://www.toradex.com/accessories/csi-camera-ov5640 + */ + +/dts-v1/; +/plugin/; + +#include "k3-am69-aquila-csi2-ov5640.dtsi" + +&clock_camera_csi_2 { + clock-frequency = <27000000>; +}; From ff8398281a1863f0c2f9664149c2ae01d461455b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 12 Jul 2026 16:04:48 +0200 Subject: [PATCH 437/864] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62 Add devicetree bindings for Variscite VAR-SOM-AM62 System on Module and its carrier boards. Acked-by: Conor Dooley Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/20d42ed8808c477c79b4d45fea6fd474ee42b06d.1783864932.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 060e879bc104..eebb3523303c 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -105,6 +105,12 @@ properties: - const: tq,am625-tqma6254 - const: ti,am625 + - description: K3 AM625 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62-symphony + - const: variscite,var-som-am62 + - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards items: - enum: From 887d9e03c4879153845656df9ea12b1f74c64ae7 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 12 Jul 2026 16:04:49 +0200 Subject: [PATCH 438/864] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62 Add device tree support for the Variscite VAR-SOM-AM62 system on module. This SOM is designed to be used with various carrier boards. The module includes: - AM62x Sitara MPU processor - Up to 4GB of DDR4-3733 memory - Up to 128GB eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices - Audio codec wm8904 - Resistive touch panel interface controller - I2C, UART and SPI interfaces - Bluetooth 5.2 + WiFi single or dual band Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/ Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/0a7bdfda80309eaa207b5b369d72f4bcb16e0604.1783864932.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi | 483 +++++++++++++++++++ 1 file changed, 483 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi new file mode 100644 index 000000000000..c2daa56c35e1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi @@ -0,0 +1,483 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for Variscite VAR-SOM-AM62 + * + * Link: https://variscite.com/system-on-module-som/ti-sitara-am62x/var-som-am62/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * Copyright (C) 2026 Stefano Radaelli + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "variscite,var-som-am62", "ti,am625"; + + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + bootph-pre-ram; + }; + + mmc_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc_pwrseq>; + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: memory@9da00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_phy: regulator-3v3-phy { + compatible = "regulator-fixed"; + regulator-name = "On-module +V3.3_PHY"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_phy>; + gpios = <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "dsp_b"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + }; +}; + +&audio_refclk1 { + assigned-clock-rates = <12000000>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@4 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <4>; + bootph-all; + reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + }; +}; + +&cpsw_port1 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy0>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_refclk1>; + clock-names = "mclk"; + AVDD-supply = <®_1v8>; + CPVDD-supply = <®_1v8>; + DBVDD-supply = <®_3v3>; + DCVDD-supply = <®_1v8>; + MICVDD-supply = <®_1v8>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ + AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ + >; + }; + + pinctrl_mcasp1: main-mcasp1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ + >; + }; + + pinctrl_mdio1: main-mdio1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_INPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + pinctrl_mmc_pwrseq: pinmux-mmc-pwrseq-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (Y25) VOUT0_DATA4.GPIO0_49 */ + >; + }; + + pinctrl_mmc0: main-mmc0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + pinctrl_mmc2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT_PULLUP, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT_PULLDOWN, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT_PULLUP, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x110, PIN_INPUT_PULLUP, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x10c, PIN_INPUT_PULLUP, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x108, PIN_INPUT_PULLUP, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x11c, PIN_INPUT_PULLUP, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + pinctrl_restouch: main-restouch-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (W24) VOUT0_DATA3.GPIO0_48 */ + >; + }; + + pinctrl_rgmii1: main-rgmii1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_INPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_INPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_INPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_INPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_INPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_INPUT, 0) /* (AD19) RGMII1_TX_CTL */ + AM62X_IOPAD(0x00bc, PIN_INPUT, 7) /* (V24) VOUT0_DATA1.GPIO0_46 */ + >; + }; + + pinctrl_eth_phy: main-eth-phy-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b8, PIN_INPUT, 7) /* (U22) VOUT0_DATA0.GPIO0_45 */ + >; + }; + + pinctrl_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (A14) SPI0_CLK */ + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (A13) SPI0_CS0 */ + AM62X_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B13) SPI0_D0 */ + AM62X_IOPAD(0x01c4, PIN_INPUT, 0) /* (B14) SPI0_D1 */ + >; + }; + + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00ec, PIN_INPUT, 4) /* (AA24) VOUT0_DATA13.UART5_CTSn */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AB25) VOUT0_DATA12.UART5_RTSn */ + AM62X_IOPAD(0x00d0, PIN_INPUT, 4) /* (Y23) VOUT0_DATA6.UART5_RXD */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AA25) VOUT0_DATA7.UART5_TXD */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_wkup_clkout0: wkup-clkout0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ + >; + }; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + /* Resistive touch controller */ + ads7846: touchscreen@0 { + compatible = "ti,ads7846"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&main_gpio0>; + interrupts = <48 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&main_gpio0 48 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +/* On-module Bluetooth */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* MCASP_IIS_MODE */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + bootph-all; + disable-wp; + mmc-pwrseq = <&mmc_pwrseq>; + non-removable; + status="okay"; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2>, <&pinctrl_wkup_clkout0>; + #address-cells = <1>; + #size-cells = <0>; + assigned-clocks = <&k3_clks 157 158>; /* wkup_clkout_sel_out0 */ + assigned-clock-parents = <&k3_clks 157 164>; /* clk_32k_rc_sel_out0 */ + bus-width = <4>; + disable-wp; + non-removable; + cap-power-off-card; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&usbss1 { + ti,vbus-divider; +}; + +/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */ +&mcu_gpio0 { + status = "reserved"; +}; + +&mcu_gpio_intr { + status = "reserved"; +}; + +&wkup_rtc0 { + status = "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status = "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +#include "k3-am62-ti-ipc-firmware.dtsi" From acb4cd35dbd23c7b9f10640fb6476e2869c1721f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 12 Jul 2026 16:04:50 +0200 Subject: [PATCH 439/864] arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62 system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - OV5640 Camera support - GPIO Expander and TPM - CAN, I2C and general purpose interfaces - Capacitive touch controller Link: https://www.variscite.it/product/single-board-computers/symphony-board/ Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/42decef4f84db8fc0474675a23e157b68b3b1a1b.1783864932.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am625-var-som-symphony.dts | 555 ++++++++++++++++++ 2 files changed, 556 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 8dfb46af79b0..faa11016bcb7 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-can.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts new file mode 100644 index 000000000000..7951d7ec952b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Variscite Symphony carrier board for VAR-SOM-AM62 + * + * Link: https://www.variscite.it/product/single-board-computers/symphony-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * Copyright (C) 2026 Stefano Radaelli + * + */ + +/dts-v1/; + +#include "k3-am625-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-AM62 on Symphony-Board"; + compatible = "variscite,var-som-am62-symphony", "variscite,var-som-am62", "ti,am625"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + serial0 = &main_uart0; + serial2 = &main_uart2; + serial5 = &main_uart5; + serial6 = &main_uart6; + spi5 = &main_spi2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ov5640_fixed: clock-24000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + linux,code = ; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + }; + + button-home { + label = "Home"; + linux,code = ; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + }; + + button-menu { + label = "Menu"; + linux,code = ; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-heartbeat { + label = "Heartbeat"; + linux,default-trigger = "heartbeat"; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + }; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + vin-supply = <®_3v3>; + regulator-always-on; + }; + + reg_sdhc1_vmmc: regulator-sdhc1 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_SD"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vmmc>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "+V3.3_SD_VQMMC"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_vqmmc>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 56 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + reg_ov5640_buf_en: regulator-camera-buf-en { + compatible = "regulator-fixed"; + regulator-name = "ov5640_buf_en"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640_buf>; + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_extcon>; + label = "USB-C"; + id-gpios = <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + usb_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, + <&pinctrl_rgmii2>; + status = "okay"; + + cpts@3d000 { + /* MAP HW3_TS_PUSH to GENF1 */ + ti,pps = <2 1>; + }; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@5 { + compatible = "ethernet-phy-id0283.bc30"; + reg = <5>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + }; +}; + +&cpsw_port2 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the Symphony PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <&cpsw3g_phy1>; + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; + +&epwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm1>; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + + usb3-sel-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "usb3_sel"; + }; + + eth-som-vselect-hog { + gpio-hog; + gpios = <6 0>; + output-low; + line-name = "eth-vselect"; + }; + + eth-mdio-enable-hog { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "eth-mdio-enable"; + }; + }; + + ov5640: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&clk_ov5640_fixed>; + clock-names = "xclk"; + AVDD-supply = <®_2p8v>; + DOVDD-supply = <®_1p8v>; + DVDD-supply = <®_1p5v>; + powerdown-gpios = <&main_gpio0 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov5640>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + label = "tpm"; + reg = <0x2e>; + reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + }; + + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch_pins>; + interrupt-parent = <&main_gpio1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcan0>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_pmx0 { + pinctrl_captouch_pins: main-captouch-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_INPUT, 7) /* (C13) SPI0_CS1.GPIO1_16 */ + >; + }; + + pinctrl_epwm1: main-epwm1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_OUTPUT, 6) /* (B18) MCASP0_AXR1.EHRPWM1_A */ + >; + }; + + pinctrl_extcon: main-extcon-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + pinctrl_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + pinctrl_i2c1: main-i2c1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + pinctrl_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + pinctrl_mmc1: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + + pinctrl_ov5640: main-ov5640-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0028, PIN_OUTPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ + AM62X_IOPAD(0x0058, PIN_OUTPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ + >; + }; + + pinctrl_ov5640_buf: main-ov5640-buf-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0054, PIN_OUTPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + pinctrl_pca9534: main-pca9534-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f0, PIN_INPUT, 7) /* (A18) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + pinctrl_rgmii2: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_INPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_INPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_INPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_INPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_INPUT_PULLDOWN, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_INPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + pinctrl_sd1_vmmc: main-sd1-vmmc-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ + >; + }; + + pinctrl_sd1_vqmmc: main-sd1-vqmmc-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AA23) VOUT0_DATA11.GPIO0_56 */ + >; + }; + + pinctrl_spi2: main-spi2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ + AM62X_IOPAD(0x0194, PIN_OUTPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ + AM62X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (E19) MCASP0_AFSR.GPIO1_13 */ + >; + }; + + pinctrl_uart0: main-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD, change muxmode from 0 to 7 to deactivate Debug UART RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (R24) GPMC0_AD8.UART2_RXD */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 2) /* (R25) GPMC0_AD9.UART2_TXD */ + >; + }; + + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_INPUT, 3) /* (V25) GPMC0_WAIT1.UART6_RXD */ + AM62X_IOPAD(0x0244, PIN_OUTPUT, 1) /* (C17) MMC1_SDWP.UART6_TXD */ + >; + }; + + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; +}; + +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + ti,pindir-d0-out-d1-in; + cs-gpios = <&main_gpio1 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&sdhci1 { + /* SD Card */ + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1>; + disable-wp; + bootph-all; + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&usb0 { + usb-role-switch; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usbss0 { + status = "okay"; +}; + +&usbss1 { + status = "okay"; +}; From 4b92d84c6cd6a144a2a9171c52bbd8600412142a Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 28 Jun 2026 22:56:05 +0200 Subject: [PATCH 440/864] arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration Fix the Ethernet device tree description on the VAR-SOM-AM62P. Enable the CPSW Ethernet controller and correct the Ethernet PHY description by modelling the PHY power supply and adding the required board-specific PHY properties. Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/4d1ba0d1b9bd4957224213cf17dca93392788e03.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi index fc5a3942cde0..ca2483a04b9d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi @@ -113,6 +113,15 @@ reg_3v3_phy: regulator-3v3-phy { regulator-always-on; }; + reg_eth_phy_vdd: regulator-eth-vdd { + compatible = "regulator-fixed"; + regulator-name = "reg_eth_phy_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&codec_dai>; @@ -149,6 +158,7 @@ &audio_refclk1 { &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii1>; + status = "okay"; }; &cpsw3g_mdio { @@ -159,9 +169,9 @@ &cpsw3g_mdio { cpsw3g_phy0: ethernet-phy@4 { compatible = "ethernet-phy-id0283.bc30"; reg = <4>; - reset-gpios = <&main_gpio0 46 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <100000>; + bootph-all; + enet-phy-lane-no-swap; + vdd-supply = <®_eth_phy_vdd>; }; }; From d8c22a5005b46f1ad26cf1e5291dfc375b917564 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 28 Jun 2026 22:56:06 +0200 Subject: [PATCH 441/864] arm64: dts: ti: var-som-am62p: update audio codec configuration Update the WM8904 audio codec configuration on the VAR-SOM-AM62P. Set the audio reference clock rate to 12 MHz and add the codec DRC, GPIO and DMIC configuration required by the board. Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/76e49b33e7810b7cf6452cf827d88b5d0f04ba3b.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi index ca2483a04b9d..8a8dec80cb30 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi @@ -152,7 +152,7 @@ simple-audio-card,cpu { }; &audio_refclk1 { - assigned-clock-rates = <100000000>; + assigned-clock-rates = <12000000>; }; &cpsw3g { @@ -203,6 +203,23 @@ wm8904: audio-codec@1a { DBVDD-supply = <®_3v3>; DCVDD-supply = <®_1v8>; MICVDD-supply = <®_1v8>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; From 1362968f1566b57366851186444ec0ad57434272 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 28 Jun 2026 22:56:07 +0200 Subject: [PATCH 442/864] arm64: dts: am62p5-var-som-symphony: add touchscreen support Add support for the capacitive touchscreen on the Symphony carrier board. Describe the FT5x06 touchscreen controller, configure its interrupt, and mark it as a wakeup source. Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/eaf0479114137e4472b4adb3df82a5bcf78405a2.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-am62p5-var-som-symphony.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts index 5ba4ed56755b..5c41647ff43f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -293,6 +293,21 @@ &main_i2c1 { clock-frequency = <400000>; status = "okay"; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch_pins>; + interrupt-parent = <&main_gpio1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + rtc@68 { compatible = "dallas,ds1337"; reg = <0x68>; @@ -307,6 +322,12 @@ &main_mcan0 { }; &main_pmx0 { + pinctrl_captouch_pins: main-captouch-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_INPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */ + >; + }; + pinctrl_extcon: main-extcon-pins { pinctrl-single,pins = < AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ From a3f708261769901d3e52ccd670982aa2a4106835 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 28 Jun 2026 22:56:08 +0200 Subject: [PATCH 443/864] arm64: dts: am62p5-var-som-symphony: add TPM support Add the ST33KTPM2XI2C TPM device on the Symphony carrier board. The TPM reset signal is driven through a PCAL6408 GPIO expander, so add the corresponding GPIO expander node. Configure the RGB_SEL board signal through a GPIO hog to keep the board in the expected configuration. Signed-off-by: Stefano Radaelli Link: https://patch.msgid.link/d3ac1ce507b48f8debc8857814be00600b5a14f9.1782680023.git.stefano.r@variscite.com Signed-off-by: Vignesh Raghavendra --- .../dts/ti/k3-am62p5-var-som-symphony.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts index 5c41647ff43f..8fe8ec903d3d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -293,6 +293,28 @@ &main_i2c1 { clock-frequency = <400000>; status = "okay"; + pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + label = "tpm"; + reg = <0x2e>; + reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5206"; From 4185d10a60d617c5ba7dae4cc56498621c11cd00 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 14 Jul 2026 16:31:52 +0200 Subject: [PATCH 444/864] arm64: dts: add tqma9596la-mba95xxca This adds support for TQMa95xxLA modules, designed to be soldered on a carrier board. MBa95xxCA is a carrier reference board / starter kit design. There is a common device tree for all variants with e.g. reduced CPU core / feature count. Enable the external accessible PCIe controllers as host, add clocking and reset GPIO. While at it, add hogs for GPIO lines from the M.2 slots until M.2 connector driver is available. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx95-tqma9596la-mba95xxca.dts | 958 ++++++++++++++++++ .../boot/dts/freescale/imx95-tqma9596la.dtsi | 278 +++++ 3 files changed, 1237 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index be3c858f1eeb..9a864990d7e3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -673,6 +673,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-frdm-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-clover.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-aquila-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596la-mba95xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts new file mode 100644 index 000000000000..1d745d66997c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la-mba95xxca.dts @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "imx95-tqma9596la.dtsi" + +/ { + model = "TQ-Systems i.MX95 TQMa95xxLA on MBa95xxCA"; + compatible = "tq,imx95-tqma9596la-mba95xxca", "tq,imx95-tqma9596la", "fsl,imx95"; + chassis-type = "embedded"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + ethernet2 = &enetc_port2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &scmi_bbm; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + spi0 = &flexspi1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&tpm5 2 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + clk_eth: clk-eth { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + /* + * TODO: gate is disabled for now and GPIO are hogged + * ENETC driver switches the clock far too late for ENETC2 + SFP + */ + clk_eth_gate: clk-eth-gate { + compatible = "gpio-gate-clock"; + enable-gpios = <&expander2 0 GPIO_ACTIVE_HIGH>; + clocks = <&clk_eth>; + #clock-cells = <0>; + status = "disabled"; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-b { + label = "BUTTON_B#"; + linux,code = ; + gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + reg_v1v8_mb: regulator-v1v8-mb { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_MB"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_v3v3_mb: regulator-v3v3-mb { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_3v3a_10g: regulator-3v3a-10g { + compatible = "regulator-fixed"; + regulator-name = "3V3A_10G"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + enable-active-high; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_12v0>; + /* + * emc2305 fan driver lacks support for fan-supply, so + * alway enable it for now. + * Remove this line once support is added + */ + regulator-always-on; + }; + + reg_lvds: regulator-lvds { + compatible = "regulator-fixed"; + regulator-name = "LCD_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + /* USB NC limitations, RM 162.1.2 VBUS limitations */ + reg_vbus_usb3: regulator-vbus-usb3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "USB3_VBUS"; + gpio = <&gpio4 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + }; + + sfp_xfi: sfp-xfi { + compatible = "sff,sfp"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sfp>; + i2c-bus = <&lpi2c7>; + maximum-power-milliwatt = <2000>; + mod-def0-gpios = <&expander1 3 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + los-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-codec = <&tlv320aic3x04>; + audio-cpu = <&sai3>; + audio-routing = + "IN3_L", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HPL", + "Headphone Jack", "HPR", + "IN1_L", "Line In Jack", + "IN1_R", "Line In Jack", + "Line Out Jack", "LOL", + "Line Out Jack", "LOR"; + }; + + wifi-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <®_v3v3_mb>; + vpcie1v8-supply = <®_v1v8_mb>; + i2c-parent = <&lpi2c2>; + w-disable1-gpios = <&expander2 9 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&expander2 10 GPIO_ACTIVE_LOW>; + /* UART_WAKE is connected to SM */ + /* SDIO_WAKE is connected to SM */ + sdio-reset-gpios = <&expander3 2 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +/* No support for XFI yet */ +&enetc_port2 { + sfp = <&sfp_xfi>; + phy-mode = "10gbase-r"; + clocks = <&clk_eth>; + managed = "in-band-status"; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&lpi2c2 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + reset-gpios = <&expander1 14 GPIO_ACTIVE_LOW>; + iov-supply = <®_v3v3_mb>; + ldoin-supply = <®_v3v3_mb>; + }; + + sensor_mb: temperature-sensor@1e { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1e>; + }; + + fan_controller: fan-controller@2f { + compatible = "microchip,emc2301", "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + status = "okay"; + + fan: fan@0 { + reg = <0x0>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + fan-supply = <®_pwm_fan>; + }; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio2>; + interrupts = <28 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "X9"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom_mb: eeprom@56 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x56>; + pagesize = <16>; + vcc-supply = <®_v3v3_mb>; + }; + + pcieclk: clock-generator@68 { + compatible = "renesas,9fgv0441"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; + + /* D39 IN/OUT 3V3 */ + expander1: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + vcc-supply = <®_v3v3_mb>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + gpio-line-names = + /* 00 */ "BUTTON_B#", "CAM0_SYNC_3V3", + /* 02 */ "CAM1_SYNC_3V3", "SFP_MOD_ABS", + /* 04 */ "DIG_IN1", "DIG_IN2", + /* 06 */ "DIG_IN3", "DIG_IN4", + /* 08 */ "DIG_OUT_1_2_STATE", "DIG_OUT_3_4_STATE", + /* 10 */ "DIG_OUT_1_EN", "DIG_OUT_2_EN", + /* 12 */ "DIG_OUT_3_EN", "DIG_OUT_4_EN", + /* 14 */ "AUDIO_RST#", "12V_EN"; + }; + + /* D40 OUT 3V3 */ + expander2: gpio@75 { + compatible = "ti,tca9539"; + reg = <0x75>; + vcc-supply = <®_v3v3_mb>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + /* 00 */ "ETH10G_REFCLK_EN", "ETH10G_REFCLK_RST#", + /* 02 */ "SFP_TX_DIS", "USB3_RESET#", + /* 04 */ "USB2_RESET#", "LCD_RESET#", + /* 06 */ "LCD_BLT_EN", "LCD_PWR_EN", + /* 08 */ "M2_KEYE_PERST#", "M2_KEYE_WDISABLE1#", + /* 10 */ "M2_KEYE_WDISABLE2#", "M2_KEYB_PERST#", + /* 12 */ "M2_KEYB_WDISABLE1#", "USER_LED1", + /* 14 */ "USER_LED2", "3V3A_10G_EN"; + + eth10g-refclk-en-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ETH10G_REFCLK_EN"; + }; + + eth10g-refclk-rst-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + output-low; + line-name = "ETH10G_REFCLK_RST#"; + }; + + m2-keyb-wdisable1-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_WDISABLE1#"; + }; + }; + + /* D41 OUT 1V8 */ + expander3: gpio@76 { + compatible = "ti,tca9539"; + reg = <0x76>; + vcc-supply = <®_v1v8_mb>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + /* 00 */ "ENET1_RESET#", "ENET2_RESET#", + /* 02 */ "M2_KEYE_SDIO_RST#", "M2_KEYE_DEV_WLAN_WAKE#", + /* 04 */ "M2_KEYE_DEV_BT_WAKE", "M2_KEYB_W_DISABLE2#", + /* 06 */ "M2_KEYB_RST#", "M2_KEYB_FULL_CARD_PWR_OFF#", + /* 08 */ "M2_KEYB_DPR", "CAM0_PWR#", + /* 10 */ "CAM1_PWR#", "CAM0_RST#", + /* 12 */ "CAM1_RST#", "CAM0_TRIGGER", + /* 14 */ "CAM1_TRIGGER", "FAN_PWR_EN"; + + /* vendor defined pin 42 */ + m2-keye-dev_wlan-wake-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_LOW>; + input; + line-name = "M2_KEYE_DEV_WLAN_WAKE#"; + }; + + /* vendor defined pin 40 */ + m2-keye-dev_bt-wake-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "M2_KEYE_DEV_BT_WAKE#"; + }; + + m2-keyb-wdisable2-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_WDISABLE2#"; + }; + + m2-keyb-rst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_RST#"; + }; + + m2-keyb-full-card-pwr-off-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-low; + line-name = "M2_KEYB_FULL_CARD_PWR_OFF#"; + }; + }; +}; + +/* X4 + SFP */ +&lpi2c7 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c7>; + pinctrl-1 = <&pinctrl_lpi2c7_recovery>; + scl-gpios = <&gpio2 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* TODO: 0x19: retimer */ + + /* 0x50 / 0x51: SFP EEPROM */ +}; + +/* X4 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio5 14 GPIO_ACTIVE_LOW>, <&gpio5 13 GPIO_ACTIVE_LOW>; + /* max 30 MHz as per datasheet, without SCK loopback via pad (LPSPI_CFGR1[SAMPLE]) */ + status = "okay"; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&lpuart2 { + /* SM */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "reserved"; +}; + +&lpuart5 { + /* X16 M.2 KEY E */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart5>; + status = "okay"; +}; + +&lpuart7 { + /* X5 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; + status = "okay"; +}; + +&lpuart8 { + /* X15 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart8>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + /* IRQ pin is AON GPIO, not usable */ + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&expander3 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy1>; + reset-gpios = <&expander3 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio4>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +/* X16 M2 / E-Key mPCIe */ +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcieclk 1>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; + reset-gpios = <&expander2 8 GPIO_ACTIVE_LOW>; + /* Not supported on REV.0100 */ + /* supports-clkreq; */ + status = "okay"; +}; + +/* X17 M2 / B-Key PCIe */ +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>, + <&pcieclk 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; + reset-gpios = <&expander2 11 GPIO_ACTIVE_LOW>; + /* Not supported on REV.0100 */ + /* supports-clkreq; */ + status = "okay"; +}; + +®_sdvmmc { + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_bbm { + linux,code = ; +}; + +&thermal_zones { + a55-thermal { + trips { + cpu_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + cpu_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_active0>; + cooling-device = <&fan 0 2>; + }; + + map2 { + trip = <&cpu_active1>; + cooling-device = <&fan 3 5>; + }; + + map3 { + trip = <&cpu_active2>; + cooling-device = <&fan 6 10>; + }; + }; + }; +}; + +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; + status = "okay"; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usb2 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + vdd-supply = <®_v3v3_mb>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_1: hub@1 { + compatible = "usb424,2514"; + reg = <1>; + reset-gpios = <&expander2 4 GPIO_ACTIVE_LOW>; + vdd-supply = <®_v3v3_mb>; + vdda-supply = <®_v3v3_mb>; + }; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; + vdd-supply = <®_v3v3_mb>; + }; +}; + +&usb3_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + vbus-supply = <®_vbus_usb3>; + status = "okay"; +}; + +/* X7 µSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_sdvmmc>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_enetc0: enetc0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_ethphy1: ethphy1grp { + fsl,pins = ; + }; + + pinctrl_expander1: expander1grp { + fsl,pins = ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c7_recovery: lpi2c7recoverygrp { + fsl,pins = , + ; + }; + + pinctrl_lpspi4: lpspi4grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart8: lpuart8grp { + fsl,pins = , + , + ; + }; + + pinctrl_emdio: emdiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = ; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_retimer: retimergrp { + fsl,pins = ; + }; + + pinctrl_sfp: sfpgrp { + fsl,pins = , + ; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = ; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = ; + }; + + pinctrl_typec: typecgrp { + fsl,pins = ; + }; + + pinctrl_usb3: usb3grp { + fsl,pins = ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi new file mode 100644 index 000000000000..aa2756c14e46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596la.dtsi @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + * Author: Markus Niebel + */ + +/dts-v1/; + +#include +#include "imx95.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, size : 2048 MiB DRAM + * should be corrected by bootloader + */ + reg = <0 0x80000000 0 0x80000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdvmmc: regulator-sdvmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdvmmc>; + regulator-name = "SD_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; + enable-active-high; + /* can be enabled by mainboard with SD-Card support */ + status = "disabled"; + }; +}; + +&adc1 { + vref-supply = <®_1v8>; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <66000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +/* System Manager */ +&gpio1 { + status = "reserved"; +}; + +/* System Manager */ +&lpi2c1 { + status = "reserved"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + m24c64: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; + + /* protectable identification memory (part of M24C64-D @54) */ + eeprom@5c { + compatible = "atmel,24c64d-wl"; + reg = <0x5c>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; + + imu@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + }; +}; + +&thermal_zones { + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + trip = <&pf5301_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = , + , + , + , + , + /* SION to allow clock loopback from pad */ + , + ; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , + ; + }; + + pinctrl_sdvmmc: sdvmmcgrp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; +}; From 85220be437fa0cf8515a172848ca71fc298dfde7 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Mon, 22 Jun 2026 06:54:09 +0000 Subject: [PATCH 445/864] dt-bindings: iommu: Fix interrupt type in example The CMDQV interrupt on Tegra264 is edge-triggered per the hardware interrupt documentation, but the binding example describes it as level-triggered. Correct the example to use IRQ_TYPE_EDGE_RISING so that it does not propagate the wrong trigger type. Fixes: 8a59954192eb ("dt-bindings: iommu: Add NVIDIA Tegra CMDQV support") Reported-by: Nicolin Chen Signed-off-by: Ashish Mhetre Acked-by: Jon Hunter Acked-by: Nicolin Chen Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml index 3f5006a59805..76ef34fe5c72 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -38,5 +38,5 @@ examples: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x5200000 0x830000>; - interrupts = ; + interrupts = ; }; From d28b49f11f8cbb7d76382998c84c18f465b347a4 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 1 Jul 2026 18:06:55 +0200 Subject: [PATCH 446/864] dt-bindings: gpu: host1x: Fix email address These bindings had mixed up local and domain parts, the combination of which doesn't exist. Fix them up. Acked-by: Conor Dooley Signed-off-by: Thierry Reding --- .../devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml | 2 +- .../devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml | 2 +- .../devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml | 2 +- .../devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml index ba4c6473ff92..84a84275432a 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml index c23dae713eb8..8916a868dafb 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml index 99a33a5eac3f..582eb44eb157 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -12,7 +12,7 @@ description: | through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml index 0b7561c8b9bb..4eb325cfd296 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding + - Thierry Reding - Mikko Perttunen properties: From 259bd77e9f635e058c045a880427570e534c8737 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:31 +0200 Subject: [PATCH 447/864] arm64: dts: freescale: imx8mn-var-som: Move UART4 description to Symphony The VAR-SOM-MX8MN module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART. Move the UART4 node from the SOM device tree to the imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-var-som-symphony.dts | 18 ++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 3434b189fa58..b07e71d3adee 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -15,6 +15,10 @@ / { model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; + chosen { + stdout-path = &uart4; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -171,6 +175,13 @@ &uart3 { status = "okay"; }; +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -234,4 +245,11 @@ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 38ef9e4fdf07..32f101ef2850 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -11,10 +11,6 @@ / { model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; - chosen { - stdout-path = &uart4; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x40000000>; @@ -274,13 +270,6 @@ &uart2 { status = "okay"; }; -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - &usbotg1 { dr_mode = "otg"; usb-role-switch; @@ -432,13 +421,6 @@ MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 From bc5217a4e354ebe0a2f52d2188ef952fd630defc Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:32 +0200 Subject: [PATCH 448/864] arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier boards The VAR-SOM-MX8MN module does not provide an onboard SD card slot. USDHC2 is routed to the SD card slot on the carrier boards. Move the USDHC2 node and pinctrl configuration from the SOM device tree to imx8mn-var-som-symphony.dts and imx8mn-rve-gateway.dts, keeping the SOM dtsi limited to hardware present on the module itself. Add the required off-on-delay-us property for the USDHC2 regulator on the Symphony carrier board. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-rve-gateway.dts | 47 ++++++++++++++- .../dts/freescale/imx8mn-var-som-symphony.dts | 57 +++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 56 ------------------ 3 files changed, 102 insertions(+), 58 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts index ea1855171fb0..056ea2f9e963 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts @@ -207,8 +207,16 @@ &usbotg1 { /* SD interface on expansion connector. */ &usdhc2 { - vmmc-supply = <®_3p3v>; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; }; &iomuxc { @@ -276,10 +284,45 @@ MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x00000156 /* B */ >; }; - /* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */ pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 >; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index b07e71d3adee..7308613a48b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -28,6 +28,7 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { regulator-max-microvolt = <3300000>; gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; enable-active-high; + off-on-delay-us = <20000>; }; gpio-keys { @@ -200,6 +201,20 @@ usb1_drd_sw: endpoint { }; }; +/* SD */ +&usdhc2 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + &iomuxc { pinctrl_captouch: captouchgrp { fsl,pins = < @@ -252,4 +267,46 @@ MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 >; }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 32f101ef2850..e1d2e2a72e1f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -295,20 +295,6 @@ brcmf: wifi@1 { }; }; -/* SD */ -&usdhc2 { - assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; - assigned-clock-rates = <200000000>; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; @@ -454,48 +440,6 @@ MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 From 763a267bc2ccf637bd0f35492ca1e6ab6c9dc13b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:33 +0200 Subject: [PATCH 449/864] arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables Reformat the fsl,pins tables in the i.MX8MN VAR-SOM device tree to use consistent column alignment across all pinctrl groups. Align the entries to match the formatting already used in the pinctrl_fec1 group, which contains the longest pin definitions, for improved readability and consistency. No functional changes intended. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 126 +++++++++--------- 1 file changed, 63 insertions(+), 63 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index e1d2e2a72e1f..71a2f0866822 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -368,129 +368,129 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 >; }; pinctrl_reg_eth_phy: regethphygrp { fsl,pins = < - MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 >; }; pinctrl_restouch: restouchgrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; }; From a6c8d4f9c2db6254681d78ec93f5bd944a0cf89d Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:34 +0200 Subject: [PATCH 450/864] arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY. Add the PHY VDDIO supply regulator and adjust reset timings. The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring. Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony). Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-var-som-symphony.dts | 20 ++++++++++++++++++- .../boot/dts/freescale/imx8mn-var-som.dtsi | 20 ++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 7308613a48b2..520aff23e587 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -8,6 +8,7 @@ /dts-v1/; +#include #include #include "imx8mn-var-som.dtsi" @@ -74,7 +75,24 @@ reg_per_3v3: regulator-peripheral-3v3 { }; ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; &i2c2 { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 71a2f0866822..09146ab76385 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -35,6 +35,13 @@ reg_3v3_fixed: regulator-3v3-fixed { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &A53_0 { @@ -96,24 +103,19 @@ &fec1 { phy-mode = "rgmii"; phy-handle = <ðphy>; phy-supply = <®_eth_phy>; - fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; - ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */ + ethphy: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - /* - * Deassert delay: - * ADIN1300 requires 5ms. - * AR8033 requires 1ms. - */ - reset-deassert-us = <20000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; }; }; }; @@ -342,7 +344,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159 + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 >; }; From ed99c5c5c5e88f31ed8de6eff9c3da2ca188d947 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:35 +0200 Subject: [PATCH 451/864] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec The VAR-SOM-MX8MN can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications. Add the WM8904 device to the appropriate I2C bus, enable the SAI peripheral, and introduce the sound node to expose the sound card to the system. Add I2C3 recovery gpio properties. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 98 ++++++++++++++++++- 1 file changed, 95 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 09146ab76385..e2e04ad2fbb6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -16,6 +16,14 @@ memory@40000000 { reg = <0x0 0x40000000 0 0x40000000>; }; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_eth_phy: regulator-eth-phy { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; }; &A53_0 { @@ -246,18 +282,55 @@ eeprom_som: eeprom@52 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - /* TODO: configure audio, as of now just put a placeholder */ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - status = "disabled"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MN_CLK_SAI5_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -375,6 +448,13 @@ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 @@ -400,6 +480,18 @@ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 From 42a066c24cc673b4317acb382597c0a3230b9f6f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:36 +0200 Subject: [PATCH 452/864] arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MN VAR-SOM. The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO. Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index e2e04ad2fbb6..ac22dd3e6542 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -11,6 +11,13 @@ / { model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x40000000>; @@ -130,6 +137,19 @@ touchscreen@0 { ti,keep-vref-on; wakeup-source; }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + clocks = <&clk40m>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <20000000>; + microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + }; }; &fec1 { @@ -391,6 +411,13 @@ &wdog1 { }; &iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c0 + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 From 040bf14c102570fee953fc2124737a988c3fb6a6 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:37 +0200 Subject: [PATCH 453/864] arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts The VAR-SOM-MX8MN currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART. Move the wireless module configuration out of the base imx8mn-var-som.dtsi and provide dedicated variant includes. The IW61x configuration is moved to imx8mn-var-som-wifi-bt-iw61x.dtsi and used by the Symphony evaluation board device tree. A separate imx8mn-var-som-wifi-brcm-legacy.dtsi include is added to keep the configuration for the legacy Broadcom SDIO WiFi module used on earlier SOM revisions. To preserve compatibility with older SOM revisions, add a separate imx8mn-var-som-symphony-legacy.dtb, which disables the IW61x setup and applies the Broadcom-specific configuration. The Broadcom-based SOM revision is no longer in production, but support is kept for existing users. This keeps the VAR-SOM-MX8MN support aligned with the existing VAR-SOM-MX8MM implementation. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-rve-gateway.dts | 1 + .../imx8mn-var-som-symphony-legacy.dts | 19 ++++++++ .../dts/freescale/imx8mn-var-som-symphony.dts | 1 + .../imx8mn-var-som-wifi-brcm-legacy.dtsi | 19 ++++++++ .../imx8mn-var-som-wifi-bt-iw61x.dtsi | 46 +++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 8 ---- 7 files changed, 87 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9a864990d7e3..7021c2db54df 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -207,6 +207,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb DTC_FLAGS_imx8mn-solidsense-n8-compact += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ diff --git a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts index 056ea2f9e963..d9981d9a7362 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts @@ -7,6 +7,7 @@ #include #include "imx8mn-var-som.dtsi" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" / { model = "RVE gateway"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file mode 100644 index 000000000000..5998ebcef474 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +#include "imx8mn-var-som-symphony.dts" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" + +&bluetooth_iw61x { + status = "disabled"; +}; + +&iw61x_pwrseq { + status = "disabled"; +}; + +&usdhc1 { + /delete-property/ mmc-pwrseq; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 520aff23e587..53130b521b5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -11,6 +11,7 @@ #include #include #include "imx8mn-var-som.dtsi" +#include "imx8mn-var-som-wifi-bt-iw61x.dtsi" / { model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi new file mode 100644 index 000000000000..9ca2038943d4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi new file mode 100644 index 000000000000..9ec341ed57d3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/ { + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 20 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>; + + bluetooth_iw61x: bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + mmc-pwrseq = <&iw61x_pwrseq>; +}; + +&iomuxc { + pinctrl_bt: bluetoothgrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0xc1 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x140 + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index ac22dd3e6542..5d8cd8c13633 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -371,10 +371,7 @@ &usbotg1 { status = "okay"; }; -/* WIFI */ &usdhc1 { - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; @@ -383,11 +380,6 @@ &usdhc1 { non-removable; keep-power-in-suspend; status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; }; /* eMMC */ From 0504e4d12fd3c3b5062b49086ce17a2743c60658 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:38 +0200 Subject: [PATCH 454/864] arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node The VAR-SOM-MX8MN module does not provide an onboard USB connector. The complete USB OTG description, including the Type-C role switch configuration, is already provided by the Symphony carrier board device tree. Remove the duplicate USB OTG node from the SOM dtsi to avoid describing the same hardware in two places. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 5d8cd8c13633..7a4c7455a162 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -365,12 +365,6 @@ &uart2 { status = "okay"; }; -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; From 5580a6278c5ce77a8492d76571929321894934f3 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:39 +0200 Subject: [PATCH 455/864] arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface Enable the FlexSPI controller on the VAR-SOM-MX8MN and add the corresponding pin multiplexing configuration. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index 7a4c7455a162..0bc9fb44069e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -176,6 +176,12 @@ ethphy: ethernet-phy@4 { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -454,6 +460,17 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 From 8576126c7ccf632c8edeeb69f57f17ee5e125de5 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:40 +0200 Subject: [PATCH 456/864] arm64: dts: imx8mn-var-som-symphony: Add TPM2 support Add support for the TPM2 device on the VAR-SOM Symphony carrier board. The ST33K TPM2 is connected over I2C, and A PCA6408 GPIO expander is used to control the reset signal required to release the TPM from reset. Add the PCA6408 GPIO expander and the ST33K TPM2 device node. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 53130b521b5b..7d016ed5e911 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -160,6 +160,20 @@ typec1_dr_sw: endpoint { }; &i2c3 { + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5406"; From ab80a67f5cdb42797d0a92d7951242291bb97f3a Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:41 +0200 Subject: [PATCH 457/864] arm64: dts: imx8mn-var-som-symphony: Enable I2C4 Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../dts/freescale/imx8mn-var-som-symphony.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 7d016ed5e911..4898018f030c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -195,6 +195,16 @@ rtc@68 { }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -262,6 +272,20 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 From e2e47af10c90f4c5eaf415fa98f6ca2f33ef30da Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:42 +0200 Subject: [PATCH 458/864] arm64: dts: imx8mn-var-som-symphony: add wakeup sources Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 4898018f030c..c98dca8e7889 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -40,18 +40,21 @@ key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; }; @@ -187,6 +190,7 @@ ft5x06_ts: touchscreen@38 { touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 { From 164cb0d61a3fd0d9376005aae3b112a3dbba2e07 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:43 +0200 Subject: [PATCH 459/864] arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low Keep the RGB_SEL line driven low on the Symphony carrier board. This avoids leaving the line floating and ensures the board remains in the expected display configuration. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index c98dca8e7889..ddd4651b35d7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -168,6 +168,14 @@ pca6408: gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e { From 8a6c812cd5a721aa0af9b7dd35b43d12c831349e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:44 +0200 Subject: [PATCH 460/864] arm64: dts: imx8mn-var-som-symphony: enable PWM1 Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mn-var-som-symphony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index ddd4651b35d7..2afb5b438b68 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -217,6 +217,12 @@ &i2c4 { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; @@ -310,6 +316,12 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 From be578db51f789f0b88ec4f5e5f78e232b42c6b15 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Mon, 6 Jul 2026 11:34:45 +0200 Subject: [PATCH 461/864] arm64: dts: imx8mn-var-som-symphony: Disable internal RTC Disable the internal SNVS RTC on the Symphony carrier board and use the external DS1337 RTC instead. Signed-off-by: Stefano Radaelli Reviewed-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 2afb5b438b68..364127257309 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -223,6 +223,10 @@ &pwm1 { status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + /* Header */ &uart1 { pinctrl-names = "default"; From 4a3f4d08f53242dd6524285fd37c01886aacd0bc Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 17 Jul 2026 12:29:37 +0200 Subject: [PATCH 462/864] dt-bindings: arm: fsl: add Variscite VAR-SOM-MX8 QuadMax Boards Add DT compatible strings for Variscite VAR-SOM-MX8 QuadMax SoM and Variscite Symphony development carrier Board. Acked-by: Krzysztof Kozlowski Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7b57a6ee1b50..52f08bc1f8ea 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1393,6 +1393,12 @@ properties: - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - const: fsl,imx8qm + - description: i.MX8QM Variscite VAR-SOM-MX8 based Boards + items: + - const: variscite,var-som-imx8qm-symphony + - const: variscite,var-som-imx8qm + - const: fsl,imx8qm + - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules items: - enum: From 868ced4df4ef1169802c400a685820f2f1fc059b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 17 Jul 2026 12:29:38 +0200 Subject: [PATCH 463/864] arm64: dts: freescale: Add support for Variscite VAR-SOM-MX8 QuadMax Add device tree support for the Variscite VAR-SOM-MX8 QuadMax system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX8 QuadMax MPU processor - Up to 8GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-var-som.dtsi | 531 ++++++++++++++++++ 1 file changed, 531 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi new file mode 100644 index 000000000000..b11da10c5ae3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som.dtsi @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite VAR-SOM-MX8 + * + * Link: https://variscite.com/system-on-module-som/i-mx-8/i-mx-8-quadmax-quadplus/var-som-mx8/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "imx8qm.dtsi" + +/ { + model = "Variscite i.MX8QM VAR-SOM-MX8 Module"; + compatible = "variscite,var-som-imx8qm", "fsl,imx8qm"; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_audio_supply: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: memory@90000000 { + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@90008000 { + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@90010000 { + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@90018000 { + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + rsc_table0: memory@900ff000 { + reg = <0 0x900ff000 0 0x1000>; + no-map; + }; + + vdev2vring0: memory@90100000 { + reg = <0 0x90100000 0 0x8000>; + no-map; + }; + + vdev2vring1: memory@90108000 { + reg = <0 0x90108000 0 0x8000>; + no-map; + }; + + vdev3vring0: memory@90110000 { + reg = <0 0x90110000 0 0x8000>; + no-map; + }; + + vdev3vring1: memory@90118000 { + reg = <0 0x90118000 0 0x8000>; + no-map; + }; + + rsc_table1: memory@901ff000 { + reg = <0 0x901ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: memory@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + dsp_reserved: memory@92400000 { + reg = <0 0x92400000 0 0x1000000>; + no-map; + }; + + dsp_vdev0vring0: memory@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: memory@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: memory@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + /* VAR-SOM-MX8QM doesn't have 1GB variant */ + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + sound-wm8904 { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&esai0>; + }; + }; +}; + +&acm { + status = "okay"; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&asrc1 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&cm41_intmux { + status = "okay"; +}; + +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + reset-gpios = <&lsio_gpio2 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + vddio-supply = <®_phy_vddio>; + }; + }; +}; + +&gpio0_mipi_csi0 { + status = "disabled"; +}; + +&gpio0_mipi_csi1 { + status = "disabled"; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + wm8904: codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +/* Bluetooth */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + uart-has-rtscts; + status = "okay"; +}; + +&mu_m0{ + status = "okay"; +}; + +&mu1_m0{ + status = "okay"; +}; + +&mu2_m0{ + status = "okay"; +}; + +&rtc { + status = "disabled"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&thermal_zones { + pmic-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* WIFI */ +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000048 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x06000028 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000041 + IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + IMX8QM_ESAI1_SCKR_LSIO_GPIO2_IO06 0x00000041 + IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000041 + IMX8QM_SPDIF0_EXT_CLK_LSIO_GPIO2_IO16 0x00000041 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc6000020 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020 + IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020 + IMX8QM_UART1_CTS_B_DMA_UART1_RTS_B 0x06000020 + IMX8QM_UART1_RTS_B_DMA_UART1_CTS_B 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + /* GPIOs used by user space WiFi init */ + IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0xc600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x06000021 + IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 + IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; +}; From a40fdbf706cc643671e41b9ac2f9ec3a832e769e Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 17 Jul 2026 12:29:39 +0200 Subject: [PATCH 464/864] arm64: dts: imx8qm-var-som: Add support for Variscite Symphony board Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-MX8 QuadMax system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart, SPI and I2C interfaces - GPIO Expanders - RTC module - TPM module - CAN peripherals - PCIE support Link: https://variscite.com/carrier-boards/symphony-board/ Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qm-var-som-symphony.dts | 490 ++++++++++++++++++ 2 files changed, 491 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7021c2db54df..7d77856d3e7d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -543,6 +543,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-tqma8qm-mba8x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-var-som-symphony.dtb imx8qm-mek-ov5640-csi0-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi0.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts new file mode 100644 index 000000000000..c7d3073b4041 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Variscite Symphony carrier board for VAR-SOM-MX8 QuadMax + * + * Link: https://variscite.com/carrier-boards/symphony-board/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include "imx8qm-var-som.dtsi" + +/ { + model = "Variscite VAR-SOM-MX8 on Symphony evaluation board"; + compatible = "variscite,var-som-imx8qm-symphony", + "variscite,var-som-imx8qm", "fsl,imx8qm"; + chosen { + stdout-path = &lpuart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-back { + label = "Back"; + gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-home { + label = "Home"; + gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-menu { + label = "Menu"; + gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-heartbeat { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_fec_phy: regulator-fec-phy { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <20000>; + vin-supply = <®_vselect>; + gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio0 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_vselect: regulator-vselect { + compatible = "regulator-fixed"; + regulator-name = "reg_vselect"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&pca9534 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +ðphy0 { + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; +}; + +&fec1 { + mdio { + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + vddio-supply = <®_phy_vddio>; + reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <100000>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_fec_phy>; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&hsio_phy { + fsl,hsio-cfg = "pciea-pcieb-sata"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + }; + + /* USB Type-C Controller */ + typec_ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "lvds_brg_en"; + }; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + + /* Capacitive touch */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5406"; + pinctrl-names = "default"; + reg = <0x38>; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&lsio_gpio0>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + + rtc@68 { + compatible = "dallas,ds1337"; + reg = <0x68>; + }; +}; + +&lpspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi1>; + cs-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* console */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +/* header */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&pca9534 { + usb3-signal-route-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "usb3_signal_route"; + }; +}; + +&pciea{ + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + status = "okay"; +}; + +&pciea_port0 { + reset-gpios = <&pca6408 1 GPIO_ACTIVE_LOW>; +}; + +&usb3_phy { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + +&usbphy1 { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + IMX8QM_GPT1_COMPARE_LSIO_GPIO0_IO19 0x06000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000048 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000048 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000048 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000048 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000048 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000048 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000048 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000048 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000048 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000048 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000048 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000048 + >; + }; + + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QM_USB_SS3_TC3_DMA_I2C1_SDA 0xc6000020 + IMX8QM_USB_SS3_TC1_DMA_I2C1_SCL 0xc6000020 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + IMX8QM_ENET1_MDC_DMA_I2C4_SCL 0xc6000020 + IMX8QM_ENET1_MDIO_DMA_I2C4_SDA 0xc6000020 + >; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins = < + IMX8QM_ADC_IN3_DMA_SPI1_SCK 0x0600004c + IMX8QM_ADC_IN4_DMA_SPI1_SDO 0x0600004c + IMX8QM_ADC_IN5_DMA_SPI1_SDI 0x0600004c + IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021 + >; + }; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + >; + }; + + pinctrl_usbotg1: otg1grp { + fsl,pins = < + IMX8QM_GPT1_CAPTURE_LSIO_GPIO0_IO18 0x06000048 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + IMX8QM_GPT0_CLK_LSIO_GPIO0_IO14 0x00000021 + >; + }; +}; From 356894c37aa1f8ab430cef5d69176123b0ec98b3 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Fri, 10 Jul 2026 18:12:20 +0800 Subject: [PATCH 465/864] arm64: dts: imx91-9x9-qsb: add CAN support overlay file On the i.MX91 9x9 QSB, CAN1 and MICFIL share pins. A TMUX1574RSVR analog mux controls the routing: when SEL is driven high, CAN1 is selected; when SEL is driven low, MICFIL is selected. By default, SEL is kept low. To enable CAN1, SEL must be driven high. This is done via the can_fun function defined in the pinctrl-gpiomux node. CAN1 uses the TJA1057GT/3 PHY. Signed-off-by: Haibo Chen Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx91-9x9-qsb-can1.dtso | 48 +++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7d77856d3e7d..b60b43071936 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -580,7 +580,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb +imx91-9x9-qsb-can1-dtbs += imx91-9x9-qsb.dtb imx91-9x9-qsb-can1.dtbo imx91-phyboard-segin-peb-av-18-dtbs += imx91-phyboard-segin.dtb imx91-phyboard-segin-peb-av-18.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso new file mode 100644 index 000000000000..b8343d653e51 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb-can1.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +#include +#include "imx91-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_phy>; + silent-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&flexcan1 { + phys = <&flexcan_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>, <&can_fun>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexcan_phy: flexcanphygrp { + fsl,pins = < + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__CAN1_TX 0x139e + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; + +/* micfil uses PDM port A pins, conflicts with can1 */ +&micfil { + status = "disabled"; +}; From e0e1a9712fb1767dcf5ab69ae47dac2d1a080c3c Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 14 Jul 2026 12:05:18 +0800 Subject: [PATCH 466/864] arm64: dts: imx943-evk: Remove 'supports-clkreq' from PCIe1 Remove the 'supports-clkreq' property from PCIe1 as the standard PCIe slot on i.MX943 EVK may not have CLKREQ# signal wired, causing compatibility issues with some PCIe cards. Fixes: 9a8f11f6f786 ("arm64: dts: imx943-evk: Add pcie[0,1] and pcie-ep[0,1] support") Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 674410e541cb..49fb1744d992 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -1061,7 +1061,6 @@ &pcie1 { <&pcie_ref_clk>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref", "extref"; - supports-clkreq; status = "okay"; }; From 092d1fad3b2c224e465e4ecc5d7a17f3da3cf1a8 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 14:55:13 -0400 Subject: [PATCH 467/864] dt-bindings: fsl,fpga-qixis: Add fsl,ls1021aqds-fpga compatible string Add fsl,ls1021aqds-fpga compatible string for ls1021a qds's FPGA on board controller chips, which connect CFI interface. With following patches to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: 'oneOf' conditional failed, one must be fixed: 'bank-width', 'device-width' do not match any of the regexes: '^gpio@[0-9a-f]+$', '^mdio-mux@[a-f0-9,]+$', '^pinctrl-[0-9]+$' /home/lizhi/source/linux-upstream-pci-ep-arm/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0:compatible: 'oneOf' conditional failed, one must be fixed: ['simple-mfd'] is too short Acked-by: Rob Herring (Arm) Reviewed-by: Ioana Ciornei Signed-off-by: Frank Li --- Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml index 2eacb581b9fd..ea1e3fbca202 100644 --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml @@ -24,6 +24,7 @@ properties: - const: fsl,fpga-qixis - items: - enum: + - fsl,ls1021aqds-fpga - fsl,ls1043aqds-fpga - fsl,ls1043ardb-fpga - fsl,ls1046aqds-fpga From 28228f9ea570a94e1873adda5ee284134af28cd6 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 14:55:14 -0400 Subject: [PATCH 468/864] ARM: dts: ls1021a-qds: add compatible string "fsl,ls1021aqds-fpga" for on boards FPGA chip Add front compatible string "fsl,ls1021aqds-fpga" for on boards FPGA chip and remove unused property bank-width and device-width, which used for MTD devices and FPGA is not a MTD devices. Fix below CHECK_DTBS warning: rch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: 'oneOf' conditional failed, one must be fixed: 'bank-width', 'device-width' do not match any of the regexes: '^gpio@[0-9a-f]+$', '^mdio-mux@[a-f0-9,]+$', '^pinctrl-[0-9]+$' /home/lizhi/source/linux-upstream-pci-ep-arm/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0:compatible: 'oneOf' conditional failed, one must be fixed: ['simple-mfd'] is too short arch/arm/boot/dts/nxp/ls/ls1021a-qds.dtb: memory-controller@1530000 (fsl,ifc): board-control@3,0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'bank-width', 'compatible', 'device-width', 'mdio-mux@54', 'ranges', 'reg' were unexpected) Reviewed-by: Ioana Ciornei Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts index a880875ced83..34c88650c828 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-qds.dts @@ -205,10 +205,8 @@ nand@2,0 { fpga: board-control@3,0 { #address-cells = <1>; #size-cells = <1>; - compatible = "simple-mfd"; + compatible = "fsl,ls1021aqds-fpga", "fsl,fpga-qixis", "simple-mfd"; reg = <0x3 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; ranges = <0 3 0 0x100>; mdio-mux@54 { From f922f586c67d2b2c5d476679a4afaebbc4126817 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Jul 2026 19:33:42 +0200 Subject: [PATCH 469/864] arm64: dts: qcom: smb2370: Disable SMB2370_2 by default It's absent on laptops that only have 2 type-C ports (the majority so far, including the CRD). Keep it disabled by default, following established practice from the previous generation. Signed-off-by: Konrad Dybcio Reviewed-by: Gopikrishna Garmidi Link: https://lore.kernel.org/r/20260716-topic-smb2370_port2-v1-1-83d02b2ba4b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/smb2370.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qcom/smb2370.dtsi index 80f3fdae5705..1e02578e4ee3 100644 --- a/arch/arm64/boot/dts/qcom/smb2370.dtsi +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -36,6 +36,8 @@ smb2370_l_e2: pmic@b { #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + smb2370_l_e2_eusb2_repeater: phy@fd00 { compatible = "qcom,smb2370-eusb2-repeater"; reg = <0xfd00>; From e9d928da6f25e2c0d926c15b66fab52602e86f8f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Jul 2026 19:33:43 +0200 Subject: [PATCH 470/864] arm64: dts: qcom: glymur: Add PCIe port compatibles and ports Centrally define the endpoints to let device DTs that describe PCIe devices and/or M.2 connectors refer to them without error-prone duplication. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260716-topic-smb2370_port2-v1-2-83d02b2ba4b0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index c557ce942782..5de367b64647 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2946,6 +2946,7 @@ opp-32000000-4 { pcie4_port0: pcie@0 { device_type = "pci"; + compatible = "pciclass,0604"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2954,6 +2955,11 @@ pcie4_port0: pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + port { + pcie4_port0_ep: endpoint { + }; + }; }; }; @@ -3212,6 +3218,7 @@ opp-128000000-5 { pcie5_port0: pcie@0 { device_type = "pci"; + compatible = "pciclass,0604"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -3220,6 +3227,11 @@ pcie5_port0: pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + port { + pcie5_port0_ep: endpoint { + }; + }; }; }; @@ -3422,6 +3434,7 @@ opp-32000000-4 { pcie6_port0: pcie@0 { device_type = "pci"; + compatible = "pciclass,0604"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -3430,6 +3443,11 @@ pcie6_port0: pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + port { + pcie6_port0_ep: endpoint { + }; + }; }; }; @@ -3688,6 +3706,7 @@ opp-128000000-5 { pcie3b_port0: pcie@0 { device_type = "pci"; + compatible = "pciclass,0604"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -3696,6 +3715,11 @@ pcie3b_port0: pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + port { + pcie3b_port0_ep: endpoint { + }; + }; }; }; From 394b63a2bbf2d1e98d411ee5ec52d68f66bbf984 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 14 Jul 2026 14:50:58 +0800 Subject: [PATCH 471/864] arm64: dts: qcom: glymur: enable ETR and CTCU devices Embedded Trace Router(ETR) is working as a DDR memory sink to collect tracing data from source device and the CTCU device serves as the control unit for the ETR device. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260714-add-ctcu-etr-for-glymur-v1-1-791de63c0713@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 152 +++++++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 5de367b64647..beb8edce1916 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -6290,6 +6290,35 @@ rx-pins { }; }; + ctcu@10001000 { + compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x10001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm: stm@10002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x10002000 0x0 0x1000>, @@ -6403,6 +6432,121 @@ funnel0_out: endpoint { }; }; + replicator@10046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x10046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc@10048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x00e0 0x0000>; + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@1004e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x1004e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc@1004f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x1004f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + iommus = <&apps_smmu 0x0100 0x0000>; + arm,scatter-gather; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@1102c000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x1102c000 0x0 0x1000>; @@ -7168,6 +7312,14 @@ out-ports { #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; From 5d7ebb1f36ad8a51f4e60819a8c5bddf04a8d1a2 Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Fri, 24 Apr 2026 14:05:08 +0530 Subject: [PATCH 472/864] arm64: dts: qcom: glymur: add TRNG node Glymur has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Tested-by: Kuldeep Singh Link: https://lore.kernel.org/r/20260424-glymur_trng_enablement-v2-2-0603cbe68440@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index beb8edce1916..c16c60642899 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3758,6 +3758,11 @@ pcie3b_phy: phy@f10000 { status = "disabled"; }; + rng: rng@10c3000 { + compatible = "qcom,glymur-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From d3ca4252d21ec85ada29689f78d13d4596749e3a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Jun 2026 16:16:09 +0200 Subject: [PATCH 473/864] arm64: dts: qcom: glymur: Drop fake PCIe phy 3B According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da35@quoll/ Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260609141608.354186-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 5 --- arch/arm64/boot/dts/qcom/glymur.dtsi | 39 +----------------------- 2 files changed, 1 insertion(+), 43 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index b314c6dd423c..c12808abbfe1 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -750,11 +750,6 @@ &pcie3b { pinctrl-names = "default"; }; -&pcie3b_phy { - vdda-phy-supply = <&vreg_l3c_e1_0p89>; - vdda-pll-supply = <&vreg_l2c_e1_1p14>; -}; - &pcie3b_port0 { reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index c16c60642899..ee34dcbfacda 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -802,7 +802,7 @@ gcc: clock-controller@100000 { <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ <0>, /* PCIe 3a */ - <&pcie3b_phy>, /* PCIe 3b */ + <0>, /* PCIe 3b */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ <&pcie6_phy>, /* PCIe 6 */ @@ -3710,8 +3710,6 @@ pcie3b_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; - phys = <&pcie3b_phy>; - #address-cells = <3>; #size-cells = <2>; ranges; @@ -3723,41 +3721,6 @@ pcie3b_port0_ep: endpoint { }; }; - pcie3b_phy: phy@f10000 { - compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; - reg = <0x0 0x00f10000 0x0 0x10000>; - - clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_3_CLKREF_EN>, - <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_3B_PIPE_CLK>, - <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets = <&gcc GCC_PCIE_3B_PHY_BCR>, - <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; - reset-names = "phy", - "phy_nocsr"; - - assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie3b_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - rng: rng@10c3000 { compatible = "qcom,glymur-trng", "qcom,trng"; reg = <0x0 0x010c3000 0x0 0x1000>; From 2edbea82d8edbddb2a235b8f988f17b86f075476 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 15 Jul 2026 16:29:16 +0300 Subject: [PATCH 474/864] arm64: dts: qcom: glymur: Add CX power domain to GCC The GCC GDSCs on Glymur are backed by the RPMh CX power domain. Without describing that parent domain, consumers of GCC-provided GDSCs can enable their local domain without causing the required CX vote to be held. Add the CX power-domain reference to the GCC node so votes from GCC GDSC consumers can propagate to RPMh CX. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260715-glymur-fix-gcc-cx-scaling-v3-3-72eb5adad156@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index ee34dcbfacda..8145c8721b86 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -829,6 +829,7 @@ gcc: clock-controller@100000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd RPMHPD_CX>; }; gpi_dma2: dma-controller@800000 { From 89efdbd8ea62ff03071fd177a1f1030ff30303e4 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:08 +1000 Subject: [PATCH 475/864] arm64: dts: apple: t8112: Add SMC hwmon node Add the SMC hwmon subdevice Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-1-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 85c47422d4e8..a3241c816c26 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -921,6 +921,10 @@ smc_reboot: reboot { "boot_error_count", "panic_count"; }; + smc_hwmon: hwmon { + compatible = "apple,smc-hwmon"; + }; + rtc { compatible = "apple,smc-rtc"; nvmem-cells = <&rtc_offset>; From 4dea4ee249ec3f435773a1144fd5fe17b70015a8 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:09 +1000 Subject: [PATCH 476/864] arm64: dts: apple: t8103: Add SMC hwmon node Add the SMC hwmon subdevice Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-2-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index da774096b667..4d6a0411f086 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -918,6 +918,10 @@ smc_reboot: reboot { "boot_error_count", "panic_count"; }; + smc_hwmon: hwmon { + compatible = "apple,smc-hwmon"; + }; + rtc { compatible = "apple,smc-rtc"; nvmem-cells = <&rtc_offset>; From d02aeb6980b61a7a0b9c27bc6bd3384cee44ce7c Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:10 +1000 Subject: [PATCH 477/864] arm64: dts: apple: t600x: Add SMC hwmon node Add the SMC hwmon subdevice Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-3-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 3271d234b483..49b23f3da980 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -52,6 +52,10 @@ smc_reboot: reboot { "boot_error_count", "panic_count"; }; + smc_hwmon: hwmon { + compatible = "apple,smc-hwmon"; + }; + rtc { compatible = "apple,smc-rtc"; nvmem-cells = <&rtc_offset>; From f424abc3075b3139834e2d17c363c8f835f1cd74 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:11 +1000 Subject: [PATCH 478/864] arm64: dts: apple: t602x: Add SMC hwmon node Add the SMC hwmon subdevice Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-4-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t602x-die0.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi index 121f2cf75915..c33623f0e27a 100644 --- a/arch/arm64/boot/dts/apple/t602x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -129,6 +129,10 @@ smc_reboot: reboot { "boot_error_count", "panic_count"; }; + smc_hwmon: hwmon { + compatible = "apple,smc-hwmon"; + }; + rtc { compatible = "apple,smc-rtc"; nvmem-cells = <&rtc_offset>; From 56c65dc95f3d1513fd0806bd59da0392e8b6913c Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:12 +1000 Subject: [PATCH 479/864] arm64: dts: apple: Add common SMC hwmon infrastructure Apple's System Management Controller exposes the readings from numerous sensors scattered around the SoC and elsewhere in the machine. Some of these sensors are reliably common on all devices, whereas others are exposed at SMC keys specific to either the SoC or even the particular device. To account for this and expose the right sensors for the right device without tedious Devicetree duplication, we can include fragments of increasing specificity in the per-device .dts files such that the individual keys (of which there are potentially hundreds) do not need to be copied in for every device. Add the initial set of SMC hwmon sensors that are common to multiple devices so that they can be included in the per-device Devicetrees. Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-5-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/hwmon-common.dtsi | 38 +++++++++++++++++++ arch/arm64/boot/dts/apple/hwmon-fan-dual.dtsi | 23 +++++++++++ arch/arm64/boot/dts/apple/hwmon-fan.dtsi | 17 +++++++++ arch/arm64/boot/dts/apple/hwmon-laptop.dtsi | 38 +++++++++++++++++++ arch/arm64/boot/dts/apple/hwmon-mini.dtsi | 16 ++++++++ 5 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/hwmon-common.dtsi create mode 100644 arch/arm64/boot/dts/apple/hwmon-fan-dual.dtsi create mode 100644 arch/arm64/boot/dts/apple/hwmon-fan.dtsi create mode 100644 arch/arm64/boot/dts/apple/hwmon-laptop.dtsi create mode 100644 arch/arm64/boot/dts/apple/hwmon-mini.dtsi diff --git a/arch/arm64/boot/dts/apple/hwmon-common.dtsi b/arch/arm64/boot/dts/apple/hwmon-common.dtsi new file mode 100644 index 000000000000..a35c7b14fec8 --- /dev/null +++ b/arch/arm64/boot/dts/apple/hwmon-common.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * hwmon sensors expected on all systems + * + * Copyright The Asahi Linux Contributors + */ + +&smc_hwmon { + power-PSTR { + apple,key-id = "PSTR"; + label = "Total System Power"; + }; + + power-PDTR { + apple,key-id = "PDTR"; + label = "AC Input Power"; + }; + + power-PMVR { + apple,key-id = "PMVR"; + label = "3.8 V Rail Power"; + }; + + temperature-TH0x { + apple,key-id = "TH0x"; + label = "NAND Flash Temperature"; + }; + + voltage-VD0R { + apple,key-id = "VD0R"; + label = "AC Input Voltage"; + }; + + current-ID0R { + apple,key-id = "ID0R"; + label = "AC Input Current"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/hwmon-fan-dual.dtsi b/arch/arm64/boot/dts/apple/hwmon-fan-dual.dtsi new file mode 100644 index 000000000000..e87997d21e22 --- /dev/null +++ b/arch/arm64/boot/dts/apple/hwmon-fan-dual.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright The Asahi Linux Contributors + * + * Fan hwmon sensors for machines with 2 fan. + */ + +#include "hwmon-fan.dtsi" + +&smc_hwmon { + fan-F0Ac { + label = "Fan 1"; + }; + + fan-F1Ac { + apple,key-id = "F1Ac"; + label = "Fan 2"; + apple,fan-minimum = "F1Mn"; + apple,fan-maximum = "F1Mx"; + apple,fan-target = "F1Tg"; + apple,fan-mode = "F1Md"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/hwmon-fan.dtsi b/arch/arm64/boot/dts/apple/hwmon-fan.dtsi new file mode 100644 index 000000000000..180eb8d7441f --- /dev/null +++ b/arch/arm64/boot/dts/apple/hwmon-fan.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright The Asahi Linux Contributors + * + * Fan hwmon sensors for machines with a single fan. + */ + +&smc_hwmon { + fan-F0Ac { + apple,key-id = "F0Ac"; + label = "Fan"; + apple,fan-minimum = "F0Mn"; + apple,fan-maximum = "F0Mx"; + apple,fan-target = "F0Tg"; + apple,fan-mode = "F0Md"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/hwmon-laptop.dtsi b/arch/arm64/boot/dts/apple/hwmon-laptop.dtsi new file mode 100644 index 000000000000..cadffd000c76 --- /dev/null +++ b/arch/arm64/boot/dts/apple/hwmon-laptop.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * hwmon sensors expected on all laptops + * + * Copyright The Asahi Linux Contributors + */ + +&smc_hwmon { + power-PHPC { + apple,key-id = "PHPC"; + label = "Heatpipe Power"; + }; + + temperature-TB0T { + apple,key-id = "TB0T"; + label = "Battery Hotspot"; + }; + + temperature-TCHP { + apple,key-id = "TCHP"; + label = "Charge Regulator Temp"; + }; + + temperature-TW0P { + apple,key-id = "TW0P"; + label = "WiFi/BT Module Temp"; + }; + + voltage-SBAV { + apple,key-id = "SBAV"; + label = "Battery Voltage"; + }; + + voltage-VD0R { + apple,key-id = "VD0R"; + label = "Charger Input Voltage"; + }; +}; diff --git a/arch/arm64/boot/dts/apple/hwmon-mini.dtsi b/arch/arm64/boot/dts/apple/hwmon-mini.dtsi new file mode 100644 index 000000000000..7fd86e911acf --- /dev/null +++ b/arch/arm64/boot/dts/apple/hwmon-mini.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * hwmon sensors common to the Mac mini desktop + * models, but not the Studio or Pro. + * + * Copyright The Asahi Linux Contributors + */ + +#include "hwmon-fan.dtsi" + +&smc_hwmon { + temperature-TW0P { + apple,key-id = "TW0P"; + label = "WiFi/BT Module Temp"; + }; +}; From d77603e44f55fd7fb1760523ecf60d24cb406937 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:13 +1000 Subject: [PATCH 480/864] arm64: dts: apple: t8103: Add common SMC hwmon sensors Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-6-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 4d6a0411f086..5b68bf0df4e6 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -1250,3 +1250,4 @@ port02: pci@2,0 { }; #include "t8103-pmgr.dtsi" +#include "hwmon-common.dtsi" From ae42d7fe079311432db42c7f3b95e1e0ff9e38cb Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:14 +1000 Subject: [PATCH 481/864] arm64: dts: apple: t8112: Add common SMC hwmon sensors Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-7-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index a3241c816c26..ec248ca052cb 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -1289,3 +1289,4 @@ port03: pci@3,0 { }; #include "t8112-pmgr.dtsi" +#include "hwmon-common.dtsi" From fe521d15d9c5d063333aed3b8010bc6cb03f0418 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:15 +1000 Subject: [PATCH 482/864] arm64: dts: apple: t600x: Add common SMC hwmon sensors Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-8-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6001.dtsi | 2 ++ arch/arm64/boot/dts/apple/t6002.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi index 6dcb71a1d65a..4fb934d7e71f 100644 --- a/arch/arm64/boot/dts/apple/t6001.dtsi +++ b/arch/arm64/boot/dts/apple/t6001.dtsi @@ -67,3 +67,5 @@ p-core-pmu-affinity { &gpu { compatible = "apple,agx-g13c", "apple,agx-g13s"; }; + +#include "hwmon-common.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index a532e5401c4e..0f81fc612a2a 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -305,3 +305,5 @@ &ps_gfx { &gpu { compatible = "apple,agx-g13d", "apple,agx-g13s"; }; + +#include "hwmon-common.dtsi" From fd42ff865357f6bb0ca29cde622989051addd483 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:16 +1000 Subject: [PATCH 483/864] arm64: dts: apple: t602x: Add common SMC hwmon sensors Add the SMC hwmon sensors common to all SoCs Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-9-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6021.dtsi | 2 ++ arch/arm64/boot/dts/apple/t6022.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6021.dtsi b/arch/arm64/boot/dts/apple/t6021.dtsi index 62907ad6a546..5175797baf62 100644 --- a/arch/arm64/boot/dts/apple/t6021.dtsi +++ b/arch/arm64/boot/dts/apple/t6021.dtsi @@ -67,3 +67,5 @@ p-core-pmu-affinity { &gpu { compatible = "apple,agx-g14c", "apple,agx-g14s"; }; + +#include "hwmon-common.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6022.dtsi b/arch/arm64/boot/dts/apple/t6022.dtsi index e73bf2f7510a..7585fd609d34 100644 --- a/arch/arm64/boot/dts/apple/t6022.dtsi +++ b/arch/arm64/boot/dts/apple/t6022.dtsi @@ -347,3 +347,5 @@ &ps_gfx { &gpu { compatible = "apple,agx-g14d", "apple,agx-g14s"; }; + +#include "hwmon-common.dtsi" From b6935375d5360c166efcf2e755513caad2be6b01 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:17 +1000 Subject: [PATCH 484/864] arm64: dts: apple: t8103: jxxx: Add device-specific SMC hwmon sensors Add the device-specific hwmon sensors for select T8103-based devices Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-10-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-j274.dts | 2 ++ arch/arm64/boot/dts/apple/t8103-j293.dts | 3 +++ arch/arm64/boot/dts/apple/t8103-j313.dts | 2 ++ 3 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 52965258200d..1212852251e0 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -74,3 +74,5 @@ &pcie0_dart_2 { &i2c2 { status = "okay"; }; + +#include "hwmon-mini.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 52f63ae7a58d..1d074b9e6018 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -132,3 +132,6 @@ dfr_panel_in: endpoint { &displaydfr_dart { status = "okay"; }; + +#include "hwmon-laptop.dtsi" +#include "hwmon-fan.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts index 9eb2825d25dc..f8b2b1637b9d 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -54,3 +54,5 @@ &typec0 { &typec1 { label = "USB-C Left-front"; }; + +#include "hwmon-laptop.dtsi" From da160f258c36bf329ff00294f8f06d036b502b0d Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:18 +1000 Subject: [PATCH 485/864] arm64: dts: apple: t8112: jxxx: Add device-specific SMC hwmon sensors Add the device-specific hwmon sensors for select T8112-based devices Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-11-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112-j413.dts | 2 ++ arch/arm64/boot/dts/apple/t8112-j415.dts | 2 ++ arch/arm64/boot/dts/apple/t8112-j473.dts | 2 ++ arch/arm64/boot/dts/apple/t8112-j493.dts | 3 +++ 4 files changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts index 1a08a41f369b..7ccfceb08093 100644 --- a/arch/arm64/boot/dts/apple/t8112-j413.dts +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -91,3 +91,5 @@ &i2c4 { &fpwm1 { status = "okay"; }; + +#include "hwmon-laptop.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts index e37c56d9fb4d..fdc3409d2e07 100644 --- a/arch/arm64/boot/dts/apple/t8112-j415.dts +++ b/arch/arm64/boot/dts/apple/t8112-j415.dts @@ -91,3 +91,5 @@ &i2c4 { &fpwm1 { status = "okay"; }; + +#include "hwmon-laptop.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts index 438f972546b8..105a9d118980 100644 --- a/arch/arm64/boot/dts/apple/t8112-j473.dts +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -84,3 +84,5 @@ &typec0 { &typec1 { label = "USB-C Back-right"; }; + +#include "hwmon-mini.dtsi" diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts index ec116da3e4dd..7cea5c594810 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -146,3 +146,6 @@ touchbar0: touchbar@0 { touchscreen-inverted-y; }; }; + +#include "hwmon-laptop.dtsi" +#include "hwmon-fan.dtsi" From e88070b745788928b87b1a3c0c11f481bf849ae4 Mon Sep 17 00:00:00 2001 From: James Calligeros Date: Tue, 14 Jul 2026 16:28:19 +1000 Subject: [PATCH 486/864] arm64: dts: apple: t60xx: jxxx: Add device-specific SMC hwmon sensors Add the device-specific hwmon sensors for select T60xx-based devices Signed-off-by: James Calligeros Link: https://patch.msgid.link/20260714-smc-subdev-dt-v2-12-13fa78873121@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6001-j375c.dts | 2 ++ arch/arm64/boot/dts/apple/t6002-j375d.dts | 2 ++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 2 ++ arch/arm64/boot/dts/apple/t6020-j474s.dts | 2 ++ arch/arm64/boot/dts/apple/t6021-j475c.dts | 2 ++ arch/arm64/boot/dts/apple/t6022-j475d.dts | 2 ++ 6 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6001-j375c.dts b/arch/arm64/boot/dts/apple/t6001-j375c.dts index 2e7c23714d4d..08276114c1d8 100644 --- a/arch/arm64/boot/dts/apple/t6001-j375c.dts +++ b/arch/arm64/boot/dts/apple/t6001-j375c.dts @@ -24,3 +24,5 @@ &wifi0 { &bluetooth0 { brcm,board-type = "apple,okinawa"; }; + +#include "hwmon-fan-dual.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts index a2a24d028cbb..e6eb6b6c386d 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -184,6 +184,8 @@ atcphy5_usb3: endpoint { }; }; +#include "hwmon-fan-dual.dtsi" + /* delete unused USB nodes on die 1 */ /delete-node/ &dwc3_2_dart_0_die1; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index fee84f809a9c..caded1636f3d 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -367,3 +367,5 @@ &atcphy3 { }; #include "spi1-nvram.dtsi" +#include "hwmon-laptop.dtsi" +#include "hwmon-fan-dual.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6020-j474s.dts b/arch/arm64/boot/dts/apple/t6020-j474s.dts index 7c7ad5b8ad18..e3c2635d84fa 100644 --- a/arch/arm64/boot/dts/apple/t6020-j474s.dts +++ b/arch/arm64/boot/dts/apple/t6020-j474s.dts @@ -45,3 +45,5 @@ &pcie0 { <0x200 &pcie0_dart_2 1 1>, <0x300 &pcie0_dart_3 1 1>; }; + +#include "hwmon-mini.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6021-j475c.dts b/arch/arm64/boot/dts/apple/t6021-j475c.dts index 533e35774874..9fe17f1f7f59 100644 --- a/arch/arm64/boot/dts/apple/t6021-j475c.dts +++ b/arch/arm64/boot/dts/apple/t6021-j475c.dts @@ -35,3 +35,5 @@ &port01 { &pcie0_dart_1 { status = "okay"; }; + +#include "hwmon-fan-dual.dtsi" diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dts/apple/t6022-j475d.dts index 31f24bbda968..32938a3bf96a 100644 --- a/arch/arm64/boot/dts/apple/t6022-j475d.dts +++ b/arch/arm64/boot/dts/apple/t6022-j475d.dts @@ -44,6 +44,8 @@ &typec5 { label = "USB-C Front Left"; }; +#include "hwmon-fan-dual.dtsi" + /* delete unused USB nodes on die 1 */ /delete-node/ &dwc3_2_dart_0_die1; /delete-node/ &dwc3_2_dart_1_die1; From 23ef479b60e2da14d227ce488583ab31e3ea190c Mon Sep 17 00:00:00 2001 From: Jun Guo Date: Thu, 21 May 2026 15:29:24 +0800 Subject: [PATCH 487/864] arm64: dts: cix: add sky1 DMA-350 node with channel IRQ entries Describe the DMA-350 channel interrupt sources in DT using 8 interrupt entries, while all entries map to the same GIC SPI as wired on this platform. Signed-off-by: Jun Guo Link: https://lore.kernel.org/r/20260521072924.3000282-3-jun.guo@cixtech.com/ Signed-off-by: Gary Yang --- arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index a77c52296ebd..04b17ab866fb 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -514,6 +514,20 @@ iomuxc: pinctrl@4170000 { reg = <0x0 0x04170000 0x0 0x1000>; }; + fch_dmac: dma-controller@4190000 { + compatible = "arm,dma-350"; + reg = <0x0 0x4190000 0x0 0x10000>; + interrupts = , + , + , + , + , + , + , + ; + #dma-cells = <1>; + }; + mbox_ap2se: mailbox@5060000 { compatible = "cix,sky1-mbox"; reg = <0x0 0x05060000 0x0 0x10000>; From 6c4345eb714f094ea579e3234cafed9f8c0634f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:35:09 +0200 Subject: [PATCH 488/864] arm64: dts: amlogic: Correct indentation and whitespace Correct spaces or mix of tabs+spaces into proper tab-indented lines and remove other whitespace violations. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260706093508.273968-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-g12b-a311d.dtsi | 32 +++++++++---------- .../dts/amlogic/meson-gxl-s905d-sml5442tw.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 2 +- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi index f15baa708b36..8254e51d5e27 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi @@ -88,25 +88,25 @@ opp-1800000000 { opp-microvolt = <831000>; }; - opp-1908000000 { - opp-hz = /bits/ 64 <1908000000>; - opp-microvolt = <861000>; - }; + opp-1908000000 { + opp-hz = /bits/ 64 <1908000000>; + opp-microvolt = <861000>; + }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <911000>; - }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <911000>; + }; - opp-2108000000 { - opp-hz = /bits/ 64 <2108000000>; - opp-microvolt = <951000>; - }; + opp-2108000000 { + opp-hz = /bits/ 64 <2108000000>; + opp-microvolt = <951000>; + }; - opp-2208000000 { - opp-hz = /bits/ 64 <2208000000>; - opp-microvolt = <1011000>; - }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <1011000>; + }; }; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts index c490dbbf063b..5913e59ff294 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-sml5442tw.dts @@ -64,7 +64,7 @@ &internal_phy { }; &ir { - linux,rc-map-name = "rc-khamsin"; + linux,rc-map-name = "rc-khamsin"; }; /* This is connected to the Bluetooth module: */ diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index e202d84f0672..d5e0f72892f8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -642,7 +642,7 @@ mux { function = "eth_led"; }; }; - + pwm_a_pins: pwm_a { mux { groups = "pwm_a"; From 77c63ef3be3972eb3d8aac2dd36f349d78620b0d Mon Sep 17 00:00:00 2001 From: Jun Yan Date: Wed, 24 Jun 2026 21:56:41 +0800 Subject: [PATCH 489/864] arm64: dts: amlogic: meson-axg: Disable nfc node by default nand_rb0 and emmc_ds share one pad. Before enabling nand_rb0 for nfc, disable nfc nodes by default to resolve pinctrl resource contention. No mainline AXG boards enable nfc currently thus no extra DTS adjustments are needed. Signed-off-by: Jun Yan Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260624135650.727077-2-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index f1f53fd98ae2..6457667d974e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1999,6 +1999,7 @@ nfc: nand-controller@7800 { clocks = <&clkc CLKID_SD_EMMC_C>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "device"; + status = "disabled"; }; usb2_phy1: phy@9020 { From 45eb76f9ab6854f79690d56d04df227429a536b8 Mon Sep 17 00:00:00 2001 From: Jun Yan Date: Wed, 24 Jun 2026 21:56:42 +0800 Subject: [PATCH 490/864] arm64: dts: amlogic: meson-axg: Add missing nand_rb0 pin to nand_all_pins The nand_all_pins pinctrl node was missing the nand_rb0 (ready/busy) pin description, which is required for NAND controller operation. Add it to the pinmux list. Fixes: be18d53c32b2 ("arm64: dts: amlogic: meson-axg: pinctrl node for NAND") Signed-off-by: Jun Yan Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260624135650.727077-3-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 6457667d974e..8ca3ac09b306 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -481,7 +481,8 @@ mux { "nand_ale", "nand_cle", "nand_wen_clk", - "nand_ren_wr"; + "nand_ren_wr", + "nand_rb0"; function = "nand"; input-enable; bias-pull-up; From 25ab968f7d27f46927658150bf466cac856e4f4f Mon Sep 17 00:00:00 2001 From: Jun Yan Date: Wed, 24 Jun 2026 21:56:43 +0800 Subject: [PATCH 491/864] arm64: dts: amlogic: meson-axg: Disable pcie_phy node by default Set the pcie_phy node to "disabled" as it is not used on some boards and should be enabled per-board when necessary. This change suppresses the deferred probe warning: platform ff644000.phy: deferred probe pending: (reason unknown) The meson-axg dtsi now disables pcie_phy by default, so enable it for the s400 board to support PCIe functionality. Signed-off-by: Jun Yan Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260624135650.727077-4-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 4 ++++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 285c6ac1dd61..7ba249cc3d56 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -448,6 +448,10 @@ &pcieB { status = "okay"; }; +&pcie_phy { + status = "okay"; +}; + &pwm_ab { status = "okay"; pinctrl-0 = <&pwm_a_x20_pins>; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 8ca3ac09b306..5b8ef98f6d03 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -328,6 +328,7 @@ pcie_phy: phy@ff644000 { phys = <&mipi_pcie_analog_dphy>; phy-names = "analog"; #phy-cells = <0>; + status = "disabled"; }; pdm: audio-controller@ff632000 { From 7f1d0cc86cb70fa550163b6f70fd1d484c03218e Mon Sep 17 00:00:00 2001 From: Jun Yan Date: Wed, 24 Jun 2026 21:56:44 +0800 Subject: [PATCH 492/864] arm64: dts: amlogic: meson-axg-s400: enable mipi_pcie_analog_dphy for PCIe The PCIe PHY node references mipi_pcie_analog_dphy via its phys property. Enable this analog PHY node to make PCIe functionally viable. Fixes: 9715b01da6cf ("arm64: dts: meson-axg-s400: enable PCIe M.2 Key E slots") Signed-off-by: Jun Yan Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260624135650.727077-5-jerrysteve1101@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 7ba249cc3d56..4f13e2b041e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -431,6 +431,10 @@ gpio_speaker: gpio-controller@1f { }; }; +&mipi_pcie_analog_dphy { + status = "okay"; +}; + &pdm { pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>, <&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>; From 934cccd2c6795a20d04bd470ec7eb3151950fbfc Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 20 Jul 2026 17:27:57 +0800 Subject: [PATCH 493/864] arm64: dts: mediatek: mt8192-asurada: Disable mmc1 on Spherion Spherion does not have an micro SD card slot. Disable mmc1. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index 163960f58db5..68caf4c58cfe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -64,6 +64,10 @@ &rt5682 { VBAT-supply = <&pp3300_ldo_z>; }; +&mmc1 { + status = "disabled"; +}; + &sound { compatible = "mediatek,mt8192_mt6359_rt1015p_rt5682"; From b68333c76738be779876f0c619dddd4b0a7ddd50 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 16:00:44 -0400 Subject: [PATCH 494/864] dt-bindings: soc: imx: Add fsl,eim-bus Add the fsl,eim-bus compatible strings for i.MX51 variants. These compatibles are only intended for existing legacy chips (more than 15 years old) and will not be used for new device trees. Fix below CHECK_DTBS warnings arch/arm/boot/dts/nxp/imx/imx53-ard.dtb: /eim-cs1@f4000000: failed to match any schema with compatible: ['fsl,eim-bus', 'simple-bus'] Acked-by: Rob Herring (Arm) Signed-off-by: Frank Li --- Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml index 4808065fc911..5e872ddacaab 100644 --- a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -28,6 +28,7 @@ select: enum: - fsl,aipi-bus - fsl,aips + - fsl,eim-bus - fsl,emi - fsl,emi-bus - fsl,spba-bus @@ -36,13 +37,14 @@ select: properties: $nodename: - pattern: "^((spba|emi)-bus|bus)(@[0-9a-f]+)?$" + pattern: "^((spba|emi|eim)-bus|bus)(@[0-9a-f]+)?$" compatible: items: - enum: - fsl,aipi-bus - fsl,aips + - fsl,eim-bus - fsl,emi - fsl,emi-bus - fsl,spba-bus From 9d40f2a740fd64991919d6f58d741a44f736535e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 16:00:45 -0400 Subject: [PATCH 495/864] ARM: dts: imx53-ard: change node name eim-cs1 to eim-cs1-bus Change node name eim-cs1 to eim-cs1-bus to fix below CHECK_DTS warnings: arch/arm/boot/dts/nxp/imx/imx53-ard.dtb: eim-cs1@f4000000 (fsl,eim-bus): $nodename:0: 'eim-cs1@f4000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-ard.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ard.dts b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts index e580427660b1..c19ac3bb0a19 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts @@ -17,7 +17,7 @@ memory@70000000 { reg = <0x70000000 0x40000000>; }; - eim-cs1@f4000000 { + eim-bus@f4000000 { #address-cells = <1>; #size-cells = <1>; compatible = "fsl,eim-bus", "simple-bus"; From 8381098761d85ec09a838c02827df3b1dca8db6b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:26:09 -0400 Subject: [PATCH 496/864] ARM: dts: ls1021a-moxa-uc-8410a: add led suffix to fix CHECK_DTBS warnings Add led suffix to fix below CHECK_DTBS warnings: ls1021a-moxa-uc-8410a.dtb: leds (gpio-leds): 'beeper', ... do not match any of the regexes: '(^led-[0-9a-f]$|led)', '^pinctrl-[0-9]+$' Signed-off-by: Frank Li --- .../boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts index d2cae8c7d7a6..8efe6b615ca8 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts @@ -40,13 +40,13 @@ reg_3p3v: regulator-3p3v { leds { compatible = "gpio-leds"; - cel-pwr { + cel-pwr-led { label = "UC8410A:CEL-PWR"; gpios = <&gpio3 27 GPIO_ACTIVE_LOW>; default-state = "off"; }; - cel-reset { + cel-reset-led { label = "UC8410A:CEL-RESET"; gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; default-state = "off"; @@ -58,13 +58,13 @@ str-led { linux,default-trigger = "mmc0"; }; - sw-ready { + sw-ready-led { label = "UC8410A:GREEN:SWRDY"; gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - beeper { + beeper-led { label = "UC8410A:BEEP"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -88,37 +88,37 @@ prog-led2 { default-state = "off"; }; - wifi-signal0 { + wifi-signal0-led { label = "UC8410A:GREEN:CEL2"; gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - wifi-signal1 { + wifi-signal1-led { label = "UC8410A:GREEN:CEL1"; gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - wifi-signal2 { + wifi-signal2-led { label = "UC8410A:GREEN:CEL0"; gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - cpu-diag-red { + cpu-diag-red-led { label = "UC8410A:RED:DIA"; gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - cpu-diag-green { + cpu-diag-green-led { label = "UC8410A:GREEN:DIA"; gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - cpu-diag-yellow { + cpu-diag-yellow-led { label = "UC8410A:YELLOW:DIA"; gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; default-state = "off"; From 5bd40da5afd7a09a0dfe655b26189197935eb493 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:26:10 -0400 Subject: [PATCH 497/864] ARM: dts: ls1021a-twr: add power-supply for lcd panel Add power-supply for lcd panel to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-twr.dtb: panel (nec,nl4827hc19-05b): 'power-supply' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts index 7341945de3ce..ca5c66c066db 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-twr.dts @@ -61,6 +61,7 @@ simple-audio-card,codec { panel: panel { compatible = "nec,nl4827hc19-05b"; + power-supply = <®_3p3v>; port { panel_in: endpoint { From 09ea402c1c2c5f6bf6ef7b0f00045f91b5e8e926 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:26:11 -0400 Subject: [PATCH 498/864] ARM: dts: ls1021a-moxa-uc-8410a: use compatible string ethernet-phy-ieee802.3-c22 Replace marvell,88e1118 with ethernet-phy-ieee802.3-c22. In drivers/net/mdio/of_mdio.c /* The following is a list of PHY compatible strings which appear in * some DTBs. The compatible string is never matched against a PHY * driver, so is pointless. We only expect devices which are not PHYs * to have a compatible string, so they can be matched to an MDIO * driver. Encourage users to upgrade their DT blobs to remove these. */ static const struct of_device_id whitelist_phys[] Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dtb: /soc/mdio@2d24000/ethernet-phy@0: failed to match any schema with compatible: ['marvell,88e1118'] No other known DTB user this dts file. Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts index 8efe6b615ca8..5b652a45bb9a 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts @@ -176,7 +176,7 @@ &lpuart0 { &mdio0 { rgmii_phy0: ethernet-phy@0 { - compatible = "marvell,88e1118"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; marvell,reg-init = <3 0x11 0 0x4415>, /* Reg 3,17 */ @@ -184,7 +184,7 @@ rgmii_phy0: ethernet-phy@0 { }; rgmii_phy1: ethernet-phy@1 { - compatible = "marvell,88e1118"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x1>; marvell,reg-init = <3 0x11 0 0x4415>, /* Reg 3,17 */ @@ -192,7 +192,7 @@ rgmii_phy1: ethernet-phy@1 { }; rgmii_phy2: ethernet-phy@2 { - compatible = "marvell,88e1118"; + compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x2>; marvell,reg-init = <3 0x11 0 0x4415>, /* Reg 3,17 */ From b5a62376f6f0a3dbf585c9007aa1b196022435f9 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:26:12 -0400 Subject: [PATCH 499/864] ARM: dts: ls1021a-moxa-uc-8410a: replace spansion,s25fl164k with jedec,spi-nor spansion,s25fl164k (drivers/mtd/spi-nor/spansion.c) can be identified with the READ ID opcode (0x9F). Replace spansion,s25fl164k with jedec,spi-nor to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dtb: /soc/spi@1550000/flash@0: failed to match any schema with compatible: ['spansion,s25fl064l', 'spansion,s25fl164k'] So no other known DTB user this dts file and it is fine to broken potential back compatibility since spansion,s25fl164k already support by use jedec,spi-nor since 2015 commit 413780d7d7040 ("mtd: spi-nor: Add support for Spansion S25FL164K") Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts index 5b652a45bb9a..b2a87ef23c8e 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts @@ -204,7 +204,7 @@ &qspi { status = "okay"; flash: flash@0 { - compatible = "spansion,s25fl064l", "spansion,s25fl164k"; + compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; From b022b074d615aa04abf3d73ec497c88d7ce09a9d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:26:13 -0400 Subject: [PATCH 500/864] ARM: dts: ls1021a-moxa-uc-8410a: remove undocument property default-state of gpio-keys default-state = "on" is wrong copied from gpio-leds nodes. Remove it to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dtb: gpio-keys (gpio-keys): pushbtn-key: Unevaluated properties are not allowed ('default-state' was unexpected) from schema $id: http://devicetree.org/schemas/input/gpio-keys.yaml Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts index b2a87ef23c8e..ad83d8814fbb 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-moxa-uc-8410a.dts @@ -132,7 +132,6 @@ pushbtn-key { label = "push button key"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; linux,code = ; - default-state = "on"; }; }; }; From b8d669c5805736a7664524ec625425111863eec0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 16:08:30 -0400 Subject: [PATCH 501/864] ARM: dts: imx6dl-plym2m: change #io-channel-cells to 1 of voltage divider Change #io-channel-cells to 1 of voltage divider to fix below CHENCK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dtb: voltage-divider-vaccu (voltage-divider): #io-channel-cells: 1 was expected from schema $id: http://devicetree.org/schemas/iio/afe/voltage-divider.yaml Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts index fbff77944ce3..635c5a1e1fc7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-plym2m.dts @@ -52,7 +52,7 @@ display_out: endpoint { iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&vdiv_vaccu>; + io-channels = <&vdiv_vaccu 0>; }; leds { @@ -187,7 +187,7 @@ vdiv_vaccu: voltage-divider-vaccu { io-channels = <&adc_ts 2>; output-ohms = <2500>; full-ohms = <64000>; - #io-channel-cells = <0>; + #io-channel-cells = <1>; }; }; From aa5c8f1b5ee936661058455480e6e843fdf1d5b7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 16:08:31 -0400 Subject: [PATCH 502/864] ARM: dts: imx53-smd: remove undocument property clock-names of ovti,ov5642 Remove undocument properties ovti,ov5642 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx53-smd.dtb: ov5642@3c (ovti,ov5642): 'clock-names' does not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/media/i2c/ovti,ov5642.yaml Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-smd.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts index 8c02731c7ba9..29d38484cd38 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts @@ -306,7 +306,6 @@ camera: ov5642@3c { <&clks IMX5_CLK_SSI_EXT1_PODF>; assigned-clock-rates = <0>, <24000000>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; - clock-names = "xclk"; DVDD-supply = <&ldo9_reg>; AVDD-supply = <&ldo7_reg>; reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; From 5af3e703f2604f7a3bc44422c1d30b128aa49f7c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 16:08:32 -0400 Subject: [PATCH 503/864] ARM: dts: imx6ul-isiot: remove undocument property clock-names of fsl,sgtl5000 Remove undocument property clock-names of fsl,sgtl5000 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ul-isiot-nand.dtb: codec@a (fsl,sgtl5000): Unevaluated properties are not allowed ('clock-names' was unexpected) from schema $id: http://devicetree.org/schemas/sound/fsl,sgtl5000.yaml Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi index e34c8cbe36ae..2e3a71f94f31 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi @@ -116,7 +116,6 @@ sgtl5000: codec@a { reg = <0x0a>; #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_OSC>; - clock-names = "mclk"; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; VDDD-supply = <®_1p8v>; From 12ed4b9ab36a84a5082e13004d799c0d70200382 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 16:08:33 -0400 Subject: [PATCH 504/864] ARM: dts: imx6ull-engicam-microgea: remove nand-ecc-strength and nand-ecc-step-size The nand-ecc-strength and nand-ecc-step-size is bigger than 0. It doesn't make sense to set to 0. Remove it to fix below DTB_CHECKS warnings: arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): nand-ecc-strength: 0 is less than the minimum of 1 Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi index 43518bf07602..2c36c248f6bd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi @@ -44,8 +44,6 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; nand-ecc-mode = "hw"; - nand-ecc-strength = <0>; - nand-ecc-step-size = <0>; nand-on-flash-bbt; status = "okay"; }; From d879cc948e6f7046af65c867a496bc9cde1da8ef Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:43 -0400 Subject: [PATCH 505/864] arm64: dts: imx8qm-ss-dma: add lpuart4 node Add lpuart4 node for imx8qm. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 974e193f8dcb..738c6f05c4ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -8,6 +8,21 @@ /delete-node/ &adma_pwm_lpcg; &dma_subsys { + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + reg = <0x5a0a0000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart4_lpcg IMX_LPCG_CLK_4>, <&uart4_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_4>; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx","tx"; + status = "disabled"; + }; + uart4_lpcg: clock-controller@5a4a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a4a0000 0x10000>; From f57bf4c11d7fa95afaea45a14d91b067406c60f0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:44 -0400 Subject: [PATCH 506/864] arm64: dts: imx8qm-ss-audio: add spdif1 node Add spdif1 and related lpcg node for imx8qm. Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-ss-audio.dtsi | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi index 7c5386d4ab2b..5cb644837d93 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -74,6 +74,31 @@ &asrc1_lpcg { }; &audio_subsys { + spdif1: spdif@59030000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x59030000 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&spdif1_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif1_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 10 0 5>, <&edma0 11 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; sai4: sai@59080000 { compatible = "fsl,imx8qm-sai"; @@ -109,6 +134,19 @@ sai5: sai@59090000 { status = "disabled"; }; + spdif1_lpcg: clock-controller@59430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59430000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "spdif1_lpcg_tx_clk", + "spdif1_lpcg_gclkw"; + power-domains = <&pd IMX_SC_R_SPDIF_1>; + status = "disabled"; + }; + sai4_lpcg: clock-controller@59480000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x59480000 0x10000>; From 617bcacbf0905d2ac25c1fe6d2ab45afc4f9fc3c Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:45 -0400 Subject: [PATCH 507/864] arm64: dts: imx8qm-ss-lsio: add lsio mu8 and mu8b Add mu8 and mu8b mailbox nodes. Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-ss-lsio.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index b483134f84d1..e055d41f77cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -3,6 +3,27 @@ * Copyright 2019-2020 NXP * Dong Aisheng */ +&lsio_subsys { + lsio_mu8: mailbox@5d230000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d230000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_8A>; + status = "disabled"; + }; + + lsio_mu8b: mailbox@5d2c0000 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; + reg = <0x5d2c0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + fsl,mu-side-b; + power-domains = <&pd IMX_SC_R_MU_8B>; + status = "disabled"; + }; + +}; &lsio_gpio0 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; From 8563591f76ca02c1a6fd70ce986df1d0dde8d249 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 9 Jul 2026 16:29:46 -0400 Subject: [PATCH 508/864] arm64: dts: imx8-ss-audio: Fix LPCG clock indices for ASRC0 The LPCG clock indices for ASRC0 and AUD_PLL_DIV0 are swapped. The ASRC0 LPCG provides only IMX_LPCG_CLK_4, so update the ASRC0 clock consumer to use IMX_LPCG_CLK_4 instead of the non-existent IMX_LPCG_CLK_0. Likewise, the AUD_PLL_DIV0 LPCG provides only IMX_LPCG_CLK_0, so update its clock consumer to use IMX_LPCG_CLK_0 instead of the non-existent IMX_LPCG_CLK_4. Fixes: 5125617c7a4d3 ("arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif0 and sai[4,5]") Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 5e4233ccfde4..f473d81f67ff 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -124,10 +124,10 @@ asrc0: asrc@59000000 { compatible = "fsl,imx8qm-asrc"; reg = <0x59000000 0x10000>; interrupts = ; - clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, - <&asrc0_lpcg IMX_LPCG_CLK_0>, - <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, - <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, + clocks = <&asrc0_lpcg IMX_LPCG_CLK_4>, + <&asrc0_lpcg IMX_LPCG_CLK_4>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, <&clk_dummy>, From 174b7dfb7dce9017e482c1fb2aa04ed28a141936 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 13 Jul 2026 11:19:21 +0200 Subject: [PATCH 509/864] dt-bindings: arm: add MBa93xxCA as mainboard for TQMa91xxCA and TQMa91xxLA SOM TQMa91xxLA and TQMa91xxCA are two series of feature compatible SOM using NXP i.MX91 SoC in 11x11 mm package. MBa93xxCA is a starterkit base board usable for TQMa91xxCA and TQMa91xxLA soldered on an adapter board to demonstrate use cases without display but more interfaces. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Acked-by: Conor Dooley Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 52f08bc1f8ea..656f2596e1d5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1619,11 +1619,13 @@ properties: in the assembled SOC. MBa91xxCA mainboard can be used as starterkit for the SOM soldered on an adapter board or for the connector variant - MBa91xxLA mainboard is a single board computer using the solderable - SOM variant + to demonstrate parallel display and majority of interfaces while + MBa93xxCA starterkit mainboard is focused on communication + interfaces without display support. items: - enum: - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA + - tq,imx91-tqma9131-mba93xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa93xxCA - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM - const: fsl,imx91 From 4d0d3a3d1993a41b2bf8d28aa6c6071fa1a3bff7 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 13 Jul 2026 11:19:22 +0200 Subject: [PATCH 510/864] arm64: dts: add devicetree for TQMa91xx on MBa93xxCA This allows using TQMa91xxCA / TQMa91xxLA SoM on MBa93xxCA starter kit. While not having display all other interfaces of this mainboard can be used. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx91-tqma9131-mba93xxca.dts | 937 ++++++++++++++++++ 2 files changed, 938 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b60b43071936..d5c2dc720197 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -586,6 +586,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba93xxca.dtb imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts new file mode 100644 index 000000000000..3fb5bb71b622 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts @@ -0,0 +1,937 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include +#include +#include +#include + +#include "imx91-tqma9131.dtsi" + +/{ + model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa93xxCA starter kit"; + compatible = "tq,imx91-tqma9131-mba93xxca", + "tq,imx91-tqma9131", "fsl,imx91"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + ethernet0 = &eqos; + ethernet1 = &fec; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial5 = &lpuart6; + serial7 = &lpuart8; + }; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + status = "disabled"; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwmfan>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = ; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = ; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_12v0>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + cpu_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&cpu_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&cpu_active2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + /* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#", + /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = + /* 00 */ "SPI6_PCS0#", "", "", "", + /* 04 */ "", "", "", "SPI_CS#", + /* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC", + /* 12 */ "", "", "", "", + /* 16 */ "X1_11", "X1_21", "X1_17", "X1_13", + /* 20 */ "X1_15", "X1_9", "", "", + /* 24 */ "", "", "X1_7", "", + /* 28 */ "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + /* 00 */ "SD2_CD#", "", "", "", + /* 04 */ "", "", "", "SD2_RST#", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", + /* 28 */ "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + /* 00 */ "", "", "", "", + /* 04 */ "", "", "", "", + /* 08 */ "", "", "", "", + /* 12 */ "", "", "", "", + /* 16 */ "", "", "", "", + /* 20 */ "", "", "", "", + /* 24 */ "", "", "", "", + /* 28 */ "", "DP_INT", "", ""; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + ptn5110: usb-typec@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + label = "X17"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + typec-power-opmode = "default"; + pd-disable; + self-powered; + + port { + typec_con_hs: endpoint { + remote-endpoint = <&typec_hs>; + }; + }; + }; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + mpcie-wake-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card's low-active power down pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card's low-active disable pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card's reset pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "DP_EN", + "MIPI_CSI_EN", "MIPI_CSI_RST#", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + toshiba,hpd-pin = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp_dsi_in: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + }; + }; +}; + +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&se97_som { + /* TEMP_EVENT# from SoM is connected on mainboard */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_temp_sensor_som>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; + +/* on LVDS connector, not usable */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + typec_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2517"; + reg = <1>; + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000 + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000 + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000 + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000 + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000 + /* HYS | PD | FSEL_0 | DSE no drive */ + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400 + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = < + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e + /* SION | HYS | FSEL_2 | DSE X4 */ + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000 + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000 + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000 + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000 + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000 + /* HYS | PD | FSEL_0 | DSE no drive */ + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400 + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = < + /* HYS | FSEL_0 | DSE no drive */ + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + /* HYS | PU | FSEL_0 | DSE no drive */ + MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200 + /* PU | FSEL_3 | DSE X4 */ + MX91_PAD_PDM_CLK__CAN1_TX 0x039e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + /* HYS | PU | FSEL_0 | DSE no drive */ + MX91_PAD_GPIO_IO27__CAN2_RX 0x1200 + /* PU | FSEL_3 | DSE X4 */ + MX91_PAD_GPIO_IO25__CAN2_TX 0x039e + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + /* HYS | PD | FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x151e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x151e + MX91_PAD_GPIO_IO18__GPIO2_IO18 0x151e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x151e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x151e + MX91_PAD_GPIO_IO21__GPIO2_IO21 0x151e + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x151e + >; + }; + + pinctrl_jtag: jtaggrp { + fsl,pins = < + MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e + MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200 + MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e + MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200 + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + /* SION | HYS | OD | FSEL_3 | DSE X4 */ + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + /* SION | HYS | OD | FSEL_3 | DSE X4 */ + MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e + MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e + >; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + /* HYS | PD | FSEL_0 | DSE no drive */ + MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x1400 + /* PD | FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e + MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x051e + >; + }; + + pinctrl_lpspi6_cs: lpspi6csgrp { + fsl,pins = < + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO00__GPIO2_IO0 0x011e + MX91_PAD_GPIO_IO07__GPIO2_IO7 0x011e + >; + }; + + pinctrl_mipi_csi: mipicsigrp { + fsl,pins = < + MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */ + MX91_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */ + MX91_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */ + >; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = < + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 + >; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000 + >; + }; + + pinctrl_pwmfan: pwmfangrp { + fsl,pins = < + /* HYS | PU | FSEL_0 | no DSE */ + MX91_PAD_GPIO_IO09__GPIO2_IO9 0x1200 + >; + }; + + pinctrl_tc9595: tc9595-grp { + fsl,pins = < + /* HYS | PD | FSEL_0 | no DSE */ + MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 + >; + }; + + pinctrl_temp_sensor_som: tempsensorsomgrp { + fsl,pins = < + /* HYS | FSEL_0 | no DSE */ + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 + >; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = < + MX91_PAD_GPIO_IO06__TPM5_CH0 0x57e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + MX91_PAD_GPIO_IO08__TPM6_CH0 0x57e + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_I2C2_SCL__GPIO1_IO2 0x1000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_UART1_RXD__LPUART1_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_UART1_TXD__LPUART1_TX 0x011e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_UART2_RXD__LPUART2_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_UART2_TXD__LPUART2_TX 0x011e + /* FSEL_2 | DSE X4 */ + MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_GPIO_IO15__LPUART3_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO14__LPUART3_TX 0x011e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_GPIO_IO05__LPUART6_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO04__LPUART6_TX 0x011e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_GPIO_IO13__LPUART8_RX 0x1000 + /* FSEL_2 | DSE X4 */ + MX91_PAD_GPIO_IO12__LPUART8_TX 0x011e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + /* HYS | FSEL_0 | No DSE */ + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000 + >; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = < + /* PD | FSEL_3 | DSE X5 */ + MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be + /* HYS | PU | FSEL_3 | DSE X4 */ + MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + /* HYS | PU | FSEL_3 | DSE X3 */ + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + /* FSEL_2 | DSE X3 */ + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e + >; + }; + + /* enable SION for data and cmd pad due to ERR052021 */ + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = < + /* PD | FSEL_3 | DSE X6 */ + MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe + /* HYS | PU | FSEL_3 | DSE X4 */ + MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e + /* FSEL_2 | DSE X3 */ + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e + >; + }; +}; From 959393e81cf1fe7f2a75d639b90cd7c816103f25 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:22 +0200 Subject: [PATCH 511/864] dt-bindings: firmware: xilinx: Add missing example for ZynqMP Document clock-controller under zynqmp-firmware in the binding example so ZynqMP DTs validate against xlnx,versal-clk.yaml (Versal example already did). Acked-by: Conor Dooley Link: https://patch.msgid.link/12dba601a8b631e565dd98e52a89b0ec18fcdce2.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index d50438b0fca8..680082c29f01 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -132,6 +132,14 @@ examples: zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; nvmem-layout { From 6e32cb10cf32e60cf40ad0baa37c54969f10101f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:23 +0200 Subject: [PATCH 512/864] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins), but a regex character class cannot express a multi-digit decimal range. Replace the bogus character class with an explicit alternation that enumerates the two-digit decimal values 00..77. Fixes: 03d4a1004053 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml") Acked-by: Conor Dooley Link: https://patch.msgid.link/e742b7da70c2bf10650a81e537f1b90d76799416.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index bef109d163a8..b1623c2ab0f6 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -116,7 +116,7 @@ allOf: - const: pss_alt_ref_clk - const: aux_ref_clk - const: gt_crx_ref_clk - - pattern: "^mio_clk[00-77]+.*$" + - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" - pattern: "gem[0-3]+_emio_clk.*$" - pattern: "swdt[0-1]+_ext_clk.*$" From d0d3f0f8aed45c93802e79e8a0dd959d538a49fa Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:24 +0200 Subject: [PATCH 513/864] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema The ZynqMP clock controller binding shares only #clock-cells with the Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema. Also remove "(Optional clock)" from clock description because it is visible from schema itself. Also update versal-firmware example to match changes in xlnx,zynqmp-firmware.yaml. Suggested-by: Rob Herring Acked-by: Conor Dooley Link: https://patch.msgid.link/973a8a5441cf13622594b95dd0dd20a5f42ccece.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/clock/xlnx,versal-clk.yaml | 54 ++------------- .../bindings/clock/xlnx,zynqmp-clk.yaml | 68 +++++++++++++++++++ .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +- 3 files changed, 78 insertions(+), 51 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index b1623c2ab0f6..7b6d9ec83863 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -17,9 +17,7 @@ description: | properties: compatible: oneOf: - - enum: - - xlnx,versal-clk - - xlnx,zynqmp-clk + - const: xlnx,versal-clk - items: - enum: - xlnx,versal-net-clk @@ -32,11 +30,11 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 8 + maxItems: 3 clock-names: minItems: 2 - maxItems: 8 + maxItems: 3 required: - compatible @@ -87,44 +85,11 @@ allOf: - const: pl_alt_ref - const: alt_ref - - if: - properties: - compatible: - contains: - enum: - - xlnx,zynqmp-clk - - then: - properties: - clocks: - minItems: 5 - items: - - description: PS reference clock - - description: reference clock for video system - - description: alternative PS reference clock - - description: auxiliary reference clock - - description: transceiver reference clock - - description: (E)MIO clock source (Optional clock) - - description: GEM emio clock (Optional clock) - - description: Watchdog external clock (Optional clock) - - clock-names: - minItems: 5 - items: - - const: pss_ref_clk - - const: video_clk - - const: pss_alt_ref_clk - - const: aux_ref_clk - - const: gt_crx_ref_clk - - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" - - pattern: "gem[0-3]+_emio_clk.*$" - - pattern: "swdt[0-1]+_ext_clk.*$" - examples: - | firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; + versal-firmware { + compatible = "xlnx,versal-firmware"; method = "smc"; versal_clk: clock-controller { #clock-cells = <1>; @@ -134,13 +99,4 @@ examples: }; }; }; - - clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, - <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", - "aux_ref_clk", "gt_crx_ref_clk"; - }; ... diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml new file mode 100644 index 000000000000..c64550471581 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP clock controller + +maintainers: + - Michal Simek + +description: + The clock controller is a hardware block of Xilinx ZynqMP clock tree. It + reads required input clock frequencies from the devicetree and acts as clock + provider for all clock consumers of PS clocks. + +properties: + compatible: + const: xlnx,zynqmp-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + minItems: 5 + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + - description: (E)MIO clock source + - description: GEM emio clock + - description: Watchdog external clock + + clock-names: + minItems: 5 + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" + - pattern: "gem[0-3]+_emio_clk.*$" + - pattern: "swdt[0-1]+_ext_clk.*$" + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index 680082c29f01..72af37cdb103 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -48,8 +48,7 @@ properties: const: 1 clock-controller: - $ref: /schemas/clock/xlnx,versal-clk.yaml# - description: The clock controller is a hardware block of Xilinx versal + description: The clock controller is a hardware block of Xilinx SoC clock tree. It reads required input clock frequencies from the devicetree and acts as clock provider for all clock consumers of PS clocks.list of clock specifiers which are external input clocks to the given clock @@ -113,10 +112,14 @@ allOf: const: xlnx,zynqmp-firmware then: properties: + clock-controller: + $ref: /schemas/clock/xlnx,zynqmp-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# else: properties: + clock-controller: + $ref: /schemas/clock/xlnx,versal-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,versal-pinctrl.yaml# From 7dc3776a5f98463e6c332d3a62d5021ffa3a4004 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:25 +0200 Subject: [PATCH 514/864] dt-bindings: clock: versal-clk: Fix Versal NET clock validation The Versal NET clock controller compatible is specified as: compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; with xlnx,versal-clk listed as fallback. The original binding had two separate if/then blocks - one matching xlnx,versal-clk (2 clocks) and another matching xlnx,versal-net-clk (3 clocks). Since both compatible strings are present, both conditions matched simultaneously and JSON Schema applied the more restrictive 2-clock constraint, causing false "too long" validation errors for Versal NET. Define clock-names at the top-level and use if/then only to constrain the clock count (2 for Versal, 3 for Versal NET). Add a dedicated example for the Versal NET 3-clock configuration. Fixes: 39118392d19a ("dt-bindings: Remove alt_ref from versal") Acked-by: Conor Dooley Link: https://patch.msgid.link/202e448e57cf979e1b5be61da0bad7778defdd4e.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../bindings/clock/xlnx,versal-clk.yaml | 55 ++++++++----------- 1 file changed, 24 insertions(+), 31 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 7b6d9ec83863..1f36ccc4cde1 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -30,11 +30,17 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 3 + items: + - description: reference clock + - description: alternate reference clock for programmable logic + - description: alternate reference clock clock-names: minItems: 2 - maxItems: 3 + items: + - const: ref + - const: pl_alt_ref + - const: alt_ref required: - compatible @@ -45,45 +51,24 @@ required: additionalProperties: false allOf: - - if: - properties: - compatible: - contains: - enum: - - xlnx,versal-clk - - then: - properties: - clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - clock-names: - items: - - const: ref - - const: pl_alt_ref - - if: properties: compatible: contains: enum: - xlnx,versal-net-clk - then: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - description: alternate reference clock - + minItems: 3 clock-names: - items: - - const: ref - - const: pl_alt_ref - - const: alt_ref + minItems: 3 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 examples: - | @@ -99,4 +84,12 @@ examples: }; }; }; + + - | + clock-controller { + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; + clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>; + clock-names = "ref", "pl_alt_ref", "alt_ref"; + #clock-cells = <1>; + }; ... From e1ab33a3b2892f56102ce90b20d2445847e758a5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 8 Jul 2026 15:12:26 +0200 Subject: [PATCH 515/864] arm64: versal-net: Switch Versal NET to firmware clock interface Switch Versal NET from using fixed clocks to the firmware-based clock interface (versal-net-clk.dtsi). This enables proper clock management through the platform firmware instead of relying on static fixed-clock definitions. Add DT macro headers for Versal NET and base Versal clocks, power domains and mandatory resets required by the clock dtsi. Link: https://patch.msgid.link/77e6234f6cef3f78fb1c6c97142fa8055982e14e.1783516336.git.michal.simek@amd.com Signed-off-by: Michal Simek --- .../arm64/boot/dts/xilinx/versal-net-clk.dtsi | 351 +++++++++++++----- arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h | 123 ++++++ .../boot/dts/xilinx/xlnx-versal-net-clk.h | 74 ++++ .../boot/dts/xilinx/xlnx-versal-net-power.h | 38 ++ .../boot/dts/xilinx/xlnx-versal-net-resets.h | 53 +++ .../arm64/boot/dts/xilinx/xlnx-versal-power.h | 55 +++ .../boot/dts/xilinx/xlnx-versal-resets.h | 106 ++++++ 7 files changed, 698 insertions(+), 102 deletions(-) create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h diff --git a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi index b7a8a1a512cb..d3a27da90090 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi @@ -1,72 +1,52 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx Versal NET fixed clock + * dts file for Xilinx Versal NET with PM * - * (C) Copyright 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek */ +#include +#include +#include "xlnx-versal-net-clk.h" +#include "xlnx-versal-net-power.h" +#include "xlnx-versal-net-resets.h" + / { - clk60: clk60 { + ref_clk: clock-33333333 { compatible = "fixed-clock"; + bootph-all; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; #clock-cells = <0>; - clock-frequency = <60000000>; }; - clk100: clk100 { + rtc_clk: clock-32768 { compatible = "fixed-clock"; + bootph-all; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; #clock-cells = <0>; - clock-frequency = <100000000>; }; - clk125: clk125 { - compatible = "fixed-clock"; + can0_clk: can0-clk { + compatible = "fixed-factor-clock"; + clocks = <&versal_net_clk CAN0_REF_2X>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "can0_clk"; #clock-cells = <0>; - clock-frequency = <125000000>; }; - clk150: clk150 { - compatible = "fixed-clock"; + can1_clk: can1-clk { + compatible = "fixed-factor-clock"; + clocks = <&versal_net_clk CAN1_REF_2X>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "can1_clk"; #clock-cells = <0>; - clock-frequency = <150000000>; - }; - - clk160: clk160 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <160000000>; - }; - - clk200: clk200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - }; - - clk250: clk250 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - }; - - clk300: clk300 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <300000000>; - }; - - clk450: clk450 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <450000000>; - }; - - clk1200: clk1200 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1200000000>; }; firmware { @@ -74,158 +54,325 @@ versal_net_firmware: versal-net-firmware { compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; bootph-all; method = "smc"; + #power-domain-cells = <1>; + + versal_net_reset: reset-controller { + compatible = "xlnx,versal-net-reset"; + #reset-cells = <1>; + }; + + versal_net_clk: clock-controller { + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; + bootph-all; + clocks = <&ref_clk>, <&ref_clk>, <&ref_clk>; + clock-names = "ref", "pl_alt_ref", "alt_ref"; + #clock-cells = <1>; + }; + + versal_net_power: power-management { + compatible = "xlnx,zynqmp-power"; + mboxes = <&ipi_mailbox_pmu1 0>, + <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; + }; + }; + }; + + zynqmp-ipi { + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = ; + xlnx,ipi-id = <2>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ipi_mailbox_pmu1: mailbox@eb3f0440 { + compatible = "xlnx,zynqmp-ipi-dest-mailbox"; + reg = <0 0xeb3f0440 0 0x20>, + <0 0xeb3f0460 0 0x20>, + <0 0xeb3f0280 0 0x20>, + <0 0xeb3f02a0 0 0x20>; + reg-names = "local_request_region", "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <1>; }; }; }; -&adma0 { - clocks = <&clk450>, <&clk450>; +&cpu0 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma1 { - clocks = <&clk450>, <&clk450>; +&cpu100 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma2 { - clocks = <&clk450>, <&clk450>; +&cpu200 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma3 { - clocks = <&clk450>, <&clk450>; +&cpu300 { + clocks = <&versal_net_clk ACPU_0>; }; -&adma4 { - clocks = <&clk450>, <&clk450>; +&cpu10000 { + clocks = <&versal_net_clk ACPU_1>; }; -&adma5 { - clocks = <&clk450>, <&clk450>; +&cpu10100 { + clocks = <&versal_net_clk ACPU_1>; }; -&adma6 { - clocks = <&clk450>, <&clk450>; +&cpu10200 { + clocks = <&versal_net_clk ACPU_1>; }; -&adma7 { - clocks = <&clk450>, <&clk450>; +&cpu10300 { + clocks = <&versal_net_clk ACPU_1>; +}; + +&cpu20000 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu20100 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu20200 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu20300 { + clocks = <&versal_net_clk ACPU_2>; +}; + +&cpu30000 { + clocks = <&versal_net_clk ACPU_3>; +}; + +&cpu30100 { + clocks = <&versal_net_clk ACPU_3>; +}; + +&cpu30200 { + clocks = <&versal_net_clk ACPU_3>; +}; + +&cpu30300 { + clocks = <&versal_net_clk ACPU_3>; }; &can0 { - clocks = <&clk160>, <&clk160>; + clocks = <&can0_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_CAN_FD_0>; }; &can1 { - clocks = <&clk160>, <&clk160>; + clocks = <&can1_clk>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_CAN_FD_1>; }; &gem0 { - clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; + clocks = <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM0_REF>, <&versal_net_clk GEM0_TX>, + <&versal_net_clk GEM0_RX>, <&versal_net_clk GEM_TSU>; + power-domains = <&versal_net_firmware PM_DEV_GEM_0>; }; &gem1 { - clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; + clocks = <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk GEM1_REF>, <&versal_net_clk GEM1_TX>, + <&versal_net_clk GEM1_RX>, <&versal_net_clk GEM_TSU>; + power-domains = <&versal_net_firmware PM_DEV_GEM_1>; }; &gpio0 { - clocks = <&clk100>; + clocks = <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_GPIO>; }; &gpio1 { - clocks = <&clk100>; + clocks = <&versal_net_clk PMC_LSBUS_REF>; + power-domains = <&versal_net_firmware PM_DEV_GPIO_PMC>; }; &i2c0 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C0_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i2c1 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C1_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; &i3c0 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C0_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_0>; }; &i3c1 { - clocks = <&clk100>; + clocks = <&versal_net_clk I3C1_REF>; + power-domains = <&versal_net_firmware PM_DEV_I2C_1>; }; -&ospi { - clocks = <&clk200>; +&adma0 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_0>; +}; + +&adma1 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_1>; +}; + +&adma2 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_2>; +}; + +&adma3 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_3>; +}; + +&adma4 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_4>; +}; + +&adma5 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_5>; +}; + +&adma6 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_6>; +}; + +&adma7 { + clocks = <&versal_net_clk ADMA>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_ADMA_7>; }; &qspi { - clocks = <&clk300>, <&clk300>; + clocks = <&versal_net_clk QSPI_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_QSPI>; +}; + +&ospi { + clocks = <&versal_net_clk OSPI_REF>; + power-domains = <&versal_net_firmware PM_DEV_OSPI>; }; &rtc { - /* Nothing */ -}; - -&sdhci0 { - clocks = <&clk200>, <&clk200>, <&clk1200>; -}; - -&sdhci1 { - clocks = <&clk200>, <&clk200>, <&clk1200>; + clocks = <&rtc_clk>; + clock-names = "rtc"; + power-domains = <&versal_net_firmware PM_DEV_RTC>; }; &serial0 { - clocks = <&clk100>, <&clk100>; + clocks = <&versal_net_clk UART0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_UART_0>; }; &serial1 { - clocks = <&clk100>, <&clk100>; + clocks = <&versal_net_clk UART1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_UART_1>; +}; + +&sdhci0 { + clocks = <&versal_net_clk SDIO0_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains = <&versal_net_firmware PM_DEV_SDIO_0>; +}; + +&sdhci1 { + clocks = <&versal_net_clk SDIO1_REF>, <&versal_net_clk LPD_LSBUS>, + <&versal_net_clk SD_DLL_REF>; + power-domains = <&versal_net_firmware PM_DEV_SDIO_1>; }; &spi0 { - clocks = <&clk200>, <&clk200>; + clocks = <&versal_net_clk SPI0_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_SPI_0>; }; &spi1 { - clocks = <&clk200>, <&clk200>; + clocks = <&versal_net_clk SPI1_REF>, <&versal_net_clk LPD_LSBUS>; + power-domains = <&versal_net_firmware PM_DEV_SPI_1>; }; &ttc0 { - clocks = <&clk150>; + clocks = <&versal_net_clk TTC0>; + power-domains = <&versal_net_firmware PM_DEV_TTC_0>; +}; + +&ttc1 { + clocks = <&versal_net_clk TTC1>; + power-domains = <&versal_net_firmware PM_DEV_TTC_1>; +}; + +&ttc2 { + clocks = <&versal_net_clk TTC2>; + power-domains = <&versal_net_firmware PM_DEV_TTC_2>; +}; + +&ttc3 { + clocks = <&versal_net_clk TTC3>; + power-domains = <&versal_net_firmware PM_DEV_TTC_3>; }; &usb0 { - clocks = <&clk60>, <&clk60>; + clocks = <&versal_net_clk USB0_BUS_REF>, <&versal_net_clk USB0_BUS_REF>; + power-domains = <&versal_net_firmware PM_DEV_USB_0>; + resets = <&versal_net_reset VERSAL_RST_USB_0>; }; &dwc3_0 { - clocks = <&clk60>; + clocks = <&versal_net_clk USB0_BUS_REF>; }; &usb1 { - clocks = <&clk60>, <&clk60>; + clocks = <&versal_net_clk USB1_BUS_REF>, <&versal_net_clk USB1_BUS_REF>; + power-domains = <&versal_net_firmware PM_DEV_USB_1>; + resets = <&versal_net_reset VERSAL_RST_USB_1>; }; &dwc3_1 { - clocks = <&clk60>; + clocks = <&versal_net_clk USB1_BUS_REF>; }; &wwdt0 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT0>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_0>; }; &wwdt1 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT1>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_1>; }; &wwdt2 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT2>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_2>; }; &wwdt3 { - clocks = <&clk150>; + clocks = <&versal_net_clk FPD_WWDT3>; + power-domains = <&versal_net_firmware PM_DEV_FPD_SWDT_3>; }; &lpd_wwdt0 { - clocks = <&clk150>; + clocks = <&versal_net_clk LPD_WWDT0>; + power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_0>; }; &lpd_wwdt1 { - clocks = <&clk150>; + clocks = <&versal_net_clk LPD_WWDT1>; + power-domains = <&versal_net_firmware PM_DEV_LPD_SWDT_1>; }; diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h new file mode 100644 index 000000000000..d0c4abf78f30 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_CLK_H +#define _XLNX_VERSAL_CLK_H + +#define PMC_PLL 1 +#define APU_PLL 2 +#define RPU_PLL 3 +#define CPM_PLL 4 +#define NOC_PLL 5 +#define PLL_MAX 6 +#define PMC_PRESRC 7 +#define PMC_POSTCLK 8 +#define PMC_PLL_OUT 9 +#define PPLL 10 +#define NOC_PRESRC 11 +#define NOC_POSTCLK 12 +#define NOC_PLL_OUT 13 +#define NPLL 14 +#define APU_PRESRC 15 +#define APU_POSTCLK 16 +#define APU_PLL_OUT 17 +#define APLL 18 +#define RPU_PRESRC 19 +#define RPU_POSTCLK 20 +#define RPU_PLL_OUT 21 +#define RPLL 22 +#define CPM_PRESRC 23 +#define CPM_POSTCLK 24 +#define CPM_PLL_OUT 25 +#define CPLL 26 +#define PPLL_TO_XPD 27 +#define NPLL_TO_XPD 28 +#define APLL_TO_XPD 29 +#define RPLL_TO_XPD 30 +#define EFUSE_REF 31 +#define SYSMON_REF 32 +#define IRO_SUSPEND_REF 33 +#define USB_SUSPEND 34 +#define SWITCH_TIMEOUT 35 +#define RCLK_PMC 36 +#define RCLK_LPD 37 +#define WDT 38 +#define TTC0 39 +#define TTC1 40 +#define TTC2 41 +#define TTC3 42 +#define GEM_TSU 43 +#define GEM_TSU_LB 44 +#define MUXED_IRO_DIV2 45 +#define MUXED_IRO_DIV4 46 +#define PSM_REF 47 +#define GEM0_RX 48 +#define GEM0_TX 49 +#define GEM1_RX 50 +#define GEM1_TX 51 +#define CPM_CORE_REF 52 +#define CPM_LSBUS_REF 53 +#define CPM_DBG_REF 54 +#define CPM_AUX0_REF 55 +#define CPM_AUX1_REF 56 +#define QSPI_REF 57 +#define OSPI_REF 58 +#define SDIO0_REF 59 +#define SDIO1_REF 60 +#define PMC_LSBUS_REF 61 +#define I2C_REF 62 +#define TEST_PATTERN_REF 63 +#define DFT_OSC_REF 64 +#define PMC_PL0_REF 65 +#define PMC_PL1_REF 66 +#define PMC_PL2_REF 67 +#define PMC_PL3_REF 68 +#define CFU_REF 69 +#define SPARE_REF 70 +#define NPI_REF 71 +#define HSM0_REF 72 +#define HSM1_REF 73 +#define SD_DLL_REF 74 +#define FPD_TOP_SWITCH 75 +#define FPD_LSBUS 76 +#define ACPU 77 +#define DBG_TRACE 78 +#define DBG_FPD 79 +#define LPD_TOP_SWITCH 80 +#define ADMA 81 +#define LPD_LSBUS 82 +#define CPU_R5 83 +#define CPU_R5_CORE 84 +#define CPU_R5_OCM 85 +#define CPU_R5_OCM2 86 +#define IOU_SWITCH 87 +#define GEM0_REF 88 +#define GEM1_REF 89 +#define GEM_TSU_REF 90 +#define USB0_BUS_REF 91 +#define UART0_REF 92 +#define UART1_REF 93 +#define SPI0_REF 94 +#define SPI1_REF 95 +#define CAN0_REF 96 +#define CAN1_REF 97 +#define I2C0_REF 98 +#define I2C1_REF 99 +#define DBG_LPD 100 +#define TIMESTAMP_REF 101 +#define DBG_TSTMP 102 +#define CPM_TOPSW_REF 103 +#define USB3_DUAL_REF 104 +#define OUTCLK_MAX 105 +#define REF_CLK 106 +#define PL_ALT_REF_CLK 107 +#define MUXED_IRO 108 +#define PL_EXT 109 +#define PL_LB 110 +#define MIO_50_OR_51 111 +#define MIO_24_OR_25 112 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h new file mode 100644 index 000000000000..4a6add03c173 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_CLK_H +#define _XLNX_VERSAL_NET_CLK_H + +#include "xlnx-versal-clk.h" + +#define CAN0_REF_2X 0x9e +#define CAN1_REF_2X 0xac +#define FPD_WWDT0 0xb5 +#define FPD_WWDT1 0xb6 +#define FPD_WWDT2 0xb7 +#define FPD_WWDT3 0xb8 +#define LPD_WWDT0 0xb9 +#define LPD_WWDT1 0xba +#define ACPU_0 0x98 +#define ACPU_1 0x9b +#define ACPU_2 0x9a +#define ACPU_3 0x99 +#define I3C0_REF 0x9d +#define I3C1_REF 0x9f +#define USB1_BUS_REF 0xae +#define LPD_WWDT 0xad + +/* Remove Versal specific node IDs */ +#undef APU_PLL +#undef RPU_PLL +#undef CPM_PLL +#undef APU_PRESRC +#undef APU_POSTCLK +#undef APU_PLL_OUT +#undef APLL +#undef RPU_PRESRC +#undef RPU_POSTCLK +#undef RPU_PLL_OUT +#undef RPLL +#undef CPM_PRESRC +#undef CPM_POSTCLK +#undef CPM_PLL_OUT +#undef CPLL +#undef APLL_TO_XPD +#undef RPLL_TO_XPD +#undef RCLK_PMC +#undef RCLK_LPD +#undef WDT +#undef MUXED_IRO_DIV2 +#undef MUXED_IRO_DIV4 +#undef PSM_REF +#undef CPM_CORE_REF +#undef CPM_LSBUS_REF +#undef CPM_DBG_REF +#undef CPM_AUX0_REF +#undef CPM_AUX1_REF +#undef CPU_R5 +#undef CPU_R5_CORE +#undef CPU_R5_OCM +#undef CPU_R5_OCM2 +#undef CAN0_REF +#undef CAN1_REF +#undef I2C0_REF +#undef I2C1_REF +#undef CPM_TOPSW_REF +#undef USB3_DUAL_REF +#undef MUXED_IRO +#undef PL_EXT +#undef PL_LB +#undef MIO_50_OR_51 +#undef MIO_24_OR_25 + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h new file mode 100644 index 000000000000..4f73593c966b --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_POWER_H +#define _XLNX_VERSAL_NET_POWER_H + +#include "xlnx-versal-power.h" + +#define PM_DEV_USB_1 (0x182240d7U) +#define PM_DEV_FPD_SWDT_0 (0x182240dbU) +#define PM_DEV_FPD_SWDT_1 (0x182240dcU) +#define PM_DEV_FPD_SWDT_2 (0x182240ddU) +#define PM_DEV_FPD_SWDT_3 (0x182240deU) +#define PM_DEV_TCM_A_0A (0x183180cbU) +#define PM_DEV_TCM_A_0B (0x183180ccU) +#define PM_DEV_TCM_A_0C (0x183180cdU) +#define PM_DEV_RPU_A_0 (0x181100bfU) +#define PM_DEV_LPD_SWDT_0 (0x182240d9U) +#define PM_DEV_LPD_SWDT_1 (0x182240daU) + +/* Remove Versal specific node IDs */ +#undef PM_DEV_RPU0_0 +#undef PM_DEV_RPU0_1 +#undef PM_DEV_OCM_0 +#undef PM_DEV_OCM_1 +#undef PM_DEV_OCM_2 +#undef PM_DEV_OCM_3 +#undef PM_DEV_TCM_0_A +#undef PM_DEV_TCM_1_A +#undef PM_DEV_TCM_0_B +#undef PM_DEV_TCM_1_B +#undef PM_DEV_SWDT_FPD +#undef PM_DEV_AI + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h new file mode 100644 index 000000000000..edc5841df214 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_NET_RESETS_H +#define _XLNX_VERSAL_NET_RESETS_H + +#include "xlnx-versal-resets.h" + +#define VERSAL_RST_USB_1 (0xc1040c6U) + +/* Remove Versal specific reset IDs */ +#undef VERSAL_RST_ACPU_0_POR +#undef VERSAL_RST_ACPU_1_POR +#undef VERSAL_RST_OCM2_POR +#undef VERSAL_RST_APU +#undef VERSAL_RST_ACPU_0 +#undef VERSAL_RST_ACPU_1 +#undef VERSAL_RST_ACPU_L2 +#undef VERSAL_RST_RPU_ISLAND +#undef VERSAL_RST_RPU_AMBA +#undef VERSAL_RST_R5_0 +#undef VERSAL_RST_R5_1 +#undef VERSAL_RST_OCM2_RST +#undef VERSAL_RST_I2C_PMC +#undef VERSAL_RST_I2C_0 +#undef VERSAL_RST_I2C_1 +#undef VERSAL_RST_SWDT_FPD +#undef VERSAL_RST_SWDT_LPD +#undef VERSAL_RST_USB +#undef VERSAL_RST_DPC +#undef VERSAL_RST_DBG_TRACE +#undef VERSAL_RST_DBG_TSTMP +#undef VERSAL_RST_RPU0_DBG +#undef VERSAL_RST_RPU1_DBG +#undef VERSAL_RST_HSDP +#undef VERSAL_RST_CPMDBG +#undef VERSAL_RST_PCIE_CFG +#undef VERSAL_RST_PCIE_CORE0 +#undef VERSAL_RST_PCIE_CORE1 +#undef VERSAL_RST_PCIE_DMA +#undef VERSAL_RST_L2_0 +#undef VERSAL_RST_L2_1 +#undef VERSAL_RST_ADDR_REMAP +#undef VERSAL_RST_CPI0 +#undef VERSAL_RST_CPI1 +#undef VERSAL_RST_XRAM +#undef VERSAL_RST_AIE_ARRAY +#undef VERSAL_RST_AIE_SHIM + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h new file mode 100644 index 000000000000..c3450675658a --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-power.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_POWER_H +#define _XLNX_VERSAL_POWER_H + +#define PM_DEV_RPU0_0 (0x18110005U) +#define PM_DEV_RPU0_1 (0x18110006U) +#define PM_DEV_OCM_0 (0x18314007U) +#define PM_DEV_OCM_1 (0x18314008U) +#define PM_DEV_OCM_2 (0x18314009U) +#define PM_DEV_OCM_3 (0x1831400aU) +#define PM_DEV_TCM_0_A (0x1831800bU) +#define PM_DEV_TCM_0_B (0x1831800cU) +#define PM_DEV_TCM_1_A (0x1831800dU) +#define PM_DEV_TCM_1_B (0x1831800eU) +#define PM_DEV_USB_0 (0x18224018U) +#define PM_DEV_GEM_0 (0x18224019U) +#define PM_DEV_GEM_1 (0x1822401aU) +#define PM_DEV_SPI_0 (0x1822401bU) +#define PM_DEV_SPI_1 (0x1822401cU) +#define PM_DEV_I2C_0 (0x1822401dU) +#define PM_DEV_I2C_1 (0x1822401eU) +#define PM_DEV_CAN_FD_0 (0x1822401fU) +#define PM_DEV_CAN_FD_1 (0x18224020U) +#define PM_DEV_UART_0 (0x18224021U) +#define PM_DEV_UART_1 (0x18224022U) +#define PM_DEV_GPIO (0x18224023U) +#define PM_DEV_TTC_0 (0x18224024U) +#define PM_DEV_TTC_1 (0x18224025U) +#define PM_DEV_TTC_2 (0x18224026U) +#define PM_DEV_TTC_3 (0x18224027U) +#define PM_DEV_SWDT_LPD (0x18224028U) +#define PM_DEV_SWDT_FPD (0x18224029U) +#define PM_DEV_OSPI (0x1822402aU) +#define PM_DEV_QSPI (0x1822402bU) +#define PM_DEV_GPIO_PMC (0x1822402cU) +#define PM_DEV_I2C_PMC (0x1822402dU) +#define PM_DEV_SDIO_0 (0x1822402eU) +#define PM_DEV_SDIO_1 (0x1822402fU) +#define PM_DEV_RTC (0x18224034U) +#define PM_DEV_ADMA_0 (0x18224035U) +#define PM_DEV_ADMA_1 (0x18224036U) +#define PM_DEV_ADMA_2 (0x18224037U) +#define PM_DEV_ADMA_3 (0x18224038U) +#define PM_DEV_ADMA_4 (0x18224039U) +#define PM_DEV_ADMA_5 (0x1822403aU) +#define PM_DEV_ADMA_6 (0x1822403bU) +#define PM_DEV_ADMA_7 (0x1822403cU) +#define PM_DEV_AI (0x18224072U) + +#endif diff --git a/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h new file mode 100644 index 000000000000..fe00f4a0ba65 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 - 2022, Xilinx, Inc. + * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. + */ + +#ifndef _XLNX_VERSAL_RESETS_H +#define _XLNX_VERSAL_RESETS_H + +#define VERSAL_RST_PMC_POR (0xc30c001U) +#define VERSAL_RST_PMC (0xc410002U) +#define VERSAL_RST_PS_POR (0xc30c003U) +#define VERSAL_RST_PL_POR (0xc30c004U) +#define VERSAL_RST_NOC_POR (0xc30c005U) +#define VERSAL_RST_FPD_POR (0xc30c006U) +#define VERSAL_RST_ACPU_0_POR (0xc30c007U) +#define VERSAL_RST_ACPU_1_POR (0xc30c008U) +#define VERSAL_RST_OCM2_POR (0xc30c009U) +#define VERSAL_RST_PS_SRST (0xc41000aU) +#define VERSAL_RST_PL_SRST (0xc41000bU) +#define VERSAL_RST_NOC (0xc41000cU) +#define VERSAL_RST_NPI (0xc41000dU) +#define VERSAL_RST_SYS_RST_1 (0xc41000eU) +#define VERSAL_RST_SYS_RST_2 (0xc41000fU) +#define VERSAL_RST_SYS_RST_3 (0xc410010U) +#define VERSAL_RST_FPD (0xc410011U) +#define VERSAL_RST_PL0 (0xc410012U) +#define VERSAL_RST_PL1 (0xc410013U) +#define VERSAL_RST_PL2 (0xc410014U) +#define VERSAL_RST_PL3 (0xc410015U) +#define VERSAL_RST_APU (0xc410016U) +#define VERSAL_RST_ACPU_0 (0xc410017U) +#define VERSAL_RST_ACPU_1 (0xc410018U) +#define VERSAL_RST_ACPU_L2 (0xc410019U) +#define VERSAL_RST_ACPU_GIC (0xc41001aU) +#define VERSAL_RST_RPU_ISLAND (0xc41001bU) +#define VERSAL_RST_RPU_AMBA (0xc41001cU) +#define VERSAL_RST_R5_0 (0xc41001dU) +#define VERSAL_RST_R5_1 (0xc41001eU) +#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) +#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) +#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) +#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) +#define VERSAL_RST_SYSMON_LPD (0xc410023U) +#define VERSAL_RST_PDMA_RST1 (0xc410024U) +#define VERSAL_RST_PDMA_RST0 (0xc410025U) +#define VERSAL_RST_ADMA (0xc410026U) +#define VERSAL_RST_TIMESTAMP (0xc410027U) +#define VERSAL_RST_OCM (0xc410028U) +#define VERSAL_RST_OCM2_RST (0xc410029U) +#define VERSAL_RST_IPI (0xc41002aU) +#define VERSAL_RST_SBI (0xc41002bU) +#define VERSAL_RST_LPD (0xc41002cU) +#define VERSAL_RST_QSPI (0xc10402dU) +#define VERSAL_RST_OSPI (0xc10402eU) +#define VERSAL_RST_SDIO_0 (0xc10402fU) +#define VERSAL_RST_SDIO_1 (0xc104030U) +#define VERSAL_RST_I2C_PMC (0xc104031U) +#define VERSAL_RST_GPIO_PMC (0xc104032U) +#define VERSAL_RST_GEM_0 (0xc104033U) +#define VERSAL_RST_GEM_1 (0xc104034U) +#define VERSAL_RST_SPARE (0xc104035U) +#define VERSAL_RST_USB_0 (0xc104036U) +#define VERSAL_RST_UART_0 (0xc104037U) +#define VERSAL_RST_UART_1 (0xc104038U) +#define VERSAL_RST_SPI_0 (0xc104039U) +#define VERSAL_RST_SPI_1 (0xc10403aU) +#define VERSAL_RST_CAN_FD_0 (0xc10403bU) +#define VERSAL_RST_CAN_FD_1 (0xc10403cU) +#define VERSAL_RST_I2C_0 (0xc10403dU) +#define VERSAL_RST_I2C_1 (0xc10403eU) +#define VERSAL_RST_GPIO_LPD (0xc10403fU) +#define VERSAL_RST_TTC_0 (0xc104040U) +#define VERSAL_RST_TTC_1 (0xc104041U) +#define VERSAL_RST_TTC_2 (0xc104042U) +#define VERSAL_RST_TTC_3 (0xc104043U) +#define VERSAL_RST_SWDT_FPD (0xc104044U) +#define VERSAL_RST_SWDT_LPD (0xc104045U) +#define VERSAL_RST_USB (0xc104046U) +#define VERSAL_RST_DPC (0xc208047U) +#define VERSAL_RST_PMCDBG (0xc208048U) +#define VERSAL_RST_DBG_TRACE (0xc208049U) +#define VERSAL_RST_DBG_FPD (0xc20804aU) +#define VERSAL_RST_DBG_TSTMP (0xc20804bU) +#define VERSAL_RST_RPU0_DBG (0xc20804cU) +#define VERSAL_RST_RPU1_DBG (0xc20804dU) +#define VERSAL_RST_HSDP (0xc20804eU) +#define VERSAL_RST_DBG_LPD (0xc20804fU) +#define VERSAL_RST_CPM_POR (0xc30c050U) +#define VERSAL_RST_CPM (0xc410051U) +#define VERSAL_RST_CPMDBG (0xc208052U) +#define VERSAL_RST_PCIE_CFG (0xc410053U) +#define VERSAL_RST_PCIE_CORE0 (0xc410054U) +#define VERSAL_RST_PCIE_CORE1 (0xc410055U) +#define VERSAL_RST_PCIE_DMA (0xc410056U) +#define VERSAL_RST_CMN (0xc410057U) +#define VERSAL_RST_L2_0 (0xc410058U) +#define VERSAL_RST_L2_1 (0xc410059U) +#define VERSAL_RST_ADDR_REMAP (0xc41005aU) +#define VERSAL_RST_CPI0 (0xc41005bU) +#define VERSAL_RST_CPI1 (0xc41005cU) +#define VERSAL_RST_XRAM (0xc30c05dU) +#define VERSAL_RST_AIE_ARRAY (0xc10405eU) +#define VERSAL_RST_AIE_SHIM (0xc10405fU) + +#endif From 917b5c98d768a47daff91f2d21a000bc3e24a7a4 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Mon, 1 Jun 2026 16:15:45 +0200 Subject: [PATCH 516/864] arm64: dts: mediatek: mt8390-genio-common: Add MT6365 PMIC supplies Mediatek Genio 510 and 700 EVK boards integrate a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board common definition include file. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8390-genio-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index ce27f314d19d..0dfd0c7de41d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1304,6 +1304,23 @@ ethernet_phy0: ethernet-phy@1 { &pmic { interrupt-parent = <&pio>; interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <®_vsys>; + vsys-vcore-supply = <®_vsys>; + vsys-vgpu11-supply = <®_vsys>; + vsys-vgpu12-supply = <®_vsys>; + vsys-vpa-supply = <®_vsys>; + vsys-vproc1-supply = <®_vsys>; + vsys-vproc2-supply = <®_vsys>; + vsys-vpu-supply = <®_vsys>; + vsys-vs1-supply = <®_vsys>; + vsys-vs2-supply = <®_vsys>; + vsys-vmodem-supply = <®_vsys>; + vsys-ldo1-supply = <®_vsys>; + vsys-ldo2-supply = <®_vsys>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; mt6365keys: keys { compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; From cc90ec9b892061a3e4dbd4e944e18a81758da2ff Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Mon, 1 Jun 2026 16:15:46 +0200 Subject: [PATCH 517/864] arm64: dts: mediatek: mt8395-genio-common: Add MT6365 PMIC supplies Mediatek Genio 1200 EVK board integrates a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board common definition include file. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-genio-common.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index edc5539bebde..7ea45b6bc663 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -1170,6 +1170,23 @@ pins { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <®_vsys>; + vsys-vcore-supply = <®_vsys>; + vsys-vgpu11-supply = <®_vsys>; + vsys-vgpu12-supply = <®_vsys>; + vsys-vpa-supply = <®_vsys>; + vsys-vproc1-supply = <®_vsys>; + vsys-vproc2-supply = <®_vsys>; + vsys-vpu-supply = <®_vsys>; + vsys-vs1-supply = <®_vsys>; + vsys-vs2-supply = <®_vsys>; + vsys-vmodem-supply = <®_vsys>; + vsys-ldo1-supply = <®_vsys_buck>; + vsys-ldo2-supply = <®_vsys_buck>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; mt6365keys: keys { compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; From 759e989b840b4c2ffdb74cf1e1da0cee66e89f4c Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Mon, 1 Jun 2026 16:15:47 +0200 Subject: [PATCH 518/864] arm64: dts: mediatek: mt8395-radxa-nio-12l: Add MT6365 PMIC supplies Radxa NIO-12L EVK board integrates a MT6365 PMIC, that has a number of power inputs for its various buck and LDO regulators. Add the supplies for this PMIC regulators to the board devicetree file. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index b279eed1bfc3..9cf0315da035 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -1033,6 +1033,23 @@ &pciephy { &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + vsys-smps-supply = <&vsys>; + vsys-vcore-supply = <&vsys>; + vsys-vgpu11-supply = <&vsys>; + vsys-vgpu12-supply = <&vsys>; + vsys-vpa-supply = <&vsys>; + vsys-vproc1-supply = <&vsys>; + vsys-vproc2-supply = <&vsys>; + vsys-vpu-supply = <&vsys>; + vsys-vs1-supply = <&vsys>; + vsys-vs2-supply = <&vsys>; + vsys-vmodem-supply = <&vsys>; + vsys-ldo1-supply = <&vsys_buck>; + vsys-ldo2-supply = <&vsys_buck>; + vs1-ldo1-supply = <&mt6359_vs1_buck_reg>; + vs1-ldo2-supply = <&mt6359_vs1_buck_reg>; + vs2-ldo1-supply = <&mt6359_vs2_buck_reg>; + vs2-ldo2-supply = <&mt6359_vs2_buck_reg>; mt6365keys: keys { compatible = "mediatek,mt6365-keys", "mediatek,mt6359-keys"; From 3dc552c1bab6e83bb45af0a49f3a900845a24495 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 1 Jul 2026 10:38:21 +0200 Subject: [PATCH 519/864] arm64: dts: mediatek: mt6359: use proper compatible for rtc The MT6359 PMIC include file uses directly "mediatek,mt6358-rtc" compatible string for the rtc subnode, but not its own compatible string. Now that the "mediatek,mt6359-rtc" compatible is properly declared in the dt-bindings, use it with "mediatek,mt6358-rtc" as fallback. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index a953fb527b69..52fb0f832260 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -287,7 +287,7 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { }; mt6359rtc: rtc { - compatible = "mediatek,mt6358-rtc"; + compatible = "mediatek,mt6359-rtc", "mediatek,mt6358-rtc"; }; }; }; From 1e8024c42939c7da98615e3e41a97dc044e66710 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Tue, 21 Jul 2026 19:01:59 +0800 Subject: [PATCH 520/864] ARM: dts: aspeed: sanmiguel: Fix FIO IOEXP interrupt pin The interrupt properties for fio_ioexp (pca9555 on i2c14) were incorrectly configured to gpio1 with ASPEED_GPIO(B, 6). Update the interrupt-parent to gpio0 and the interrupt pin to ASPEED_GPIO(C, 6) according to the hardware specification. Signed-off-by: Potin Lai Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts index d7ed497d7227..cb07c3615279 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -578,8 +578,8 @@ fio_ioexp: gpio@20 { reg = <0x20>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = ; + interrupt-parent = <&gpio0>; + interrupts = ; gpio-line-names = "", "", "", "", From 1420679cffcea4067f4004f8cf0e651cadebf9a1 Mon Sep 17 00:00:00 2001 From: Potin Lai Date: Thu, 16 Jul 2026 10:31:17 +0800 Subject: [PATCH 521/864] ARM: dts: aspeed: sanmiguel: Fix PWRGD_RMC_N active-low hog configuration GPIO 14 on the fio_ioexp (pca9555) controller corresponds to the PWRGD_RMC_N signal, which is active-low. The pwrgd-rmc-hog node currently specifies output-low for this GPIO with GPIO_ACTIVE_LOW flags. Under Linux gpiolib, configuring an active-low GPIO hog with output-low sets the logical value to inactive (0), causing the subsystem to drive the physical line high. Correct the hog configuration to output-high, which sets the logical value to active (1), driving the physical pin low on boot as intended. [arj: tidy subject line] Signed-off-by: Potin Lai Link: https://patch.msgid.link/20260716-upstream-sanmiguel-fix-pwrgd-rmc-n-v1-1-8287b306e02a@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts index cb07c3615279..ee406a6c1604 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -592,7 +592,7 @@ fio_ioexp: gpio@20 { pwrgd-rmc-hog { gpio-hog; gpios = <14 GPIO_ACTIVE_LOW>; - output-low; + output-high; }; }; From 050253f365022f3e0d9dc7cc80a93b25134e0bf7 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 8 Jul 2026 19:59:26 +0300 Subject: [PATCH 522/864] arm64: dts: nuvoton: npcm845: Drop redundant timer clock-names The NPCM845 timer0 node references a single clock, but its clock-names property is not described by the timer binding. Drop the undocumented name so the DTS matches the binding. Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20260708165929.2233934-2-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index c781190b42c5..9e4fa2669f4d 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -73,7 +73,6 @@ timer0: timer@8000 { interrupts = ; reg = <0x8000 0x1C>; clocks = <&refclk>; - clock-names = "refclk"; }; serial0: serial@0 { From 60b9d5b8ca8b09019d8b162bf41fdf24f847fa02 Mon Sep 17 00:00:00 2001 From: Tomer Maimon Date: Wed, 8 Jul 2026 19:59:27 +0300 Subject: [PATCH 523/864] arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes Move the timer0 and PECI nodes so the APB children are ordered by ascending unit address. Signed-off-by: Tomer Maimon Link: https://patch.msgid.link/20260708165929.2233934-3-tmaimon77@gmail.com Signed-off-by: Andrew Jeffery --- .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 9e4fa2669f4d..545034ac11a0 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -59,22 +59,6 @@ apb { ranges = <0x0 0x0 0xf0000000 0x00300000>, <0xfff00000 0x0 0xfff00000 0x00016000>; - peci: peci-controller@100000 { - compatible = "nuvoton,npcm845-peci"; - reg = <0x100000 0x1000>; - interrupts = ; - clocks = <&clk NPCM8XX_CLK_APB3>; - cmd-timeout-ms = <1000>; - status = "disabled"; - }; - - timer0: timer@8000 { - compatible = "nuvoton,npcm845-timer"; - interrupts = ; - reg = <0x8000 0x1C>; - clocks = <&refclk>; - }; - serial0: serial@0 { compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; reg = <0x0 0x1000>; @@ -138,6 +122,13 @@ serial6: serial@6000 { status = "disabled"; }; + timer0: timer@8000 { + compatible = "nuvoton,npcm845-timer"; + interrupts = ; + reg = <0x8000 0x1C>; + clocks = <&refclk>; + }; + watchdog0: watchdog@801c { compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt"; interrupts = ; @@ -161,6 +152,15 @@ watchdog2: watchdog@a01c { status = "disabled"; clocks = <&refclk>; }; + + peci: peci-controller@100000 { + compatible = "nuvoton,npcm845-peci"; + reg = <0x100000 0x1000>; + interrupts = ; + clocks = <&clk NPCM8XX_CLK_APB3>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; }; }; From cb96bb0b28e981903527c50ad7de5149a9a38dc4 Mon Sep 17 00:00:00 2001 From: Mike Hsieh Date: Thu, 18 Jun 2026 15:41:44 +0800 Subject: [PATCH 524/864] ARM: dts: aspeed: sanmiguel: fix PDB HSC shunt resistor Correct the shunt-resistor-micro-ohms values for the four TI LM5066i hot-swap controllers on the PDB. This ensures accurate current and power sensor readings from the hardware monitors. Signed-off-by: Mike Hsieh Link: https://patch.msgid.link/20260618-sanmiguel-dts-config-hsc-lm5066i-v1-1-cccf959c9b78@gmail.com Signed-off-by: Andrew Jeffery --- .../arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts index ee406a6c1604..3cc6e772cc8c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-sanmiguel.dts @@ -450,7 +450,7 @@ pdb_mps_hsc1: power-monitor@10 { pdb_ti_hsc1: power-monitor@11 { compatible = "ti,lm5066i"; reg = <0x11>; - shunt-resistor-micro-ohms = <763>; + shunt-resistor-micro-ohms = <1000>; }; pdb_mps_hsc2: power-monitor@12 { @@ -461,7 +461,7 @@ pdb_mps_hsc2: power-monitor@12 { pdb_ti_hsc2: power-monitor@13 { compatible = "ti,lm5066i"; reg = <0x13>; - shunt-resistor-micro-ohms = <294>; + shunt-resistor-micro-ohms = <321>; }; pdb_mps_hsc3: power-monitor@14 { @@ -472,7 +472,7 @@ pdb_mps_hsc3: power-monitor@14 { pdb_ti_hsc3: power-monitor@15 { compatible = "ti,lm5066i"; reg = <0x15>; - shunt-resistor-micro-ohms = <294>; + shunt-resistor-micro-ohms = <321>; }; pdb_mps_hsc4: power-monitor@16 { @@ -483,7 +483,7 @@ pdb_mps_hsc4: power-monitor@16 { pdb_ti_hsc4: power-monitor@17 { compatible = "ti,lm5066i"; reg = <0x17>; - shunt-resistor-micro-ohms = <381>; + shunt-resistor-micro-ohms = <500>; }; pdb_ioexp_20: gpio@20 { From 749c34389679f8d56cb200a69b62f9a64670034f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 20:03:08 +0200 Subject: [PATCH 525/864] ARM: dts: aspeed: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Andrew Jeffery --- .../aspeed-bmc-inventec-transformers.dts | 432 +++++++++--------- .../boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts | 2 +- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 2 +- 3 files changed, 218 insertions(+), 218 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts index c713cb7a6187..45ee0f2cc2bb 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts @@ -9,320 +9,320 @@ #include / { - model = "TRANSFORMERS BMC"; - compatible = "inventec,transformer-bmc", "aspeed,ast2600"; + model = "TRANSFORMERS BMC"; + compatible = "inventec,transformer-bmc", "aspeed,ast2600"; - aliases { - serial4 = &uart5; - }; + aliases { + serial4 = &uart5; + }; - chosen { - stdout-path = &uart5; - bootargs = "console=ttyS4,115200n8"; - }; + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; - leds { - compatible = "gpio-leds"; + leds { + compatible = "gpio-leds"; - // UID led - uid { - label = "UID_LED"; - gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; - }; + // UID led + uid { + label = "UID_LED"; + gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; + }; - // Heart beat led - heartbeat { - label = "HB_LED"; - gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - }; - }; + // Heart beat led + heartbeat { + label = "HB_LED"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + }; + }; }; &mdio0 { - status = "okay"; + status = "okay"; - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; }; &mac3 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii4_default>; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; }; &fmc { - status = "okay"; + status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <33000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <33000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; #include "openbmc-flash-layout.dtsi" - }; + }; - flash@1 { - status = "okay"; - m25p,fast-read; - label = "bmc2"; - spi-max-frequency = <33000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-max-frequency = <33000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; }; &spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bios"; - spi-max-frequency = <33000000>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <1>; - }; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <33000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; }; &wdt1 { - status = "okay"; + status = "okay"; }; &uart1 { - status = "okay"; + status = "okay"; }; &uart5 { - status = "okay"; + status = "okay"; }; &i2c0 { - status = "okay"; + status = "okay"; - //Set bmc' slave address; - bmc_slave@10 { - compatible = "ipmb-dev"; - reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; - i2c-protocol; - }; + //Set bmc' slave address; + bmc_slave@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &i2c2 { - status = "okay"; + status = "okay"; }; &i2c3 { - // FRU AT24C512C-SSHM-T - status = "okay"; - eeprom@50 { - compatible = "atmel,24c512"; - reg = <0x50>; - pagesize = <128>; - }; + // FRU AT24C512C-SSHM-T + status = "okay"; + eeprom@50 { + compatible = "atmel,24c512"; + reg = <0x50>; + pagesize = <128>; + }; }; &i2c5 { - status = "okay"; + status = "okay"; }; &i2c6 { - status = "okay"; + status = "okay"; - tmp75@49 { - compatible = "ti,tmp75"; - reg = <0x49>; - }; + tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; - tmp75@4f { - compatible = "ti,tmp75"; - reg = <0x4f>; - }; + tmp75@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; - tmp468@48 { - compatible = "ti,tmp468"; - reg = <0x48>; - }; + tmp468@48 { + compatible = "ti,tmp468"; + reg = <0x48>; + }; }; &i2c7 { - status = "okay"; - adm1278@40 { - compatible = "adi,adm1278"; - reg = <0x40>; - }; + status = "okay"; + adm1278@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; }; &i2c8 { - // FRU AT24C512C-SSHM-T - status = "okay"; + // FRU AT24C512C-SSHM-T + status = "okay"; - eeprom@51 { - compatible = "atmel,24c512"; - reg = <0x51>; - pagesize = <128>; - }; + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + pagesize = <128>; + }; - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - pagesize = <128>; - }; + eeprom@53 { + compatible = "atmel,24c512"; + reg = <0x53>; + pagesize = <128>; + }; }; &i2c9 { - // M.2 - status = "okay"; + // M.2 + status = "okay"; }; &i2c10 { - // I2C EXPANDER - status = "okay"; + // I2C EXPANDER + status = "okay"; - i2c-mux@71 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x71>; - }; + i2c-mux@71 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; - i2c-mux@73 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x73>; - }; + i2c-mux@73 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + }; }; &i2c11 { - // I2C EXPANDER - status = "okay"; + // I2C EXPANDER + status = "okay"; - i2c-mux@70 { - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x70>; + i2c-mux@70 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; - pcie_eeprom_riser1: i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; + pcie_eeprom_riser1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; - eeprom@55 { - compatible = "atmel,24c512"; - reg = <0x55>; - pagesize = <128>; - }; - }; + eeprom@55 { + compatible = "atmel,24c512"; + reg = <0x55>; + pagesize = <128>; + }; + }; - pcie_eeprom_riser2: i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; + pcie_eeprom_riser2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; - eeprom@55 { - compatible = "atmel,24c512"; - reg = <0x55>; - pagesize = <128>; - }; - }; + eeprom@55 { + compatible = "atmel,24c512"; + reg = <0x55>; + pagesize = <128>; + }; + }; - pcie_eeprom_riser3: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; + pcie_eeprom_riser3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; - eeprom@55 { - compatible = "atmel,24c512"; - reg = <0x55>; - pagesize = <128>; - }; - }; - }; + eeprom@55 { + compatible = "atmel,24c512"; + reg = <0x55>; + pagesize = <128>; + }; + }; + }; }; &i2c12 { - status = "okay"; + status = "okay"; - psu0:psu0@58 { - compatible = "pmbus"; - reg = <0x58>; - }; + psu0:psu0@58 { + compatible = "pmbus"; + reg = <0x58>; + }; }; &gpio0 { - status = "okay"; - gpio-line-names = - /*A0-A7*/ "","","","","","","","", - /*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","", - /*C0-C7*/ "","","","","","","","", - /*D0-D7*/ "","","","","","","","", - /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","power-chassis-control","","","", - /*G0-G7*/ "","","jtag-mux","","","","","", - /*H0-H7*/ "","","","","reset-button","power-button","","", - /*I0-I7*/ "","","","","","","","", - /*J0-J7*/ "","","","","","","","", - /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "","","","","","","","", - /*N0-N7*/ "","","","","","","","", - /*O0-O7*/ "","","","","","","","", - /*P0-P7*/ "","","","tck-mux","","","","", - /*Q0-Q7*/ "","","","","","","","", - /*R0-R7*/ "","","","","","","","", - /*S0-S7*/ "","","","","","","","", - /*T0-T7*/ "","","","","","","","", - /*U0-U7*/ "","nmi-button","","","","","","", - /*V0-V7*/ "","","","","power-config-full-load","","","", - /*W0-W7*/ "","","","","","","","", - /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","","","","","","", - /*Z0-Z7*/ "","","","","","","","", - /*AA0-AA7*/ "","","","","","","","", - /*AB0-AB7*/ "","","","","","","","", - /*AC0-AC7*/ "","","","","","","",""; + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "presence-ps0","power-chassis-good","","","","","presence-ps1","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","power-chassis-control","","","", + /*G0-G7*/ "","","jtag-mux","","","","","", + /*H0-H7*/ "","","","","reset-button","power-button","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","tck-mux","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","nmi-button","","","","","","", + /*V0-V7*/ "","","","","power-config-full-load","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; }; &lpc_snoop { - status = "okay"; - snoop-ports = <0x80>; + status = "okay"; + snoop-ports = <0x80>; }; &emmc_controller { - status = "okay"; + status = "okay"; }; &emmc { - status = "okay"; - non-removable; - max-frequency = <52000000>; - bus-width = <8>; + status = "okay"; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; }; &vhub { - status = "okay"; - aspeed,vhub-downstream-ports = <7>; - aspeed,vhub-generic-endpoints = <21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2ad_default>; + status = "okay"; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; }; &rtc { - status = "okay"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts index 8a7fb55ab489..5a3e8a3941d4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-vesnin.dts @@ -82,7 +82,7 @@ &fmc { flash@0 { status = "okay"; m25p,fast-read; - label = "bmc"; + label = "bmc"; #include "openbmc-flash-layout.dtsi" }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 56bb3b0444f7..edf4b74f5aba 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -517,7 +517,7 @@ timer: timer@1e782000 { clocks = <&syscon ASPEED_CLK_APB1>; clock-names = "PCLK"; status = "disabled"; - }; + }; uart1: serial@1e783000 { compatible = "ns16550a"; From eb7051f756460d7b951e94d9656e31ebb631ba28 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Jul 2026 23:51:28 +0200 Subject: [PATCH 526/864] ARM: dts: allwinner: a10: Fix PMU interrupt The Performance Monitoring Unit of the Cortex-A8 cores in the Allwinner A10 SoC is connected to interrupt line 66, not 3. This is shown in the manual (where interrupt 3 is assigned to UART2, also in our .dtsi), but has also been confirmed by triggering an PMU overflow interrupt and inspecting the IRQ controller status registers (from U-Boot). Please note that "perf stat" does not use interrupts, this might explain why this evaded the initial testing. Fixes: 7e345d25c796 ("ARM: dts: sun4i-a10: Add PMU node") Signed-off-by: Andre Przywara Link: https://patch.msgid.link/20260720215128.5761-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun4i-a10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi index 51a6464aab9a..cabf619c2e21 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi @@ -185,7 +185,7 @@ de: display-engine { pmu { compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; + interrupts = <66>; }; reserved-memory { From 788ed93b3b85baa3b5817655ce621ff1f6c300e9 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Jun 2026 22:43:45 +0200 Subject: [PATCH 527/864] riscv: dts: spacemit: set console baud rate on K3 Pico-ITX board Because the default console's baud rate is not set, defconfig kernels do not have any serial output on this platform. Set the baud rate to 115200, matching what is used by U-Boot etc on this platform. Fixes: 7a6131804986 ("riscv: dts: spacemit: add K3 Pico-ITX board support") Signed-off-by: Aurelien Jarno Reviewed-by: Guodong Xu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260623204431.498700-2-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index b89c1521e664..509cebc0c956 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -18,7 +18,7 @@ aliases { }; chosen { - stdout-path = "serial0"; + stdout-path = "serial0:115200n8"; }; memory@100000000 { From 48dd3d020528e05795dfa46308ba5b59a1835bba Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Jun 2026 22:43:46 +0200 Subject: [PATCH 528/864] riscv: dts: spacemit: enable the i2c2 adapter on K3 Pico-ITX board Define I2C2 pinctrl properties, and enable it on the K3 Pico-ITX board. It will be used by the 24c02 eeprom. Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260623204431.498700-3-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 6 ++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 11 +++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 509cebc0c956..5fe9041ec570 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -43,6 +43,12 @@ reg_aux_vcc5v: regulator-aux-vcc5v { }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_cfg>; + status = "okay"; +}; + &i2c8 { pinctrl-names = "default"; pinctrl-0 = <&i2c8_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 6b808f890a28..627fbda1ad76 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -78,6 +78,17 @@ gmac1-phy-0-pins { }; }; + /omit-if-no-ref/ + i2c2_1_cfg: i2c2-1-cfg { + i2c2-1-pins { + pinmux = , /* i2c2 scl */ + ; /* i2c2 sda */ + + bias-pull-up = <0>; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ i2c8_cfg: i2c8-cfg { i2c8-pins { From 930491838c55c41317da9f263e3e9b013cb9aaa8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Jun 2026 22:43:47 +0200 Subject: [PATCH 529/864] riscv: dts: spacemit: add 24c02 eeprom on K3 Pico-ITX board The K3 Pico-ITX board includes a 24c02 eeprom, that stores the product name, the part name, the MAC address of the network interfaces and the board's serial number. These values are also exposed via an onie,tlv-layout nvmem layout. The eeprom is marked as read-only since its contents are not supposed to be modified. Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260623204431.498700-4-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 5fe9041ec570..0a0c221c99e7 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -47,6 +47,36 @@ &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_1_cfg>; status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <8>; + read-only; + size = <256>; + status = "okay"; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + part-number { + }; + + product-name { + }; + + serial-number { + }; + + }; + }; }; &i2c8 { From ae4e84366b5d621171da2e9fae2b1f8bea3312b8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Jun 2026 22:43:48 +0200 Subject: [PATCH 530/864] riscv: dts: spacemit: add i2c aliases on K3 Pico-ITX board Add i2c aliases for i2c2 and i2c8 on K3 Pico-ITX board. This is useful to keep a stable number for the /dev entries after loading the i2c-dev module. Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260623204431.498700-5-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 0a0c221c99e7..bf64b6c6f867 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -14,6 +14,8 @@ / { aliases { ethernet0 = ð0; + i2c2 = &i2c2; + i2c8 = &i2c8; serial0 = &uart0; }; From e0c1145f4c8ea0515b32e0b9620412528a4312b1 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Jun 2026 22:43:49 +0200 Subject: [PATCH 531/864] riscv: dts: spacemit: improve RTL8211F PHY configuration on K3 Pico-ITX board Vendor kernel enabled ALDPS (Advanced Link Down Power Saving) on the RTL8211F PHY to save power when link down. Vendor kernel also disabled the 125MHz clkout clock signal, and indeed the schematics confirms that it only goes to a test point (TP14), so let's do the same. Signed-off-by: Aurelien Jarno Tested-by: Yixun Lan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260623204431.498700-6-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index bf64b6c6f867..e12d798b48a4 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -234,6 +234,8 @@ phy0: phy@1 { reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <10000>; + realtek,aldps-enable; + realtek,clkout-disable; }; }; }; From c7d6ed1ebb133a68fd4aadbe959f5b0e5a2d7e40 Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Sat, 11 Jul 2026 09:38:52 +0800 Subject: [PATCH 532/864] riscv: dts: spacemit: k3: Add QSPI support for Pico-ITX board Enable QSPI with proper pinmux on the Pico-ITX board, and describe the NOR flash wired to it. Tested-by: Aurelien Jarno Reviewed-by: Aurelien Jarno Signed-off-by: Cody Kang Signed-off-by: Zhengyu He Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260711-k3-pico-itx-qspi-v3-v3-1-d6b37fc86c39@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 56 ++++++++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 21 ++++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 17 ++++++ 3 files changed, 94 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index e12d798b48a4..8b2a120b02d1 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -240,6 +240,62 @@ phy0: phy@1 { }; }; +&qspi_cfg { + qspi-pins { + power-source = <1800>; + }; + + qspi-cs0-pins { + power-source = <1800>; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <26500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + vcc-supply = <&aldo2>; /* PMIC_VCC1V8_QSPI */ + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootinfo@0 { + reg = <0x0 0x20000>; + }; + + fsbl@20000 { + reg = <0x20000 0x80000>; + }; + + env@a0000 { + reg = <0xa0000 0x10000>; + }; + + esos@b0000 { + reg = <0xb0000 0x100000>; + }; + + opensbi@1b0000 { + reg = <0x1b0000 0x60000>; + }; + + uboot@210000 { + reg = <0x210000 0x5f0000>; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_0_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 627fbda1ad76..5b9045e01434 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -690,6 +690,27 @@ pwm19-2-pins { }; }; + /omit-if-no-ref/ + qspi_cfg: qspi-cfg { + qspi-pins { + pinmux = , /* qspi dat0 */ + , /* qspi dat1 */ + , /* qspi dat2 */ + , /* qspi dat3 */ + ; /* qspi clk */ + + bias-disable; + drive-strength = <25>; + }; + + qspi-cs0-pins { + pinmux = ; /* qspi cs0 */ + + bias-disable; + drive-strength = <25>; + }; + }; + /omit-if-no-ref/ uart0_0_cfg: uart0-0-cfg { uart0-0-pins { diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index dabb0d5e6bad..fc46e34465e4 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1099,6 +1099,23 @@ pll: clock-controller@d4090000 { #clock-cells = <1>; }; + qspi: spi@d420c000 { + compatible = "spacemit,k3-qspi", + "spacemit,k1-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0xd420c000 0x0 0x1000>, + <0x0 0xb8000000 0x0 0xc00000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + clocks = <&syscon_apmu CLK_APMU_QSPI_BUS>, + <&syscon_apmu CLK_APMU_QSPI>; + clock-names = "qspi_en", "qspi"; + resets = <&syscon_apmu RESET_APMU_QSPI>, + <&syscon_apmu RESET_APMU_QSPI_BUS>; + interrupts = <117 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + sdhci0: mmc@d4280000 { compatible = "spacemit,k3-sdhci"; reg = <0x0 0xd4280000 0x0 0x200>; From 736d655c842f4d782d43e6e0461e9a2cd59fc39a Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Fri, 26 Jun 2026 16:10:23 +0800 Subject: [PATCH 533/864] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allowlist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the compatible string for supporting the generic cpufreq driver on the SpacemiT K1 SoC. Signed-off-by: Shuwei Wu Acked-by: Viresh Kumar Reviewed-by: Yixun Lan Tested-by: Aurelien Jarno Reviewed-by: Aurelien Jarno Tested-by: Milan P. Stanić Tested-by: Gong Shuai # OrangePi-RV2 Link: https://patch.msgid.link/20260626-shadow-deps-v4-1-bba9831f2f1d@mailbox.org Signed-off-by: Yixun Lan --- drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index ff1204c666b1..26f81f4d56df 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -81,6 +81,8 @@ static const struct of_device_id allowlist[] __initconst = { { .have_governor_per_policy = true, }, }, + { .compatible = "spacemit,k1", }, + { .compatible = "st-ericsson,u8500", }, { .compatible = "st-ericsson,u8540", }, { .compatible = "st-ericsson,u9500", }, From 3b9c34556fc1bb6639a9227e96ce7b368432d08c Mon Sep 17 00:00:00 2001 From: Shuwei Wu Date: Fri, 26 Jun 2026 16:10:24 +0800 Subject: [PATCH 534/864] riscv: dts: spacemit: Add cpu scaling for K1 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add CPU clock properties and OPP tables for the two CPU clusters in the SpacemiT K1 SoC. The OPP entries use voltage ranges because the CPU supply is shared by both clusters. Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP tables and wiring the CPU nodes to the CPU regulator supply. Signed-off-by: Shuwei Wu Tested-by: Andre Heider # k1-musepi-pro Reviewed-by: Yixun Lan Tested-by: Aurelien Jarno Reviewed-by: Aurelien Jarno Tested-by: Milan P. Stanić Tested-by: Gong Shuai # OrangePi-RV2 Link: https://patch.msgid.link/20260626-shadow-deps-v4-2-bba9831f2f1d@mailbox.org Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 35 +++++- arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 105 ++++++++++++++++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++ 3 files changed, 147 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/spacemit/k1-opp.dtsi diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 72f77e9edd63..307a7e4a8943 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -4,6 +4,7 @@ */ #include "k1.dtsi" +#include "k1-opp.dtsi" #include "k1-pinctrl.dtsi" / { @@ -87,6 +88,38 @@ &combo_phy { status = "okay"; }; +&cpu_0 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_1 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_2 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_3 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_4 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_5 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_6 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_7 { + cpu-supply = <&buck1_0v9>; +}; + &emmc { bus-width = <8>; mmc-hs400-1_8v; @@ -202,7 +235,7 @@ pmic@41 { dldoin2-supply = <&buck5>; regulators { - buck1 { + buck1_0v9: buck1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <3450000>; regulator-ramp-delay = <5000>; diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi new file mode 100644 index 000000000000..4cebfcd87485 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-819000000 { + opp-hz = /bits/ 64 <819000000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1050000 1050000 1050000>; + clock-latency-ns = <200000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz = /bits/ 64 <614400000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-819000000 { + opp-hz = /bits/ 64 <819000000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-microvolt = <950000 950000 1050000>; + clock-latency-ns = <200000>; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1050000 1050000 1050000>; + clock-latency-ns = <200000>; + }; + }; +}; + +&cpu_0 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_1 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_2 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_3 { + operating-points-v2 = <&cluster0_opp_table>; +}; + +&cpu_4 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_5 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_6 { + operating-points-v2 = <&cluster1_opp_table>; +}; + +&cpu_7 { + operating-points-v2 = <&cluster1_opp_table>; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 7d414e15d2cc..3fabfd34114b 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -56,6 +56,7 @@ cpu_0: cpu@0 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <0>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -86,6 +87,7 @@ cpu_1: cpu@1 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <1>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -116,6 +118,7 @@ cpu_2: cpu@2 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <2>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -146,6 +149,7 @@ cpu_3: cpu@3 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <3>; + clocks = <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -176,6 +180,7 @@ cpu_4: cpu@4 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <4>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -206,6 +211,7 @@ cpu_5: cpu@5 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <5>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -236,6 +242,7 @@ cpu_6: cpu@6 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <6>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", @@ -266,6 +273,7 @@ cpu_7: cpu@7 { compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <7>; + clocks = <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", From c5b108626dc5f21c34cf5119c6f5e0cd7561daa8 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sun, 12 Jul 2026 12:00:01 +0800 Subject: [PATCH 535/864] dt-bindings: riscv: spacemit: Add Banana Pi BPI-CM6 compatible The Banana Pi BPI-CM6 IO board consists of the BPI-CM6 compute module plugged into an IO carrier board, which is used for evaluation and development. The core CM6 module is based on the SpacemiT K1 SoC and provides PMIC, DDR, the eth0 PHY and wireless connectivity. The carrier board extends this by adding the eth1 PHY and external interfaces including Ethernet, PCIe M.2, USB, MicroSD, QSPI, and serial console connectivity. Acked-by: Conor Dooley Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260712-bpi-cm6-v3-1-8d1e2045179d@pigmoral.tech Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 311bbccba0ba..4ee9c88984b4 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -19,6 +19,11 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - bananapi,bpi-cm6-io + - const: bananapi,bpi-cm6 + - const: spacemit,k1 - items: - enum: - bananapi,bpi-f3 From 8270311d70fdf36bc8aab1e52b554e654a8839ff Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sun, 12 Jul 2026 12:00:02 +0800 Subject: [PATCH 536/864] riscv: dts: spacemit: k1: Split gmac_clk_ref into independent pinctrl groups The gmac_clk_ref signal is optional for the GMAC controller and is not strictly required for all hardware designs. The pins for gmac0_clk_ref (GPIO 45) and gmac1_clk_ref (GPIO 46) may also be used as GPIOs for other functions even when the Ethernet controller is active. Split the refclk pins into independent pinctrl groups so boards can request them only when the reference clock path is actually needed. Among the already mainlined boards, BPI-F3, Jupiter and MusePi Pro have optional hardware paths for the GMAC refclk pins. BPI-F3 and Jupiter route both GMAC refclk pins to the PHYs through NC/0R option resistors, while MusePi Pro only does so for GMAC0. Keep referencing the new clk-ref pinctrl groups on these boards so the optional hardware paths remain usable if the option resistors are populated. OrangePi R2S has no publicly available schematic, so also keep the clk-ref groups there to preserve the previous pinmux behavior. Fixes: 60775f28cfb7 ("riscv: dts: spacemit: Add Ethernet support for K1") Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260712-bpi-cm6-v3-2-8d1e2045179d@pigmoral.tech Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++-- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 2 +- .../boot/dts/spacemit/k1-orangepi-r2s.dts | 4 ++-- arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 24 +++++++++++++++---- 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 307a7e4a8943..e2961b7e0a3e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -134,7 +134,7 @@ ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac0_cfg>; + pinctrl-0 = <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; status = "okay"; @@ -157,7 +157,7 @@ ð1 { phy-handle = <&rgmii1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac1_cfg>; + pinctrl-0 = <&gmac1_cfg>, <&gmac1_clk_ref_cfg>; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <250>; status = "okay"; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 2fc8d6533786..b61f5995ec77 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -121,7 +121,7 @@ ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac0_cfg>; + pinctrl-0 = <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; status = "okay"; @@ -144,7 +144,7 @@ ð1 { phy-handle = <&rgmii1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac1_cfg>; + pinctrl-0 = <&gmac1_cfg>, <&gmac1_clk_ref_cfg>; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <250>; status = "okay"; diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 0d809e4ad3b1..3078ffb5cb87 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -102,7 +102,7 @@ &combo_phy { ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; - pinctrl-0 = <&gmac0_cfg>; + pinctrl-0 = <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; pinctrl-names = "default"; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index b13a8d6a2670..dd72c33bd54c 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -60,7 +60,7 @@ ð0 { phy-handle = <&rgmii0>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac0_cfg>; + pinctrl-0 = <&gmac0_cfg>, <&gmac0_clk_ref_cfg>; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; status = "okay"; @@ -84,7 +84,7 @@ ð1 { phy-handle = <&rgmii1>; phy-mode = "rgmii-id"; pinctrl-names = "default"; - pinctrl-0 = <&gmac1_cfg>; + pinctrl-0 = <&gmac1_cfg>, <&gmac1_clk_ref_cfg>; rx-internal-delay-ps = <0>; tx-internal-delay-ps = <250>; status = "okay"; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index 4e9a62d0e85b..8c57ca05dabd 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -27,8 +27,16 @@ gmac0-pins { , /* gmac0_tx_en */ , /* gmac0_mdc */ , /* gmac0_mdio */ - , /* gmac0_int_n */ - ; /* gmac0_clk_ref */ + ; /* gmac0_int_n */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + + gmac0_clk_ref_cfg: gmac0-clk-ref-cfg { + gmac0-clk-ref-pins { + pinmux = ; /* gmac0_clk_ref */ bias-pull-up = <0>; drive-strength = <21>; @@ -51,8 +59,16 @@ gmac1-pins { , /* gmac1_tx_en */ , /* gmac1_mdc */ , /* gmac1_mdio */ - , /* gmac1_int_n */ - ; /* gmac1_clk_ref */ + ; /* gmac1_int_n */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + + gmac1_clk_ref_cfg: gmac1-clk-ref-cfg { + gmac1-clk-ref-pins { + pinmux = ; /* gmac1_clk_ref */ bias-pull-up = <0>; drive-strength = <21>; From 46a8c01700ac21e1b83385df00aa0baa5d287b44 Mon Sep 17 00:00:00 2001 From: Junhui Liu Date: Sun, 12 Jul 2026 12:00:03 +0800 Subject: [PATCH 537/864] riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board The Banana Pi BPI-CM6 IO board combines the BPI-CM6 compute module with an IO carrier board. The core module integrates the SpacemiT K1 SoC, PMIC, DDR, eMMC, the eth0 PHY, and wireless connectivity. The companion IO carrier board extends it by providing the eth1 PHY and exposing standard interfaces, including dual Gigabit Ethernet, MicroSD, two USB-A ports, a USB Type-C port, two PCIe M.2 slots, and a serial console. The board also has two I2C EEPROMs. One is on the core module, which stores factory manufacturing data and is marked read-only. The other is on the carrier board, which is shipped unprogrammed and left writable for evaluation purposes. Add initial support for UART console, eMMC, SD card, I2C, EEPROMs, PCIe, USB, and dual Ethernet interfaces. Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6 Reviewed-by: Michael Opdenacker Tested-by: Michael Opdenacker Signed-off-by: Junhui Liu Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260712-bpi-cm6-v3-3-8d1e2045179d@pigmoral.tech Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + .../boot/dts/spacemit/k1-bananapi-cm6-io.dts | 177 ++++++++++++++ .../boot/dts/spacemit/k1-bananapi-cm6.dtsi | 217 ++++++++++++++++++ 3 files changed, 395 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts create mode 100644 arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index 28ec9e1e0a62..851b701e5da4 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-cm6-io.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts new file mode 100644 index 000000000000..2c2d78aee98a --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2026 Junhui Liu + */ + +#include "k1-bananapi-cm6.dtsi" + +#include + +/ { + model = "Banana Pi BPI-CM6 IO Board"; + compatible = "bananapi,bpi-cm6-io", "bananapi,bpi-cm6", "spacemit,k1"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + color = ; + gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_LOW>; + }; + + led1 { + color = ; + gpios = <&gpio K1_GPIO(97) GPIO_ACTIVE_LOW>; + }; + }; + + pcie_vcc_3v3: regulator-pcie-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "NGFF_KEYM_VDD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + usb_vbus_5v: regulator-usb-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "VBUS_A_B"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio K1_GPIO(124) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sd_vcc_3v3: regulator-sd-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3VS_CARD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&combo_phy { + status = "okay"; +}; + +ð0 { + status = "okay"; +}; + +ð1 { + nvmem-cells = <&mac_address 1>; + nvmem-cell-names = "mac-address"; + phy-handle = <&rgmii1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_cfg>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <250>; + status = "okay"; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(46) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii1: phy@1 { + reg = <0x1>; + }; + }; +}; + +&i2c2 { + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + vcc-supply = <&buck3_1v8>; + pagesize = <16>; + size = <1024>; + }; +}; + +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc_3v3>; +}; + +&pcie2 { + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&qspi_cfg>; + status = "okay"; +}; + +&sdhci0 { + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&mmc1_cfg>; + pinctrl-1 = <&mmc1_uhs_cfg>; + bus-width = <4>; + cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + no-mmc; + no-sdio; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_vcc_3v3>; + vqmmc-supply = <&aldo1>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + vbus-supply = <&usb_vbus_5v>; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi new file mode 100644 index 000000000000..bf502c87040a --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2026 Junhui Liu + */ + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model = "Banana Pi BPI-CM6 Module"; + compatible = "bananapi,bpi-cm6", "spacemit,k1"; + + aliases { + i2c2 = &i2c2; + i2c8 = &i2c8; + }; + + reg_vcc_4v: regulator-vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "VCC4V0_SYS"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&emmc { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +ð0 { + nvmem-cells = <&mac_address 0>; + nvmem-cell-names = "mac-address"; + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_cfg>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + reset-gpios = <&gpio K1_GPIO(45) GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + reset-post-delay-us = <100000>; + + rgmii0: phy@1 { + reg = <0x1>; + }; + }; +}; + +&pdma { + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_0_cfg>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&buck3_1v8>; + pagesize = <16>; + read-only; + size = <256>; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac_address: mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + serial-number { + }; + }; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_cfg>; + status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin1-supply = <®_vcc_4v>; + vin2-supply = <®_vcc_4v>; + vin3-supply = <®_vcc_4v>; + vin4-supply = <®_vcc_4v>; + vin5-supply = <®_vcc_4v>; + vin6-supply = <®_vcc_4v>; + aldoin-supply = <®_vcc_4v>; + dldoin1-supply = <&buck5>; + dldoin2-supply = <&buck5>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; From 5ed8cdb56cd90859e0c7f269b4a7c2b1571419b2 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 14 Jul 2026 15:45:11 +0800 Subject: [PATCH 538/864] riscv: dts: thead: th1520: remove pclk for I2C1 The I2C1 node added previously to the th1520.dtsi file has two clocks set -- one "ref" clock (CLK_I2C1) and one "pclk" (CLK_PERI_APB_PCLK). However, the CLK_I2C1 clock is just a clock gate with the CLK_PERI_APB_PCLK clock as its input. In addition, when it's gated, reading registers from the I2C controller returns fixed value (the last read value) for all registers. These facts indicate that the CLK_I2C1 clock is the true APB clock fed into the I2C controller instead of a dedicated reference clock. Leave only the CLK_I2C1 clock as the `clocks` property of the I2C1 device node and remove `clock-names` property, which represents the I2C controller only takes a single clock both as the APB clock and the reference clock. Fixes: 2f60e3516330 ("riscv: dts: thead: Add TH1520 I2C1 controller") Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini Link: https://lore.kernel.org/r/20260714074515.1959352-2-zhengxingda@iscas.ac.cn Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 94932c51b7e3..db23624696b7 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -415,8 +415,7 @@ i2c1: i2c@ffe7f24000 { compatible = "thead,th1520-i2c", "snps,designware-i2c"; reg = <0xff 0xe7f24000 0x0 0x4000>; interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>; - clock-names = "ref", "pclk"; + clocks = <&clk CLK_I2C1>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From b6e4c8fe4cbeb71365e579904fbd4cb6437ff278 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Tue, 14 Jul 2026 15:45:12 +0800 Subject: [PATCH 539/864] riscv: dts: thead: Add TH1520 I2C nodes Add nodes for the remaining five I2C controllers on the T-Head TH1520 RISCV SoC. Link: https://lore.kernel.org/r/20260714074515.1959352-3-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Thomas Bonnefille [Icenowy: rebase and reword commit message to exclude I2C1] Signed-off-by: Icenowy Zheng Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index db23624696b7..b01a94785d87 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -411,6 +411,16 @@ uart3: serial@ffe7f04000 { status = "disabled"; }; + i2c0: i2c@ffe7f20000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f20000 0x0 0x4000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@ffe7f24000 { compatible = "thead,th1520-i2c", "snps,designware-i2c"; reg = <0xff 0xe7f24000 0x0 0x4000>; @@ -421,6 +431,16 @@ i2c1: i2c@ffe7f24000 { status = "disabled"; }; + i2c4: i2c@ffe7f28000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xe7f28000 0x0 0x4000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; @@ -519,6 +539,16 @@ padctrl0_apsys: pinctrl@ffec007000 { thead,pad-group = <3>; }; + i2c2: i2c@ffec00c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec00c000 0x0 0x4000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -530,6 +560,16 @@ uart2: serial@ffec010000 { status = "disabled"; }; + i2c3: i2c@ffec014000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xec014000 0x0 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pwm: pwm@ffec01c000 { compatible = "thead,th1520-pwm"; reg = <0xff 0xec01c000 0x0 0x4000>; @@ -735,6 +775,16 @@ uart5: serial@fff7f0c000 { status = "disabled"; }; + i2c5: i2c@fff7f2c000 { + compatible = "thead,th1520-i2c", "snps,designware-i2c"; + reg = <0xff 0xf7f2c000 0x0 0x4000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_I2C5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; From c8f71218e9ac1a01fd355eabe62957df17d13b83 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 14 Jul 2026 15:45:13 +0800 Subject: [PATCH 540/864] riscv: dts: thead: lpi4a: sort nodes Although "D", "H" and "I" are earlier in the alphabet than "P", the DPU, HDMI and I2C1 nodes were added after PADCTRL nodes in the Lichee Pi 4A device tree; in addition the PADCTRL1 node is placed before the PADCTRL0 one. Sort the nodes in this device tree. Link: https://lore.kernel.org/r/20260714074515.1959352-4-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Icenowy Zheng Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 72 +++++++++---------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index af6f25ebbf60..74b120c6b063 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -103,17 +103,31 @@ fan: pwm-fan { }; -&padctrl1_apsys { - i2c1_pins: i2c1-0 { - i2c-pins { - pins = "I2C1_SCL", "I2C1_SDA"; - function = "i2c"; - bias-pull-up = <2100>; - drive-strength = <7>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; +&dpu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; + + ioexp2: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; }; }; @@ -153,17 +167,17 @@ rx-pins { }; }; -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - status = "okay"; - - ioexp2: gpio@18 { - compatible = "nxp,pca9557"; - reg = <0x18>; - gpio-controller; - #gpio-cells = <2>; +&padctrl1_apsys { + i2c1_pins: i2c1-0 { + i2c-pins { + pins = "I2C1_SCL", "I2C1_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; }; }; @@ -179,20 +193,6 @@ &sdio1 { status = "okay"; }; -&dpu { - status = "okay"; -}; - -&hdmi { - status = "okay"; -}; - -&hdmi_out_port { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; From 01ba55917c27161f8480adf17c1bb8c6f6b62a09 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 14 Jul 2026 15:45:14 +0800 Subject: [PATCH 541/864] riscv: dts: thead: Add IO labels for the IO expansion on I2C1 Add labels for GPIOs on the IO expansion chip on the I2C1 bus. Link: https://lore.kernel.org/r/20260714074515.1959352-5-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Emil Renner Berthing [Icenowy: Splitted off the patch adding all 3 IO expansions] Signed-off-by: Icenowy Zheng [fustini: align ioexp2 gpio-line-names with schematic] Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 74b120c6b063..5523957430ea 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -128,6 +128,14 @@ ioexp2: gpio@18 { reg = <0x18>; gpio-controller; #gpio-cells = <2>; + gpio-line-names = "", + "cam0_reset", + "cam1_reset", + "cam2_reset", + "wl_host_wake_dev", + "bt_resetn", + "", + "bt_host_wake_dev"; }; }; From 15d32aaf6300b832814a9930fdbd20efdbc9adcf Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 14 Jul 2026 15:45:15 +0800 Subject: [PATCH 542/864] riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the I2C0/1/3 busses. The I2C1 one is already added to the device tree, but the I2C0/3 ones are not yet added. Add device tree nodes for them. Link: https://lore.kernel.org/r/20260714074515.1959352-6-zhengxingda@iscas.ac.cn Reviewed-by: Drew Fustini Signed-off-by: Emil Renner Berthing [Icenowy: added commit description, enable SoC pull-up, remove I2C1 and aliases] Signed-off-by: Icenowy Zheng Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index 5523957430ea..1eb575aa9a74 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -117,6 +117,23 @@ hdmi_out_con: endpoint { }; }; +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + ioexp1: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "cam0_dvdd12", + "cam0_avdd28", + "cam0_dovdd18"; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -139,6 +156,28 @@ ioexp2: gpio@18 { }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; + + ioexp3: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "tp0_rst", + "", + "", + "vcc5v_usb", + "vdd28_tp0", + "vdd33_lcd0", + "vdd18_lcd0", + "lcd0_reset"; + }; +}; + &padctrl0_apsys { fan_pins: fan-0 { pwm1-pins { @@ -152,6 +191,18 @@ pwm1-pins { }; }; + i2c3_pins: i2c3-0 { + i2c-pins { + pins = "I2C3_SCL", "I2C3_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins = "UART0_TXD"; @@ -176,6 +227,18 @@ rx-pins { }; &padctrl1_apsys { + i2c0_pins: i2c0-0 { + i2c-pins { + pins = "I2C0_SCL", "I2C0_SDA"; + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + i2c1_pins: i2c1-0 { i2c-pins { pins = "I2C1_SCL", "I2C1_SDA"; From d31e5aebbe71746c1389bdf6b0a8b26cc01751e8 Mon Sep 17 00:00:00 2001 From: Leonardo Costa Date: Tue, 14 Jul 2026 11:47:35 +0530 Subject: [PATCH 543/864] arm64: dts: ti: k3-am62-verdin: Add Toradex Capacitive Touch Display 10.1" LVDS V2 Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" LVDS V2 connected via Verdin AM62 OLDI on carrier boards exposing LVDS interface (e.g., Mallow). The panel is an Opto Logic SCX1001511GGC49 10.1" WXGA TFT LCD and the touch input is provided by an ILITEK ILI251x capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Leonardo Costa Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260623195741.495734-4-leoreis.costa@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...verdin-panel-cap-touch-10inch-lvds-v2.dtso | 129 ++++++++++++++++++ 2 files changed, 134 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index faa11016bcb7..220363ba1487 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-ov5640-24mhz.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-uart4-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb @@ -268,6 +269,9 @@ k3-am625-verdin-wifi-dev-uart4-mcu-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-dtbs := \ k3-am625-verdin-wifi-mallow.dtb \ k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo +k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-v2-dtbs := \ + k3-am625-verdin-wifi-mallow.dtb \ + k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtbo k3-am62-lp-sk-hdmi-audio-dtbs := k3-am62-lp-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am62-lp-sk-nand-dtbs := k3-am62-lp-sk.dtb k3-am62-lp-sk-nand.dtbo k3-am62a7-phyboard-lyra-disable-eth-phy-dtbs := k3-am62a7-phyboard-lyra-rdk.dtb \ @@ -398,6 +402,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb \ k3-am625-verdin-wifi-dev-uart4-mcu.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ + k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-v2.dtb \ k3-am62-lp-sk-hdmi-audio.dtb \ k3-am62-lp-sk-nand.dtb \ k3-am62a7-phyboard-lyra-disable-eth-phy.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtso new file mode 100644 index 000000000000..3ea8ccb8bff9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtso @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" V2 connected via Verdin AM62 OLDI + * on carrier boards with a Toradex standard LVDS display connector + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include "k3-pinctrl.h" + +&{/} { + backlight_pwm2: backlight-pwm2 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_gpio>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT as GPIO (SODIMM 46) */ + enable-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) */ + pwms = <&epwm0 1 6666667 0>; + }; + + panel-lvds-native { + compatible = "optologic,scx1001511ggc49", "panel-lvds"; + backlight = <&backlight_pwm2>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <64500000>; + hactive = <1280>; + hback-porch = <20>; + hfront-porch = <20>; + hsync-len = <2>; + vactive = <800>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <3>; + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_lvds_native_in: endpoint { + remote-endpoint = <&oldi0_out>; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS VP1: internal DPI output to OLDIx */ + port@0 { + reg = <0>; + + dss0_out: endpoint { + remote-endpoint = <&oldi0_in>; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_in_gpio>, + <&pinctrl_i2s_2_sync_gpio>; + /* Verdin I2S_2_SYNC as GPIO (SODIMM 44) */ + interrupt-parent = <&main_gpio0>; + interrupts = <37 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_D_IN as GPIO(SODIMM 48) */ + reset-gpios = <&main_gpio0 33 GPIO_ACTIVE_LOW>; + }; +}; + +&main_pmx0 { + pinctrl_i2s_2_d_in_gpio: main-gpio0-33-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0088, PIN_INPUT, 7) /* (L24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + >; + }; + + pinctrl_i2s_2_sync_gpio: main-gpio0-37-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0098, PIN_INPUT, 7) /* (U23) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + >; + }; +}; + +&oldi0 { + status = "okay"; +}; + +&oldi0_port0 { + oldi0_in: endpoint { + remote-endpoint = <&dss0_out>; + }; +}; + +&oldi0_port1 { + oldi0_out: endpoint { + remote-endpoint = <&panel_lvds_native_in>; + }; +}; From abc20b6665329a6ae9b78f5da9232509f2a0a68e Mon Sep 17 00:00:00 2001 From: Leonardo Costa Date: Tue, 23 Jun 2026 16:57:40 -0300 Subject: [PATCH 544/864] arm64: dts: ti: k3-am62-verdin: Add Toradex DSI to LVDS adapter with the 10.1" V2 display Add a device tree overlay for the Toradex DSI to LVDS Adapter with the Toradex Capacitive Touch Display 10.1" LVDS V2. The adapter connects to the Verdin DSI_1 interface. It is based on the Texas Instruments SN65DSI84 DSI-to-LVDS bridge and drives an Opto Logic SCX1001511GGC49 10.1" WXGA TFT LCD LVDS panel. Touch input is provided by an ILITEK ILI251x capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Leonardo Costa Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260623195741.495734-5-leoreis.costa@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...dsi-to-lvds-v2-panel-cap-touch-10inch.dtso | 143 ++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-v2-panel-cap-touch-10inch.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 220363ba1487..dcde6be758b8 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lv dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-v2-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb @@ -250,6 +251,9 @@ k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo +k3-am625-verdin-wifi-dev-dsi-to-lvds-v2-panel-cap-touch-10inch-dtbs := \ + k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dsi-to-lvds-v2-panel-cap-touch-10inch.dtbo k3-am625-verdin-wifi-dev-mezzanine-can-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-mezzanine-can.dtbo k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds-dtbs := \ @@ -394,6 +398,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ + k3-am625-verdin-wifi-dev-dsi-to-lvds-v2-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-mezzanine-can.dtb \ k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds.dtb \ k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-v2-panel-cap-touch-10inch.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-v2-panel-cap-touch-10inch.dtso new file mode 100644 index 000000000000..dba0b6b9f02d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dsi-to-lvds-v2-panel-cap-touch-10inch.dtso @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to LVDS Adapter on Verdin DSI_1 with Capacitive Touch Display 10.1" + * Used on Dahlia (X17) and Development Board (X48) that expose DSI_1 via an + * Samtec LSS-130 connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter + * https://www.toradex.com/accessories/verdin-dsi-to-lvds-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_gpio>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT as GPIO (SODIMM 46) */ + enable-gpios = <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + pwms = <&epwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "optologic,scx1001511ggc49", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + /* + * The timings here are different from the nominal ones for the + * SCX1001511GGC49 display. They are adjusted to ensure that + * the Horizontal Front Porch is long enough for the Verdin + * AM62 DPI->DSI bridge (Toshiba TC358768) to enter/exit LP + * mode. This is required for the display pipeline to work + * correctly. + */ + panel-timing { + clock-frequency = <69500000>; + hactive = <1280>; + hback-porch = <20>; + hfront-porch = <100>; + hsync-len = <24>; + vactive = <800>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <3>; + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +&dsi_bridge { + status = "okay"; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_bridge_out: endpoint { + remote-endpoint = <&dsi_lvds_bridge_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_bkl_en>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_bridge_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi1_int>, <&pinctrl_i2s_2_bclk_gpio>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + interrupt-parent = <&main_gpio1>; + interrupts = <49 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&main_gpio0 35 GPIO_ACTIVE_LOW>; + }; +}; From 654c5986e36295e594158fc22a0b206bf9c04733 Mon Sep 17 00:00:00 2001 From: Leonardo Costa Date: Tue, 23 Jun 2026 16:57:41 -0300 Subject: [PATCH 545/864] arm64: dts: ti: k3-am62-verdin: Add Mezzanine with Toradex Display 10.1" LVDS Add a device tree overlay enabling the Toradex Capacitive Touch Display 10.1" LVDS V2 on the Verdin Development Board with Verdin AM62 Mezzanine expansion board. The panel connects via the AM62 OLDI0 on the Mezzanine LVDS interface (J10). The panel is an Opto Logic SCX1001511GGC49 10.1" WXGA TFT LCD LVDS and the touch input is provided by an ILITEK ILI251x capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Leonardo Costa Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260623195741.495734-6-leoreis.costa@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + ...zanine-panel-cap-touch-10inch-lvds-v2.dtso | 109 ++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index dcde6be758b8..448fcdeb408b 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-can.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -259,6 +260,9 @@ k3-am625-verdin-wifi-dev-mezzanine-can-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds.dtbo +k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds-v2-dtbs := \ + k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtbo k3-am625-verdin-wifi-dev-nau8822-btl-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dev-nau8822-btl.dtbo k3-am625-verdin-wifi-dev-ov5640-24mhz-dtbs := k3-am625-verdin-wifi-dev.dtb \ @@ -401,6 +405,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-v2-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-mezzanine-can.dtb \ k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds.dtb \ + k3-am625-verdin-wifi-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtb \ k3-am625-verdin-wifi-dev-nau8822-btl.dtb \ k3-am625-verdin-wifi-dev-ov5640-24mhz.dtb \ k3-am625-verdin-wifi-dev-ov5640.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtso new file mode 100644 index 000000000000..26f671546398 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-dev-mezzanine-panel-cap-touch-10inch-lvds-v2.dtso @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" LVDS V2 on the Verdin AM62 Mezzanine + * LVDS interface (J10), used with the Verdin Development Board. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm2: backlight-pwm2 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin GPIO_4 (SODIMM 212) - LVDS_BKL_EN */ + enable-gpios = <&mcu_gpio0 4 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) - LVDS_PWM */ + pwms = <&epwm0 1 6666667 0>; + }; + + panel-lvds-native { + compatible = "optologic,scx1001511ggc49", "panel-lvds"; + backlight = <&backlight_pwm2>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <64500000>; + hactive = <1280>; + hback-porch = <20>; + hfront-porch = <20>; + hsync-len = <2>; + vactive = <800>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <3>; + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_lvds_native_in: endpoint { + remote-endpoint = <&oldi0_out>; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* DSS VP1: internal DPI output to OLDIx */ + port@0 { + reg = <0>; + + dss0_out: endpoint { + remote-endpoint = <&oldi0_in>; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + /* Verdin GPIO_3 (SODIMM 210) - LVDS_TOUCH_INT# */ + interrupt-parent = <&mcu_gpio0>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + /* Verdin GPIO_2 (SODIMM 208) - LVDS_TOUCH_RST# */ + reset-gpios = <&mcu_gpio0 2 GPIO_ACTIVE_LOW>; + }; +}; + +&oldi0 { + status = "okay"; +}; + +&oldi0_port0 { + oldi0_in: endpoint { + remote-endpoint = <&dss0_out>; + }; +}; + +&oldi0_port1 { + oldi0_out: endpoint { + remote-endpoint = <&panel_lvds_native_in>; + }; +}; From a8dd4468629fac5e0d93bbbb98a487e4190a5ce9 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Wed, 15 Jul 2026 07:54:45 +0200 Subject: [PATCH 546/864] arm64: dts: ti: k3-am62-verdin: Add RPi Touch Display 2 7-inch Add a device tree overlay for the Raspberry Pi Touch Display 2 7" on the Verdin DSI_1 interface. Link: https://www.raspberrypi.com/products/touch-display-2/ Signed-off-by: Francesco Dolcini Link: https://patch.msgid.link/20260715055446.31139-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 5 + .../ti/k3-am625-verdin-rpi-display-2-7in.dtso | 101 ++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-rpi-display-2-7in.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 448fcdeb408b..1fbcc0efdafb 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-rpi-display-2-7in.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-uart4-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb @@ -272,6 +273,9 @@ k3-am625-verdin-wifi-dev-ov5640-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo +k3-am625-verdin-wifi-dev-rpi-display-2-7in-dtbs := \ + k3-am625-verdin-wifi-dev.dtb \ + k3-am625-verdin-rpi-display-2-7in.dtbo k3-am625-verdin-wifi-dev-uart4-mcu-dtbs := k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-uart4-mcu.dtbo k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-dtbs := \ @@ -410,6 +414,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-verdin-wifi-dev-ov5640-24mhz.dtb \ k3-am625-verdin-wifi-dev-ov5640.dtb \ k3-am625-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb \ + k3-am625-verdin-wifi-dev-rpi-display-2-7in.dtb \ k3-am625-verdin-wifi-dev-uart4-mcu.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds.dtb \ k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-v2.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-rpi-display-2-7in.dtso b/arch/arm64/boot/dts/ti/k3-am625-verdin-rpi-display-2-7in.dtso new file mode 100644 index 000000000000..8366bebbd5d2 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-rpi-display-2-7in.dtso @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Raspberry Pi Touch Display 2 7" on Verdin DSI_1 and I2C_2_DSI + * + * https://www.raspberrypi.com/products/touch-display-2/ + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + backlight_rpi: backlight-rpi-display { + compatible = "pwm-backlight"; + brightness-levels = <0 31>; + default-brightness-level = <15>; + num-interpolated-steps = <31>; + pwms = <&mcu_display_rpi 0 200000 0>; + }; + + reg_display_rpi: regulator-rpi-display { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "rpi-display"; + }; + + reg_display_rpi_touch: regulator-rpi-display-touch { + compatible = "regulator-fixed"; + gpio = <&mcu_display_rpi 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "rpi-display-touch"; + startup-delay-us = <50000>; + }; + +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + mcu_display_rpi: regulator@45 { + compatible = "raspberrypi,touchscreen-panel-regulator-v2"; + reg = <0x45>; + #gpio-cells = <2>; + #pwm-cells = <3>; + gpio-controller; + }; + + touchscreen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + AVDD28-supply = <®_display_rpi_touch>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + }; +}; + +&dsi_bridge { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + panel@0 { + compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c"; + reg = <0>; + backlight = <&backlight_rpi>; + power-supply = <®_display_rpi>; + reset-gpios = <&mcu_display_rpi 0 GPIO_ACTIVE_LOW>; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi_bridge_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_bridge_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; + }; +}; + +&dss { + status = "okay"; +}; From 6060bb0c91346a12924e9060518188b0eba6d072 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Thu, 16 Jul 2026 19:43:00 +0100 Subject: [PATCH 547/864] arm64: dts: ti: k3-am62p-verdin: Add NAU8822 Bridge Tied Load Add a device tree overlay enabling Bridge Tied Load (BTL) mode on the Nuvoton NAU8822 audio codec present on the Verdin Development Board. In BTL mode, the two loudspeaker outputs are bridged to deliver higher output power on the X28 speaker connector. Reviewed-by: Francesco Dolcini Signed-off-by: Vitor Soares Link: https://patch.msgid.link/20260716184300.85413-6-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 ++++ .../dts/ti/k3-am62p5-verdin-dev-nau8822-btl.dtso | 14 ++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-dev-nau8822-btl.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 1fbcc0efdafb..51625c3f592e 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62l3-evm.dtb # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb @@ -309,6 +310,8 @@ k3-am62p5-sk-csi2-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-ov5640.dtbo k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo +k3-am62p5-verdin-wifi-dev-nau8822-btl-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ + k3-am62p5-verdin-dev-nau8822-btl.dtbo k3-am642-evm-icssg0-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg0.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ @@ -431,6 +434,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-imx219.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ + k3-am62p5-verdin-wifi-dev-nau8822-btl.dtb \ k3-am642-evm-icssg0.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-evm-icssg1-dualemac-mii.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-dev-nau8822-btl.dtso b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-dev-nau8822-btl.dtso new file mode 100644 index 000000000000..e4b662519a6b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-dev-nau8822-btl.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Enable Bridge Tied Load (BTL) speaker mode on the Verdin Development Board, + * combining the two loudspeaker outputs for higher output power. + */ + +/dts-v1/; +/plugin/; + +&nau8822_1a { + nuvoton,spk-btl; +}; From 8fa44cad1af27e117d60ef90606aa3e824dcf855 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Thu, 16 Jul 2026 19:43:01 +0100 Subject: [PATCH 548/864] arm64: dts: ti: k3-am62p-verdin: Add Toradex OV5640 CSI Cameras Add device tree overlays for the Toradex OV5640 CSI Cameras on Verdin AM62P CSI_1. Two variants are supported: the current CSI Camera Set 5MP OV5640 with a 27 MHz oscillator and the legacy CSI Camera Module 5MP OV5640 with a 24 MHz oscillator. Link: https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam Link: https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ Reviewed-by: Francesco Dolcini Signed-off-by: Vitor Soares Link: https://patch.msgid.link/20260716184300.85413-7-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 8 +++ .../dts/ti/k3-am62p5-verdin-ov5640-24mhz.dtso | 17 +++++ .../boot/dts/ti/k3-am62p5-verdin-ov5640.dtsi | 72 +++++++++++++++++++ .../boot/dts/ti/k3-am62p5-verdin-ov5640.dtso | 18 +++++ 4 files changed, 115 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640-24mhz.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 51625c3f592e..4904a40898eb 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -90,6 +90,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-nonwifi-yavia.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-ov5640-24mhz.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62p5-verdin-wifi-ivy.dtb @@ -312,6 +314,10 @@ k3-am62p5-sk-csi2-tevi-ov5640-dtbs := k3-am62p5-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am62p5-verdin-wifi-dev-nau8822-btl-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ k3-am62p5-verdin-dev-nau8822-btl.dtbo +k3-am62p5-verdin-wifi-dev-ov5640-24mhz-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ + k3-am62p5-verdin-ov5640-24mhz.dtbo +k3-am62p5-verdin-wifi-dev-ov5640-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ + k3-am62p5-verdin-ov5640.dtbo k3-am642-evm-icssg0-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg0.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ @@ -435,6 +441,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-ov5640.dtb \ k3-am62p5-sk-csi2-tevi-ov5640.dtb \ k3-am62p5-verdin-wifi-dev-nau8822-btl.dtb \ + k3-am62p5-verdin-wifi-dev-ov5640-24mhz.dtb \ + k3-am62p5-verdin-wifi-dev-ov5640.dtb \ k3-am642-evm-icssg0.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-evm-icssg1-dualemac-mii.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640-24mhz.dtso b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640-24mhz.dtso new file mode 100644 index 000000000000..1da6329065e6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640-24mhz.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Module 5MP OV5640 on Verdin AM62P CSI_1. + * + * https://developer.toradex.com/hardware/legacy-products/other/csi-camera-module-5mp-ov5640/ + */ + +/dts-v1/; +/plugin/; + +#include "k3-am62p5-verdin-ov5640.dtsi" + +&clock_camera { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtsi new file mode 100644 index 000000000000..ab6c00884fb2 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Common device tree include for Toradex OV5640 CSI camera on Verdin AM62P CSI_1. + */ + +#include + +&{/} { + clock_camera: clock-camera { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + regulator_camera: regulator-camera { + compatible = "regulator-fixed"; + /* Verdin GPIO_8_CSI (SODIMM 222) - CAM_1_CON_PWRCTRL */ + gpio = <&main_gpio0 52 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "V_CSI"; + startup-delay-us = <5000>; + }; +}; + +&csi0_port0 { + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; +}; + +&dphy0 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + + clocks = <&clock_camera>; + clock-names = "xclk"; + AVDD-supply = <®ulator_camera>; + DOVDD-supply = <®ulator_camera>; + DVDD-supply = <®ulator_camera>; + /* Verdin GPIO_6 (SODIMM 218) - CAM_1_CON_PWRDWN */ + powerdown-gpios = <&main_gpio0 50 GPIO_ACTIVE_HIGH>; + /* Verdin GPIO_5 (SODIMM 216) - CAM_1_CON_RST */ + reset-gpios = <&main_gpio0 49 GPIO_ACTIVE_LOW>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtso b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtso new file mode 100644 index 000000000000..2e90aeb448b9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-verdin-ov5640.dtso @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex CSI Camera Set 5MP OV5640 on Verdin AM62P CSI_1. + * + * https://developer.toradex.com/hardware/accessories/cameras/csi-camera-module-5mp-ov5640-arducam + * https://www.toradex.com/accessories/csi-camera-ov5640 + */ + +/dts-v1/; +/plugin/; + +#include "k3-am62p5-verdin-ov5640.dtsi" + +&clock_camera { + clock-frequency = <27000000>; +}; From e706dc8f121d9245ccf53f51acc169875198b912 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Thu, 16 Jul 2026 19:43:02 +0100 Subject: [PATCH 549/864] arm64: dts: ti: k3-am62x-verdin: Share UART_4 MCU reservation overlay Verdin AM62 and AM62P both expose mcu_uart0 as Verdin UART_4, and the reservation needed when this UART is used by the MCU firmware is identical on both SoMs. Rename the AM625-specific overlay added in commit ca61bcec3e8a ("arm64: dts: ti: k3-am62-verdin: Reserve UART_4 for Cortex-M4F") to a common k3-am62x-verdin overlay and use it for both AM625 and AM62P5 Verdin combined DTBs. This avoids carrying identical SoC-specific overlays for each remoteproc firmware/peripheral combination. Signed-off-by: Vitor Soares Link: https://patch.msgid.link/20260716184300.85413-8-ivitro@gmail.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 9 +++++++-- ...din-uart4-mcu.dtso => k3-am62x-verdin-uart4-mcu.dtso} | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) rename arch/arm64/boot/dts/ti/{k3-am625-verdin-uart4-mcu.dtso => k3-am62x-verdin-uart4-mcu.dtso} (69%) diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4904a40898eb..f4d109ef6798 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -53,7 +53,6 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-10inch-lvds-v2.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-rpi-display-2-7in.dtbo -dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-uart4-mcu.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb @@ -104,6 +103,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-csi2-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo +# Common overlays for Verdin AM62 and AM62P family of boards +dtb-$(CONFIG_ARCH_K3) += k3-am62x-verdin-uart4-mcu.dtbo + # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm-icssg0.dtbo @@ -280,7 +282,7 @@ k3-am625-verdin-wifi-dev-rpi-display-2-7in-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-rpi-display-2-7in.dtbo k3-am625-verdin-wifi-dev-uart4-mcu-dtbs := k3-am625-verdin-wifi-dev.dtb \ - k3-am625-verdin-uart4-mcu.dtbo + k3-am62x-verdin-uart4-mcu.dtbo k3-am625-verdin-wifi-mallow-panel-cap-touch-10inch-lvds-dtbs := \ k3-am625-verdin-wifi-mallow.dtb \ k3-am625-verdin-panel-cap-touch-10inch-lvds.dtbo @@ -318,6 +320,8 @@ k3-am62p5-verdin-wifi-dev-ov5640-24mhz-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ k3-am62p5-verdin-ov5640-24mhz.dtbo k3-am62p5-verdin-wifi-dev-ov5640-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ k3-am62p5-verdin-ov5640.dtbo +k3-am62p5-verdin-wifi-dev-uart4-mcu-dtbs := k3-am62p5-verdin-wifi-dev.dtb \ + k3-am62x-verdin-uart4-mcu.dtbo k3-am642-evm-icssg0-dtbs := \ k3-am642-evm.dtb k3-am642-evm-icssg0.dtbo k3-am642-evm-icssg1-dualemac-dtbs := \ @@ -443,6 +447,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62p5-verdin-wifi-dev-nau8822-btl.dtb \ k3-am62p5-verdin-wifi-dev-ov5640-24mhz.dtb \ k3-am62p5-verdin-wifi-dev-ov5640.dtb \ + k3-am62p5-verdin-wifi-dev-uart4-mcu.dtb \ k3-am642-evm-icssg0.dtb \ k3-am642-evm-icssg1-dualemac.dtb \ k3-am642-evm-icssg1-dualemac-mii.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso b/arch/arm64/boot/dts/ti/k3-am62x-verdin-uart4-mcu.dtso similarity index 69% rename from arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso rename to arch/arm64/boot/dts/ti/k3-am62x-verdin-uart4-mcu.dtso index e263809cdf74..a3b50efbe52b 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-verdin-uart4-mcu.dtso +++ b/arch/arm64/boot/dts/ti/k3-am62x-verdin-uart4-mcu.dtso @@ -2,7 +2,7 @@ /* * Copyright (c) Toradex * - * Verdin AM62 Cortex-M4F debug UART + * Verdin AM62 and AM62P UART_4 reserved for the MCU co-processor */ /dts-v1/; From fbe849c4b5ae435d873547f522363c7220ca36c7 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Tue, 14 Jul 2026 18:05:48 -0500 Subject: [PATCH 550/864] arm64: dts: ti: k3-am62l: Add bootph to usb0 The AM62L-EVM has the ability to boot via DFU. Add the boot phase property to the usb0 node to enable this boot mode. Signed-off-by: Anshul Dalal Signed-off-by: Bryan Brattlof Link: https://patch.msgid.link/20260714-am62lx-evm-dfu-v1-1-62b025bea71a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62l3-evm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts index a1af4571a815..84a0cfaaf196 100644 --- a/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62l3-evm.dts @@ -356,6 +356,7 @@ &usbss0 { &usb0 { usb-role-switch; + bootph-all; port { usb0_hs_ep: endpoint { From 77b7c62b50f95443865fb6e10bafc8739362478c Mon Sep 17 00:00:00 2001 From: Aradhya Bhatia Date: Thu, 23 Jul 2026 13:03:41 +0530 Subject: [PATCH 551/864] arm64: dts: ti: Add Microtips OLDI SK-LCD1 Overlay for AM625-SK The panel is Microtips Technology USA MF-101HIEBCAF0[1]. It is a Dual-Link LVDS panel and supports WUXGA resolution (1920x1200). Furthermore, it has an i2c based touch controller: Ilitek-ILI2511. Add DT overlay for the OLDI Panel. [1]: https://www.ti.com/tool/SK-LCD1 Signed-off-by: Aradhya Bhatia Signed-off-by: Swamil Jain Link: https://patch.msgid.link/20260723073341.3229436-1-s-jain1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../k3-am625-sk-microtips-mf101hie-panel.dtso | 121 ++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index f4d109ef6798..dba641193144 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-microtips-mf101hie-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-tqma62xx-mba62xx.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-dev-mezzanine-can.dtbo @@ -255,6 +256,8 @@ k3-am625-sk-csi2-ov5640-dtbs := k3-am625-sk.dtb \ k3-am625-sk-csi2-tevi-ov5640-dtbs := k3-am625-sk.dtb \ k3-am62x-sk-csi2-tevi-ov5640.dtbo k3-am625-sk-hdmi-audio-dtbs := k3-am625-sk.dtb k3-am62x-sk-hdmi-audio.dtbo +k3-am625-sk-microtips-mf101hie-panel-dtbs := k3-am625-sk.dtb \ + k3-am625-sk-microtips-mf101hie-panel.dtbo k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := \ k3-am625-verdin-wifi-dev.dtb \ k3-am625-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo @@ -418,6 +421,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-sk-csi2-ov5640.dtb \ k3-am625-sk-csi2-tevi-ov5640.dtb \ k3-am625-sk-hdmi-audio.dtb \ + k3-am625-sk-microtips-mf101hie-panel.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-dsi-to-lvds-v2-panel-cap-touch-10inch.dtb \ k3-am625-verdin-wifi-dev-mezzanine-can.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso b/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso new file mode 100644 index 000000000000..ce7b31c5b9a6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Microtips integrated OLDI panel (MF-101HIEBCAF0) and touch DT overlay for AM625 - SK + * + * Copyright (C) 2026 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + display { + compatible = "microtips,mf-101hiebcaf0"; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + power-supply = <&vcc_3v3_sys>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0>; +}; + +&oldi0_port0 { + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; +}; + +&oldi0_port1 { + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; +}; + +&oldi1_port0 { + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; +}; + +&oldi1_port1 { + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&exp1>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + }; +}; From 8a78168e98a93a6f4f2617347a83286f519ac247 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 24 Jul 2026 09:50:04 +0200 Subject: [PATCH 552/864] ARM: dts: ixp4xx: Drop the reg-offset hack The reg-offset hack only works when the IXP4xx platform is running in big endian mode, and it is there to byte-offset the byte where the serial registers appear in the BE config. This is clearly wrong, workarounds need to be in the drivers. Drop the reg-offset. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20260724-ixp4xx-dts-fix-v1-1-09bf7111e94e@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi index 0adeccabd4fe..b0f98da8def4 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi @@ -84,11 +84,6 @@ pci@c0000000 { uart0: serial@c8000000 { compatible = "intel,xscale-uart"; reg = <0xc8000000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; reg-shift = <2>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <14745600>; @@ -98,11 +93,6 @@ uart0: serial@c8000000 { uart1: serial@c8001000 { compatible = "intel,xscale-uart"; reg = <0xc8001000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; reg-shift = <2>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <14745600>; From 66f407e2c3b9ee768ae164687c2c293deb27d382 Mon Sep 17 00:00:00 2001 From: Daniele Briguglio Date: Wed, 10 Jun 2026 15:59:00 +0200 Subject: [PATCH 553/864] arm64: dts: rockchip: Add Youyeetoo YY3588 The YY3588 is a single board computer built around the Rockchip RK3588. Specification: - Rockchip RK3588 SoC - 4/8/16/32 GB LPDDR4/4x - up to 256 GB eMMC - microSD card slot - 1x 1000Base-T (Realtek RTL8211F) and 1x 2500Base-T (Realtek RTL8125) - HDMI 2.1 output - HDMI input - 4x USB 3.0 Type-A via onboard hub, 1x USB 2.0 Type-A - USB Type-C with USB 3.0 - M.2 M-key with PCIe 3.0 x4 - Mini PCIe slot for WiFi/BT or 4G modules - SATA 3.0 - ES8388 audio codec with headphone jack and onboard microphone - fan connector, RTC, recovery key - 12 V DC input Both Ethernet ports, eMMC, SD card, USB, Type-C, HDMI output, WiFi on the Mini PCIe slot, audio, the recovery key and the fan have been tested on the board. Link: https://wiki.youyeetoo.com/YY3588 Signed-off-by: Daniele Briguglio Link: https://patch.msgid.link/20260610-yy3588-board-v1-3-4bb7176b6826@superkali.me Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-youyeetoo-yy3588.dts | 1180 +++++++++++++++++ 2 files changed, 1181 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 761d82b4f4f2..6cab03c9c4a4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -213,6 +213,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-youyeetoo-yy3588.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-gameforce-ace.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts new file mode 100644 index 000000000000..d631731346f7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts @@ -0,0 +1,1180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Youyeetoo + * Copyright (c) 2026 Daniele Briguglio + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Youyeetoo YY3588"; + compatible = "youyeetoo,yy3588", "rockchip,rk3588"; + + aliases { + ethernet0 = &gmac1; + ethernet1 = &r8125; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + simple-audio-card,name = "rockchip-es8388"; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,pin-switches = "Headphones", "Speaker"; + simple-audio-card,routing = + "Headphones", "LOUT2", + "Headphones", "ROUT2", + "Speaker Amp INL", "LOUT1", + "Speaker Amp INR", "ROUT1", + "Speaker", "Speaker Amp OUTL", + "Speaker", "Speaker Amp OUTR", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + /* PI6C557-05BLE PCIe 3.0 reference clock generator */ + pcie30_port0_refclk: pcie-oscillator { + compatible = "gated-fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie30_refclk"; + vdd-supply = <&vcc3v3_pi6c_05>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 100 150 200 255>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 50000 0>; + }; + + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: regulator-pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pi6c_05_pwren>; + regulator-name = "vcc3v3_pi6c_05"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sd_s0: regulator-vcc3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spk_en>; + sound-name-prefix = "Speaker Amp"; + VCC-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "input"; + phy-handle = <&rgmii_phy>; + /* RX delay is added by the PHY, TX delay by the GMAC */ + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout>; + tx_delay = <0x43>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi0 { + frl-enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_det>; + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "source"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc3v3_sys>; + DVDD-supply = <&vcc_1v8_s3>; + HPVDD-supply = <&vcc3v3_sys>; + PVDD-supply = <&vcc_1v8_s3>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + r8125: ethernet@0,0 { + reg = <0x310000 0 0 0 0>; + }; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie30_port0_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3x4_perstn>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_sys>; + status = "okay"; +}; + +&pinctrl { + hdmirx { + hdmirx_5v_det: hdmirx-5v-det { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_pins: led-pins { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pi6c_05_pwren: pi6c-05-pwren { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3x4_perstn: pcie3x4-perstn { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + spk_en: spk-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-0 = <&pwm2m2_pins>; + status = "okay"; +}; + +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1m0_xfer>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&uart6 { + pinctrl-0 = <&uart6m0_xfer>; + status = "okay"; +}; + +&uart7 { + pinctrl-0 = <&uart7m0_xfer>; + status = "okay"; +}; + +&uart9 { + pinctrl-0 = <&uart9m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; From 70f46aa2007e2a6d27e68d37d498ff893e9bc255 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Fri, 5 Jun 2026 13:54:35 +0200 Subject: [PATCH 554/864] arm64: dts: rockchip: fix regulator names on NanoPC-T6 Three fixed-regulator names on the NanoPC-T6 don't match the board schematic [1]. - vcc3v3_pcie2x1l0 -> vdd_mpcie_3v3 This GPIO-switched 3v3 regulator is labeled vcc3v3_pcie2x1l0, but it is wired to and consumed by &pcie2x1l1. Per the schematic, the GPIO PCIE_M2_1_PWREN controls the power net VDD_MPCIE_3.3V; rename to match. - vdd_2v0_pldo_s3 -> vcc_2v0_pldo_s3 Typo in the regulator-name property of RK806-1 DCDC reg7. The node label and the schematic power-net name both already use the vcc_ form; only the regulator-name string had vdd_. - vcc3v3_pcie30 -> vcc3v3_pcie_m2_0 The GPIO-switched 3v3 feeding the M.2 M-Key (NVMe) slot is named after the PCIe controller it sits behind rather than the schematic power net. The schematic names it VCC3V3_PCIE_M2_0 (produced by an MP2143-based buck off VCC_5V0, enabled by PCIE_M2_0_PWREN); rename to match. No functional change. [1] https://wiki.friendlyelec.com/wiki/images/9/97/NanoPC-T6_2301_SCH.PDF Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260605-rk3588-dts-rockchip-nanopct6-fix-schematic-names-v1-1-15dd3b23ab1a@pardini.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index 7495af5bd973..cfdb5c13f860 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -201,25 +201,25 @@ vbus5v0_usb: regulator-vbus5v0-usb { vin-supply = <&vcc5v0_sys>; }; - vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 { + vdd_mpcie_3v3: regulator-vdd-mpcie-3v3 { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_m2_1_pwren>; - regulator-name = "vcc3v3_pcie2x1l0"; + regulator-name = "vdd_mpcie_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vcc5v0_sys>; }; - vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + vcc3v3_pcie_m2_0: regulator-vcc3v3-pcie-m2-0 { compatible = "regulator-fixed"; enable-active-high; gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_m2_0_pwren>; - regulator-name = "vcc3v3_pcie30"; + regulator-name = "vcc3v3_pcie_m2_0"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; vin-supply = <&vcc5v0_sys>; @@ -648,7 +648,7 @@ &pcie2x1l0 { &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + vpcie3v3-supply = <&vdd_mpcie_3v3>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_1_rst>; status = "okay"; @@ -668,7 +668,7 @@ &pcie30phy { &pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30>; + vpcie3v3-supply = <&vcc3v3_pcie_m2_0>; status = "okay"; }; @@ -985,7 +985,7 @@ vcc_2v0_pldo_s3: dcdc-reg7 { regulator-min-microvolt = <2000000>; regulator-max-microvolt = <2000000>; regulator-ramp-delay = <12500>; - regulator-name = "vdd_2v0_pldo_s3"; + regulator-name = "vcc_2v0_pldo_s3"; regulator-state-mem { regulator-on-in-suspend; From dfe078755706ed50651ebbe0442843ecd4ae8389 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Fri, 26 Jun 2026 16:40:38 +0200 Subject: [PATCH 555/864] arm64: dts: rockchip: fix eMMC reset polarity on PX30 Ringneck MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the Jedec 5.1 specification, the device is held in reset when RST_n is low, therefore the polarity of the line must be that, as specified in the Device Tree binding (mmc/mmc-pwrseq-emmc.yaml). Due to the wrong polarity, eMMC devices with RST_n_FUNCTION[162] bitfield [1:0] set to 0x1 (the default is 0x0) will be held in reset forever. Cc: stable@vger.kernel.org Fixes: c484cf93f61b ("arm64: dts: rockchip: add PX30-µQ7 (Ringneck) SoM with Haikou baseboard") Signed-off-by: Quentin Schulz Link: https://patch.msgid.link/20260626-ringneck-emmc-polarity-v1-1-90cefe57b316@cherry.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi index 973b4c5880e2..29794216592d 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi @@ -26,7 +26,7 @@ emmc_pwrseq: emmc-pwrseq { compatible = "mmc-pwrseq-emmc"; pinctrl-0 = <&emmc_reset>; pinctrl-names = "default"; - reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; }; leds { From ede2ee37f0a445cacbf24760f53befa10f64994a Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 5 Jun 2026 10:23:03 +0800 Subject: [PATCH 556/864] arm64: dts: rockchip: Add missing hclk for RK3588 eDP0 Add the required HCLK_VO1 bus clock to RK3588 eDP0 node with corresponding clock-name "hclk". This clock is necessary for the eDP controller to access video output GRF and work properly. Previously the clock was enabled implicitly via GRF phandle reference. Add it explicitly now to align with updated binding. Fixes: dc79d3d5e7c7 ("arm64: dts: rockchip: Add eDP0 node for RK3588") Signed-off-by: Damon Ding Link: https://patch.msgid.link/20260605022305.3058853-2-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index fc1fdbfd3162..376ad04e0786 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1910,8 +1910,8 @@ hdmi0_out: port@1 { edp0: edp@fdec0000 { compatible = "rockchip,rk3588-edp"; reg = <0x0 0xfdec0000 0x0 0x1000>; - clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>; - clock-names = "dp", "pclk"; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO1>; + clock-names = "dp", "pclk", "hclk"; interrupts = ; phys = <&hdptxphy0>; phy-names = "dp"; From 09820811c549ee2c408defe36b210b13c7a85fcf Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 5 Jun 2026 10:23:04 +0800 Subject: [PATCH 557/864] arm64: dts: rockchip: Add missing hclk for RK3588 eDP1 Add the required HCLK_VO1 bus clock to RK3588 eDP1 node with corresponding clock-name "hclk". This clock is necessary for the eDP controller to access video output GRF and work properly. Previously the clock was enabled implicitly via GRF phandle reference. Add it explicitly now to align with updated binding. Fixes: a481bb0b1ad9 ("arm64: dts: rockchip: Add eDP1 dt node for rk3588") Signed-off-by: Damon Ding Link: https://patch.msgid.link/20260605022305.3058853-3-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index a2640014ee04..b251bb129cdb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -285,8 +285,8 @@ hdmi1_out: port@1 { edp1: edp@fded0000 { compatible = "rockchip,rk3588-edp"; reg = <0x0 0xfded0000 0x0 0x1000>; - clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>; - clock-names = "dp", "pclk"; + clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, <&cru HCLK_VO1>; + clock-names = "dp", "pclk", "hclk"; interrupts = ; phys = <&hdptxphy1>; phy-names = "dp"; From a41687b89005f50909e59130a4c0b08e82996739 Mon Sep 17 00:00:00 2001 From: Damon Ding Date: Fri, 5 Jun 2026 10:23:05 +0800 Subject: [PATCH 558/864] arm64: dts: rockchip: Add eDP node for RK3576 Add full device tree definition for the integrated eDP controller on RK3576, following the existing RK3588 hardware layout. Configure required register range, clocks, interrupt, phy, power domain, reset and grf properties to fully describe the controller. Signed-off-by: Damon Ding Reviewed-by: Nicolas Frattaroli Link: https://patch.msgid.link/20260605022305.3058853-4-damon.ding@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index e12a2a0cfb89..b0c0d3c8b1b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1496,6 +1496,34 @@ hdmi_out: port@1 { }; }; + edp: edp@27dc0000 { + compatible = "rockchip,rk3576-edp"; + reg = <0x0 0x27dc0000 0x0 0x1000>; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, <&cru HCLK_VO0_ROOT>; + clock-names = "dp", "pclk", "hclk"; + interrupts = ; + phys = <&hdptxphy>; + phy-names = "dp"; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; + reset-names = "dp", "apb"; + rockchip,grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + }; + + edp_out: port@1 { + reg = <1>; + }; + }; + }; + dp: dp@27e40000 { compatible = "rockchip,rk3576-dp"; reg = <0x0 0x27e40000 0x0 0x30000>; From 7e2b7e7451ef145569727f4f3b6d2f3485e0f1aa Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 10 Jun 2026 18:00:05 +0800 Subject: [PATCH 559/864] dt-bindings: arm: rockchip: Add HINLINK H28K The HINLINK H28K (also known as LinkStar H28K) is a dual-gigabit SBC based on the RK3528 SoC. Add devicetree binding documentation for it. Link: https://wiki.seeedstudio.com/H28K_Datasheet/ Signed-off-by: Chukun Pan Acked-by: Conor Dooley Link: https://patch.msgid.link/20260610100006.366963-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e7894d2b8f56..e3ec99df43d8 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -724,6 +724,11 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s + - description: HINLINK H28K + items: + - const: hinlink,h28k + - const: rockchip,rk3528 + - description: HINLINK H66K / H68K items: - enum: From 5fd91b4f3ef20ecdc6db7a9e5c831209c7042c08 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Wed, 10 Jun 2026 18:00:06 +0800 Subject: [PATCH 560/864] arm64: dts: rockchip: Add HINLINK H28K The HINLINK H28K (LinkStar H28K) is a SBC with the Rockchip RK3528 SoC. It has the following features: - 1x USB 2.0 - 8/32GB eMMC - 1/2/4GB LPDDR4 - MicroSD card slot - 1x 1GbE RTL8111H Ethernet - 1x 1GbE RTL8211F Ethernet Signed-off-by: Chukun Pan Link: https://patch.msgid.link/20260610100006.366963-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3528-hinlink-h28k.dts | 318 ++++++++++++++++++ 2 files changed, 319 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 6cab03c9c4a4..7623c136ce21 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -92,6 +92,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-h28k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-nanopi-zero2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts new file mode 100644 index 000000000000..0ec50e9156eb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts @@ -0,0 +1,318 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3528.dtsi" + +/ { + model = "HINLINK H28K"; + compatible = "hinlink,h28k", "rockchip,rk3528"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-boot { + label = "BOOT"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led>, <&wan_led>, <&work_led>; + + led-0 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "netdev"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + }; + + vdd_0v9: regulator-0v9-vdd { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr: regulator-1v1-vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sd: regulator-3v3-vcc-sd { + compatible = "regulator-fixed"; + gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren_l>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-gpio"; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_vol_ctrl_h>; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_arm: regulator-vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-settling-time-up-us = <250>; + }; +}; + +&combphy { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim>, + <&rgmii_tx_bus2>, + <&rgmii_rx_bus2>, + <&rgmii_rgmii_clk>, + <&rgmii_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_l>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111hs_isolateb_l>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pinctrl { + gmac { + gmac1_rstn_l: gmac1-rstn-l { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + lan_led: lan-led { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led: wan-led { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + rtl8111hs_isolateb_l: rtl8111hs-isolateb-l { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm1m0_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; From 561ae1a2f3410148f2bde2d2a6f42709c5f46668 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:34:20 +0200 Subject: [PATCH 561/864] arm64: dts: rockchip: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706093419.273625-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/px30-ringneck-haikou-video-demo.dtso | 10 +++++----- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso index 760d5139f95d..d0725595ade0 100644 --- a/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso +++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -45,11 +45,11 @@ cam_avdd_2v8: regulator-cam-avdd-2v8 { cam_dovdd_1v8: regulator-cam-dovdd-1v8 { compatible = "regulator-fixed"; - gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "cam-dovdd-1v8"; - vin-supply = <&vcc1v8_video>; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; }; cam_dvdd_1v2: regulator-cam-dvdd-1v2 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index 7b1086682d11..acf44f8b47ed 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -382,7 +382,7 @@ &i2c4 { }; &i2s2 { - status = "okay"; + status = "okay"; }; &io_domains { From 342d6e14165eebac7279b7ea3a3d34a7224cc6f0 Mon Sep 17 00:00:00 2001 From: Brian Mayer Date: Sun, 5 Jul 2026 15:19:19 -0300 Subject: [PATCH 562/864] arm64: dts: rockchip: add HYM8563 RTC to Radxa CM5 IO board Describe the Haoyu HYM8563 RTC connected to I2C6 on the Radxa CM5 IO carrier including its interrupt line. Assisted-by: Grok:grok-build Signed-off-by: Brian Mayer Link: https://patch.msgid.link/20260705181920.8633-1-bleemayer@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-radxa-cm5-io.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts index af4a9bc015e1..dc4cc44182f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -19,6 +19,7 @@ / { aliases { ethernet0 = &gmac1; mmc1 = &sdmmc; + rtc0 = &hym8563; }; chosen { @@ -198,6 +199,18 @@ usbc0_dp_altmode_mux: endpoint { }; }; }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; }; &i2s5_8ch { @@ -227,6 +240,12 @@ hdmi0_tx_on_h: hdmi0-tx-on-h { }; }; + hym8563 { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + usb { vcc5v0_host_en: vcc5v0-host-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; From 3bbe67c4de2aa8b0c042f92ad8c7462e8699cc37 Mon Sep 17 00:00:00 2001 From: Vsevolod Kozlov Date: Sat, 4 Jul 2026 15:46:52 +0300 Subject: [PATCH 563/864] arm64: dts: rockchip: fan speed control for FriendlyELEC CM3588 NAS The FriendlyELEC CM3588 NAS kit is often supplied with a case and a fan. Enable control of the speed of the fan using the trip points and cooling maps from rk3588-nanopc-t6.dtsi as a reference. Signed-off-by: Vsevolod Kozlov Link: https://patch.msgid.link/akkAvJap-MtbKp8B@Vsevolods-MacBook-Pro.local Signed-off-by: Heiko Stuebner --- .../rk3588-friendlyelec-cm3588-nas.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index 0dce96ca8c28..f4c34da61c4d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "rk3588-friendlyelec-cm3588.dtsi" @@ -457,6 +458,36 @@ &i2c8 { status = "okay"; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_warm: package-warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_hot: package-hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l0 { /* 2. M.2 socket, CON14: pcie30phy port0 lane1, @fe170000 */ max-link-speed = <3>; From 5dd588f49b85e0a727adee125d1a61e7f6012617 Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Fri, 3 Jul 2026 04:24:29 +0800 Subject: [PATCH 564/864] arm64: dts: rockchip: Fix incorrect interrupt for the 9Tripod X3568 v4 The recently changes for 9Tripod X3568 mistakenly configured the WiFi host-wake interrupt trigger type as IRQ_TYPE_LEVEL_LOW. However, the associated pin `wifi_host_wake_irq` is configured with an internal pull-down resistor. When the WiFi module enters a low-power sleep state and leaves the pin floating, this pull-down bias drives the pin low. Since the interrupt is incorrectly set to level-low, this combination traps the kernel in an endless interrupt loop. Correct the interrupt trigger type to IRQ_TYPE_LEVEL_HIGH based on the actual hardware logic: the pin is kept low by default and driven high by the WiFi module to wake up the host. Fixes: 993555b5476c ("arm64: dts: rockchip: Add AP6275S support for 9Tripod X3568 v4") Signed-off-by: Coia Prant Link: https://patch.msgid.link/20260702202429.2341789-1-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts index 66f3cbb22a59..4903e32d0ead 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-9tripod-x3568-v4.dts @@ -798,7 +798,7 @@ wifi@1 { compatible = "brcm,bcm43752-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio3>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_irq>; From b4db45b3ec97a9d0d23446084f45e095b2ba2020 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 2 Jul 2026 23:56:48 -0300 Subject: [PATCH 565/864] arm64: dts: rockchip: Fix rk3588s-roc-pc audio description The rk3588s-roc-pc ES8388 codec is connected to the i2s0_8ch audio interface. Use the matching I2S0 MCLK output for the codec clock instead of I2S1. Using the I2S1 MCLK can leave the ALSA PCM running while the codec has no usable master clock for the active audio path, resulting in silent headphone output. Also make the CPU DAI provide bitclock and frame clock. This matches the active Rockchip I2S controller side and avoids relying on the codec to drive the bus clocks. Route the headphone output to LOUT2 and ROUT2, matching the old 5.10 BSP device tree. LOUT1 and ROUT1 are used for the speaker route there, so using them for the headphone widget can leave the headphone jack silent even while the ALSA path is active. The old BSP also used hp-con-gpio on GPIO1_A4. Model that GPIO as a simple audio amplifier so DAPM enables the headphone connection when the headphone path is active. Cc: stable@vger.kernel.org Fixes: 7f9509791507 ("arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC") Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260703025648.180135-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-roc-pc.dts | 23 +++++++++++++------ 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts index d534d662c40f..99853880aaac 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -23,16 +23,19 @@ analog-sound { compatible = "simple-audio-card"; pinctrl-names = "default"; pinctrl-0 = <&hp_detect>; + simple-audio-card,aux-devs = <&headphones_amp>; simple-audio-card,name = "rockchip,es8388"; - simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,bitclock-master = <&cpudai>; simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,frame-master = <&cpudai>; simple-audio-card,hp-det-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; simple-audio-card,mclk-fs = <256>; simple-audio-card,pin-switches = "Headphones"; simple-audio-card,routing = - "Headphones", "LOUT1", - "Headphones", "ROUT1", + "Headphones", "Headphone Amp OUTL", + "Headphones", "Headphone Amp OUTR", + "Headphone Amp INL", "LOUT2", + "Headphone Amp INR", "ROUT2", "LINPUT1", "Microphone Jack", "RINPUT1", "Microphone Jack", "LINPUT2", "Onboard Microphone", @@ -47,11 +50,17 @@ masterdai: simple-audio-card,codec { system-clock-frequency = <12288000>; }; - simple-audio-card,cpu { + cpudai: simple-audio-card,cpu { sound-dai = <&i2s0_8ch>; }; }; + headphones_amp: audio-amplifier-headphones { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Headphone Amp"; + }; + chosen { stdout-path = "serial2:1500000n8"; }; @@ -327,12 +336,12 @@ &i2c3 { es8388: audio-codec@11 { compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; - clocks = <&cru I2S1_8CH_MCLKOUT>; + clocks = <&cru I2S0_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; DVDD-supply = <&vcc_1v8_s0>; HPVDD-supply = <&vcc_3v3_s0>; PVDD-supply = <&vcc_3v3_s0>; - assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; #sound-dai-cells = <0>; }; From 02b9bc288b520c07612c945d13da651bd871e90c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 8 Jul 2026 21:50:05 -0300 Subject: [PATCH 566/864] arm64: dts: rockchip: Enable USB device mode on rk3588s-roc-pc The USB3 OTG controller on the ROC-PC can be used in device mode, but the board description only enabled the DWC3 controller and USB2 PHY. The USBDP PHY remained disabled and the controller had no role-switch default, so DWC3 did not register a UDC and USB gadget drivers such as g_mass_storage failed to bind. Enable the USBDP PHY and describe the controller as a USB role switch with peripheral as the default role. This lets the controller register as a UDC when no external role provider has selected a host role. Tested on a Firefly Station M3 by binding g_mass_storage to expose the eMMC as a USB mass-storage gadget. Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260709005006.413145-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts index 99853880aaac..7150d5f7684d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-roc-pc.dts @@ -833,6 +833,12 @@ &usb_host0_ohci { &usb_host0_xhci { extcon = <&u2phy0>; + role-switch-default-mode = "peripheral"; + usb-role-switch; + status = "okay"; +}; + +&usbdp_phy0 { status = "okay"; }; From ffc6fa1baf3d7d3798773575df5299e2279d1e9c Mon Sep 17 00:00:00 2001 From: Daniele Briguglio Date: Thu, 9 Jul 2026 08:58:38 +0200 Subject: [PATCH 567/864] arm64: dts: rockchip: fix HDMI-RX signal detect GPIO on yy3588 The YY3588 declares the HDMI-RX signal detect on GPIO1_C6, but the receiver never sees an attached source there and cannot capture any input. That value was copied from the vendor device tree and is wrong. The core-board schematics are not available and the SoM documentation does not clearly show where this signal is routed, so the correct pin was read from the device tree in the board's Android image: GPIO1_D5. With GPIO1_D5 the receiver detects a connected source and locks, and v4l2 reports the input timing (1920x1080p60). Fixes: 19847bde695f ("arm64: dts: rockchip: Add Youyeetoo YY3588") Signed-off-by: Daniele Briguglio Link: https://patch.msgid.link/20260709-yy3588-hdmirx-d5-fix-v1-1-900a6790386c@superkali.me Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts index d631731346f7..b03dc0af3e65 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-youyeetoo-yy3588.dts @@ -341,7 +341,7 @@ &hdmi_receiver_cma { }; &hdmi_receiver { - hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + hpd-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_det>; status = "okay"; @@ -605,7 +605,7 @@ &pcie3x4 { &pinctrl { hdmirx { hdmirx_5v_det: hdmirx-5v-det { - rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From 5f19535351bf28f28d702f452d11a1216ec2bd28 Mon Sep 17 00:00:00 2001 From: Oren Klopfer Date: Fri, 3 Jul 2026 16:10:10 -0400 Subject: [PATCH 568/864] Revert "arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro" This reverts commit 096bd8c679185f898cae9933c6a68650fa26ea4f. Just as with the Pinebook Pro, there are multiple chipset variants for the Pinephone Pro, and multiple firmware binaries for different distributions. The change causes issues with some of these combinations, and reverting it resolves the issues. See the Closes below for the full report. Similarly with the Pinebook Pro adjustment, the original commit only indicates "further description" and not indicative of fixing any existing issues, so reverting should not kick any back up. Fixes: 096bd8c67918 ("arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro") Cc: Heiko Stuebner Cc: Peter Robinson Cc: Thorsten Leemhuis Cc: stable@vger.kernel.org Closes: https://lore.kernel.org/r/20260607225901.64019-1-oklopfer37@gmail.com/ Signed-off-by: Oren Klopfer Link: https://patch.msgid.link/20260703201010.67311-1-oklopfer37@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-pinephone-pro.dts | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 8d26bd9b7500..d46cdfe3f784 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -734,12 +734,6 @@ light_int_l: light-int-l { }; }; - wifi { - wifi_host_wake_l: wifi-host-wake-l { - rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - wireless-bluetooth { bt_wake_pin: bt-wake-pin { rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; @@ -766,19 +760,7 @@ &sdio0 { pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; - #address-cells = <1>; - #size-cells = <0>; status = "okay"; - - brcmf: wifi@1 { - compatible = "brcm,bcm4329-fmac"; - reg = <1>; - interrupt-parent = <&gpio4>; - interrupts = ; - interrupt-names = "host-wake"; - pinctrl-names = "default"; - pinctrl-0 = <&wifi_host_wake_l>; - }; }; &pwm0 { From 0b284643f1a002248124176dc3914202a873683d Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Fri, 3 Jul 2026 04:46:27 +0800 Subject: [PATCH 569/864] dt-bindings: vendor-prefixes: Add graperain Add graperain to the vendor prefixes. Link: https://www.graperain.cn/ (China) Link: https://www.graperain.com/ (Global) Signed-off-by: Coia Prant Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260702204628.2407308-3-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 804bcce2cdb3..51b4a6317674 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -682,6 +682,8 @@ patternProperties: description: Goramo Gorecki "^gplus,.*": description: GPLUS + "^graperain,.*": + description: Shenzhen Graperain Technology Co., Ltd. "^grinn,.*": description: Grinn "^grmn,.*": From 5ea0f18618112f77073bfe9af3bea7fb02ef203f Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Fri, 3 Jul 2026 04:46:28 +0800 Subject: [PATCH 570/864] dt-bindings: arm: rockchip: Add Graperain G3568 series Document the Graperain G3568 v2, which is a development board based on the Rockchip RK3568 SoC. Graperain G3568 series also have an SBC series with the suffix "box". Graperain G3568 v2 belongs to development board series, not SBC series. Link: https://www.graperain.cn/RK3568/RK3568-Development/ (China) Link: https://www.graperain.com/ARM-Embedded-RK3568-Development-Board/ (Global) Link: https://image.chukouplus.com/upload/C_153/product_file/20211022/6daddec9e400458816dd4c57ba807fc3.pdf Signed-off-by: Coia Prant Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260702204628.2407308-4-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e3ec99df43d8..5d3614df98e0 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -684,6 +684,12 @@ properties: - const: google,veyron - const: rockchip,rk3288 + - description: Graperain G3568 series board + items: + - enum: + - graperain,g3568-v2 + - const: rockchip,rk3568 + - description: H96 Max V58 TV Box items: - const: haochuangyi,h96-max-v58 From f296bb503a24c081888435bdf50741ced1906210 Mon Sep 17 00:00:00 2001 From: Coia Prant Date: Fri, 3 Jul 2026 04:46:29 +0800 Subject: [PATCH 571/864] arm64: dts: rockchip: Add devicetree for the Graperain G3568 v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Graperain G3568 v2 is an RK3568-based development board, just like the RK3568-EVB. It always uses soldered connections between the GR3568CV2 core board and the RK3568BV2/GR3568BV2 I/O board. The G3568 board has multiple hardware revisions, and we currently support v2 (I/O board). Specification: - SoC: RockChip RK3568 ARM64 (4 cores) - eMMC: 16-128 GB - RAM: 2-16 GB - Power: DC 12V 2A - Ethernet: 2x RTL8211F RGMII (10/100/1000 Mbps) - Wireless radio: 802.11b/g/n/ac dual-band - LED: Power: AlwaysOn User: GPIO - Button: ESC: SARADC/0 <1100k µV> MENU: SARADC/0 <1400k µV> VOL-: SARADC/0 <430k µV> VOL+: SARADC/0 <50k µV> Power/Reset: PMIC RK809 - CAN CAN/1: 4-pin (PH 2.0) - PWM PWM/4: Backlight PWM/5: Backlight PWM/7: IR Receiver - UART: UART/2: Debug TTL - 1500000 8N1 (1.25mm) UART/3: TTL (PH 2.0) UART/4: TTL (PH 2.0) UART/8: AP6356S Bluetooth UART/9: TTL (PH 2.0) - I2C: I2C/0: PMIC RK809 I2C/1: Touchscreen I2C/4: Camera I2C/5: RTC@51 PCF8563 - I2S: I2S/0: HDMI Sound I2S/1: RK809 Audio Codec I2S/3: AP6356S Bluetooth Sound - SDMMC: SDMMC/0: microSD (TF) slot SDMMC/2: AP6356S SDIO WiFi card - Camera: 1x CSI - Video: HDMI / DSI0 (MIPI/LVDS) / DSI1 (MIPI/EDP) - Audio: HDMI / MIC / Speaker / SPDIF / 3.5mm Headphones / AP6356S Bluetooth - USB: USB 2.0 HOST x2 USB 2.0 OTG x1 (shared with USB 3.0 OTG/HOST) USB 3.0 HOST x1 USB 3.0 OTG/HOST x1 - SATA: 1x SATA 3.0 with Power/4-pin - PCIe: 1x PCIe 3.0 x2 (x4 connector) Link: - https://image.chukouplus.com/upload/C_153/product_file/20211022/6daddec9e400458816dd4c57ba807fc3.pdf - https://blog.gov.cooking/archives/research-graperain-g3568-v2-and-flash.html Signed-off-by: Coia Prant Reviewed-by: Andrew Lunn #gmac and mdio nodes Link: https://patch.msgid.link/20260702204628.2407308-5-coiaprant@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3568-graperain-g3568-v2.dts | 940 ++++++++++++++++++ 2 files changed, 941 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 7623c136ce21..20f2d282bb45 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-graperain-g3568-v2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts b/arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts new file mode 100644 index 000000000000..4c55c7d21159 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-graperain-g3568-v2.dts @@ -0,0 +1,940 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Graperain G3568 v2"; + compatible = "graperain,g3568-v2", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; + rtc0 = &rtc0; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-esc { + label = "esc"; + linux,code = ; + press-threshold-microvolt = <1250000>; + }; + + button-menu { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <1600000>; + }; + + button-vol-down { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <600000>; + }; + + button-vol-up { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_work: led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + pdm_codec: pdm-codec { + compatible = "dmic-codec"; + num-channels = <2>; + #sound-dai-cells = <0>; + }; + + pdm_sound: pdm-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "microphone"; + + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + + simple-audio-card,codec { + sound-dai = <&pdm_codec>; + }; + }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <300>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + pcie30_avdd0v9: regulator-pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en_pin>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + +/* used for usb_host0_xhci */ +&combphy0 { + status = "okay"; +}; + +/* used for usb_host1_xhci */ +&combphy1 { + status = "okay"; +}; + +/* connected to sata2 */ +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + rockchip,mic-in-differential; + }; + }; +}; + +&i2c5 { + status = "okay"; + + rtc0: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +/* required rk3568-codec-digital for AP6356S Bluetooth Sound */ +&i2s3_2ch { + status = "disabled"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pin>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pdm { + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_work_en: led_work_en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable: wifi-enable { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi-irq { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +/* Required remotectl for IR receiver */ +&pwm7 { + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +/* used for eMMC */ +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +/* used for microSD (TF) Slot */ +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +/* used for AP6356S WiFi */ +&sdmmc2 { + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4356-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + }; +}; + +&spdif { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* used for Debug */ +&uart2 { + status = "okay"; +}; + +&uart3 { + pinctrl-0 = <&uart3m1_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4m1_xfer>; + status = "okay"; +}; + +/* used for AP6356S Bluetooth */ +&uart8 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; + shutdown-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart9 { + pinctrl-0 = <&uart9m1_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 03b1c32f54bae3a4e73f82e1ccb322cfead24a2c Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Sun, 10 May 2026 21:53:47 -0500 Subject: [PATCH 572/864] dt-bindings: arm: rockchip: Add Orange Pi 5 Pro Add compatible string for the Orange Pi 5 Pro. Acked-by: Krzysztof Kozlowski Signed-off-by: Dennis Gilmore Link: https://patch.msgid.link/20260511025352.106126-2-dennis@ausil.us Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 5d3614df98e0..e023c296d3d3 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1349,6 +1349,7 @@ properties: items: - enum: - xunlong,orangepi-5 + - xunlong,orangepi-5-pro - xunlong,orangepi-5b - const: rockchip,rk3588s From e3132dc1f4ebc9dd28ef9108f2aac84e5d4c5a15 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Sun, 10 May 2026 21:53:48 -0500 Subject: [PATCH 573/864] arm64: dts: rockchip: rename PLDO regulator labels to match schematic on rk3588s-orangepi-5 The Orange Pi 5, 5B and 5 Pro schematics label the RK806 PLDO outputs using the pattern VCC_*_S0 / VCCA_*_S0 / VDDA_*_S0. Rename the base dtsi regulator labels (and the es8388 supply references) to match: pldo-reg1: avcc_1v8_s0 -> vcc_1v8_s0 pldo-reg2: vcc_1v8_s0 -> vcca_1v8_s0 pldo-reg3: avdd_1v2_s0 -> vdda_1v2_s0 pldo-reg4: vcc_3v3_s0 -> vcca_3v3_s0 Also update the saradc vref-supply reference to track the pldo-reg1 rename. No functional change. Signed-off-by: Dennis Gilmore Link: https://patch.msgid.link/20260511025352.106126-3-dennis@ausil.us Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 9da13f96f13a..269cd89276f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -278,10 +278,10 @@ es8388: audio-codec@10 { compatible = "everest,es8388", "everest,es8328"; reg = <0x10>; clocks = <&cru I2S1_8CH_MCLKOUT>; - AVDD-supply = <&vcc_3v3_s0>; - DVDD-supply = <&vcc_1v8_s0>; - HPVDD-supply = <&vcc_3v3_s0>; - PVDD-supply = <&vcc_3v3_s0>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcca_1v8_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcca_3v3_s0>; assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; #sound-dai-cells = <0>; @@ -451,7 +451,7 @@ &rknn_mmu_2 { }; &saradc { - vref-supply = <&avcc_1v8_s0>; + vref-supply = <&vcc_1v8_s0>; status = "okay"; }; @@ -676,8 +676,8 @@ regulator-state-mem { }; }; - avcc_1v8_s0: pldo-reg1 { - regulator-name = "avcc_1v8_s0"; + vcc_1v8_s0: pldo-reg1 { + regulator-name = "vcc_1v8_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -688,8 +688,8 @@ regulator-state-mem { }; }; - vcc_1v8_s0: pldo-reg2 { - regulator-name = "vcc_1v8_s0"; + vcca_1v8_s0: pldo-reg2 { + regulator-name = "vcca_1v8_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1800000>; @@ -701,8 +701,8 @@ regulator-state-mem { }; }; - avdd_1v2_s0: pldo-reg3 { - regulator-name = "avdd_1v2_s0"; + vdda_1v2_s0: pldo-reg3 { + regulator-name = "vdda_1v2_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <1200000>; @@ -713,8 +713,8 @@ regulator-state-mem { }; }; - vcc_3v3_s0: pldo-reg4 { - regulator-name = "vcc_3v3_s0"; + vcca_3v3_s0: pldo-reg4 { + regulator-name = "vcca_3v3_s0"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; From b7a806c1c35eef2ddd8145e818427f285feb2413 Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Sun, 10 May 2026 21:53:49 -0500 Subject: [PATCH 574/864] arm64: dts: rockchip: refactor items from Orange Pi 5/b to prep for Pro The Orange Pi 5 Pro uses the same SoC and base as the Orange Pi 5 and Orange Pi 5B but has had sound, USB, and leds wired up differently. The 5 and 5B boards use gmac for ethernet where the Pro has a PCIe attached NIC. Move the 5/5B-specific bits (analog-sound/es8388, FUSB302 Type-C, gmac1, pwm-leds, i2s1_8ch routing, USB role-switch plumbing) out of rk3588s-orangepi-5.dtsi into a new rk3588s-orangepi-5-5b.dtsi that is included by both 5 and 5B. The RK806 PLDO1 and PLDO2 outputs are wired differently between the 5/5B and the Pro (PLDO1/PLDO2 are swapped), so label the PMIC node rk806 in the base dtsi, drop pldo-reg1/pldo-reg2 from it, and define them via a &rk806 regulators augmentation in rk3588s-orangepi-5-5b.dtsi. The Pro will supply its own mapping. Signed-off-by: Dennis Gilmore Reviewed-by: Alexey Charkov Link: https://patch.msgid.link/20260511025352.106126-4-dennis@ausil.us Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-orangepi-5-5b.dtsi | 256 ++++++++++++++++++ .../boot/dts/rockchip/rk3588s-orangepi-5.dts | 6 +- .../boot/dts/rockchip/rk3588s-orangepi-5.dtsi | 253 +---------------- .../boot/dts/rockchip/rk3588s-orangepi-5b.dts | 2 +- 4 files changed, 272 insertions(+), 245 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-5b.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-5b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-5b.dtsi new file mode 100644 index 000000000000..6e081bc06cfe --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-5b.dtsi @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree definitions shared by the Orange Pi 5 and Orange Pi 5B + * but not the Orange Pi 5 Pro. + */ + +#include +#include "rk3588s-orangepi-5.dtsi" + +/ { + aliases { + ethernet0 = &gmac1; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "rockchip,es8388"; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm0 0 25000 0>; + }; + }; + + vbus_typec: regulator-vbus-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x42>; + status = "okay"; +}; + +&i2c6 { + es8388: audio-codec@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcca_1v8_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcca_3v3_s0>; + assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + }; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "source"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&i2s1_8ch { + rockchip,i2s-tx-route = <3 2 1 0>; + rockchip,i2s-rx-route = <1 3 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_mclk + &i2s1m0_lrck + &i2s1m0_sdi1 + &i2s1m0_sdo3>; + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rk806 { + regulators { + vcc_1v8_s0: pldo-reg1 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg2 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + + port { + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts index 83b9b6645a1e..d76bdf1b5e90 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -2,12 +2,16 @@ /dts-v1/; -#include "rk3588s-orangepi-5.dtsi" +#include "rk3588s-orangepi-5-5b.dtsi" / { model = "Xunlong Orange Pi 5"; compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; + aliases { + mmc0 = &sdmmc; + }; + vcc3v3_pcie20: regulator-vcc3v3-pcie20 { compatible = "regulator-fixed"; enable-active-high; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi index 269cd89276f2..fd0efa8d1bfb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dtsi @@ -3,19 +3,13 @@ /dts-v1/; #include -#include #include +#include #include #include -#include #include "rk3588s.dtsi" / { - aliases { - ethernet0 = &gmac1; - mmc0 = &sdmmc; - }; - chosen { stdout-path = "serial2:1500000n8"; }; @@ -34,38 +28,6 @@ button-recovery { }; }; - analog-sound { - compatible = "simple-audio-card"; - pinctrl-names = "default"; - pinctrl-0 = <&hp_detect>; - simple-audio-card,name = "rockchip,es8388"; - simple-audio-card,bitclock-master = <&masterdai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&masterdai>; - simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,routing = - "Headphones", "LOUT1", - "Headphones", "ROUT1", - "LINPUT1", "Microphone Jack", - "RINPUT1", "Microphone Jack", - "LINPUT2", "Onboard Microphone", - "RINPUT2", "Onboard Microphone"; - simple-audio-card,widgets = - "Microphone", "Microphone Jack", - "Microphone", "Onboard Microphone", - "Headphone", "Headphones"; - - simple-audio-card,cpu { - sound-dai = <&i2s1_8ch>; - }; - - masterdai: simple-audio-card,codec { - sound-dai = <&es8388>; - system-clock-frequency = <12288000>; - }; - }; - hdmi0-con { compatible = "hdmi-connector"; type = "a"; @@ -77,28 +39,14 @@ hdmi0_con_in: endpoint { }; }; - pwm-leds { - compatible = "pwm-leds"; - - led { - color = ; - function = LED_FUNCTION_STATUS; - linux,default-trigger = "heartbeat"; - max-brightness = <255>; - pwms = <&pwm0 0 25000 0>; - }; - }; - - vbus_typec: regulator-vbus-typec { + vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&typec5v_pwren>; - regulator-name = "vbus_typec"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; }; vcc5v0_sys: regulator-vcc5v0-sys { @@ -109,16 +57,6 @@ vcc5v0_sys: regulator-vcc5v0-sys { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; - - vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 { - compatible = "regulator-fixed"; - gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; - regulator-name = "vcc_3v3_sd_s0"; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_3v3_s3>; - }; }; &combphy0_ps { @@ -161,20 +99,6 @@ &cpu_l3 { cpu-supply = <&vdd_cpu_lit_s0>; }; -&gmac1 { - clock_in_out = "output"; - phy-handle = <&rgmii_phy1>; - phy-mode = "rgmii-rxid"; - pinctrl-0 = <&gmac1_miim - &gmac1_tx_bus2 - &gmac1_rx_bus2 - &gmac1_rgmii_clk - &gmac1_rgmii_bus>; - pinctrl-names = "default"; - tx_delay = <0x42>; - status = "okay"; -}; - &gpu { mali-supply = <&vdd_gpu_s0>; status = "okay"; @@ -274,69 +198,6 @@ &i2c6 { pinctrl-0 = <&i2c6m3_xfer>; status = "okay"; - es8388: audio-codec@10 { - compatible = "everest,es8388", "everest,es8328"; - reg = <0x10>; - clocks = <&cru I2S1_8CH_MCLKOUT>; - AVDD-supply = <&vcca_3v3_s0>; - DVDD-supply = <&vcca_1v8_s0>; - HPVDD-supply = <&vcca_3v3_s0>; - PVDD-supply = <&vcca_3v3_s0>; - assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; - assigned-clock-rates = <12288000>; - #sound-dai-cells = <0>; - }; - - usbc0: usb-typec@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - interrupt-parent = <&gpio0>; - interrupts = ; - pinctrl-names = "default"; - pinctrl-0 = <&usbc0_int>; - vbus-supply = <&vbus_typec>; - status = "okay"; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - sink-pdos = - ; - source-pdos = - ; - try-power-role = "source"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - usbc0_hs: endpoint { - remote-endpoint = <&usb_host0_xhci_drd_sw>; - }; - }; - - port@1 { - reg = <1>; - usbc0_ss: endpoint { - remote-endpoint = <&usbdp_phy0_typec_ss>; - }; - }; - - port@2 { - reg = <2>; - usbc0_sbu: endpoint { - remote-endpoint = <&usbdp_phy0_typec_sbu>; - }; - }; - }; - }; - }; - hym8563: rtc@51 { compatible = "haoyu,hym8563"; reg = <0x51>; @@ -350,32 +211,10 @@ hym8563: rtc@51 { }; }; -&i2s1_8ch { - rockchip,i2s-tx-route = <3 2 1 0>; - rockchip,i2s-rx-route = <1 3 2 0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclk - &i2s1m0_mclk - &i2s1m0_lrck - &i2s1m0_sdi1 - &i2s1m0_sdo3>; - status = "okay"; -}; - &i2s5_8ch { status = "okay"; }; -&mdio1 { - rgmii_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0x1>; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - }; -}; - &pd_gpu { domain-supply = <&vdd_gpu_s0>; }; @@ -402,22 +241,6 @@ hp_detect: hp-detect { rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - usb-typec { - usbc0_int: usbc0-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - - typec5v_pwren: typec5v-pwren { - rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm0 { - pinctrl-0 = <&pwm0m2_pins>; - pinctrl-names = "default"; - status = "okay"; }; &rknn_core_0 { @@ -501,7 +324,7 @@ &spi2 { pinctrl-names = "default"; pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; - pmic@0 { + rk806: pmic@0 { compatible = "rockchip,rk806"; reg = <0x0>; interrupt-parent = <&gpio0>; @@ -676,31 +499,6 @@ regulator-state-mem { }; }; - vcc_1v8_s0: pldo-reg1 { - regulator-name = "vcc_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca_1v8_s0: pldo-reg2 { - regulator-name = "vcca_1v8_s0"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - vdda_1v2_s0: pldo-reg3 { regulator-name = "vdda_1v2_s0"; regulator-always-on; @@ -852,26 +650,7 @@ &uart2 { }; &usbdp_phy0 { - mode-switch; - orientation-switch; - sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; - sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; status = "okay"; - - port { - #address-cells = <1>; - #size-cells = <0>; - - usbdp_phy0_typec_ss: endpoint@0 { - reg = <0>; - remote-endpoint = <&usbc0_ss>; - }; - - usbdp_phy0_typec_sbu: endpoint@1 { - reg = <1>; - remote-endpoint = <&usbc0_sbu>; - }; - }; }; &usb_host0_ehci { @@ -883,15 +662,7 @@ &usb_host0_ohci { }; &usb_host0_xhci { - dr_mode = "otg"; - usb-role-switch; status = "okay"; - - port { - usb_host0_xhci_drd_sw: endpoint { - remote-endpoint = <&usbc0_hs>; - }; - }; }; &usb_host1_ehci { @@ -902,7 +673,7 @@ &usb_host1_ohci { status = "okay"; }; -&usb_host2_xhci { +&vop { status = "okay"; }; @@ -910,10 +681,6 @@ &vop_mmu { status = "okay"; }; -&vop { - status = "okay"; -}; - &vp0 { vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { reg = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts index d21ec320d295..8af174777809 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include "rk3588s-orangepi-5.dtsi" +#include "rk3588s-orangepi-5-5b.dtsi" / { model = "Xunlong Orange Pi 5B"; From f47af8ebbe5381e761a8019f29f3016ea9faee5b Mon Sep 17 00:00:00 2001 From: Dennis Gilmore Date: Sun, 10 May 2026 21:53:50 -0500 Subject: [PATCH 575/864] arm64: dts: rockchip: Add Orange Pi 5 Pro board support Add device tree for the Xunlong Orange Pi 5 Pro (RK3588S). - eMMC module, you can optionally solder a SPI NOR in place and turn off the eMMC - PCIe-attached NIC (pcie2x1l2) - PCIe NVMe slot (pcie2x1l1) - AP6256 WiFi (BCM43456) via SDIO with mmc-pwrseq - BCM4345C5 Bluetooth - es8388 audio - USB 2.0 and USB 3.0 - HDMI output is enabled - the second HDMI port connected to the DP bridge is left out for a followup set Vendors schematics are available at: https://drive.google.com/file/d/1qs1DratHuh7C6J6MEtQIwUsiSrg8qgTi/view Signed-off-by: Dennis Gilmore Reviewed-by: Alexey Charkov Link: https://patch.msgid.link/20260511025352.106126-5-dennis@ausil.us Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588s-orangepi-5-pro.dts | 358 ++++++++++++++++++ 2 files changed, 359 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 20f2d282bb45..326ed13fc91f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-cm5-base.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts new file mode 100644 index 000000000000..c9679bac1db7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588s-orangepi-5.dtsi" + +/ { + model = "Xunlong Orange Pi 5 Pro"; + compatible = "xunlong,orangepi-5-pro", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8388"; + simple-audio-card,routing = + "Headphones", "LOUT1", + "Headphones", "ROUT1", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones"; + + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm15 0 1000000 0>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_ACTIVITY; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm3 0 1000000 0>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <0 50 100 150 200 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm2 0 20000000 0>; + }; + + vcc3v3_eth: regulator-vcc3v3-eth { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_eth"; + startup-delay-us = <50000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_otg: regulator-vcc5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_otg"; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_LOW>; + }; + + typea_con: usb-a-connector { + compatible = "usb-a-connector"; + data-role = "host"; + label = "USB3 Type-A"; + power-role = "source"; + vbus-supply = <&vcc5v0_otg>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m4_xfer>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x11>; + #sound-dai-cells = <0>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcca_1v8_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcca_1v8_s0>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S2_2CH_MCLKOUT>; + clocks = <&cru I2S2_2CH_MCLKOUT>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_mclk>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk + &i2s2m1_sdi &i2s2m1_sdo>; + status = "okay"; +}; + +&package_thermal { + polling-delay = <1000>; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; + + trips { + package_fan0: package-fan0 { + hysteresis = <2000>; + temperature = <55000>; + type = "active"; + }; + + package_fan1: package-fan1 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + }; +}; + +/* NVMe */ +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m1_1_perstn>, <&pcie30x1m1_1_clkreqn>, + <&pcie30x1m1_1_waken>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + supports-clkreq; + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +/* NIC */ +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1m0_perstn>, <&pcie20x1m0_clkreqn>, + <&pcie20x1m0_waken>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_eth>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_wake_gpio: bt-wake-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + ethernet { + ethernet_en: ethernet-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wlan { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm15 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m2_pins>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2m1_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m2_pins>; + status = "okay"; +}; + +&rk806 { + regulators { + vcca_1v8_s0: pldo-reg1 { + regulator-name = "vcca_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&sdio { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + status = "okay"; + + ap6256: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-names = "host-wake"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + }; +}; + +&uart9 { + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn &uart9m2_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wakeup"; + interrupt-parent = <&gpio0>; + interrupts = ; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_wake_host_irq &bt_wake_gpio>; + shutdown-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_s3>; + vddio-supply = <&vcc_1v8_s3>; + }; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_otg>; +}; + +&usb_host0_xhci { + dr_mode = "host"; +}; + +&usbdp_phy0 { + /* + * The USB3 Type-A host connector is wired to PHY lanes 2/3. Lanes 0/1 + * are connected to the LT8711UXD DP-to-HDMI bridge on the board. + * dp-lane-mux routes USB3 SuperSpeed to the correct lanes. + */ + rockchip,dp-lane-mux = <0 1>; +}; From 0c9d80d2471aa4be144a66b32d87a85ff57b3390 Mon Sep 17 00:00:00 2001 From: Liu Changjie Date: Tue, 14 Jul 2026 14:54:59 +0800 Subject: [PATCH 576/864] dt-bindings: arm: rockchip: Add LCKFB Taishan Pi 3M Add the compatible string for LCKFB Taishan Pi 3M, a board based on the Rockchip RK3576 SoC. Acked-by: Rob Herring (Arm) Signed-off-by: Liu Changjie Link: https://patch.msgid.link/MN0PR19MB6091201B6DAEE197762F6468ACF92@MN0PR19MB6091.namprd19.prod.outlook.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e023c296d3d3..e6d1a3136463 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -790,6 +790,11 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 + - description: LCKFB Taishan Pi 3M RK3576 + items: + - const: lckfb,tspi-3m-rk3576 + - const: rockchip,rk3576 + - description: LinkEase EasePi R1 items: - const: linkease,easepi-r1 From c748c71d3b2c75e275f24b9fb163ae4994a7cccd Mon Sep 17 00:00:00 2001 From: Liu Changjie Date: Tue, 14 Jul 2026 14:54:59 +0800 Subject: [PATCH 577/864] arm64: dts: rockchip: Add LCKFB Taishan Pi 3M Add the device tree for LCKFB Taishan Pi 3M, a board based on the Rockchip RK3576 SoC. The board schematics are available at: https://oshwhub.com/li-chuang-kai-fa-ban/project_gzzvrwqn Describe the RK806 supplies, eMMC, recovery key, RTC, SD card, Gigabit Ethernet, USB Type-A hosts, source-only USB Type-C host, mSATA, HDMI video and audio, AP6256 Wi-Fi and Bluetooth, status LED, thermal sensors, and debug UART. The MAE0621A PHY CLKOUT supplies the GMAC reference-clock input, so request its validated 125 MHz setting. The following interfaces were tested on the hardware: eMMC, RTC register access, recovery key, SD card, 1GbE, USB 2.0 Type-A storage, USB 3.0 Type-A 5 Gbit/s enumeration and 64 MiB storage I/O, USB-C source/host enumeration in both orientations, mSATA, HDMI video and audio, AP6256 2.4/5 GHz Wi-Fi scan, WPA2 association, ping and bidirectional throughput, Bluetooth firmware load and HCI bring-up, and UART0. Bluetooth active discovery was additionally exercised during bring-up. Signed-off-by: Liu Changjie Link: https://patch.msgid.link/MN0PR19MB6091D3101FD2D8F940F0CE4DACF92@MN0PR19MB6091.namprd19.prod.outlook.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3576-lckfb-tspi-3m.dts | 997 ++++++++++++++++++ 2 files changed, 998 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 326ed13fc91f..3fc54b1a09b6 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -173,6 +173,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb2-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-khadas-edge-2l.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-lckfb-tspi-3m.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts b/arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts new file mode 100644 index 000000000000..b6b56999017b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-lckfb-tspi-3m.dts @@ -0,0 +1,997 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 LCKFB + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model = "LCKFB TaishanPi 3M"; + compatible = "lckfb,tspi-3m-rk3576", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_5v0_usb2_host: regulator-vcc-5v0-usb2-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_host_pwren>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc_5v0_usb2_host"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_usb3_host: regulator-vcc-5v0-usb3-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_host_pwren>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc_5v0_usb3_host"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_typec: regulator-vcc-5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec_vbus_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc_5v0_typec"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_minipcie: regulator-vcc-3v3-minipcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&minipcie_pwren>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_minipcie"; + startup-delay-us = <5000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_wl: regulator-3v3-wl { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwren_l>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_wl"; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clock-names = "ext_clock"; + clocks = <&hym8563>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + usb_a_3_0: usb-a-connector-0 { + compatible = "usb-a-connector"; + label = "USB 3.0 Type-A"; + vbus-supply = <&vcc_5v0_usb3_host>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_a_3_0_hs: endpoint { + remote-endpoint = <&usb_hub_port1>; + }; + }; + + port@1 { + reg = <1>; + + usb_a_3_0_ss: endpoint { + remote-endpoint = <&usb_drd1_ss>; + }; + }; + }; + }; + + usb_a_2_0_1: usb-a-connector-1 { + compatible = "usb-a-connector"; + label = "USB 2.0 Type-A 1"; + vbus-supply = <&vcc_5v0_usb3_host>; + + port { + usb_a_2_0_1_hs: endpoint { + remote-endpoint = <&usb_hub_port2>; + }; + }; + }; + + usb_a_2_0_2: usb-a-connector-2 { + compatible = "usb-a-connector"; + label = "USB 2.0 Type-A 2"; + vbus-supply = <&vcc_5v0_usb2_host>; + + port { + usb_a_2_0_2_hs: endpoint { + remote-endpoint = <&usb_hub_port3>; + }; + }; + }; + + usb_a_2_0_3: usb-a-connector-3 { + compatible = "usb-a-connector"; + label = "USB 2.0 Type-A 3"; + vbus-supply = <&vcc_5v0_usb2_host>; + + port { + usb_a_2_0_3_hs: endpoint { + remote-endpoint = <&usb_hub_port4>; + }; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "input"; + phy-handle = <&rgmii_phy0>; + /* RX delay is added by the PHY, TX delay by the GMAC. */ + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ð0m0_mclk>; + tx_delay = <0x24>; + status = "okay"; +}; + +&hdmi { + /* The external level shifters must be on for TMDS operation. */ + frl-enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + simple-audio-card,mclk-fs = <128>; + status = "okay"; + + simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb302_int>; + vbus-supply = <&vcc_5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + power-role = "source"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_c_hs: endpoint { + remote-endpoint = <&usb_drd0_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb_c_ss: endpoint { + remote-endpoint = <&usbdp_phy_ep>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id7b74.4412"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_phy_reset>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + gmac0_phy_reset: gmac0-phy-reset { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + minipcie { + minipcie_pwren: minipcie-pwren { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + bt_host_wake_h: bt-host-wake-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_h: bt-wake-h { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_h: wifi-host-wake-h { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_pwren_l: wifi-pwren-l { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-host { + usb2_host_pwren: usb2-host-pwren { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb3_host_pwren: usb3-host-pwren { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + fusb302_int: fusb302-int { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec_vbus_en: typec-vbus-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai6 { + rockchip,sai-tx-route = <0>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_pldo2_s0>; + status = "okay"; +}; + +&sata0 { + target-supply = <&vcc_3v3_minipcie>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_wl>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_h>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <50000000>; + no-mmc; + no-sdio; + pinctrl-names = "default"; + /* GPIO0_B6/SDMMC0_PWREN is not connected on this board. */ + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det_l &sdmmc0_bus4>; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&hym8563>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wakeup"; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_h>; + shutdown-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_wl>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usbdp_phy { + mode-switch; + orientation-switch; + status = "okay"; + + port { + usbdp_phy_ep: endpoint { + remote-endpoint = <&usb_c_ss>; + }; + }; +}; + +&usb_drd0_dwc3 { + usb-role-switch; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_drd0_hs: endpoint { + remote-endpoint = <&usb_c_hs>; + }; + }; + }; +}; + +&usb_drd1_dwc3 { + #address-cells = <1>; + #size-cells = <0>; + + dr_mode = "host"; + status = "okay"; + + usb_hub: hub@1 { + compatible = "usb1a40,0201"; + reg = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_hub_port1: endpoint { + remote-endpoint = <&usb_a_3_0_hs>; + }; + }; + + port@2 { + reg = <2>; + + usb_hub_port2: endpoint { + remote-endpoint = <&usb_a_2_0_1_hs>; + }; + }; + + port@3 { + reg = <3>; + + usb_hub_port3: endpoint { + remote-endpoint = <&usb_a_2_0_2_hs>; + }; + }; + + port@4 { + reg = <4>; + + usb_hub_port4: endpoint { + remote-endpoint = <&usb_a_2_0_3_hs>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + usb_drd1_ss: endpoint { + remote-endpoint = <&usb_a_3_0_ss>; + }; + }; + }; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 58db5a28c85150411f3b6035b9a7eb3b23ca7789 Mon Sep 17 00:00:00 2001 From: Hrushiraj Gandhi Date: Mon, 8 Jun 2026 11:39:39 +0530 Subject: [PATCH 578/864] dt-bindings: arm: rockchip: add Vicharak Axon board Add the device tree binding for the Vicharak Axon single-board computer based on the Rockchip RK3588 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Hrushiraj Gandhi Link: https://patch.msgid.link/20260608060940.52549-2-hrushirajg23@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index e6d1a3136463..5f2d45fc5a2a 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1322,6 +1322,11 @@ properties: - const: turing,rk1 - const: rockchip,rk3588 + - description: Vicharak Axon + items: + - const: vicharak,axon + - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 From c42f01f053a7be77f534c850911cd8d54777af19 Mon Sep 17 00:00:00 2001 From: Hrushiraj Gandhi Date: Mon, 8 Jun 2026 11:39:40 +0530 Subject: [PATCH 579/864] arm64: dts: rockchip: add Vicharak Axon board Add initial support for the Vicharak Axon single-board computer based on the Rockchip RK3588 SoC. The board supports: - eMMC storage - microSD card - Gigabit Ethernet - HDMI output (dual HDMI) - HDMI input - USB 2.0 host ports - PCIe 2.0 slots - PCIe 3.0 x4 slot - SATA - RTC - Status LEDs The board uses an RK806 PMIC and provides the regulators required by the RK3588 SoC. Signed-off-by: Hrushiraj Gandhi Link: https://patch.msgid.link/20260714053419.265523-3-hrushirajg23@gmail.com [some sorting, dropped deprecated regulator-suspend-microvolt properties] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-vicharak-axon.dts | 842 ++++++++++++++++++ 2 files changed, 843 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3fc54b1a09b6..d922aa93d292 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -216,6 +216,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vicharak-axon.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-youyeetoo-yy3588.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts new file mode 100644 index 000000000000..9a540bd84850 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-axon.dts @@ -0,0 +1,842 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Vicharak Axon"; + compatible = "vicharak,axon", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + power_led: led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pca9554 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + status_led: led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pca9554 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_io_expander: regulator-vcc3v3-io-expander { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_io_expander"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc3v3_pcie20_sata30: regulator-vcc3v3-pcie20-sata30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie20_sata30"; + regulator-boot-on; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc3v3_pcie30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host: regulator-vcc5v0-usb20-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + phy-supply = <&vcc_3v3_s3>; + pinctrl-0 = <&gmac1_rgmii_bus + &gmac1_rgmii_clk + &gmac1_rx_bus2 + &gmac1_tx_bus2 + &gmac1_miim>; + pinctrl-names = "default"; + snps,reset-active-low; + snps,reset-delays-us = <0 20000 100000>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + tx_delay = <0x43>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <500>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + pca9554: gpio@24 { + compatible = "nxp,pca9554"; + reg = <0x24>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <&vcc3v3_io_expander>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clock-rates = <200000000>; + assigned-clocks = <&cru CLK_SPI2>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20_sata30>; + status = "okay"; +}; + +&pcie2x1l1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20_sata30>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = + <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From 89be7a07156c0b4109d07644664474cb20782f43 Mon Sep 17 00:00:00 2001 From: Hrushiraj Gandhi Date: Tue, 14 Jul 2026 11:16:52 +0530 Subject: [PATCH 580/864] dt-bindings: arm: rockchip: Add Vicharak Vaaman2 Add device tree binding documentation for the Vicharak Vaaman2, a single-board computer based on the Rockchip RK3588 SoC. Signed-off-by: Hrushiraj Gandhi Acked-by: Conor Dooley Link: https://patch.msgid.link/20260714054653.266842-2-hrushirajg23@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 5f2d45fc5a2a..00f45e94f79d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1327,6 +1327,11 @@ properties: - const: vicharak,axon - const: rockchip,rk3588 + - description: Vicharak Vaaman2 + items: + - const: vicharak,vaaman2 + - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 From 896e4c4508b66f9b4c9ff12b536bd1a031621aa5 Mon Sep 17 00:00:00 2001 From: Hrushiraj Gandhi Date: Tue, 14 Jul 2026 11:16:53 +0530 Subject: [PATCH 581/864] arm64: dts: rockchip: Add Vicharak Vaaman2 board Add device tree for the Vicharak Vaaman2, a single-board computer based on the Rockchip RK3588 SoC. The board features: - RK3588 SoC with 4x Cortex-A76 (big) + 4x Cortex-A55 (little) - eMMC storage via SDHCI (HS400) - microSD card via SDMMC - RK806 PMIC on SPI2 providing all required power domains - Two RK8602/RK8603 CPU regulators on I2C0 (big clusters) - RK8602 NPU regulator on I2C1 - HYM8563 RTC on I2C0 - Status LED on GPIO2_C5 (active-low, heartbeat trigger) - UART2 as serial console at 1500000 baud - SARADC with 1.8V reference Signed-off-by: Hrushiraj Gandhi Link: https://patch.msgid.link/20260714054653.266842-3-hrushirajg23@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-vicharak-vaaman2.dts | 535 ++++++++++++++++++ 2 files changed, 536 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index d922aa93d292..390f41736488 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -217,6 +217,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vicharak-axon.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vicharak-vaaman2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-youyeetoo-yy3588.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts new file mode 100644 index 000000000000..f5b0cfc28e00 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model = "Vicharak Vaaman2"; + compatible = "vicharak,vaaman2", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + status_led: led-0 { + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + retain-state-suspended; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc20v_dcin: regulator-vcc20v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <20000000>; + regulator-max-microvolt = <20000000>; + regulator-name = "vcc20v_dcin"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc20v_dcin>; + regulator-name = "vcc5v0_sys"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + wakeup-source; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-name = "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <500>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + fcs,suspend-voltage-selector = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clock-rates = <200000000>; + assigned-clocks = <&cru CLK_SPI2>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_log_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; From a761818d9ee11183df0aefd16bf9fe46cc1c4c6d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 21 Jul 2026 10:34:45 -0300 Subject: [PATCH 582/864] arm64: dts: rockchip: Fix Gru WLAN sideband interrupt The Marvell WLAN host wake interrupt is wired to GPIO0 8 and is not one of the PCI INTx interrupts. The PCI device schema therefore interprets the two-cell GPIO interrupt specifier as an invalid PCI interrupt and reports dtbs_check warnings: pcie@0,0: wifi@0,0:interrupts:0:0: 8 is not one of [1, 2, 3, 4] pcie@0,0: wifi@0,0:interrupts:0: [8, 8] is too long Describe the sideband interrupt with interrupts-extended, which explicitly carries the interrupt controller and removes the ambiguity. Fixes: 48f4d9796d99 ("arm64: dts: rockchip: add Gru/Kevin DTS") Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260721133445.44283-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3f3cb0eb5809..5435fbc27095 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -505,8 +505,7 @@ &pci_rootport { mvl_wifi: wifi@0,0 { compatible = "pci1b4b,2b42"; reg = <0x0000 0x0 0x0 0x0 0x0>; - interrupt-parent = <&gpio0>; - interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended = <&gpio0 8 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&wlan_host_wake_l>; wakeup-source; From 7f1f09ed517de6b98fbd64393a3efc8b5055c2cc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 21 Jul 2026 10:34:21 -0300 Subject: [PATCH 583/864] arm64: dts: rockchip: Fix the rk3566-radxa-cm3 Wifi compatible According to brcm,bcm4329-fmac.yaml, "brcm,bcm43455-fmac" needs the "brcm,bcm4329-fmac" fallback. Change it accordingly to fix the following dt-schema warning: ['brcm,bcm43455-fmac'] is too short Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260721133421.44258-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi index 8453f06c261c..73c72eba72e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi @@ -369,7 +369,7 @@ &sdmmc1 { status = "okay"; wifi@1 { - compatible = "brcm,bcm43455-fmac"; + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio2>; interrupts = ; From f4fb08d6d735ddd64ae507e0b32679df0135cd8e Mon Sep 17 00:00:00 2001 From: Vic B Date: Sun, 19 Jul 2026 20:49:14 +0200 Subject: [PATCH 584/864] arm64: dts: rockchip: fix label of sys_led for nanopi-r4s This commit corrects the system LED configuration for the NanoPi R4S by replacing the deprecated label property with color and function. This changes the resulting label of mislabeled sys_led from red:power to green:status, while the labels of the other two leds stay intact (green:lan for lan_led and green:wan for wan_led). Signed-off-by: Vic B Link: https://patch.msgid.link/al0cKhqvPbBO_5q8@vicb.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi index 4274d1b6e80a..4ad012a9bdc8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dtsi @@ -14,6 +14,7 @@ /dts-v1/; +#include #include "rk3399-nanopi4.dtsi" / { @@ -25,19 +26,22 @@ gpio-leds { /delete-node/ led-0; lan_led: led-lan { + color = ; + function = LED_FUNCTION_LAN; gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; - label = "green:lan"; }; sys_led: led-sys { + color = ; + function = LED_FUNCTION_STATUS; gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; - label = "red:power"; default-state = "on"; }; wan_led: led-wan { + color = ; + function = LED_FUNCTION_WAN; gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; - label = "green:wan"; }; }; From 7707e4555cf1d52689621e3206df8ad2debaa0dd Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 21 Jul 2026 10:54:50 -0300 Subject: [PATCH 585/864] arm64: dts: rockchip: Fix rk3566-bigtreetech-cb2 touchscreen property The TSC2007 driver uses the ti,max-rt property to specify the maximum touch resistance, but the rk3566-bigtreetech-cb2 device tree uses the undocumented ti,rt-thr property instead. As a result, the configured value is ignored and the driver falls back to its default maximum resistance value of 4095. Replace ti,rt-thr with ti,max-rt to preserve the intended resistance threshold of 3000. Fixes: bfbc663d2733 ("arm64: dts: rockchip: Add BigTreeTech CB2 and Pi2") Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260721135450.45286-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi index b6cf03a7ba66..04cf285e6c2a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -569,7 +569,7 @@ tft_tp: touchscreen@48 { reg = <0x48>; status = "okay"; ti,x-plate-ohms = <660>; - ti,rt-thr = <3000>; + ti,max-rt = <3000>; ti,fuzzx = <32>; ti,fuzzy = <16>; }; From 862de1b7ff9a3ad4151ebca050a4f44d8be83f9f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:39:51 -0400 Subject: [PATCH 586/864] dt-bindings: display: imx: Add deprecated property display and display0 Add deprecated property display and display0 to allow old platform lx1021a (>10 years) to put display timing under dcu node. Following patch rename display@0 to display0 and mode0 to timing0. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: dcu@2ce0000 (fsl,ls1021a-dcu): 'display', 'display@0' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml Acked-by: Rob Herring (Arm) Signed-off-by: Frank Li --- .../bindings/display/fsl,ls1021a-dcu.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml b/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml index 72d14babe993..6ac5ababbe00 100644 --- a/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml +++ b/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml @@ -45,6 +45,15 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: The phandle to the timing controller node. + display: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to display panel + deprecated: true + + display0: + $ref: panel/panel-common.yaml# + deprecated: true + required: - compatible - reg @@ -53,6 +62,19 @@ required: additionalProperties: false +allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,ls1021a-dcu + then: + properties: + display: false + display0: false + examples: - | display-controller@2ce0000 { From 6db9b23f3c0ebda050a4d38fda2b59db146ca161 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 8 Jul 2026 15:39:52 -0400 Subject: [PATCH 587/864] ARM: dts: ls1021a-iot: rename display@0 to display0 Rename node name display@0 to display0 since no reg under it. Rename mode0 to timing0. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: dcu@2ce0000 (fsl,ls1021a-dcu): 'display', 'display@0' do not match any of the regexes: '^pinctrl-[0-9]+$' from schema $id: http://devicetree.org/schemas/display/fsl,ls1021a-dcu.yaml arch/arm/boot/dts/nxp/ls/ls1021a-iot.dtb: display-timings: 'mode0' does not match any of the regexes: '^pinctrl-[0-9]+$', '^timing' from schema $id: http://devicetree.org/schemas/display/panel/display-timings.yaml Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts index e13ccae629a7..07b01434fc04 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts @@ -82,13 +82,13 @@ &dcu { display = <&display>; status = "okay"; - display: display@0 { + display: display0 { bits-per-pixel = <24>; display-timings { native-mode = <&timing0>; - timing0: mode0 { + timing0: timing0 { clock-frequency = <25000000>; hactive = <640>; vactive = <480>; From a225e19a4cc4e040ca0389cf0bbe209c23f5c92d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 10 Jul 2026 14:33:12 +0800 Subject: [PATCH 588/864] riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX RTL8211F require at least 50ms deassert to guarantee the register access, 10ms is only enough for the PHY reset. Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") Signed-off-by: Inochi Amaoto Reviewed-by: Yixun Lan Tested-by: E Shattow Link: https://patch.msgid.link/20260710063314.1030249-1-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 8b2a120b02d1..37ce58a09e4e 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -233,7 +233,7 @@ phy0: phy@1 { reg = <1>; reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - reset-deassert-us = <10000>; + reset-deassert-us = <50000>; realtek,aldps-enable; realtek,clkout-disable; }; From 12b0d602e8642297ec369eeb99366d37c8a3a120 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 10 Jul 2026 14:33:13 +0800 Subject: [PATCH 589/864] riscv: dts: spacemit: Add enough deassert time for the PHY on com260 board RTL8211F require at least 50ms deassert to guarantee the register access, 10ms is only enough for the PHY reset. Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") Signed-off-by: Inochi Amaoto Link: https://patch.msgid.link/20260710063314.1030249-2-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi index a38d7b738258..b704b537385c 100644 --- a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi @@ -178,7 +178,7 @@ phy1: phy@1 { reg = <1>; reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - reset-deassert-us = <10000>; + reset-deassert-us = <50000>; }; }; }; From fc87f5285304b51b586218d22f7d1f01e72d9328 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 20:04:05 +0200 Subject: [PATCH 590/864] ARM: dts: sigmastar: Correct indentation Correct indentation to one tab. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Acked-by: Daniel Palmer Link: https://patch.msgid.link/20260706180404.648545-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/sigmastar/mstar-infinity2m.dtsi | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi b/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi index 1b485efd7156..437329fb912a 100644 --- a/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/sigmastar/mstar-infinity2m.dtsi @@ -7,17 +7,17 @@ #include "mstar-infinity.dtsi" &cpu0_opp_table { - opp-1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1000000>; - clock-latency-ns = <300000>; - }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; }; &cpus { From 14f816138bdcb0e0c00f4b82be75d0485af22b30 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:19:43 +0200 Subject: [PATCH 591/864] ARM: dts: arm: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Acked-by: Liviu Dudau Link: https://patch.msgid.link/20260706101942.341681-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/arm/arm-realview-eb.dtsi | 2 +- arch/arm/boot/dts/arm/arm-realview-pb1176.dts | 2 +- arch/arm/boot/dts/arm/arm-realview-pb11mp.dts | 6 +++--- arch/arm/boot/dts/arm/arm-realview-pbx.dtsi | 6 +++--- arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi index ae370d4eb9d8..f90e28ee4cb9 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi @@ -51,7 +51,7 @@ vmmc: regulator-vmmc { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - }; + }; xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts index a75d8b107fe1..1cd095496832 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -53,7 +53,7 @@ vmmc: regulator-vmmc { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - }; + }; veth: regulator-veth { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts index 59c78def83f2..635b09030f60 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts @@ -153,7 +153,7 @@ vmmc: regulator-vmmc { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - }; + }; veth: regulator-veth { compatible = "regulator-fixed"; @@ -544,7 +544,7 @@ timer01: timer@10011000 { interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; arm,sp804-has-irq = <1>; clocks = <&sp810_syscon 0>, - <&sp810_syscon 1>, + <&sp810_syscon 1>, <&pclk>; clock-names = "timer0clk", "timer1clk", @@ -558,7 +558,7 @@ timer23: timer@10012000 { interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; arm,sp804-has-irq = <1>; clocks = <&sp810_syscon 2>, - <&sp810_syscon 3>, + <&sp810_syscon 3>, <&pclk>; clock-names = "timer0clk", "timer1clk", diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi index 0d3d96ffa6e6..366c8baefe8c 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi @@ -52,7 +52,7 @@ vmmc: regulator-vmmc { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - }; + }; veth: regulator-veth { compatible = "regulator-fixed"; @@ -373,7 +373,7 @@ timer01: timer@10011000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10011000 0x1000>; clocks = <&sp810_syscon0 0>, - <&sp810_syscon0 1>, + <&sp810_syscon0 1>, <&pclk>; clock-names = "timerclk0", "timerclk1", @@ -384,7 +384,7 @@ timer23: timer@10012000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x10012000 0x1000>; clocks = <&sp810_syscon0 2>, - <&sp810_syscon0 3>, + <&sp810_syscon0 3>, <&pclk>; clock-names = "timerclk2", "timerclk3", diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts index 6ef23c53d2d8..64f87e6c12bf 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts @@ -209,11 +209,11 @@ dma@7ff00000 { clock-names = "apb_pclk"; }; - scc@7fff0000 { + scc@7fff0000 { compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc"; reg = <0 0x7fff0000 0 0x1000>; interrupts = <0 95 4>; - }; + }; timer { compatible = "arm,armv7-timer"; From b364559b491ada54eefdd948606767621d2cedde Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:44 +0200 Subject: [PATCH 592/864] ARM: dts: microchip: at91: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706101843.341339-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts | 8 ++++---- arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts index 45edf6214cf7..25af4ceb67b4 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d27_som1_ek.dts @@ -258,10 +258,10 @@ pinctrl_i2c1_default: i2c1_default { }; pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; + pinmux = , + ; + bias-disable; + }; pinctrl_isc_base: isc_base { diff --git a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts index fbae6a9af6c3..b7ebd8e5f0bb 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d2_icp.dts @@ -451,10 +451,10 @@ pinctrl_i2c1_default: i2c1_default { }; pinctrl_i2c1_gpio: i2c1_gpio { - pinmux = , - ; - bias-disable; - }; + pinmux = , + ; + bias-disable; + }; pinctrl_key_gpio_default: key_gpio_default { pinmux = ; From eed86f8c39a2f76c1b0b017aecb63b3a8a53eda8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:18:06 +0200 Subject: [PATCH 593/864] ARM: dts: vt8500: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706101805.341103-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/vt8500/wm8505.dtsi | 4 +- arch/arm/boot/dts/vt8500/wm8650.dtsi | 8 +-- arch/arm/boot/dts/vt8500/wm8750.dtsi | 104 +++++++++++++-------------- arch/arm/boot/dts/vt8500/wm8850.dtsi | 54 +++++++------- 4 files changed, 85 insertions(+), 85 deletions(-) diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi index 915adbf6e1e0..40fa00f82fad 100644 --- a/arch/arm/boot/dts/vt8500/wm8505.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi @@ -21,14 +21,14 @@ cpu@0 { }; }; - aliases { + aliases { serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; serial5 = &uart5; - }; + }; soc { #address-cells = <1>; diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi index 82eef7504364..d27a6aac8aa4 100644 --- a/arch/arm/boot/dts/vt8500/wm8650.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi @@ -21,7 +21,7 @@ cpu@0 { }; }; - aliases { + aliases { serial0 = &uart0; serial1 = &uart1; }; @@ -147,12 +147,12 @@ clkddr: ddr { }; clkuart0: uart0 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; clocks = <&ref24>; enable-reg = <0x250>; enable-bit = <1>; - }; + }; clkuart1: uart1 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi index 5342b7fe4ef8..d8c21097784d 100644 --- a/arch/arm/boot/dts/vt8500/wm8750.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi @@ -168,37 +168,37 @@ clkuart1: uart1 { enable-bit = <25>; }; - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; - clkuart4: uart4 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <28>; - }; + clkuart4: uart4 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <28>; + }; - clkuart5: uart5 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <29>; - }; + clkuart5: uart5 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <29>; + }; clkpwm: pwm { #clock-cells = <0>; @@ -286,37 +286,37 @@ uart1: serial@d82b0000 { status = "disabled"; }; - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; status = "disabled"; - }; + }; - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; status = "disabled"; - }; + }; - uart4: serial@d8370000 { - compatible = "via,vt8500-uart"; - reg = <0xd8370000 0x1040>; - interrupts = <30>; - clocks = <&clkuart4>; + uart4: serial@d8370000 { + compatible = "via,vt8500-uart"; + reg = <0xd8370000 0x1040>; + interrupts = <30>; + clocks = <&clkuart4>; status = "disabled"; - }; + }; - uart5: serial@d8380000 { - compatible = "via,vt8500-uart"; - reg = <0xd8380000 0x1040>; - interrupts = <43>; - clocks = <&clkuart5>; + uart5: serial@d8380000 { + compatible = "via,vt8500-uart"; + reg = <0xd8380000 0x1040>; + interrupts = <43>; + clocks = <&clkuart5>; status = "disabled"; - }; + }; rtc@d8100000 { compatible = "via,vt8500-rtc"; diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi index 58109aa05f74..a17ac3515985 100644 --- a/arch/arm/boot/dts/vt8500/wm8850.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -179,21 +179,21 @@ clkuart1: uart1 { enable-bit = <25>; }; - clkuart2: uart2 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <26>; - }; + clkuart2: uart2 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <26>; + }; - clkuart3: uart3 { - #clock-cells = <0>; - compatible = "via,vt8500-device-clock"; - clocks = <&ref24>; - enable-reg = <0x254>; - enable-bit = <27>; - }; + clkuart3: uart3 { + #clock-cells = <0>; + compatible = "via,vt8500-device-clock"; + clocks = <&ref24>; + enable-reg = <0x254>; + enable-bit = <27>; + }; clkpwm: pwm { #clock-cells = <0>; @@ -273,21 +273,21 @@ uart1: serial@d82b0000 { status = "disabled"; }; - uart2: serial@d8210000 { - compatible = "via,vt8500-uart"; - reg = <0xd8210000 0x1040>; - interrupts = <47>; - clocks = <&clkuart2>; + uart2: serial@d8210000 { + compatible = "via,vt8500-uart"; + reg = <0xd8210000 0x1040>; + interrupts = <47>; + clocks = <&clkuart2>; status = "disabled"; - }; + }; - uart3: serial@d82c0000 { - compatible = "via,vt8500-uart"; - reg = <0xd82c0000 0x1040>; - interrupts = <50>; - clocks = <&clkuart3>; + uart3: serial@d82c0000 { + compatible = "via,vt8500-uart"; + reg = <0xd82c0000 0x1040>; + interrupts = <50>; + clocks = <&clkuart3>; status = "disabled"; - }; + }; rtc@d8100000 { compatible = "via,vt8500-rtc"; @@ -308,7 +308,7 @@ ethernet@d8004000 { compatible = "via,vt8500-rhine"; reg = <0xd8004000 0x100>; interrupts = <10>; - }; + }; l2_cache: cache-controller@d9000000 { compatible = "arm,pl310-cache"; From 6a5a6cc5e9ad5655186ff289f21db532b44e14b2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:17:58 +0200 Subject: [PATCH 594/864] ARM: dts: nvidia: tegra114-asus-tf701t: Correct trailing whitespace Drop trailing whitespace. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706101757.340149-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts index f02e2cf65fe8..e563beaa2bb1 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -386,7 +386,7 @@ cam-i2c { nvidia,open-drain = ; nvidia,lock = ; }; - + ddc-i2c { nvidia,pins = "ddc_scl_pv4", "ddc_sda_pv5"; From 26b8eb8a98c18b2ee4ea76d99fa2b2a5ccbc1b6c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:35:24 +0200 Subject: [PATCH 595/864] arm64: dts: amd: seattle: Remove useless clocks DTSI include The "amd-seattle-clks.dtsi" file is included exactly once, so paste the contents directly in proper DTSI. No functional impact. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706093523.274093-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi | 43 ------------------- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 36 +++++++++++++++- 2 files changed, 35 insertions(+), 44 deletions(-) delete mode 100644 arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi deleted file mode 100644 index 73f687773ce6..000000000000 --- a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle Clocks - * - * Copyright (C) 2014 Advanced Micro Devices, Inc. - */ - - adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "adl3clk_100mhz"; - }; - - ccpclk_375mhz: clock-375000000 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <375000000>; - clock-output-names = "ccpclk_375mhz"; - }; - - sataclk_333mhz: clock-333000000 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <333000000>; - clock-output-names = "sataclk_333mhz"; - }; - - dmaclk_500mhz: pcieclk_500mhz: clock-500000000 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "pcieclk_500mhz"; - }; - - xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz: - miscclk_250mhz: clock-250000000 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "miscclk_250mhz"; - }; - diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi index a611f8288b3e..c5b9dbfdf014 100644 --- a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi @@ -11,7 +11,41 @@ / { #address-cells = <2>; #size-cells = <2>; - /include/ "amd-seattle-clks.dtsi" + adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "adl3clk_100mhz"; + }; + + ccpclk_375mhz: clock-375000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <375000000>; + clock-output-names = "ccpclk_375mhz"; + }; + + sataclk_333mhz: clock-333000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333000000>; + clock-output-names = "sataclk_333mhz"; + }; + + dmaclk_500mhz: pcieclk_500mhz: clock-500000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + clock-output-names = "pcieclk_500mhz"; + }; + + xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz: + miscclk_250mhz: clock-250000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "miscclk_250mhz"; + }; gic0: interrupt-controller@e1101000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; From 8461050861aeea29138dd25d5fb78c6f643c708c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 11:35:25 +0200 Subject: [PATCH 596/864] arm64: dts: amd: seattle: Remove useless xgbe DTSI include The "amd-seattle-xgbe-b.dtsi" file is included exactly once, so paste the contents directly in proper DTSI. No functional impact. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260706093523.274093-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/amd/amd-overdrive-rev-b0.dts | 78 ++++++++++++++++- .../boot/dts/amd/amd-seattle-xgbe-b.dtsi | 84 ------------------- 2 files changed, 77 insertions(+), 85 deletions(-) delete mode 100644 arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi diff --git a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts index 8862adae44e9..0860fc7a6927 100644 --- a/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts +++ b/arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts @@ -71,5 +71,81 @@ sdcard0: mmc@0 { }; &smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" + xgmac0: ethernet@e0700000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0 0xe0700000 0 0x80000>, + <0 0xe0780000 0 0x80000>, + <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ + <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ + <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ + interrupts = <0 325 4>, + <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, + <0 323 4>; + amd,per-channel-interrupt; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <18>; + amd,serdes-tx-amp = <0>, <0>, <0>; + amd,serdes-dfe-tap-config = <3>, <3>, <3>; + amd,serdes-dfe-tap-enable = <0>, <0>, <7>; + mac-address = [ 02 A1 A2 A3 A4 A5 ]; + clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; + clock-names = "dma_clk", "ptp_clk"; + phy-mode = "xgmii"; + iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */ + dma-coherent; + }; + + xgmac1: ethernet@e0900000 { + compatible = "amd,xgbe-seattle-v1a"; + reg = <0 0xe0900000 0 0x80000>, + <0 0xe0980000 0 0x80000>, + <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ + <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ + <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ + interrupts = <0 324 4>, + <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, + <0 322 4>; + amd,per-channel-interrupt; + amd,speed-set = <0>; + amd,serdes-blwc = <1>, <1>, <0>; + amd,serdes-cdr-rate = <2>, <2>, <7>; + amd,serdes-pq-skew = <10>, <10>, <18>; + amd,serdes-tx-amp = <0>, <0>, <0>; + amd,serdes-dfe-tap-config = <3>, <3>, <3>; + amd,serdes-dfe-tap-enable = <0>, <0>, <7>; + mac-address = [ 02 B1 B2 B3 B4 B5 ]; + clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; + clock-names = "dma_clk", "ptp_clk"; + phy-mode = "xgmii"; + iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */ + dma-coherent; + }; + + xgmac0_smmu: iommu@e0600000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0600000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 336 4>, + <0 336 4>; + #iommu-cells = <2>; + dma-coherent; + }; + + xgmac1_smmu: iommu@e0800000 { + compatible = "arm,mmu-401"; + reg = <0 0xe0800000 0 0x10000>; + #global-interrupts = <1>; + interrupts = /* Uses combined intr for both + * global and context + */ + <0 335 4>, + <0 335 4>; + #iommu-cells = <2>; + dma-coherent; + }; }; diff --git a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi deleted file mode 100644 index 18b0c2dd1b2d..000000000000 --- a/arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DTS file for AMD Seattle XGBE (RevB) - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - */ - - xgmac0: ethernet@e0700000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0700000 0 0x80000>, - <0 0xe0780000 0 0x80000>, - <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ - <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ - <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ - interrupts = <0 325 4>, - <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, - <0 323 4>; - amd,per-channel-interrupt; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <18>; - amd,serdes-tx-amp = <0>, <0>, <0>; - amd,serdes-dfe-tap-config = <3>, <3>, <3>; - amd,serdes-dfe-tap-enable = <0>, <0>, <7>; - mac-address = [ 02 A1 A2 A3 A4 A5 ]; - clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */ - dma-coherent; - }; - - xgmac1: ethernet@e0900000 { - compatible = "amd,xgbe-seattle-v1a"; - reg = <0 0xe0900000 0 0x80000>, - <0 0xe0980000 0 0x80000>, - <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ - <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ - <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ - interrupts = <0 324 4>, - <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, - <0 322 4>; - amd,per-channel-interrupt; - amd,speed-set = <0>; - amd,serdes-blwc = <1>, <1>, <0>; - amd,serdes-cdr-rate = <2>, <2>, <7>; - amd,serdes-pq-skew = <10>, <10>, <18>; - amd,serdes-tx-amp = <0>, <0>, <0>; - amd,serdes-dfe-tap-config = <3>, <3>, <3>; - amd,serdes-dfe-tap-enable = <0>, <0>, <7>; - mac-address = [ 02 B1 B2 B3 B4 B5 ]; - clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; - clock-names = "dma_clk", "ptp_clk"; - phy-mode = "xgmii"; - iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */ - dma-coherent; - }; - - xgmac0_smmu: iommu@e0600000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0600000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 336 4>, - <0 336 4>; - #iommu-cells = <2>; - dma-coherent; - }; - - xgmac1_smmu: iommu@e0800000 { - compatible = "arm,mmu-401"; - reg = <0 0xe0800000 0 0x10000>; - #global-interrupts = <1>; - interrupts = /* Uses combined intr for both - * global and context - */ - <0 335 4>, - <0 335 4>; - #iommu-cells = <2>; - dma-coherent; - }; From 6d6536c880febe2340d8d388f42660eccff5aa81 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Jul 2026 07:33:49 +0800 Subject: [PATCH 597/864] riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board Current phy framework can not re-initialize the phy correctly, as it will assert the phy reset GPIO so the phy id can not be read. Setting the phy id of board pico-itx manually so the phy id detection can be skipped. Fixes: 74657a376960 ("riscv: dts: spacemit: Add ethernet device for K3") Reported-by: E Shattow Reported-by: Inochi Amaoto Closes: https://lore.kernel.org/netdev/20260712045233.800748-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Tested-by: E Shattow Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260725233351.55004-2-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 37ce58a09e4e..4460e225581c 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -229,7 +229,7 @@ ð0 { mdio { phy0: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <1>; reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; From 9db839d52ccd9af67d460cb9ac893276a74b88e5 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Sun, 26 Jul 2026 07:33:50 +0800 Subject: [PATCH 598/864] riscv: dts: spacemit: Fix phy id check for the phy on com260 board Current phy framework can not re-initialize the phy correctly, as it will assert the phy reset GPIO so the phy id can not be read. Setting the phy id of board com260 manually so the phy id dectection can be skipped. Fixes: cfe5c91cb73c ("riscv: dts: spacemit: k3: Initial support for CoM260-IFX board") Signed-off-by: Inochi Amaoto Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260725233351.55004-3-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi index b704b537385c..2a07cd8f2a56 100644 --- a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi @@ -174,7 +174,7 @@ ð1 { mdio { phy1: phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <1>; reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; From e57a4beb33df5b5b91e8af7c8abac5f49838d524 Mon Sep 17 00:00:00 2001 From: liyeshan Date: Fri, 17 Jul 2026 07:45:25 -0700 Subject: [PATCH 599/864] riscv: dts: spacemit: add K3 PDMA request numbers Add a local DTS header that gives symbolic names to the SpacemiT K3 PDMA request lines of the non-secure peripherals. Device trees can use these K3_PDMA_* macros instead of hard-coded request numbers when wiring a peripheral "dmas" property. Signed-off-by: liyeshan Signed-off-by: Guodong Xu Signed-off-by: Zhengyu He Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-1-969a1b0f783f@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pdma.h | 83 ++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3-pdma.h diff --git a/arch/riscv/boot/dts/spacemit/k3-pdma.h b/arch/riscv/boot/dts/spacemit/k3-pdma.h new file mode 100644 index 000000000000..a5b723ad616a --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pdma.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * DMA request number (DRQ) definitions for non-secure peripherals of + * the SpacemiT K3 PDMA. + * + * Copyright (c) 2025 SpacemiT + * Copyright (c) 2026 Guodong Xu + */ + +#ifndef _DTS_SPACEMIT_K3_PDMA_H +#define _DTS_SPACEMIT_K3_PDMA_H + +/* UART DMA request numbers */ +#define K3_PDMA_UART0_TX 3 +#define K3_PDMA_UART0_RX 4 +#define K3_PDMA_UART2_TX 5 +#define K3_PDMA_UART2_RX 6 +#define K3_PDMA_UART3_TX 7 +#define K3_PDMA_UART3_RX 8 +#define K3_PDMA_UART4_TX 9 +#define K3_PDMA_UART4_RX 10 +#define K3_PDMA_UART5_TX 25 +#define K3_PDMA_UART5_RX 26 +#define K3_PDMA_UART6_TX 27 +#define K3_PDMA_UART6_RX 28 +#define K3_PDMA_UART7_TX 29 +#define K3_PDMA_UART7_RX 30 +#define K3_PDMA_UART8_TX 31 +#define K3_PDMA_UART8_RX 32 +#define K3_PDMA_UART9_TX 33 +#define K3_PDMA_UART9_RX 34 +#define K3_PDMA_UART10_TX 53 +#define K3_PDMA_UART10_RX 54 + +/* I2C DMA request numbers */ +#define K3_PDMA_I2C0_TX 11 +#define K3_PDMA_I2C0_RX 12 +#define K3_PDMA_I2C1_TX 13 +#define K3_PDMA_I2C1_RX 14 +#define K3_PDMA_I2C2_TX 15 +#define K3_PDMA_I2C2_RX 16 +#define K3_PDMA_I2C4_TX 17 +#define K3_PDMA_I2C4_RX 18 +#define K3_PDMA_I2C5_TX 35 +#define K3_PDMA_I2C5_RX 36 +#define K3_PDMA_I2C6_TX 37 +#define K3_PDMA_I2C6_RX 38 +#define K3_PDMA_I2C8_TX 41 +#define K3_PDMA_I2C8_RX 42 + +/* SSP/SPI DMA request numbers */ +#define K3_PDMA_SSP3_TX 19 +#define K3_PDMA_SSP3_RX 20 +#define K3_PDMA_SSPA0_TX 21 +#define K3_PDMA_SSPA0_RX 22 +#define K3_PDMA_SSPA1_TX 23 +#define K3_PDMA_SSPA1_RX 24 +#define K3_PDMA_SSPA2_TX 56 +#define K3_PDMA_SSPA2_RX 57 +#define K3_PDMA_SSPA3_TX 58 +#define K3_PDMA_SSPA3_RX 59 +#define K3_PDMA_SSPA4_TX 60 +#define K3_PDMA_SSPA4_RX 61 +#define K3_PDMA_SSPA5_TX 62 +#define K3_PDMA_SSPA5_RX 63 + +/* CAN DMA request numbers */ +#define K3_PDMA_CAN0_RX 43 +#define K3_PDMA_CAN1_RX 44 +#define K3_PDMA_CAN2_RX 51 +#define K3_PDMA_CAN3_RX 52 + +/* SSP0/1 DMA request numbers */ +#define K3_PDMA_SSP0_TX 64 +#define K3_PDMA_SSP0_RX 65 +#define K3_PDMA_SSP1_TX 66 +#define K3_PDMA_SSP1_RX 67 + +/* QSPI DMA request numbers */ +#define K3_PDMA_QSPI_RX 84 +#define K3_PDMA_QSPI_TX 85 + +#endif /* _DTS_SPACEMIT_K3_PDMA_H */ From 324c9c10839bec6da848b8947ca33e0b23d6b735 Mon Sep 17 00:00:00 2001 From: Zhengyu He Date: Fri, 17 Jul 2026 07:45:27 -0700 Subject: [PATCH 600/864] riscv: dts: spacemit: add SPI controllers for K3 Add the SPI controller nodes for K3. Signed-off-by: Cody Kang Signed-off-by: Zhengyu He Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260717-k3-com260-spi-v7-2-rc2-b4-preview-20260716-v1-3-969a1b0f783f@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 49 +++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index fc46e34465e4..7583467793e1 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -5,8 +5,10 @@ */ #include -#include #include +#include + +#include "k3-pdma.h" /dts-v1/; @@ -927,6 +929,21 @@ pwm7: pwm@d401bc00 { status = "disabled"; }; + spi3: spi@d401c000 { + compatible = "spacemit,k3-spi", "spacemit,k1-spi"; + reg = <0x0 0xd401c000 0x0 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_APBC_SPI3>, + <&syscon_apbc CLK_APBC_SPI3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_SPI3>; + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&pdma K3_PDMA_SSP3_RX>, <&pdma K3_PDMA_SSP3_TX>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + pwm8: pwm@d4020000 { compatible = "spacemit,k3-pwm", "marvell,pxa910-pwm"; reg = <0x0 0xd4020000 0x0 0x10>; @@ -1081,6 +1098,36 @@ uart10: serial@d401f000 { status = "disabled"; }; + spi0: spi@d4040000 { + compatible = "spacemit,k3-spi", "spacemit,k1-spi"; + reg = <0x0 0xd4040000 0x0 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_APBC_SPI0>, + <&syscon_apbc CLK_APBC_SPI0_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_SPI0>; + interrupts = <283 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&pdma K3_PDMA_SSP0_RX>, <&pdma K3_PDMA_SSP0_TX>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@d4040800 { + compatible = "spacemit,k3-spi", "spacemit,k1-spi"; + reg = <0x0 0xd4040800 0x0 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_APBC_SPI1>, + <&syscon_apbc CLK_APBC_SPI1_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_APBC_SPI1>; + interrupts = <282 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&pdma K3_PDMA_SSP1_RX>, <&pdma K3_PDMA_SSP1_TX>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + syscon_mpmu: system-controller@d4050000 { compatible = "spacemit,k3-syscon-mpmu"; reg = <0x0 0xd4050000 0x0 0x10000>; From 259f5639b4b1a04cef9a7f79a95ef9ab928264cd Mon Sep 17 00:00:00 2001 From: Jennifer Berringer Date: Wed, 22 Jul 2026 16:28:47 -0400 Subject: [PATCH 601/864] riscv: dts: spacemit: k3-com260: add eeprom on i2c2 Enable i2c2 on the K3 CoM260 compute module and use it for a 24c02 eeprom. This eeprom stores the product name, a MAC address, and a serial number. Signed-off-by: Jennifer Berringer Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260722202848.1817988-2-jberring@redhat.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi index 2a07cd8f2a56..289319a591b9 100644 --- a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi @@ -26,6 +26,38 @@ reg_5v_sys: regulator-5v-sys { }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1_cfg>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; + read-only; + size = <256>; + status = "okay"; + + nvmem-layout { + compatible = "onie,tlv-layout"; + + mac-address { + #nvmem-cell-cells = <1>; + }; + + num-macs { + }; + + product-name { + }; + + serial-number { + }; + }; + }; +}; + &i2c8 { pinctrl-names = "default"; pinctrl-0 = <&i2c8_cfg>; From b1d7f3e7da4230815ad732f764f7978049737bb6 Mon Sep 17 00:00:00 2001 From: Jennifer Berringer Date: Wed, 22 Jul 2026 16:28:48 -0400 Subject: [PATCH 602/864] riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1 Enable i2c1 for k3-com260-ifx and use it for a 24c02 eeprom. This eeprom, unlike the one connected to i2c2, is part of the carrier board. Some boards do not have any data programmed on this eeprom from factory. Signed-off-by: Jennifer Berringer Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260722202848.1817988-3-jberring@redhat.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts | 15 +++++++++++++++ arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi | 12 ++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts index e7f76cd24b90..a5c08a7a781a 100644 --- a/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-com260-ifx.dts @@ -20,6 +20,21 @@ chosen { }; }; +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_1_cfg>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + pagesize = <8>; + reg = <0x50>; + read-only; + size = <256>; + status = "okay"; + }; +}; + &sdhci0 { pinctrl-names = "default","uhs"; pinctrl-0 = <&mmc1_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi index 5b9045e01434..6482d24be139 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-pinctrl.dtsi @@ -78,6 +78,18 @@ gmac1-phy-0-pins { }; }; + /omit-if-no-ref/ + i2c1_1_cfg: i2c1-1-cfg { + i2c1-1-pins { + pinmux = , /* i2c1 scl */ + ; /* i2c1 sda */ + + bias-pull-up = <1>; + drive-strength = <25>; + power-source = <1800>; + }; + }; + /omit-if-no-ref/ i2c2_1_cfg: i2c2-1-cfg { i2c2-1-pins { From 31efde747b5e5d2c185e06d872a9ef9b87f505ac Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 2 Jun 2026 18:00:00 +0800 Subject: [PATCH 603/864] riscv: dts: spacemit: enable PCIe on OrangePi R2S Enable the two RTL8125 network controllers and corresponding PHYs connected via the PCIe controllers on the OrangePi R2S. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260602100000.2402784-1-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-orangepi-r2s.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index dd72c33bd54c..24591f7c3d23 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -23,6 +23,14 @@ chosen { stdout-path = "serial0"; }; + pcie_vcc3v3: regulator-pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "pcie_vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vcc4v0: regulator-vcc4v0 { compatible = "regulator-fixed"; regulator-name = "vcc4v0"; @@ -228,6 +236,36 @@ dldo7 { }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; + vpcie3v3-supply = <&pcie_vcc3v3>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; + vpcie3v3-supply = <&pcie_vcc3v3>; +}; + +&pcie2 { + status = "okay"; +}; + &pdma { status = "okay"; }; From 8258a4bcfaa9ded9b19b3c230ed85df44d580935 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 9 Jul 2026 13:19:11 +0200 Subject: [PATCH 604/864] arm64: dts: microchip: lan969x: add QSPI nodes Add the required DT nodes for both QSPI controllers. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20260709112006.390742-6-robert.marko@sartura.hr Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/microchip/lan9691.dtsi | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi index ed997d87dd09..a8541c6a098d 100644 --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi @@ -396,6 +396,39 @@ clks: clock-controller@e00c00b4 { clock-names = "cpu", "ddr", "sys"; }; + qspi0: spi@e0804000 { + compatible = "microchip,lan9691-qspi"; + reg = <0xe0804000 0x00000100>, + <0x20000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&clks GCK_ID_QSPI0>; + assigned-clock-rates = <100000000>; + dmas = <&dma AT91_XDMAC_DT_PERID(1)>, + <&dma AT91_XDMAC_DT_PERID(0)>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + qspi2: spi@e0834000 { + compatible = "microchip,lan9691-qspi"; + reg = <0xe0834000 0x00000100>, + <0x30000000 0x04000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&clks GCK_ID_QSPI2>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + reset: reset-controller@e201000c { compatible = "microchip,lan9691-switch-reset", "microchip,lan966x-switch-reset"; From 8f62ead195283b8620070985ae642a5a1db88843 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:25 +0300 Subject: [PATCH 605/864] arm64: dts: lx2160a: explicitly enable serdes_1 node Explicitly enable the serdes_1 node in all board DT files. This is needed in order to be able to change the default status of the node to "disabled" from the SoC DT file. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++ arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi index 4bc151d721dd..1f946d3a4ec0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi @@ -135,6 +135,10 @@ &sata3 { status = "okay"; }; +&serdes_1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts index d16e27307275..954b9955b1b3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts @@ -805,6 +805,10 @@ &rgmii_phy1 { status = "disabled"; }; +&serdes_1 { + status = "okay"; +}; + &serdes_2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts index 935f421475ac..39b2b04be532 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts @@ -325,6 +325,10 @@ &sata3 { status = "okay"; }; +&serdes_1 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index 99ee2b1c0f13..df2568ec7f1a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -367,6 +367,10 @@ &pcs_mdio18 { status = "okay"; }; +&serdes_1 { + status = "okay"; +}; + &serdes_2 { status = "okay"; }; From 12422fe9b3f4876f953bb1699e8c2c18084e58d9 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:26 +0300 Subject: [PATCH 606/864] arm64: dts: lx2160a: extract the PCIe nodes into a separate dtsi One of the major differences between LX2160A Rev1 and Rev2 is the PCIe controller used. With the final goal of removing any usage of delete-node or delete-property from the current LX2160A related dts files, move the PCIe nodes found on the LX2160A Rev1 into a separate dtsi file. This will make it easier to include the appropriate dtsi file describing the PCIe controller depending on the SoC revision in a follow-up patch. No actual change in the DT nodes found in the final DTBs is intended. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi | 176 ++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 170 +---------------- 2 files changed, 178 insertions(+), 168 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi new file mode 100644 index 000000000000..871f5d5d8f75 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-pcie-mbvl.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the PCIe Mobiveil's GPEX 4.0 IP +// found on LX2160A Rev1 +// +// Copyright 2026 NXP + +&soc { + pcie1: pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie2: pcie@3500000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie3: pcie@3600000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ + <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <256>; + ppio-wins = <24>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie4: pcie@3700000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ + <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie5: pcie@3800000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ + <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <256>; + ppio-wins = <24>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + pcie6: pcie@3900000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ + <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = , /* AER interrupt */ + , /* PME interrupt */ + ; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + apio-wins = <8>; + ppio-wins = <8>; + bus-range = <0x0 0xff>; + ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 1d73abffa6b7..387cd677cdc7 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -1177,174 +1177,6 @@ sata3: sata@3230000 { status = "disabled"; }; - pcie1: pcie@3400000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie2: pcie@3500000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ - <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie3: pcie@3600000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ - <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <256>; - ppio-wins = <24>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie4: pcie@3700000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ - <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie5: pcie@3800000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ - <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <256>; - ppio-wins = <24>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - - pcie6: pcie@3900000 { - compatible = "fsl,lx2160a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ - <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "csr_axi_slave", "config_axi_slave"; - interrupts = , /* AER interrupt */ - , /* PME interrupt */ - ; /* controller interrupt */ - interrupt-names = "aer", "pme", "intr"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - apio-wins = <8>; - ppio-wins = <8>; - bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its 0>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - status = "disabled"; - }; - smmu: iommu@5000000 { compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; @@ -2021,3 +1853,5 @@ optee: optee { }; }; }; + +#include "fsl-lx2160a-pcie-mbvl.dtsi" From 9f0f43baf1ed556e6b16ddd5403dc44c5f21eb6a Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:27 +0300 Subject: [PATCH 607/864] arm64: dts: lx2160a: extract the SerDes nodes into a separate dtsi In terms of its SerDes blocks, the LX2162A is not properly described since it just inherits the LX2160A SerDes nodes, which is not correct. In order to fix this but also avoid the usage of delete-node, extract the SerDes nodes currently found in fsl-lx2160a.dtsi into a separate dtsi. No any actual changes in the final dtb files, only a dt node move. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-serdes.dtsi | 21 +++++++++++++++++++ .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 14 +------------ 2 files changed, 22 insertions(+), 13 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi new file mode 100644 index 000000000000..307824eda6d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2160A +// Rev1 and Rev2 +// +// Copyright 2026 NXP + +&soc { + serdes_1: phy@1ea0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1ea0000 0x0 0x1e30>; + #phy-cells = <1>; + }; + + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 387cd677cdc7..da139e7fa30c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -621,19 +621,6 @@ soc: soc { ranges; dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; - serdes_1: phy@1ea0000 { - compatible = "fsl,lynx-28g"; - reg = <0x0 0x1ea0000 0x0 0x1e30>; - #phy-cells = <1>; - }; - - serdes_2: phy@1eb0000 { - compatible = "fsl,lynx-28g"; - reg = <0x0 0x1eb0000 0x0 0x1e30>; - #phy-cells = <1>; - status = "disabled"; - }; - crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>; @@ -1855,3 +1842,4 @@ optee: optee { }; #include "fsl-lx2160a-pcie-mbvl.dtsi" +#include "fsl-lx2160a-serdes.dtsi" From 8f69555ef54c59aa0207cdd0e15939417730a4e4 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:28 +0300 Subject: [PATCH 608/864] arm64: dts: lx2160a: extract the PCIe from LX2160A Rev2 into a separate file The LX2160A Rev2 SoC changed the PCIe controllers used. This difference is reflected in the fsl-lx2160a-rev2.dtsi file which modifies the relevant dt nodes so that they match the actual HW. Extract these modifications into a separate dtsi file as a first step into a complete overhaul of the LX216xA related dts files with the intent to not use delete-node or delete-property. No final dtb changes are expected with this patch. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 185 +---------------- .../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 187 ++++++++++++++++++ 2 files changed, 188 insertions(+), 184 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi index 3d2637fee2d3..c2a18cfd8efc 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -7,187 +7,4 @@ /dts-v1/; #include "fsl-lx2160a.dtsi" - -&pcie1 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie2 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie3 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - - -&pcie4 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie5 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie6 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&soc { - pcie_ep1: pcie-ep@3400000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03400000 0x0 0x00100000 - 0x80 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; - - pcie_ep2: pcie-ep@3500000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03500000 0x0 0x00100000 - 0x88 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; - - pcie_ep3: pcie-ep@3600000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03600000 0x0 0x00100000 - 0x90 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <256>; - num-ib-windows = <24>; - status = "disabled"; - }; - - pcie_ep4: pcie-ep@3700000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03700000 0x0 0x00100000 - 0x98 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; - - - pcie_ep5: pcie-ep@3800000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03800000 0x0 0x00100000 - 0xa0 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <256>; - num-ib-windows = <24>; - status = "disabled"; - }; - - pcie_ep6: pcie-ep@3900000 { - compatible = "fsl,lx2160ar2-pcie-ep"; - reg = <0x00 0x03900000 0x0 0x00100000 - 0xa8 0x00000000 0x8 0x00000000>; - reg-names = "regs", "addr_space"; - num-ob-windows = <8>; - num-ib-windows = <8>; - status = "disabled"; - }; -}; +#include "fsl-lx216xa-pcie-gen3.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi new file mode 100644 index 000000000000..f405b21e68fc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the PCIe IPs found on the LX2160A Rev2 and LX2162A SoCs +// +// Copyright 2026 NXP + +&pcie1 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie2 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie3 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie4 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie5 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&pcie6 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + /delete-property/ apio-wins; + /delete-property/ ppio-wins; +}; + +&soc { + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep2: pcie-ep@3500000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03500000 0x0 0x00100000 + 0x88 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep3: pcie-ep@3600000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03600000 0x0 0x00100000 + 0x90 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + num-ib-windows = <24>; + status = "disabled"; + }; + + pcie_ep4: pcie-ep@3700000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03700000 0x0 0x00100000 + 0x98 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; + + pcie_ep5: pcie-ep@3800000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03800000 0x0 0x00100000 + 0xa0 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <256>; + num-ib-windows = <24>; + status = "disabled"; + }; + + pcie_ep6: pcie-ep@3900000 { + compatible = "fsl,lx2160ar2-pcie-ep"; + reg = <0x00 0x03900000 0x0 0x00100000 + 0xa8 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + num-ob-windows = <8>; + num-ib-windows = <8>; + status = "disabled"; + }; +}; From 285560f0d39dd6cd40c5c83470e4d3e43effd4b8 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:29 +0300 Subject: [PATCH 609/864] arm64: dts: lx2160a: split the dtsi to avoid delete-property Reorganize the LX216XA related dts/dtsi files with the intent to avoid any delete-property usage. Taken into consideration the differences between the LX2160A Rev1, LX2160A Rev2 and LX2162A SoCs, the following structure is created: fsl-lx216x.dtsi ---> fsl-lx2160a-rev1.dtsi (PCIe gen4, 3 SerDes blocks) (no PCIe, no SerDes) ---> fsl-lx2160a-rev2.dtsi (PCIe gen3, 3 SerDes blocks) ---> fsl-lx2162a.dtsi (PCIe gen3, 2 SerDes blocks) Each PCIe integration or SerDes block instantiation has its own dtsi file which gets to be included only by the necessary SoC level dtsi file. The dtsi file describing the PCIe controllers found on LX2160A Rev2 is also changed so that it does not work on a already defined node but rather it describes it entirely. In order to decouple the LX2162A from LX2160A, a new dtsi fsl-lx2162a-serdes.dtsi file is added which, for the moment, only duplicates the SerDes related nodes found already for LX2160A. Any dts which previously included fsl-lx2160a.dtsi now includes the -rev1 version and any dts which is clearly intended for LX2162A based board now includes the fsl-lx2162a.dtsi. No changes for the final dtbs. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-bluebox3.dts | 2 +- .../dts/freescale/fsl-lx2160a-clearfog-cx.dts | 2 +- .../dts/freescale/fsl-lx2160a-honeycomb.dts | 2 +- .../boot/dts/freescale/fsl-lx2160a-rev1.dtsi | 9 + .../boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 3 +- .../dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi | 2 +- .../dts/freescale/fsl-lx2162a-clearfog.dts | 2 +- .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +- .../dts/freescale/fsl-lx2162a-serdes.dtsi | 21 ++ .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 9 + .../{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} | 3 - .../dts/freescale/fsl-lx216xa-pcie-gen3.dtsi | 310 +++++++++++------- 12 files changed, 237 insertions(+), 130 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi rename arch/arm64/boot/dts/freescale/{fsl-lx2160a.dtsi => fsl-lx216x.dtsi} (99%) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts index 042c486bdda2..e035e4456867 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" / { model = "NXP Layerscape LX2160ABLUEBOX3"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts index 802d7611c647..4e47bb389af6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-cx.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" #include "fsl-lx2160a-cex7.dtsi" #include "fsl-lx2160a-clearfog-itx.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts index 2b1e13053422..1a603decd034 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-honeycomb.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" #include "fsl-lx2160a-cex7.dtsi" #include "fsl-lx2160a-clearfog-itx.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi new file mode 100644 index 000000000000..7538dbdc8093 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev1.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree Include file for Layerscape-LX2160A Rev1 SoC. +// +// Copyright 2026 NXP + +#include "fsl-lx216x.dtsi" +#include "fsl-lx2160a-pcie-mbvl.dtsi" +#include "fsl-lx2160a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi index c2a18cfd8efc..47a42347c230 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi @@ -6,5 +6,6 @@ /dts-v1/; -#include "fsl-lx2160a.dtsi" +#include "fsl-lx216x.dtsi" #include "fsl-lx216xa-pcie-gen3.dtsi" +#include "fsl-lx2160a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi index 89a4765737b4..cc6b6427ec8a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi @@ -5,7 +5,7 @@ * Author: Gregor Herburger */ -#include "fsl-lx2160a.dtsi" +#include "fsl-lx2160a-rev1.dtsi" / { reg_vcc3v3: regulator-vcc3v3 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts index df2568ec7f1a..63f161610caa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -8,7 +8,7 @@ #include -#include "fsl-lx2160a-rev2.dtsi" +#include "fsl-lx2162a.dtsi" #include "fsl-lx2162a-sr-som.dtsi" / { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts index 7a595fddc027..0ba56b9819ac 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include "fsl-lx2160a-rev2.dtsi" +#include "fsl-lx2162a.dtsi" / { model = "NXP Layerscape LX2162AQDS"; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi new file mode 100644 index 000000000000..23f05a138eac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file describing the Lynx 28G SerDes blocks found on the LX2162A +// SoC +// +// Copyright 2026 NXP + +&soc { + serdes_1: phy@1ea0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1ea0000 0x0 0x1e30>; + #phy-cells = <1>; + }; + + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi new file mode 100644 index 000000000000..b710f6a8eb48 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162 SoC +// +// Copyright 2026 NXP + +#include "fsl-lx216x.dtsi" +#include "fsl-lx216xa-pcie-gen3.dtsi" +#include "fsl-lx2162a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi similarity index 99% rename from arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi rename to arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi index da139e7fa30c..ae6e37870c5e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi @@ -1840,6 +1840,3 @@ optee: optee { }; }; }; - -#include "fsl-lx2160a-pcie-mbvl.dtsi" -#include "fsl-lx2160a-serdes.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi index f405b21e68fc..068fbf9bf04f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx216xa-pcie-gen3.dtsi @@ -4,127 +4,39 @@ // // Copyright 2026 NXP -&pcie1 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie2 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie3 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie4 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ - 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie5 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ - 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - -&pcie6 { - compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; - reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ - 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - - ranges = /* 16-Bit IO Window */ - <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, - /* 32-Bit - non-prefetchable */ - <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, - /* 64-Bit - prefetchable - 16GB */ - <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; - - interrupts = ; - interrupt-names = "intr"; - - /delete-property/ apio-wins; - /delete-property/ ppio-wins; -}; - &soc { + pcie1: pcie@3400000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep1: pcie-ep@3400000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000 @@ -135,6 +47,37 @@ pcie_ep1: pcie-ep@3400000 { status = "disabled"; }; + pcie2: pcie@3500000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep2: pcie-ep@3500000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000 @@ -145,6 +88,38 @@ pcie_ep2: pcie-ep@3500000 { status = "disabled"; }; + pcie3: pcie@3600000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x90 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep3: pcie-ep@3600000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000 @@ -155,6 +130,37 @@ pcie_ep3: pcie-ep@3600000 { status = "disabled"; }; + pcie4: pcie@3700000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x98 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep4: pcie-ep@3700000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03700000 0x0 0x00100000 @@ -165,6 +171,38 @@ pcie_ep4: pcie-ep@3700000 { status = "disabled"; }; + pcie5: pcie@3800000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ + 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep5: pcie-ep@3800000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03800000 0x0 0x00100000 @@ -175,6 +213,38 @@ pcie_ep5: pcie-ep@3800000 { status = "disabled"; }; + pcie6: pcie@3900000 { + compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie"; + reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ + 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + + ranges = /* 16-Bit IO Window */ + <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>, + /* 32-Bit - non-prefetchable */ + <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>, + /* 64-Bit - prefetchable - 16GB */ + <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>; + + interrupts = ; + interrupt-names = "intr"; + msi-parent = <&its 0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + pcie_ep6: pcie-ep@3900000 { compatible = "fsl,lx2160ar2-pcie-ep"; reg = <0x00 0x03900000 0x0 0x00100000 From bc12e3ee01c82f2da45c6240b74f501b82732b27 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:30 +0300 Subject: [PATCH 610/864] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes instance is present in the compatible string, to allow reliable per-lane capability detection and per-lane customization of electrical properties. The modern bindings are backward-incompatible with old kernels, due to the consumer phandles being either in one form or in another, as explained here: https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/ Also mark the serdes_1 node as disabled by default since any dts using it enables it explicitly now. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2160a-serdes.dtsi | 150 +++++++++++++++++- 1 file changed, 148 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi index 307824eda6d6..d482920f4d17 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-serdes.dtsi @@ -6,16 +6,162 @@ // Copyright 2026 NXP &soc { + /* Note on the interpretation of SerDes lane numbering from + * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]: + * The letters (A-H) correspond to logical lane numbers in the + * SerDes register map (lane A's registers start with LNAGCR0), + * while the numbers (0-7) correspond to physical lanes as + * routed to pins. SerDes block #1 is flipped in the LX2160A + * floorplan (logical lane A goes to physical lane 7's pins), + * while SerDes blocks #2 and #3 are not. The lanes below are + * listed right to left when looking at that table. + * Both the numbers and the letters are according to the logical + * numbering scheme, and do not account for the flipping. + */ serdes_1: phy@1ea0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g"; reg = <0x0 0x1ea0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; + status = "disabled"; + + serdes_1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; serdes_2: phy@1eb0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g"; reg = <0x0 0x1eb0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; status = "disabled"; + + serdes_2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_2_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_2_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_2_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_2_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + + serdes_3: phy@1ec0000 { + compatible = "fsl,lx2160a-serdes3"; + reg = <0x0 0x1ec0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes_3_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_3_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_3_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_3_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_3_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_3_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_3_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_3_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; }; From 21cb12ad026e91aca65329531554ec1e74a32e77 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:31 +0300 Subject: [PATCH 611/864] arm64: dts: lx2162a: transition to device-specific SerDes compatible strings Align to the modern fsl,lynx-28g.yaml binding for the LX2162A SoC, where the SoC and SerDes instance is present in the compatible string, to allow reliable per-lane capability detection and per-lane customization of electrical properties. Since one of the major differences between LX2162A and LX2160A is the SerDes, add the necessary nodes to its own fsl-lx2162a-serdes.dtsi file. Also mark the serdes_1 node as disabled by default since any dts using it enables it explicitly now. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../dts/freescale/fsl-lx2162a-serdes.dtsi | 69 ++++++++++++++++++- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi index 23f05a138eac..1ab18f0c67c2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-serdes.dtsi @@ -7,15 +7,80 @@ &soc { serdes_1: phy@1ea0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g"; reg = <0x0 0x1ea0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; + status = "disabled"; + + serdes_1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; serdes_2: phy@1eb0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g"; reg = <0x0 0x1eb0000 0x0 0x1e30>; + #address-cells = <1>; + #size-cells = <0>; #phy-cells = <1>; status = "disabled"; + + serdes_2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes_2_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes_2_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes_2_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes_2_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; }; }; From 2b64e802a7c8a577616289b023a98e009318123d Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:32 +0300 Subject: [PATCH 612/864] arm64: dts: ls1028a: describe the Lynx 10G SerDes Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the LS1028A SoC. The node is left disabled at the SoC level; board DTs will be expected to enable it once the consumer Ethernet nodes use it. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index f4ba3d16ab86..ef62968590fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c { }; }; + serdes: phy@1ea0000 { + compatible = "fsl,ls1028a-serdes"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + scfg: syscon@1fc0000 { compatible = "fsl,ls1028a-scfg", "syscon"; reg = <0x0 0x1fc0000 0x0 0x10000>; From 65121d706ecd9c7b1365f91cc9f4e3c01fd9f15b Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:33 +0300 Subject: [PATCH 613/864] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1046A SoC. The nodes are left disabled at the SoC level; board DTs will be expected to enable them once the consumer Ethernet nodes appear. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 6fefe837f434..270a97711a69 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -424,6 +424,66 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls1046a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls1046a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + big-endian; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + dcfg: dcfg@1ee0000 { compatible = "fsl,ls1046a-dcfg", "syscon"; reg = <0x0 0x1ee0000 0x0 0x1000>; From 9eb4d238348fb1b81cc25ec3c50c13b85b6055d1 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Jul 2026 15:06:34 +0300 Subject: [PATCH 614/864] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS208xA SoC. The nodes are left disabled at the SoC level; board DTs will enable them once there are consumers. Signed-off-by: Vladimir Oltean Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 6073e426774a..cc1a64e63ed5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -280,6 +280,104 @@ sfp: efuse@1e80000 { clock-names = "sfp"; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls2088a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes1_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes1_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes1_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes1_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls2088a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + + serdes2_lane_e: phy@4 { + reg = <4>; + #phy-cells = <0>; + }; + + serdes2_lane_f: phy@5 { + reg = <5>; + #phy-cells = <0>; + }; + + serdes2_lane_g: phy@6 { + reg = <6>; + #phy-cells = <0>; + }; + + serdes2_lane_h: phy@7 { + reg = <7>; + #phy-cells = <0>; + }; + }; + isc: syscon@1f70000 { compatible = "fsl,ls2080a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; From c482d6c37187fe38662f278213301b7828cda662 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 17 Jul 2026 15:06:35 +0300 Subject: [PATCH 615/864] arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks Describe the two Lynx 10G SerDes blocks and their associated lanes found on the LS1088A SoC. The nodes are left disabled at the SoC level; board DTs will enable them once there are consumers. Note that the SerDes block #2 is non-networking, meaning that it will not get probed by the Lynx10G SerDes PHY driver and it's only added for a complete hardware description. Signed-off-by: Ioana Ciornei Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 99016768b73f..e02f34329988 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -239,6 +239,64 @@ reset: syscon@1e60000 { reg = <0x0 0x1e60000 0x0 0x10000>; }; + serdes1: phy@1ea0000 { + compatible = "fsl,ls1088a-serdes1"; + reg = <0x00 0x1ea0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes1_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes1_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes1_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes1_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + + serdes2: phy@1eb0000 { + compatible = "fsl,ls1088a-serdes2"; + reg = <0x00 0x1eb0000 0x0 0x2000>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + serdes2_lane_a: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + serdes2_lane_b: phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + serdes2_lane_c: phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + serdes2_lane_d: phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + isc: syscon@1f70000 { compatible = "fsl,ls1088a-isc", "syscon"; reg = <0x0 0x1f70000 0x0 0x10000>; From 853d77cc0c06e686d0214a015fe88c1047ba6302 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 21 Jul 2026 09:12:41 -0700 Subject: [PATCH 616/864] arm64: dts: s32g: Add GPR syscon region Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter [jkangas@redhat.com: GPR syscon resized from 0x3000 to 0x100] Signed-off-by: Jared Kangas Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 8dc0c5d9f368..996494e34593 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -122,6 +122,11 @@ rtc0: rtc@40060000 { clock-names = "ipg", "source0"; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g2-gpr", "syscon"; + reg = <0x4007c000 0x100>; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -814,6 +819,7 @@ gmac0: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 24fa3057e929..31f7aad00b76 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -180,6 +180,11 @@ rtc0: rtc@40060000 { clock-names = "ipg", "source0"; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g3-gpr", "syscon"; + reg = <0x4007c000 0x100>; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -893,6 +898,7 @@ gmac0: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; From e1e3f7582bb87e849bd3e4101696992878529340 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:09 +0800 Subject: [PATCH 617/864] arm64: dts: imx8ulp: Add DMA channel properties and use eDMA flag macros Add DMA channel (dmas/dma-names) properties to peripheral nodes that were missing them: - LPI2C: lpi2c4, lpi2c5, lpi2c6, lpi2c7 - LPUART: lpuart4, lpuart5, lpuart6, lpuart7 - LPSPI: lpspi4, lpspi5 Also replace hardcoded numeric DMA direction flags with the proper FSL_EDMA_RX and FSL_EDMA_MULTI_FIFO macros for SAI (sai4, sai5, sai6, sai7) and SPDIF nodes. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 32 ++++++++++++++++++---- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c6d1bb9edf38..1ab4ab270dc2 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -370,6 +371,8 @@ lpi2c4: i2c@29370000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 46 0 0>, <&edma1 45 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -383,6 +386,8 @@ lpi2c5: i2c@29380000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 48 0 0>, <&edma1 47 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -392,6 +397,8 @@ lpuart4: serial@29390000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; clock-names = "ipg"; + dmas = <&edma1 55 0 FSL_EDMA_RX>, <&edma1 56 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -401,6 +408,8 @@ lpuart5: serial@293a0000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; + dmas = <&edma1 57 0 FSL_EDMA_RX>, <&edma1 58 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -416,6 +425,8 @@ lpspi4: spi@293b0000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 64 0 0>, <&edma1 63 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -431,6 +442,8 @@ lpspi5: spi@293c0000 { assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 66 0 0>, <&edma1 65 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; }; @@ -474,6 +487,8 @@ lpi2c6: i2c@29840000 { assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 50 0 0>, <&edma1 49 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -487,6 +502,8 @@ lpi2c7: i2c@29850000 { assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; assigned-clock-rates = <48000000>; + dmas = <&edma1 52 0 0>, <&edma1 51 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -496,6 +513,8 @@ lpuart6: serial@29860000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; clock-names = "ipg"; + dmas = <&edma1 59 0 FSL_EDMA_RX>, <&edma1 60 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -505,6 +524,8 @@ lpuart7: serial@29870000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; clock-names = "ipg"; + dmas = <&edma1 61 0 FSL_EDMA_RX>, <&edma1 62 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -516,7 +537,7 @@ sai4: sai@29880000 { <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 67 0 1>, <&edma1 68 0 0>; + dmas = <&edma1 67 0 FSL_EDMA_RX>, <&edma1 68 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x03 0x03>; @@ -531,7 +552,7 @@ sai5: sai@29890000 { <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma1 69 0 1>, <&edma1 70 0 0>; + dmas = <&edma1 69 0 FSL_EDMA_RX>, <&edma1 70 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x0f 0x0f>; @@ -814,7 +835,7 @@ sai6: sai@2da90000 { <&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 71 0 1>, <&edma2 72 0 0>; + dmas = <&edma2 71 0 FSL_EDMA_RX>, <&edma2 72 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x0f 0x0f>; @@ -829,7 +850,7 @@ sai7: sai@2daa0000 { <&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>, <&cgc1 IMX8ULP_CLK_DUMMY>; clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dmas = <&edma2 73 0 1>, <&edma2 74 0 0>; + dmas = <&edma2 73 0 FSL_EDMA_RX>, <&edma2 74 0 0>; dma-names = "rx", "tx"; #sound-dai-cells = <0>; fsl,dataline = <0 0x0f 0x0f>; @@ -855,7 +876,8 @@ spdif: spdif@2dab0000 { "rxtx3", "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba"; - dmas = <&edma2 75 0 5>, <&edma2 76 0 4>; + dmas = <&edma2 75 0 (FSL_EDMA_RX | FSL_EDMA_MULTI_FIFO)>, + <&edma2 76 0 FSL_EDMA_MULTI_FIFO>; dma-names = "rx", "tx"; status = "disabled"; }; From 5f3301712f42c89df861d26518121d1deefca96c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:10 +0800 Subject: [PATCH 618/864] arm64: dts: imx8ulp: Add I3C2 controller node Add the I3C2 (i3c-master@29360000) node to the imx8ulp device tree using the Silvaco I3C master IP. Configure PCC3-gated clock with SOSC DIV2 as parent at 24 MHz for pclk and fast_clk. slow_clk uses a dummy clock. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 1ab4ab270dc2..cb0d73327d86 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -361,6 +361,22 @@ tpm5: tpm@29340000 { status = "disabled"; }; + i3c2: i3c@29360000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x29360000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&pcc3 IMX8ULP_CLK_I3C2>, + <&pcc3 IMX8ULP_CLK_I3C2>, + <&cgc1 IMX8ULP_CLK_DUMMY>; + clock-names = "pclk", "fast_clk", "slow_clk"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; + status = "disabled"; + }; + lpi2c4: i2c@29370000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29370000 0x10000>; From 92ccf83b8d58f9dca5752a824f0e81ac54665889 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:11 +0800 Subject: [PATCH 619/864] arm64: dts: imx8ulp: Correct SRAM node address and size to cover full SSRAM P2 The SSRAM P2 partition starts at 0x22010000 with a size of 64 KB. The previous node only mapped the last 4 KB (0x2201f000, 0x1000) which was used for the SCMI shared memory buffer. Update the base address and size to cover the full P2 region so it can also serve as a general purpose SRAM pool. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index cb0d73327d86..7d00fe836094 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -154,17 +154,17 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@2201f000 { + sram@22010000 { compatible = "mmio-sram"; - reg = <0x0 0x2201f000 0x0 0x1000>; + reg = <0x0 0x22010000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0 0x0 0x2201f000 0x1000>; + ranges = <0 0x0 0x22010000 0x10000>; - scmi_buf: scmi-sram-section@0 { + scmi_buf: scmi-sram-section@f000 { compatible = "arm,scmi-shmem"; - reg = <0x0 0x400>; + reg = <0xf000 0x400>; }; }; From c89839764bf17b76d6f53d5923a28bda140a46cc Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:12 +0800 Subject: [PATCH 620/864] arm64: dts: imx8ulp: Add assigned clock properties for LPUART nodes Add assigned-clocks, assigned-clock-parents and assigned-clock-rates properties to lpuart4 through lpuart7, so the LPUART input clock is configured automatically by the clock framework during probe. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 7d00fe836094..777b89ed6849 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -413,6 +413,9 @@ lpuart4: serial@29390000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART4>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; dmas = <&edma1 55 0 FSL_EDMA_RX>, <&edma1 56 0 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -424,6 +427,9 @@ lpuart5: serial@293a0000 { interrupts = ; clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; clock-names = "ipg"; + assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>; + assigned-clock-rates = <24000000>; dmas = <&edma1 57 0 FSL_EDMA_RX>, <&edma1 58 0 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -529,6 +535,9 @@ lpuart6: serial@29860000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; clock-names = "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART6>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; dmas = <&edma1 59 0 FSL_EDMA_RX>, <&edma1 60 0 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -540,6 +549,9 @@ lpuart7: serial@29870000 { interrupts = ; clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; clock-names = "ipg"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART7>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>; + assigned-clock-rates = <48000000>; dmas = <&edma1 61 0 FSL_EDMA_RX>, <&edma1 62 0 0>; dma-names = "rx", "tx"; status = "disabled"; From 011242de59d0eb69e7b8a4f42dc32cf1f5d53592 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:13 +0800 Subject: [PATCH 621/864] arm64: dts: imx8ulp-evk: Add gpio-keys node for power button Add a gpio-keys node for the power-on button, report it as KEY_POWER to user space. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 18 ++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 19 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index 5497e3d78136..af8f0d6087f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -10,6 +10,18 @@ / { model = "NXP i.MX8ULP EVK9"; compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-power-on { + label = "PowerOn"; + gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; }; &btcpu { @@ -43,6 +55,12 @@ MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 >; }; +&pinctrl_gpio_keys { + fsl,pins = < + MX8ULP_PAD_PTF11__PTF11 0x3 + >; +}; + &pinctrl_usb1 { fsl,pins = < MX8ULP_PAD_PTE16__USB0_ID 0x10003 diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 5dea66c1e7aa..6a92c5ca9a41 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8ulp.dtsi" / { @@ -20,6 +21,18 @@ chosen { stdout-path = &lpuart5; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-power-on { + label = "PowerOn"; + gpios = <&gpiof 31 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0 0x80000000>; @@ -323,6 +336,12 @@ MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 >; }; + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8ULP_PAD_PTF31__PTF31 0x3 + >; + }; + pinctrl_lpuart5: lpuart5grp { fsl,pins = < MX8ULP_PAD_PTF14__LPUART5_TX 0x3 From fdcdcb8dd47e829f5bdb4e52ecce210e845ef4f7 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 20 Jul 2026 22:12:14 +0800 Subject: [PATCH 622/864] arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth Enable lpuart6 with RTS/CTS flow control on the i.MX 8ULP EVK board and add an NXP 88W8987 Bluetooth companion node to pair the UART transport with the wireless chip. i.MX8ULP 9X9 EVK use different lpuart6 pins which used for M.2 bluetooth, also use the sai6 instead of sai5 for PCM interface on M.2, so need to update the pin setting in dts. Signed-off-by: Sherry Sun Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8ulp-9x9-evk.dts | 17 ++++++++++++++++ arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 20 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index af8f0d6087f7..71c66c58edc4 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -75,6 +75,23 @@ MX8ULP_PAD_PTE20__USB1_OC 0x10003 >; }; +&pinctrl_lpuart6 { + fsl,pins = < + MX8ULP_PAD_PTF18__LPUART6_TX 0x3 + MX8ULP_PAD_PTF19__LPUART6_RX 0x3 + MX8ULP_PAD_PTF16__LPUART6_CTS_B 0x3 + MX8ULP_PAD_PTF17__LPUART6_RTS_B 0x3 + >; +}; + +&lpspi5 { /* conflict with lpuart6 PAD_PTF16-19 */ + status = "disabled"; +}; + +&sai5 { + status = "disabled"; +}; + &sai6 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_sai6>; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 6a92c5ca9a41..84c61656f3f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -167,6 +167,17 @@ &lpuart5 { status = "okay"; }; +&lpuart6 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart6>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &lpi2c7 { #address-cells = <1>; #size-cells = <0>; @@ -349,6 +360,15 @@ MX8ULP_PAD_PTF15__LPUART5_RX 0x3 >; }; + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + MX8ULP_PAD_PTE10__LPUART6_TX 0x3 + MX8ULP_PAD_PTE11__LPUART6_RX 0x3 + MX8ULP_PAD_PTE9__LPUART6_RTS_B 0x3 + MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3 + >; + }; + pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 From 35bdffecf91b8f31a526116d488022fa0f5e09ad Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 20 Jul 2026 22:12:15 +0800 Subject: [PATCH 623/864] arm64: dts: imx8ulp-evk: Enable LPUART7 The i.MX 8ULP EVK proto1B revision routes LPUART7 TX/RX to the FT4232 PortD connector (J25/J26 pins 2-3). Enable the port by default so the additional serial console is available out of the box. Signed-off-by: Sherry Sun Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 84c61656f3f2..9da54291c753 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -178,6 +178,13 @@ bluetooth { }; }; +&lpuart7 { + /* FT4232 PortD: need to connect J25/J26 2-3 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; + status = "okay"; +}; + &lpi2c7 { #address-cells = <1>; #size-cells = <0>; @@ -369,6 +376,13 @@ MX8ULP_PAD_PTE8__LPUART6_CTS_B 0x3 >; }; + pinctrl_lpuart7: lpuart7grp { + fsl,pins = < + MX8ULP_PAD_PTF22__LPUART7_TX 0x3 + MX8ULP_PAD_PTF23__LPUART7_RX 0x3 + >; + }; + pinctrl_lpi2c7: lpi2c7grp { fsl,pins = < MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 From 7108abc25f3b6f97e3098650924816ccdbc06367 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Mon, 20 Jul 2026 22:12:16 +0800 Subject: [PATCH 624/864] arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET Change to use standard drive strength and slow slew rate on PTE14-17, 22, 23, otherwise the overshoot of ENET is too high. Signed-off-by: Wei Fang Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 9da54291c753..22c1d542798d 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -323,15 +323,15 @@ &mu { &iomuxc1 { pinctrl_enet: enetgrp { fsl,pins = < - MX8ULP_PAD_PTE15__ENET0_MDC 0x43 - MX8ULP_PAD_PTE14__ENET0_MDIO 0x43 - MX8ULP_PAD_PTE17__ENET0_RXER 0x43 + MX8ULP_PAD_PTE15__ENET0_MDC 0x7 + MX8ULP_PAD_PTE14__ENET0_MDIO 0x7 + MX8ULP_PAD_PTE17__ENET0_RXER 0x7 MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43 MX8ULP_PAD_PTF1__ENET0_RXD0 0x43 MX8ULP_PAD_PTE20__ENET0_RXD1 0x43 - MX8ULP_PAD_PTE16__ENET0_TXEN 0x43 - MX8ULP_PAD_PTE23__ENET0_TXD0 0x43 - MX8ULP_PAD_PTE22__ENET0_TXD1 0x43 + MX8ULP_PAD_PTE16__ENET0_TXEN 0x7 + MX8ULP_PAD_PTE23__ENET0_TXD0 0x7 + MX8ULP_PAD_PTE22__ENET0_TXD1 0x7 MX8ULP_PAD_PTE19__ENET0_REFCLK 0x43 MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43 >; From c4e8b643c83d4abfbd92e7161b4975f670eff0a6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 20 Jul 2026 22:12:17 +0800 Subject: [PATCH 625/864] arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size Rename the board model from "NXP i.MX8ULP EVK9" to "NXP i.MX8ULP 9x9 EVK" to follow the i.MX naming convention where the die size (9x9 mm) is used instead of an opaque board revision suffix. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts index 71c66c58edc4..e6bc6e6555f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts @@ -8,7 +8,7 @@ #include "imx8ulp-evk.dts" / { - model = "NXP i.MX8ULP EVK9"; + model = "NXP i.MX8ULP 9x9 EVK"; compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp"; gpio-keys { From 3c45ac08d2897aeb95ceecde25a6d4935c4ab8be Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Wed, 22 Jul 2026 13:33:05 +0200 Subject: [PATCH 626/864] arm64: dts: imx8qm-var-som-symphony: enable expansion header UART Enable LPUART4 and configure its pin multiplexing to expose the UART interface on the Symphony expansion header. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8qm-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts index c7d3073b4041..ec55b86c220d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-var-som-symphony.dts @@ -287,6 +287,13 @@ &lpuart2 { status = "okay"; }; +/* header */ +&lpuart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + &pca9534 { usb3-signal-route-hog { gpio-hog; @@ -428,6 +435,13 @@ IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 >; }; + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX8QM_M40_GPIO0_01_DMA_UART4_TX 0x06000020 + IMX8QM_M40_GPIO0_00_DMA_UART4_RX 0x06000020 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x00000021 From db8398bb31d740e621e3309e929a06adbc664f2f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 24 Jul 2026 14:17:55 +0800 Subject: [PATCH 627/864] arm64: dts: imx95-19x19-evk: Add CM7 node and related memory nodes Add remoteproc CM7 node and reserved memory regions to enable the Cortex-M7 remote processor. The reserved memory includes firmware memory, virtio device vring buffers, a resource table and a shared DMA pool for inter-processor communication via the MU7 mailbox. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- .../boot/dts/freescale/imx95-19x19-evk.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts index 340ab0253ec2..814da90243b2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts @@ -76,6 +76,42 @@ linux_cma: linux,cma { linux,cma-default; reusable; }; + + m7_reserved: memory@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; }; flexcan1_phy: can-phy0 { @@ -185,6 +221,16 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,name = "bt-sco-audio"; From 7d1f4e4f62a1b076fb91b708a2dc74432827c3d7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 24 Jul 2026 14:17:56 +0800 Subject: [PATCH 628/864] arm64: dts: imx952-evk: Add CM7 node and related memory nodes Add remoteproc CM7 node and reserved memory regions to enable the Cortex-M7 remote processor. The reserved memory includes firmware memory, virtio device vring buffers and a resource table for inter-processor communication via the MU7 mailbox. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 50 ++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 62d1c1c7c501..2224b90aafe9 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -82,6 +82,42 @@ linux_cma: linux,cma { linux,cma-default; reusable; }; + + m7_reserved: memory@80000000 { + no-map; + reg = <0 0x80000000 0 0x1000000>; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdev0buffer: vdev0buffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; }; flexcan1_phy: can-phy0 { @@ -151,6 +187,16 @@ reg_usb_vbus: regulator-vbus { enable-active-high; }; + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu7 0 1 + &mu7 1 1 + &mu7 3 1>; + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,bitclock-inversion; @@ -451,6 +497,10 @@ &micfil { status = "okay"; }; +&mu7 { + status = "okay"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, From 89d93ad8afedfcbc8281d07f68b18829325d73ab Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 24 Jul 2026 14:17:57 +0800 Subject: [PATCH 629/864] arm64: dts: imx943-evk: Add CM7 and CM33S nodes Add remoteproc nodes for the two Cortex-M7 cores (CM7-0, CM7-1) and the Cortex-M33S core, along with their respective reserved memory regions for firmware, virtio device vrings, resource tables and shared DMA pools. Enable the MU11, MU13 and MU15 mailbox units used for inter-processor communication with each remote processor. Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 135 +++++++++++++++++++ 1 file changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 49fb1744d992..64660f94f4e9 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -133,6 +133,36 @@ reg_audio_pwr: regulator-wm8962-pwr { enable-active-high; }; + remoteproc-cm70 { + compatible = "fsl,imx94-cm70"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu11 0 1 + &mu11 1 1 + &mu11 3 1>; + memory-region = <&cm70_vdev0buffer>, <&cm70_vdev0vring0>, <&cm70_vdev0vring1>, + <&cm70_vdev1vring0>, <&cm70_vdev1vring1>, <&cm70_rsc_table>; + }; + + remoteproc-cm71 { + compatible = "fsl,imx94-cm71"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu13 0 1 + &mu13 1 1 + &mu13 3 1>; + memory-region = <&cm71_vdev0buffer>, <&cm71_vdev0vring0>, <&cm71_vdev0vring1>, + <&cm71_vdev1vring0>, <&cm71_vdev1vring1>, <&cm71_rsc_table>; + }; + + remoteproc-cm33s { + compatible = "fsl,imx94-cm33s"; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu15 0 1 + &mu15 1 1 + &mu15 3 1>; + memory-region = <&cm33s_vdev0buffer>, <&cm33s_vdev0vring0>, <&cm33s_vdev0vring1>, + <&cm33s_vdev1vring0>, <&cm33s_vdev1vring1>, <&cm33s_rsc_table>; + }; + reserved-memory { ranges; #address-cells = <2>; @@ -145,6 +175,99 @@ linux,cma { size = <0 0x10000000>; linux,cma-default; }; + + cm33s_vdev0vring0: vdev0vring0@20800000 { + reg = <0 0x20800000 0 0x8000>; + no-map; + }; + + cm33s_vdev0vring1: vdev0vring1@20808000 { + reg = <0 0x20808000 0 0x8000>; + no-map; + }; + + cm33s_vdev1vring0: vdev1vring0@20810000 { + reg = <0 0x20810000 0 0x8000>; + no-map; + }; + + cm33s_vdev1vring1: vdev1vring1@20818000 { + reg = <0 0x20818000 0 0x8000>; + no-map; + }; + + cm33s_rsc_table: rsc-table@208a0000 { + reg = <0 0x208a0000 0 0x1000>; + no-map; + }; + + cm33s_vdev0buffer: vdev0buffer@20820000 { + compatible = "shared-dma-pool"; + reg = <0 0x20820000 0 0x80000>; + no-map; + }; + + cm70_vdev0vring0: vdev0vring0@82000000 { + reg = <0 0x82000000 0 0x8000>; + no-map; + }; + + cm70_vdev0vring1: vdev0vring1@82008000 { + reg = <0 0x82008000 0 0x8000>; + no-map; + }; + + cm70_vdev1vring0: vdev1vring0@82010000 { + reg = <0 0x82010000 0 0x8000>; + no-map; + }; + + cm70_vdev1vring1: vdev1vring1@82018000 { + reg = <0 0x82018000 0 0x8000>; + no-map; + }; + + cm70_rsc_table: rsc-table@82220000 { + reg = <0 0x82220000 0 0x1000>; + no-map; + }; + + cm70_vdev0buffer: vdev0buffer@82020000 { + compatible = "shared-dma-pool"; + reg = <0 0x82020000 0 0x100000>; + no-map; + }; + + cm71_vdev0vring0: vdev0vring0@84000000 { + reg = <0 0x84000000 0 0x8000>; + no-map; + }; + + cm71_vdev0vring1: vdev0vring1@84008000 { + reg = <0 0x84008000 0 0x8000>; + no-map; + }; + + cm71_vdev1vring0: vdev1vring0@84010000 { + reg = <0 0x84010000 0 0x8000>; + no-map; + }; + + cm71_vdev1vring1: vdev1vring1@84018000 { + reg = <0 0x84018000 0 0x8000>; + no-map; + }; + + cm71_rsc_table: rsc-table@84220000 { + reg = <0 0x84220000 0 0x1000>; + no-map; + }; + + cm71_vdev0buffer: vdev0buffer@84020000 { + compatible = "shared-dma-pool"; + reg = <0 0x84020000 0 0x100000>; + no-map; + }; }; sound-bt-sco { @@ -592,6 +715,18 @@ &micfil { status = "okay"; }; +&mu11 { + status = "okay"; +}; + +&mu13 { + status = "okay"; +}; + +&mu15 { + status = "okay"; +}; + &netc_blk_ctrl { assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>, <&scmi_clk IMX94_CLK_MAC5>; From d93dce11f39aaf5c2b246e68f20d47b92e99d331 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Fri, 24 Jul 2026 14:17:58 +0800 Subject: [PATCH 630/864] arm64: dts: imx8ulp-evk: Update rpmsg resource table address The MCU firmware copies the rsc table to a fixed address (0x1FFF8000) at startup. However, this address is occupied by variables used in the MCU firmware, so copying the rsc table there corrupts those variables. Move the rsc-table reserved memory region from 0x1FFF8000 to 0x20000000 to avoid the conflict. The M33 firmware linker script has been updated accordingly to place the rpmsg resource table at 0x20000000 (DTCM m_rsc_tbl region). Signed-off-by: Biwen Li Signed-off-by: Peng Fan Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index 22c1d542798d..4b925832bb66 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -55,8 +55,8 @@ m33_reserved: noncacheable-section@a8600000 { no-map; }; - rsc_table: rsc-table@1fff8000 { - reg = <0 0x1fff8000 0 0x1000>; + rsc_table: rsc-table@20000000 { + reg = <0 0x20000000 0 0x1000>; no-map; }; From fc913a5ad811395be4daf2ca6fed8bcd9653916b Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 21 Jul 2026 22:59:01 -0700 Subject: [PATCH 631/864] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR The TCSR clkref_en clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Link: https://lore.kernel.org/r/20260721-tcsr_qre_0721-v10-6-d2fa68c63b78@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 6125617de82a..44766a73b0d1 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -28,3 +28,23 @@ &mdss_dp1 { &mdss_dp1_out { link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0_0p72>; + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0_0p72>; + vdda-qreftx0-1p2-supply = <&vreg_l4h_e0_1p2>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply = <&vreg_l2f_e0_0p82>; + vdda-refgen3-1p2-supply = <&vreg_l4h_e0_1p2>; + vdda-refgen4-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen4-1p2-supply = <&vreg_l4f_e1_1p08>; +}; From 2947778fbc2e4cdf9b2f67f11854ebfa25194769 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Tue, 21 Jul 2026 22:59:02 -0700 Subject: [PATCH 632/864] arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR Mahua has a different QREF topology from Glymur. Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu Link: https://lore.kernel.org/r/20260721-tcsr_qre_0721-v10-7-d2fa68c63b78@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 13 +++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts index 9c8244e892dd..fa5229064b10 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -19,3 +19,19 @@ / { model = "Qualcomm Technologies, Inc. Mahua CRD"; compatible = "qcom,mahua-crd", "qcom,mahua"; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrpt5-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx3-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-1p2-supply = <&vreg_l4f_e1_1p08>; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi index 22822b6b2e8b..e6c059708912 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -115,6 +115,15 @@ &oobm_ss_noc { compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; +&pcie5_phy { + clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; +}; + &pcie_east_anoc { compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; }; @@ -286,6 +295,10 @@ gpuss-4-critical { }; }; +&tcsr { + compatible = "qcom,mahua-tcsr", "syscon"; +}; + &tlmm { compatible = "qcom,mahua-tlmm"; }; From 95870e5eb88c6efa252de89bd8dd360f1150b388 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 24 Jul 2026 21:30:04 +0200 Subject: [PATCH 633/864] arm64: dts: imx95-var-dart-sonata: enable in-band status for SFP The 10GBASE-R port is connected to an SFP cage and requires in-band status handling for link state reporting. Set managed to "in-band-status" so phylink can manage the SFP link through the PCS. Signed-off-by: Stefano Radaelli Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts index ccf7e77016e4..3479abc25df2 100644 --- a/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx95-var-dart-sonata.dts @@ -157,6 +157,7 @@ &enetc_port1 { }; &enetc_port2 { + managed = "in-band-status"; phy-mode = "10gbase-r"; sfp = <&sfp0>; status = "okay"; From 0a0ed37b68ff9e09025f9f5ed780e6b8b343302b Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:27 +0200 Subject: [PATCH 634/864] arm64: dts: freescale: imx8mm-verdin: Add NAU8822 Bridge Tied Load Add a device tree overlay for configuring the NAU8822 loudspeaker outputs as a Bridge Tied Load (BTL) output on the Verdin Development Board. The overlay adds the codec property for the BTL-capable output configuration, where the two loudspeaker outputs are combined for higher output power. Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 ++++ .../freescale/imx8mm-verdin-dev-nau8822-btl.dtso | 14 ++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index d5c2dc720197..dcc0464b4e80 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -177,6 +177,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb @@ -184,12 +185,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb +imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo + imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso new file mode 100644 index 000000000000..e4b662519a6b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev-nau8822-btl.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Enable Bridge Tied Load (BTL) speaker mode on the Verdin Development Board, + * combining the two loudspeaker outputs for higher output power. + */ + +/dts-v1/; +/plugin/; + +&nau8822_1a { + nuvoton,spk-btl; +}; From 70b923a721c9364e43967a9a0e7b37c52bc57ec7 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:28 +0200 Subject: [PATCH 635/864] arm64: dts: freescale: imx8mm-verdin: Add DSI to HDMI adapter overlay Add a device tree overlay for the Toradex DSI to HDMI Adapter, an accessory that connects to the Verdin DSI_1 interface and provides a full-size HDMI Type-A output. The adapter is based on the Lontium LT8912B DSI-to-HDMI bridge. The overlay is also combined with the Verdin iMX8M Mini carrier board device trees to provide ready-to-use DTBs for the Dahlia, Yavia and Development Board carriers, in both WiFi and non-WiFi SoM variants. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 13 +++ .../freescale/imx8mm-verdin-dsi-to-hdmi.dtso | 88 +++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index dcc0464b4e80..f55c570cb3e3 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -178,21 +178,34 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb +imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo +imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso new file mode 100644 index 000000000000..507d0bbb5935 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-hdmi.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to HDMI Adapter on Verdin DSI_1. + * + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-hdmi-adapter + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + reg_dsi_hdmi: regulator-dsi-hdmi { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "DSI_1_PWR_EN"; + }; +}; + +&hdmi_connector { + status = "okay"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&dsi_hdmi_bridge_out>; + }; + }; +}; + +&hdmi_lontium_lt8912 { + vdd-supply = <®_dsi_hdmi>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_hdmi_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + dsi_hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_hdmi_bridge_in>; +}; + +/* Verdin PWM_3_DSI (SODIMM 19) repurposed as HDMI HPD GPIO */ +&pwm1 { + status = "disabled"; +}; From e23768eba9badb72bf335e77cdfdc4eb73174bbc Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:29 +0200 Subject: [PATCH 636/864] arm64: dts: freescale: imx8mm-verdin: Add Toradex DSI to LVDS adapter with 10.1" display Add a device tree overlay for the Toradex DSI to LVDS Adapter with the Toradex Capacitive Touch Display 10.1" LVDS. The adapter connects to the Verdin DSI_1 interface. It is based on the Texas Instruments SN65DSI84 DSI-to-LVDS bridge and drives a LogicTechno LT170410-2WHC 10.1" WXGA IPS LCD panel. Touch input is provided by an Atmel maXTouch capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + ...in-dsi-to-lvds-panel-cap-touch-10inch.dtso | 104 ++++++++++++++++++ 2 files changed, 108 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f55c570cb3e3..91ae54931818 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -179,6 +179,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb @@ -191,6 +192,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb @@ -204,6 +206,8 @@ imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8 imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \ + imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso new file mode 100644 index 000000000000..2c253018893b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtso @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex DSI to LVDS Adapter on Verdin DSI_1 with Capacitive Touch Display + * 10.1". Used on Dahlia (X17) and Development Board (X48) that expose DSI_1 + * via a Samtec LSS-130 connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-lvds + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-lvds + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-lvds-adapter + * https://www.toradex.com/accessories/verdin-dsi-to-lvds-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT (SODIMM 46) - DSI_1_BKL_EN_LVDS */ + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI (SODIMM 19) - PWM_3_DSI_LVDS */ + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + }; + + panel-lvds-bridge { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight_pwm3>; + power-supply = <®_dsi_lvds>; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; + + reg_dsi_lvds: regulator-dsi-lvds { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-name = "DSI_1_PWR_EN"; + }; +}; + +&atmel_mxt_ts { + vdd-supply = <®_dsi_lvds>; + + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&lvds_ti_sn65dsi84 { + vcc-supply = <®_dsi_lvds>; + + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_lvds_bridge_in>; +}; From 16790c0bdb2b20f8ab0286f74a617839cfa81e29 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:30 +0200 Subject: [PATCH 637/864] arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 10.1" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 10.1" on the Verdin DSI_1 interface. The display features an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT101HVLNWC00 10.1" WXGA IPS TFT LCD panel. The touch input is provided by an Ilitek ILI2132 capacitive touch controller. The overlay is also combined with the Verdin iMX8M Mini Dahlia carrier board device trees to provide ready-to-use DTBs in both WiFi and non-WiFi SoM variants. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 7 + ...8mm-verdin-panel-cap-touch-10inch-dsi.dtso | 129 ++++++++++++++++++ 2 files changed, 136 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 91ae54931818..00dc2893c754 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dev-nau8822-btl.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-hdmi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb @@ -189,7 +190,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb @@ -202,9 +205,13 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-zinnia.dtb imx8mm-verdin-nonwifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-nonwifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := imx8mm-verdin-nonwifi-dahlia.dtb \ + imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo imx8mm-verdin-nonwifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-nonwifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dahlia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dahlia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo +imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi-dtbs := imx8mm-verdin-wifi-dahlia.dtb \ + imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \ imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso new file mode 100644 index 000000000000..5626903d668a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-10inch-dsi.dtso @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 10.1" on Verdin DSI_1. + * On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a + * Samtec LSS-130 connector and requires the Toradex DSI Display Adapter + * to convert to FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-101inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-10.1-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + pwms = <&pwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt101hvlnwc00", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <136>; + width-mm = <217>; + + panel-timing { + clock-frequency = <71100000>; + de-active = <1>; + hactive = <1280>; + hback-porch = <64 64 64>; + hfront-porch = <36 36 36>; + hsync-active = <0>; + hsync-len = <24 24 24>; + pixelclk-active = <1>; + vactive = <800>; + vback-porch = <24 24 24>; + vfront-porch = <8 8 8>; + vsync-active = <0>; + vsync-len = <8 8 8>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_1p8v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + /* Rising edge avoids spurious interrupts from the noisy falling edge. */ + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_lvds_bridge_in>; +}; From 4bf5b8862fae3865069b34bdde2492e3e49f1810 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:31 +0200 Subject: [PATCH 638/864] arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 7" DSI Add a device tree overlay for the Toradex Capacitive Touch Display 7" on the Verdin DSI_1 interface. The display features an internal Texas Instruments SN65DSI83 DSI-to-LVDS bridge driving a Riverdi RVT70HSLNWCA0 7" WSVGA IPS TFT LCD panel. The touch input is provided by an Ilitek ILI2132 capacitive touch controller. Link: https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi Link: https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 4 + ...x8mm-verdin-panel-cap-touch-7inch-dsi.dtso | 129 ++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 00dc2893c754..fe261d7bdab5 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -191,12 +191,14 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb @@ -216,6 +218,8 @@ imx8mm-verdin-wifi-dev-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-ver imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin-wifi-dev.dtb \ imx8mm-verdin-dsi-to-lvds-panel-cap-touch-10inch.dtbo imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo +imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := imx8mm-verdin-wifi-dev.dtb \ + imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso new file mode 100644 index 000000000000..0e15b4b3f3ec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-panel-cap-touch-7inch-dsi.dtso @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Toradex Capacitive Touch Display 7" on Verdin DSI_1. + * On Dahlia (X17) and Development Board (X48), DSI_1 is exposed via a + * Samtec LSS-130 connector and requires the Toradex DSI Display Adapter + * to convert to FFC/FPC connector. + * + * https://developer.toradex.com/hardware/accessories/displays/capacitive-touch-display-7inch-dsi + * https://www.toradex.com/accessories/capacitive-touch-display-7-inch-dsi + * https://developer.toradex.com/hardware/accessories/add-ons/dsi-display-adapter + * https://www.toradex.com/accessories/verdin-dsi-display-adapter + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_pwm3: backlight-pwm3 { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI (SODIMM 19) */ + pwms = <&pwm1 0 6666667 0>; + }; + + panel-lvds-bridge { + compatible = "riverdi,rvt70hslnwca0", "panel-lvds"; + backlight = <&backlight_pwm3>; + data-mapping = "vesa-24"; + height-mm = <86>; + width-mm = <154>; + + panel-timing { + clock-frequency = <51200000>; + de-active = <1>; + hactive = <1024>; + hback-porch = <100 100 100>; + hfront-porch = <16 160 216>; + hsync-active = <0>; + hsync-len = <50 60 140>; + pixelclk-active = <1>; + vactive = <600>; + vback-porch = <23 23 23>; + vfront-porch = <1 12 126>; + vsync-active = <0>; + vsync-len = <1 10 20>; + }; + + port { + panel_lvds_bridge_in: endpoint { + remote-endpoint = <&dsi_lvds_bridge_out>; + }; + }; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + bridge@2c { + compatible = "ti,sn65dsi83"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + /* Verdin GPIO_10_DSI (SODIMM 21) - DSI_1_BKL_EN */ + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + vcc-supply = <®_1p8v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + dsi_lvds_bridge_out: endpoint { + remote-endpoint = <&panel_lvds_bridge_in>; + }; + }; + }; + }; + + touchscreen@41 { + compatible = "ilitek,ili2132"; + reg = <0x41>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + /* Verdin GPIO_9_DSI (SODIMM 17) - TOUCH_INT# */ + /* Rising edge avoids spurious interrupts from the noisy falling edge. */ + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_RISING>; + /* Verdin I2S_2_BCLK (SODIMM 42) - TOUCH_RESET# */ + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <16000000>; + + status = "okay"; +}; + +&mipi_dsi_out { + remote-endpoint = <&dsi_lvds_bridge_in>; +}; From d4fc54ac184d036b51d1638a83f717269b86ddec Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:32 +0200 Subject: [PATCH 639/864] arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F remoteproc Describe the Cortex-M4F remote processor available on the Verdin iMX8M Mini SoM. Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- .../boot/dts/freescale/imx8mm-verdin.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 5fc177f589cb..ac450fc6cbfb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -52,6 +52,18 @@ hdmi_connector: hdmi-connector { status = "disabled"; }; + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + memory-region = <&vdev0buffer>, <&vdev0vring0>, <&vdev0vring1>, + <&rsc_table>; + syscon = <&src>; + }; + /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -164,6 +176,27 @@ reserved-memory { /* Use the kernel configuration settings instead */ /delete-node/ linux,cma; + + vdev0vring0: vdev0vring0@55000000 { + reg = <0 0x55000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@55008000 { + reg = <0 0x55008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@550ff000 { + reg = <0 0x550ff000 0 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@55400000 { + compatible = "shared-dma-pool"; + reg = <0 0x55400000 0 0x100000>; + no-map; + }; }; }; From 0c4a972d869eff8070685c055b6a9366d6c63710 Mon Sep 17 00:00:00 2001 From: Ernest Van Hoecke Date: Fri, 24 Jul 2026 18:24:33 +0200 Subject: [PATCH 640/864] arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F UART_4 overlay Verdin UART_4 can be assigned to Cortex-M4F firmware. Add an overlay that marks the UART as reserved so Linux does not claim the port. The overlay is also combined with the Verdin iMX8M Mini Development Board device tree to provide a ready-to-use DTB for the WiFi SoM variant. Signed-off-by: Ernest Van Hoecke Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/Makefile | 3 +++ .../dts/freescale/imx8mm-verdin-uart4-mcu.dtso | 14 ++++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index fe261d7bdab5..95ae85ab4adf 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -192,6 +192,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-zinnia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-10inch-dsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-uart4-mcu.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia-panel-cap-touch-10inch-dsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb @@ -199,6 +200,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-nau8822-btl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev-uart4-mcu.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb @@ -220,6 +222,7 @@ imx8mm-verdin-wifi-dev-dsi-to-lvds-panel-cap-touch-10inch-dtbs := imx8mm-verdin- imx8mm-verdin-wifi-dev-nau8822-btl-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-dev-nau8822-btl.dtbo imx8mm-verdin-wifi-dev-panel-cap-touch-7inch-dsi-dtbs := imx8mm-verdin-wifi-dev.dtb \ imx8mm-verdin-panel-cap-touch-7inch-dsi.dtbo +imx8mm-verdin-wifi-dev-uart4-mcu-dtbs := imx8mm-verdin-wifi-dev.dtb imx8mm-verdin-uart4-mcu.dtbo imx8mm-verdin-wifi-yavia-dsi-to-hdmi-dtbs := imx8mm-verdin-wifi-yavia.dtb imx8mm-verdin-dsi-to-hdmi.dtbo imx8mm-tqma8mqml-mba8mx-lvds-g133han01-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-g133han01.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso b/arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso new file mode 100644 index 000000000000..8dbecffe9e7b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-uart4-mcu.dtso @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * Verdin iMX8M Mini UART_4 for Cortex-M4F + */ + +/dts-v1/; +/plugin/; + +/* Verdin UART_4 */ +&uart4 { + status = "reserved"; +}; From 933bb140ffbd5015e940ea376a8c5c15b0fbf5d6 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 22 Jul 2026 17:00:44 -0500 Subject: [PATCH 641/864] arm64: dts: imx94-xspi: add the DMA channels Add the DMA channels for iMX94 XSPI controller. Signed-off-by: Han Xu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx94.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index dfbb73603cb2..34833e62bd79 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -827,6 +827,8 @@ xspi1: spi@42b90000 { #size-cells = <0>; clocks = <&scmi_clk IMX94_CLK_XSPI1>; clock-names = "per"; + dmas = <&edma2 27 0 0>, <&edma2 28 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -843,6 +845,8 @@ xspi2: spi@42be0000 { #size-cells = <0>; clocks = <&scmi_clk IMX94_CLK_XSPI2>; clock-names = "per"; + dmas = <&edma4 42 0 0>, <&edma4 43 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; status = "disabled"; }; }; From eba4724641990bd9975ca10ababe726b6143f0b6 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Thu, 18 Jun 2026 17:20:59 +0800 Subject: [PATCH 642/864] arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe The current PCIe device tree configuration only defines the MSI interrupt, which is sufficient for basic PCIe operation but limits advanced functionality. Add the following interrupt lines to pcie0 and pcie1 nodes: - dma: DMA interrupt for PCIe DMA operations - intr: General controller events and link state changes - aer: Advanced Error Reporting interrupt - pme: Power Management Event interrupt This enables enhanced PCIe features and capabilities that were previously unavailable due to missing interrupt definitions. Signed-off-by: Richard Zhu Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index 305751046d66..38fc47024841 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1957,8 +1957,12 @@ pcie0: pcie@4c300000 { bus-range = <0x00 0xff>; num-lanes = <1>; num-viewport = <8>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + ; + interrupt-names = "msi", "dma", "intr", "aer", "pme"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, @@ -2044,8 +2048,12 @@ pcie1: pcie@4c380000 { bus-range = <0x00 0xff>; num-lanes = <1>; num-viewport = <8>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + ; + interrupt-names = "msi", "dma", "intr", "aer", "pme"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, From 61e5b39e96aadeafa884ab96c1477b781dccf145 Mon Sep 17 00:00:00 2001 From: Ananthu C V Date: Thu, 9 Jul 2026 23:39:44 -0700 Subject: [PATCH 643/864] arm64: dts: qcom: glymur: fix SoCCP memory mappings The currently listed SoCCP and SoCCP DTB reserved memory regions don't align with the memory requested by the SoCCP Firmware. Fix this by updating the SoCCP/SoCCP DTB memory regions to reflect the memory region requirements of the SoCCP firmware, as described in the Glymur v21 memory map release. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Ananthu C V Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260709-glymur-soccp-v6-3-16f70227547d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 8145c8721b86..9bd743c78526 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -626,13 +626,13 @@ spss_region_mem: spss@88a00000 { no-map; }; - soccpdtb_mem: soccpdtb@892e0000 { - reg = <0x0 0x892e0000 0x0 0x20000>; + soccp_mem: soccp@88e00000 { + reg = <0x0 0x88e00000 0x0 0x400000>; no-map; }; - soccp_mem: soccp@89300000 { - reg = <0x0 0x89300000 0x0 0x400000>; + soccpdtb_mem: soccpdtb@89200000 { + reg = <0x0 0x89200000 0x0 0x20000>; no-map; }; From fe76d6b32eb2d3193c65c834693fa4f58b558080 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 9 Jul 2026 23:39:45 -0700 Subject: [PATCH 644/864] arm64: dts: qcom: glymur: add SoCCP DT node The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls USB Type-C, battery charging, and various other functions on Qualcomm SoCs. Add the nodes required to enable SoCCP on Glymur/Mahua SoCs. Signed-off-by: Sibi Sankar Co-developed-by: Ananthu C V Signed-off-by: Ananthu C V Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260709-glymur-soccp-v6-4-16f70227547d@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 5 +++ arch/arm64/boot/dts/qcom/glymur.dtsi | 44 ++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index c12808abbfe1..ddf9902e1c4f 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -956,6 +956,11 @@ right_tweeter: speaker@0,1 { }; }; +&remoteproc_soccp { + firmware-name = "qcom/glymur/soccp.mbn", + "qcom/glymur/soccp_dtb.mbn"; +}; + &tlmm { gpio-reserved-ranges = <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 9bd743c78526..6356f977f720 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2330,6 +2330,50 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, }; }; + remoteproc_soccp: remoteproc@d00000 { + compatible = "qcom,glymur-soccp-pas"; + reg = <0x0 0x00d00000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&soccp_mem>, + <&soccpdtb_mem>; + + qcom,smem-states = <&soccp_smp2p_out 0>, + <&soccp_smp2p_out 8>; + qcom,smem-state-names = "stop", + "ping"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + qcom,remote-pid = <19>; + label = "soccp"; + }; + }; + usb_hs_phy: phy@fa0000 { compatible = "qcom,glymur-m31-eusb2-phy", "qcom,sm8750-m31-eusb2-phy"; From ff98c9832fd430ba7b3158b8521002c8eb8aa16c Mon Sep 17 00:00:00 2001 From: Tze Yee Ng Date: Wed, 13 May 2026 01:05:46 -0700 Subject: [PATCH 645/864] arm64: dts: socfpga: use consistent QSPI boot partition label Several SoCFPGA board DTS files labeled the first QSPI MTD partition (qspi_boot / partition@0 under fixed-partitions) as "u-boot" while others already used "Boot and fpga data". Align the QSPI boot partition label only so naming matches the combined boot + FPGA image layout and stays consistent across Agilex, N5X, and Stratix 10 SoCDK variants. No QSPI partition layout or reg properties are changed. Signed-off-by: Tze Yee Ng Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts index 25e17df0cbdb..b40f28519334 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts @@ -109,7 +109,7 @@ partitions { #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x00c00000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index 57d3c5807c65..1e9b87d96765 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -88,7 +88,7 @@ partitions { #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x04200000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index 82cd4115746e..7fe113466ed8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -103,7 +103,7 @@ partitions { #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x00c00000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index 4d32b6928ce1..a2b707ae6e9e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -86,7 +86,7 @@ partitions { #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x04200000>; }; From 6326a6811b1af6674e3eef128df6a3825de26872 Mon Sep 17 00:00:00 2001 From: Roman Vivchar Date: Thu, 9 Jul 2026 13:52:50 +0300 Subject: [PATCH 646/864] ARM: dts: mediatek: mt6323: add AUXADC support Add the devicetree node for the mt6323 AUXADC. Tested-by: Ben Grisdale # Amazon Echo Dot (2nd Generation) Reviewed-by: David Lechner Signed-off-by: Roman Vivchar Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm/boot/dts/mediatek/mt6323.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6323.dtsi b/arch/arm/boot/dts/mediatek/mt6323.dtsi index c230c865116d..c070f4b0936c 100644 --- a/arch/arm/boot/dts/mediatek/mt6323.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6323.dtsi @@ -14,6 +14,11 @@ pmic: mt6323 { interrupt-controller; #interrupt-cells = <2>; + mt6323_adc: adc { + compatible = "mediatek,mt6323-auxadc"; + #io-channel-cells = <1>; + }; + mt6323_leds: leds { compatible = "mediatek,mt6323-led"; #address-cells = <1>; From 96cd41eac1f59d4fc04ac267ddfe5537518c0898 Mon Sep 17 00:00:00 2001 From: Justin Suess Date: Mon, 27 Jul 2026 22:49:13 -0400 Subject: [PATCH 647/864] media: dt-bindings: allwinner,sun4i-a10-ir: add A523 compatible The A523 (sun55i) contains a newer revision of the sunxi CIR receiver. The reset defaults match the fixed behaviour of the older IP, so the device works fine when driven as an A31 CIR receiver. Add the A523 compatible, with allwinner,sun6i-a31-ir as the fallback. While at it, merge the standalone compatible entries into a single enum. Cc: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Signed-off-by: Justin Suess Link: https://patch.msgid.link/20260728024916.993224-2-utilityemal77@gmail.com Signed-off-by: Chen-Yu Tsai --- .../devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 42dfe22ad5f1..18b28feacf83 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -16,9 +16,10 @@ allOf: properties: compatible: oneOf: - - const: allwinner,sun4i-a10-ir - - const: allwinner,sun5i-a13-ir - - const: allwinner,sun6i-a31-ir + - enum: + - allwinner,sun4i-a10-ir + - allwinner,sun5i-a13-ir + - allwinner,sun6i-a31-ir - items: - enum: - allwinner,suniv-f1c100s-ir @@ -27,6 +28,7 @@ properties: - allwinner,sun50i-a64-ir - allwinner,sun50i-h6-ir - allwinner,sun50i-h616-ir + - allwinner,sun55i-a523-ir - const: allwinner,sun6i-a31-ir reg: From 2b24f538652803dcead56a60d11e031dd564b2ad Mon Sep 17 00:00:00 2001 From: Justin Suess Date: Mon, 27 Jul 2026 22:49:14 -0400 Subject: [PATCH 648/864] arm64: dts: allwinner: a523: add IR receiver nodes The A523 has two CIR receivers, both compatible with the A31 CIR: one in the CPUX domain, clocked from the main CCU, and one in the RTC power domain, clocked from the R-CCU. The RTC domain instance's RX signal is typically muxed to PL11, as on the X96Q Pro+. The CPUX instance's can be muxed to PI8, which is what the Avaota A1 uses. Add nodes for both instances, disabled by default. Since the RX signal of each instance can be routed to more than one pin, boards with an IR receiver are expected to add the pinctrl properties next to where they enable the node. Add pinmux nodes for both pins: PL11 for the RTC domain instance, and PI8 for the CPUX one. Co-developed-by: Andre Przywara Signed-off-by: Andre Przywara Signed-off-by: Justin Suess Link: https://patch.msgid.link/20260728024916.993224-3-utilityemal77@gmail.com Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index ca6a16807049..f0b74693da7f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -155,6 +155,13 @@ i2s2_pi_pins: i2s2-pi-pins { bias-disable; }; + /omit-if-no-ref/ + ir_rx_pin: ir-rx-pi-pin { + pins = "PI8"; + allwinner,pinmux = <3>; + function = "cir_rx"; + }; + /omit-if-no-ref/ ledc_ph_pin: ledc-ph-pin { pins = "PH19"; @@ -327,6 +334,17 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ir: ir@2005000 { + compatible = "allwinner,sun55i-a523-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x02005000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_IR_RX>, <&ccu CLK_IR_RX>; + clock-names = "apb", "ir"; + resets = <&ccu RST_BUS_IR_RX>; + status = "disabled"; + }; + ledc: led-controller@2008000 { compatible = "allwinner,sun55i-a523-ledc", "allwinner,sun50i-a100-ledc"; @@ -927,6 +945,24 @@ r_i2c_pins: r-i2c-pins { allwinner,pinmux = <2>; function = "r_i2c0"; }; + + /omit-if-no-ref/ + r_ir_rx_pin: r-ir-rx-pl-pin { + pins = "PL11"; + allwinner,pinmux = <2>; + function = "s_cir_rx"; + }; + }; + + r_ir: ir@7040000 { + compatible = "allwinner,sun55i-a523-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x07040000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_IR_RX>, <&r_ccu CLK_R_IR_RX>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_BUS_R_IR_RX>; + status = "disabled"; }; pck600: power-controller@7060000 { From a3bd47e62cb2ebd96ebe5b9a8c2b95e13f4aea77 Mon Sep 17 00:00:00 2001 From: Justin Suess Date: Mon, 27 Jul 2026 22:49:15 -0400 Subject: [PATCH 649/864] arm64: dts: allwinner: a523: enable IR receiver on the X96Q Pro+ The X96Q Pro+ TV box has an IR receiver window on the front panel, wired to the SoC CIR input on PL11. Enable the CIR receiver in the RTC power domain and mux its RX signal to PL11. Tested on an X96Q Pro+ with ir-keytable and nec keybindings with the remote that it came with in the box. Reviewed-by: Andre Przywara Tested-by: Andre Przywara Signed-off-by: Justin Suess Link: https://patch.msgid.link/20260728024916.993224-4-utilityemal77@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts index a96927fbdadd..1eaee20acaab 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -266,6 +266,12 @@ reg_dcdc3_323: dcdc3 { }; }; +&r_ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + &r_pio { /* * Specifying the supply would create a circular dependency. From 75dc83d420aa134b88bb1900fb08d7745f698bff Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 27 Jul 2026 22:49:16 -0400 Subject: [PATCH 650/864] arm64: dts: allwinner: a523: enable IR on the Avaota A1 The Avaota A1 board has an IR receiver chip on the PCB (next to the Ethernet jacks), wired to the PI8 pin on the SoC. Enable the CIR receiver in the main power domain. Tested on the board with evtest and some random TV remote control. Signed-off-by: Andre Przywara [justin: move the PI8 pinmux node into the dtsi patch] Signed-off-by: Justin Suess Link: https://patch.msgid.link/20260728024916.993224-5-utilityemal77@gmail.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 474354fbfcec..994f1e4f0ce7 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -100,6 +100,12 @@ &gpu { status = "okay"; }; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx_pin>; + status = "okay"; +}; + &ledc { pinctrl-names = "default"; pinctrl-0 = <&ledc_ph_pin>; From 46380e4b1534c1626cecd7f4d0abb5e0cce09af6 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 27 Jul 2026 17:47:23 +0800 Subject: [PATCH 651/864] riscv: dts: spacemit: k3: add USB controller and USB phy support Add all USB device node to the Spacemit K3. Signed-off-by: Inochi Amaoto Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260727094726.890179-2-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 13 ++++++ arch/riscv/boot/dts/spacemit/k3.dtsi | 42 ++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index 4460e225581c..c80ab41e9851 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -220,6 +220,11 @@ dldo7: dldo7 { }; }; +&combophy { + spacemit,apmu = <&syscon_apmu 0x11>; + status = "okay"; +}; + ð0 { pinctrl-names = "default"; pinctrl-0 = <&gmac0_rgmii_0_cfg>, <&gmac0_phy_0_cfg>; @@ -317,3 +322,11 @@ hub@1 { &usb2_phy { status = "okay"; }; + +&usb3d_u2phy { + status = "okay"; +}; + +&usb3d { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 7583467793e1..c3f2dce0969c 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include "k3-pdma.h" @@ -440,6 +441,47 @@ soc: soc { dma-noncoherent; ranges; + usb3d: usb@81a00000 { + compatible = "spacemit,k3-dwc3"; + reg = <0x0 0x81a00000 0x0 0x10000>; + interrupts = <149 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&saplic>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; + clock-names = "usbdrd30"; + resets = <&syscon_apmu RESET_APMU_USB3_D_AHB>, + <&syscon_apmu RESET_APMU_USB3_D_VCC>, + <&syscon_apmu RESET_APMU_USB3_D_PHY>; + reset-names = "ahb", "vcc", "phy"; + phys = <&usb3d_u2phy>, + <&combophy 4 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-ss-quirk; + dr_mode = "host"; + status = "disabled"; + }; + + usb3d_u2phy: phy@81b00000 { + compatible = "spacemit,k3-usb2-phy"; + reg = <0x0 0x81b00000 0x0 0x200>; + clocks = <&syscon_apmu CLK_APMU_USB3_PORTD_BUS>; + #phy-cells = <0>; + status = "disabled"; + }; + + combophy: phy@81d00000 { + compatible = "spacemit,k3-combo-phy"; + reg = <0x0 0x81d00000 0x0 0x600000>; + #phy-cells = <2>; + spacemit,apb-spare = <&pll>; + status = "disabled"; + }; + usb2_host: usb@c0a00000 { compatible = "spacemit,k3-dwc3"; reg = <0x0 0xc0a00000 0x0 0x10000>; From dfc735fd93e4814e65894916ec5f807f25a391d1 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Sat, 25 Jul 2026 13:19:07 +0200 Subject: [PATCH 652/864] arm64: dts: allwinner: sun50i-a64-pinephone: Fix mpu6050 mount matrix The current mount matrix for mpu6050 is wrong. The mount matrix is a simple transform from the sensor coordinate space to the device coordinate space described in DT, where, looking at the screen, X points to the right, Y to the top, and Z towards the user. The mpu6050 is mounted like this (looking at the screen from the front; the sensor is on the near side of the PCB, so its Z axis points towards the user; o marks the pin 1 corner): +Xs ^ | +------+ +Ys <--| | | o | +------+ so this gives: Xd = -Ys [0, -1, 0] Yd = Xs [1, 0, 0] Zd = Zs [0, 0, 1] Fixes: 2496b2aaacf1 ("arm64: dts: allwinner: pinephone: Add mount matrix to accelerometer") Signed-off-by: Ondrej Jirman Link: https://patch.msgid.link/20260725111909.2244868-1-megi@xff.cz Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi index 4bc6c1ef2cde..f958bdbb0d33 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi @@ -230,8 +230,8 @@ accelerometer@68 { interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ vdd-supply = <®_dldo1>; vddio-supply = <®_dldo1>; - mount-matrix = "0", "1", "0", - "-1", "0", "0", + mount-matrix = "0", "-1", "0", + "1", "0", "0", "0", "0", "1"; }; }; From 3683d4f690b83a3ec8df566aa153076bfe2eb3f4 Mon Sep 17 00:00:00 2001 From: Per Larsson Date: Mon, 20 Jul 2026 19:42:42 +0200 Subject: [PATCH 653/864] arm64: dts: allwinner: a523: Add SPDIF output PH pin mux option When SPDIF support was added for the Allwinner A523 family of SoCs, only two of the three possible pins were added to the dtsi, since the third would clash with the first ethernet port (gmac0). However, some devices don't use gmac0 and instead use gmac1 for the only available ethernet port, leaving the pin free to use for SPDIF. Add the remaining pin mux option from the PH pin group to the dtsi so such devices can (later) use it. Signed-off-by: Per Larsson Reviewed-by: Andre Przywara Link: https://patch.msgid.link/20260720174253.7686-1-per@palvencia.se [wens@kernel.org: fix up commit message] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index f0b74693da7f..85ef492ffeae 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -223,6 +223,13 @@ spdif_out_pb_pin: spdif-pb-pin { allwinner,pinmux = <2>; }; + /omit-if-no-ref/ + spdif_out_ph_pin: spdif-ph-pin { + pins = "PH7"; + function = "spdif"; + allwinner,pinmux = <4>; + }; + /omit-if-no-ref/ spdif_out_pi_pin: spdif-pi-pin { pins = "PI10"; From 35ab3805401110513d49022db9e995069b892699 Mon Sep 17 00:00:00 2001 From: Per Larsson Date: Mon, 20 Jul 2026 19:42:43 +0200 Subject: [PATCH 654/864] arm64: dts: allwinner: a523: Enable SPDIF on X96QPRO+ The X96QPro+ TV box uses the PH7 pin for its SPDIF output. Add the relevant bits to the dts now that the dtsi knows about the pin. Signed-off-by: Per Larsson Link: https://patch.msgid.link/20260720174253.7686-2-per@palvencia.se [wens@kernel.org: reorder property order for spdif-out] [wens@kernel.org: fix up commit message] Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-h728-x96qpro+.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts index 1eaee20acaab..eb9fd0a65b41 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -44,6 +44,24 @@ reg_vcc3v3: vcc3v3 { vin-supply = <®_vcc5v>; regulator-always-on; }; + + sound-spdif { + compatible = "simple-audio-card"; + simple-audio-card,name = "spdif-out"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; }; &ehci0 { @@ -281,6 +299,12 @@ &r_pio { vcc-pm-supply = <®_aldo3>; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_out_ph_pin>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From f60f44c24b10fe7fd1fa76b360646def1bea193a Mon Sep 17 00:00:00 2001 From: Jiaxing Hu Date: Sun, 19 Jul 2026 15:46:10 +1200 Subject: [PATCH 655/864] dt-bindings: arm: rockchip: Add ArmSoM CM5 and CM5-IO Add compatibles for the ArmSoM CM5, an RK3576 compute module, and its CM5-IO carrier board. Signed-off-by: Jiaxing Hu Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260719034611.3623066-2-gahing@gahingwoo.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 00f45e94f79d..4506096babac 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -71,6 +71,13 @@ properties: - const: ariaboard,photonicat - const: rockchip,rk3568 + - description: ArmSoM CM5 Module based boards + items: + - enum: + - armsom,cm5-io + - const: armsom,cm5 + - const: rockchip,rk3576 + - description: ArmSoM Sige1 board items: - const: armsom,sige1 From 44a48a23974b86d2c551afbabee15ad70b249df5 Mon Sep 17 00:00:00 2001 From: Jiaxing Hu Date: Sun, 19 Jul 2026 15:46:11 +1200 Subject: [PATCH 656/864] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO Add the ArmSoM CM5, an RK3576 compute module (rk3576-armsom-cm5.dtsi), and its CM5-IO carrier (rk3576-armsom-cm5-io.dts). The module has the RK806 PMIC, HYM8563 RTC, eMMC, GMAC0 with an on-module MotorComm YT8531 PHY, and the SDIO bus for the on-module WiFi. The carrier adds HDMI, a GbE RJ45, two USB-A ports behind a USB3 hub, USB-C with FUSB302 and DP alt-mode, a PCIe 2.0 x1 M.2 slot, microSD, status LEDs and a 40-pin header. The YT8531 has no crystal and takes the SoC 25 MHz reference (REFCLKO25M_GMAC0_OUT), described as a clock on the PHY node and enabled by the PHY driver. The PHY is named explicitly so it is instantiated from the device tree without an MDIO ID probe, which the PHY cannot answer until that clock is running. Its reset is described at the MDIO bus level so mdiobus releases it before the scan. Signed-off-by: Jiaxing Hu Link: https://patch.msgid.link/20260719034611.3623066-3-gahing@gahingwoo.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3576-armsom-cm5-io.dts | 384 ++++++++++++ .../boot/dts/rockchip/rk3576-armsom-cm5.dtsi | 566 ++++++++++++++++++ 3 files changed, 951 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 390f41736488..7e745f890187 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -167,6 +167,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts new file mode 100644 index 000000000000..ebb231271e45 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5-io.dts @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * ArmSoM CM5-IO - official carrier board for the ArmSoM CM5 (RK3576) module. + * + * Carrier provides: + * - Full-size HDMI 2.1 (HDMI TX via HDPTX PHY) + * - Gigabit Ethernet RJ45 (GMAC0 + on-module YT8531) + * - 2x USB-A behind a USB3 hub (combphy1 + u2phy1) + * - USB-C with PD/altmode (FUSB302 on i2c0, combphy0 + USBDP PHY) + * - M.2 PCIe 2.0 x1 slot (combphy0 as PCIe lane) + * - microSD card slot + * - Green/red status LEDs, 40-pin RPi-compatible header + * - 12 V DC barrel jack + * + * Copyright (c) 2024 ArmSoM + * Copyright (c) 2026 Jiaxing Hu + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3576-armsom-cm5.dtsi" + +/ { + model = "ArmSoM CM5-IO"; + compatible = "armsom,cm5-io", "armsom,cm5", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led_green: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_green_en>; + }; + + led_red: led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_FAULT; + gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&led_red_en>; + }; + }; + + vcc_12v0_dcin: regulator-vcc-12v0-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc_12v0_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* PCIe 3.3 V for the M.2 slot */ + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc_3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_12v0_dcin>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_12v0_dcin>; + }; + + vcc_5v0_typec0: regulator-vcc-5v0-typec0 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren>; + regulator-name = "vcc_5v0_typec0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_device>; + }; + + /* USB-A host 5 V (through the hub) */ + vcc_5v0_usbhost: regulator-vcc-5v0-usbhost { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + regulator-name = "vcc_5v0_usbhost"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v0_device>; + }; +}; + +/* ComboPHY0 -> PCIe lane (M.2 slot); ComboPHY1 -> USB3 lane (USB-A hub). */ +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc_5v0_typec0>; + + usb_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + try-power-role = "sink"; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_sw: endpoint { + remote-endpoint = <&usb_drd0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +/* PCIe 2.0 x1 M.2 slot + */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + leds { + led_green_en: led-green-en { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_red_en: led-red-en { + rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pcie_reset: pcie-reset { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +/* SAI6 is the I2S CPU DAI feeding the HDMI audio path. */ +&sai6 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc_5v0_typec0>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc_5v0_usbhost>; + status = "okay"; +}; + +/* Debug UART0 on the 40-pin header. */ +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +/* USB DRD0: USB-C (USBDP SuperSpeed + USB2 HS), OTG with FUSB302 */ +&usb_drd0_dwc3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb_drd0_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +/* USB DRD1: USB-A ports behind the hub */ +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy { + status = "okay"; + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi new file mode 100644 index 000000000000..71ea11e1f8ce --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-cm5.dtsi @@ -0,0 +1,566 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * ArmSoM CM5 - Rockchip RK3576 compute module (Raspberry Pi CM4 form factor). + * + * Common to all CM5 carriers. The carrier .dts includes this file, sets the + * board model/compatible, and adds carrier-specific peripherals. + * + * On-module devices: + * - RK806 PMIC on I2C1 + * - HYM8563 RTC on I2C2 + * - eMMC (SDHCI) + * - GMAC0 + MotorComm YT8531 Gigabit Ethernet PHY (RGMII) + * - SYN43752 WiFi 6 + BT 5.x (SDIO + UART4) + * + * Copyright (c) 2024 ArmSoM + * Copyright (c) 2026 Jiaxing Hu + */ + +#include +#include +#include "rk3576.dtsi" + +/ { + compatible = "armsom,cm5", "rockchip,rk3576"; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_5v0_sys>; + }; + + /* + * WiFi power sequencer for SYN43752. Reset GPIO1 PC6 active-low, + * clock from the HYM8563 RTC oscillator. + */ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on>; + reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +/* + * GMAC0 drives an on-module MotorComm YT8531. The PHY has no local crystal and + * takes the SoC 25 MHz reference (REFCLKO25M_GMAC0_OUT); ethm0_clk0_25m_out + * routes that clock to the pad, and the PHY node consumes and enables it. + */ +&gmac0 { + phy-mode = "rgmii-id"; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-supply = <&vcc_3v3_s3>; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +/* I2C2: HYM8563 RTC @ 0x51 (interrupt on GPIO0 PA0). */ +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +/* + * The PHY reset has to be described at the MDIO bus level: mdiobus releases a + * bus level reset before it scans for PHY IDs, whereas the per-PHY reset-gpios + * is only applied by phylib once the PHY has already been found, which never + * happens while the YT8531 is still held in reset. + * + * The compatible names the YT8531 explicitly so phylib instantiates the PHY + * from the device tree without an MDIO ID probe; the crystal-less PHY does not + * answer on MDIO until its driver has enabled the reference clock below. + */ +&mdio0 { + reset-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + reset-delay-us = <20000>; + reset-post-delay-us = <100000>; + + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id4f51.e91b"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +/* eMMC: on-module, HS400 200 MHz with enhanced strobe. */ +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + /delete-property/ supports-cqe; + status = "okay"; +}; + +/* SDIO: SYN43752 WiFi, power-sequenced by sdio_pwrseq, clock from HYM8563. */ +&sdio { + bus-width = <4>; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-sd; + no-mmc; + non-removable; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + wakeup-source; + status = "okay"; +}; + +/* UART4: Bluetooth (SYN43752). */ +&uart4 { + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + /* GPIO1 PC6 - WiFi power enable / reset (sdio_pwrseq) */ + wifi_reg_on: wifi-reg-on { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; From cd01c677869affe1b01403ca2fad8fc0fe85e8bd Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Tue, 21 Jul 2026 19:35:57 -0700 Subject: [PATCH 657/864] riscv: dts: spacemit: k3: add i2s0-i2s5 nodes Add the six SSPA-based I2S controller nodes for the K3 SoC. i2s0 and i2s2-i2s5 each have a dedicated per-controller sysclk divider, so they use the published 7-clock layout (sysclk, bclk, bus, func, sysclk_div, c_sysclk, c_bclk). i2s1 uses 6 clocks (sysclk, bclk, bus, func, c_sysclk, c_bclk) because its sysclk is driven directly by a DDN (ISCCR0) and has no separate divider stage. Signed-off-by: Troy Mitchell Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260721-kx-i2s-dts-v1-3-d22cb6cfaab5@linux.spacemit.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 119 +++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index c3f2dce0969c..0eb24fac4733 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1170,6 +1170,125 @@ spi1: spi@d4040800 { status = "disabled"; }; + i2s0: i2s@d4026000 { + compatible = "spacemit,k3-i2s"; + reg = <0x0 0xd4026000 0x0 0x30>; + clocks = <&syscon_mpmu CLK_MPMU_I2S0_SYSCLK>, + <&syscon_apbc CLK_APBC_I2S0_BCLK>, + <&syscon_apbc CLK_APBC_I2S0_BUS>, + <&syscon_apbc CLK_APBC_I2S0>, + <&syscon_mpmu CLK_MPMU_I2S0_SYSCLK_DIV>, + <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, + <&syscon_mpmu CLK_MPMU_I2S_BCLK>; + clock-names = "sysclk", "bclk", "bus", "func", + "sysclk_div", "c_sysclk", "c_bclk"; + dmas = <&pdma 21>, <&pdma 22>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_APBC_I2S0>; + #sound-dai-cells = <0>; + + status = "disabled"; + }; + + i2s1: i2s@d4026800 { + compatible = "spacemit,k3-i2s"; + reg = <0x0 0xd4026800 0x0 0x30>; + clocks = <&syscon_mpmu CLK_MPMU_I2S1_SYSCLK>, + <&syscon_apbc CLK_APBC_I2S1_BCLK>, + <&syscon_apbc CLK_APBC_I2S1_BUS>, + <&syscon_apbc CLK_APBC_I2S1>, + <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, + <&syscon_mpmu CLK_MPMU_I2S_BCLK>; + clock-names = "sysclk", "bclk", "bus", "func", + "c_sysclk", "c_bclk"; + dmas = <&pdma 23>, <&pdma 24>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_APBC_I2S1>; + #sound-dai-cells = <0>; + + status = "disabled"; + }; + + i2s2: i2s@d4027000 { + compatible = "spacemit,k3-i2s"; + reg = <0x0 0xd4027000 0x0 0x30>; + clocks = <&syscon_mpmu CLK_MPMU_I2S2_SYSCLK>, + <&syscon_apbc CLK_APBC_I2S2_BCLK>, + <&syscon_apbc CLK_APBC_I2S2_BUS>, + <&syscon_apbc CLK_APBC_I2S2>, + <&syscon_mpmu CLK_MPMU_I2S2_SYSCLK_DIV>, + <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, + <&syscon_mpmu CLK_MPMU_I2S_BCLK>; + clock-names = "sysclk", "bclk", "bus", "func", + "sysclk_div", "c_sysclk", "c_bclk"; + dmas = <&pdma 56>, <&pdma 57>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_APBC_I2S2>; + #sound-dai-cells = <0>; + + status = "disabled"; + }; + + i2s3: i2s@d4027800 { + compatible = "spacemit,k3-i2s"; + reg = <0x0 0xd4027800 0x0 0x30>; + clocks = <&syscon_mpmu CLK_MPMU_I2S3_SYSCLK>, + <&syscon_apbc CLK_APBC_I2S3_BCLK>, + <&syscon_apbc CLK_APBC_I2S3_BUS>, + <&syscon_apbc CLK_APBC_I2S3>, + <&syscon_mpmu CLK_MPMU_I2S3_SYSCLK_DIV>, + <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, + <&syscon_mpmu CLK_MPMU_I2S_BCLK>; + clock-names = "sysclk", "bclk", "bus", "func", + "sysclk_div", "c_sysclk", "c_bclk"; + dmas = <&pdma 58>, <&pdma 59>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_APBC_I2S3>; + #sound-dai-cells = <0>; + + status = "disabled"; + }; + + i2s4: i2s@d4041000 { + compatible = "spacemit,k3-i2s"; + reg = <0x0 0xd4041000 0x0 0x30>; + clocks = <&syscon_mpmu CLK_MPMU_I2S4_SYSCLK>, + <&syscon_apbc CLK_APBC_I2S4_BCLK>, + <&syscon_apbc CLK_APBC_I2S4_BUS>, + <&syscon_apbc CLK_APBC_I2S4>, + <&syscon_mpmu CLK_MPMU_I2S4_SYSCLK_DIV>, + <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, + <&syscon_mpmu CLK_MPMU_I2S_BCLK>; + clock-names = "sysclk", "bclk", "bus", "func", + "sysclk_div", "c_sysclk", "c_bclk"; + dmas = <&pdma 60>, <&pdma 61>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_APBC_I2S4>; + #sound-dai-cells = <0>; + + status = "disabled"; + }; + + i2s5: i2s@d4041800 { + compatible = "spacemit,k3-i2s"; + reg = <0x0 0xd4041800 0x0 0x30>; + clocks = <&syscon_mpmu CLK_MPMU_I2S5_SYSCLK>, + <&syscon_apbc CLK_APBC_I2S5_BCLK>, + <&syscon_apbc CLK_APBC_I2S5_BUS>, + <&syscon_apbc CLK_APBC_I2S5>, + <&syscon_mpmu CLK_MPMU_I2S5_SYSCLK_DIV>, + <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, + <&syscon_mpmu CLK_MPMU_I2S_BCLK>; + clock-names = "sysclk", "bclk", "bus", "func", + "sysclk_div", "c_sysclk", "c_bclk"; + dmas = <&pdma 62>, <&pdma 63>; + dma-names = "tx", "rx"; + resets = <&syscon_apbc RESET_APBC_I2S5>; + #sound-dai-cells = <0>; + + status = "disabled"; + }; + syscon_mpmu: system-controller@d4050000 { compatible = "spacemit,k3-syscon-mpmu"; reg = <0x0 0xd4050000 0x0 0x10000>; From 9b371a8b13fd0e8e6f3b12f4ef7e58927d6f62ee Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 29 Jul 2026 09:24:16 +0800 Subject: [PATCH 658/864] riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 pico-itx board Since the previous commit does not change the phy node name, the dtschema can not recognize the type of the ethernet phy, so the following error is produced: /arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$' from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml /arch/riscv/boot/dts/spacemit/k3-pico-itx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', 're set-deassert-us', 'reset-gpios' were unexpected) from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml Change the nodename to make the dtschema can recognize the right PHY type. Fixes: 6d6536c880fe ("riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board") Signed-off-by: Inochi Amaoto Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729012418.154652-1-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts index c80ab41e9851..b084a35aa00e 100644 --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -233,7 +233,7 @@ ð0 { status = "okay"; mdio { - phy0: phy@1 { + phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; reg = <1>; reset-gpios = <&gpio 0 15 GPIO_ACTIVE_LOW>; From bff5af3c934740481a316c5ae1cd4a09a43134d0 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Wed, 29 Jul 2026 09:24:17 +0800 Subject: [PATCH 659/864] riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 com260 board Since the previous commit does not change the phy node name, the dtschema can not recognize the type of the ethernet phy, so the following error is produced: /arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): $nodename:0: 'phy@1' does not match '^ethernet-phy(@[a-f0-9]+)?$' from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml /arch/riscv/boot/dts/spacemit/k3-com260-ifx.dtb: phy@1 (ethernet-phy-id001c.c916): Unevaluated properties are not allowed ('reg', 'reset-assert-us', ' reset-deassert-us', 'reset-gpios' were unexpected) from schema $id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml Change the nodename to make the dtschema can recognize the right PHY type. Fixes: 9db839d52ccd ("riscv: dts: spacemit: Fix phy id check for the phy on com260 board") Signed-off-by: Inochi Amaoto Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729012418.154652-2-inochiama@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3-com260.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi index 289319a591b9..37627963a649 100644 --- a/arch/riscv/boot/dts/spacemit/k3-com260.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3-com260.dtsi @@ -205,7 +205,7 @@ ð1 { status = "okay"; mdio { - phy1: phy@1 { + phy1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; reg = <1>; reset-gpios = <&gpio 1 5 GPIO_ACTIVE_LOW>; From 74aab5a3042e56681eb8170bad84789fb42eae60 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 28 Jul 2026 15:38:31 -0500 Subject: [PATCH 660/864] dt-bindings: arm: rockchip: Add Anbernic RG Vita-Pro Add compatible string for the Anbernic RG Vita-Pro. Signed-off-by: Chris Morgan Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260728203832.166402-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4506096babac..ff91063bf8c4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -66,6 +66,12 @@ properties: - anbernic,rg-ds - const: rockchip,rk3568 + - description: Anbernic RK3576 Handheld Gaming Console + items: + - enum: + - anbernic,rg-vita-pro + - const: rockchip,rk3576 + - description: Ariaboard Photonicat items: - const: ariaboard,photonicat From aaed846aa94076aa670c60089a7143a0f43327b4 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 28 Jul 2026 15:38:32 -0500 Subject: [PATCH 661/864] arm64: dts: rockchip: Add Anbernic RG Vita-Pro Add device tree for the Anbernic RG Vita-Pro, based on the Rockchip RK3576. All hardware is currently working except for the accelerometer, the touchscreen, the battery monitor, and DisplayPort over USB-C. PWM is also missing currently, and as a result the LEDs and panel backlight are currently controlled via GPIO but will be changed to PWM once supported. The Anbernic RG Vita-Pro includes the following hardware: - A 1080x1920 DSI display with touch. - 21 buttons. - 3 LEDs. - 64GB eMMC, 2 SDMMC slots. - RTL8852BE WiFi (with Bluetooth via UART) - 1 USB 3.0 USB-C port in OTG mode. - 3.5mm headphone jack with play button support. - 5000mAH battery The following hardware has incomplete driver support and is not yet working: - An Invensense icm42607p accelerometer. - A Cellwise cw221x battery monitor. - A Synaptics i2c touchscreen. - DisplayPort over USB-C alt-mode. - PWM controller. - 2 Analog joysticks with LED controllers. Signed-off-by: Chris Morgan Link: https://patch.msgid.link/20260728203832.166402-5-macroalpha82@gmail.com [dropped unused pmic pinconfig definitions, sorted nodes] Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3576-anbernic-rg-vita-pro.dts | 1283 +++++++++++++++++ 2 files changed, 1284 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-anbernic-rg-vita-pro.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 7e745f890187..1799c1190c04 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -167,6 +167,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-anbernic-rg-vita-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3576-anbernic-rg-vita-pro.dts b/arch/arm64/boot/dts/rockchip/rk3576-anbernic-rg-vita-pro.dts new file mode 100644 index 000000000000..358dea43f9b6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-anbernic-rg-vita-pro.dts @@ -0,0 +1,1283 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Chris Morgan + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "rk3576.dtsi" + +/ { + model = "Anbernic RG Vita Pro"; + chassis-type = "handset"; + compatible = "anbernic,rg-vita-pro", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc_keys_home: adc-keys-home { + compatible = "adc-keys"; + io-channel-names = "buttons"; + io-channels = <&saradc 1>; + keyup-threshold-microvolt = <1800000>; + poll-interval = <60>; + + button-home { + label = "HOME"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + adc_keys_play: adc-keys-play { + compatible = "adc-keys"; + io-channel-names = "buttons"; + io-channels = <&saradc 3>; + keyup-threshold-microvolt = <1300000>; + poll-interval = <60>; + + button-play { + label = "PLAY"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + hp_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hp_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Headphone Amp"; + }; + + /* + * LEDs and Backlights can be controlled as a PWM, but PWM + * support is not yet available. + */ + gpio_backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&led_backlight_h>; + pinctrl-names = "default"; + }; + + /* + * Battery values from BSP except for the following: + * + * factory-internal-resistance-micro-ohms - This was set to 80 which + * is likely incorrect and changed to 80000. + * + * charge-full-design-microamp-hours - Was set to 8000000 but the + * physical battery says 5000000. + * + * constant-charge-current-max-microamp - Was set to 10000000 which + * both seems high and exceeds what the charger hardware can do. + * Setting to 3800000 which is the maximum input current the charger + * can handle. + */ + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <5000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <3800000>; + constant-charge-voltage-max-microvolt = <4350000>; + factory-internal-resistance-micro-ohms = <80000>; + precharge-current-microamp = <180000>; + precharge-upper-limit-microvolt = <3600000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3000000>; + }; + + gpio_keys_control: gpio-keys-control { + compatible = "gpio-keys"; + pinctrl-0 = <&gamepad_keys_l>; + pinctrl-names = "default"; + + button-a { + gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + label = "EAST"; + linux,code = ; + }; + + button-b { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + label = "SOUTH"; + linux,code = ; + }; + + button-down { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = ; + }; + + button-l1 { + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_LOW>; + label = "TL"; + linux,code = ; + }; + + button-l2 { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + label = "TL2"; + linux,code = ; + }; + + button-left { + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + + button-menu { + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + label = "MENU"; + linux,code = ; + }; + + button-right { + gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + + button-r1 { + gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + label = "T2"; + linux,code = ; + }; + + button-r2 { + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = ; + }; + + button-select { + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; + label = "SELECT"; + linux,code = ; + }; + + button-start { + gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; + label = "START"; + linux,code = ; + }; + + button-thumbl { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = ; + }; + + button-thumbr { + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = ; + }; + + button-up { + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = ; + }; + + button-x { + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + label = "NORTH"; + linux,code = ; + }; + + button-y { + gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + label = "WEST"; + linux,code = ; + }; + }; + + gpio_keys_volume: gpio-keys-volume { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&vol_keys_l>; + pinctrl-names = "default"; + + vol-down-key { + gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; + label = "VOLUMEDOWN"; + linux,code = ; + }; + + vol-up-key { + gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + label = "VOLUMEUP"; + linux,code = ; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "c"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_amber_h>, <&led_green_h>, <&led_red_h>; + pinctrl-names = "default"; + + charging-led { + color = ; + function = LED_FUNCTION_CHARGING; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + full-led { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + + bat-low-led { + color = ; + function = LED_FUNCTION_ALARM; + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc_3v8_sys>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc_3v8_sys>; + }; + + vcc_3v8_sys: regulator-vcc-3v8-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3800000>; + regulator-min-microvolt = <3800000>; + regulator-name = "vcc_3v8_sys"; + }; + + vcc3v3_sd_s0: regulator-vcc3v3-sd-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_3v3_sd_s0_h>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sdio: regulator-vcc-sdio { + compatible = "regulator-gpio"; + regulator-name = "vcc_sdio"; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_sdio_h>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0>, <3300000 1>; + }; + + vcc_wifi: regulator-vcc-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc_wifi"; + enable-active-high; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_wifi_h>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_lcd: regulator-vdd-lcd { + compatible = "regulator-fixed"; + regulator-name = "vdd_lcd"; + regulator-always-on; + enable-active-high; + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vdd_lcd_h>; + pinctrl-names = "default"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rfkill { + compatible = "rfkill-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_h>; + radio-type = "wlan"; + shutdown-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + }; + + sound: sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,aux-devs = <&aw87391_pa_l>, <&aw87391_pa_r>, + <&hp_amp>; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8388-codec"; + simple-audio-card,pin-switches = "Headphones", "Internal Speakers"; + simple-audio-card,routing = + "LINPUT1", "Mic Jack", + "LINPUT2", "Mic Jack", + "RINPUT1", "Onboard Microphone", + "RINPUT2", "Onboard Microphone", + "Headphones", "Headphone Amp OUTL", + "Headphones", "Headphone Amp OUTR", + "Headphone Amp INL", "LOUT1", + "Headphone Amp INR", "ROUT1", + "Internal Speakers", "Left Amp OUT", + "Internal Speakers", "Right Amp OUT", + "Left Amp IN", "LOUT2", + "Right Amp IN", "ROUT2"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + status = "okay"; + + simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&dsi { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + panel: panel@0 { + compatible = "anbernic,panel-vita-pro", "anbernic,td4310"; + reg = <0>; + backlight = <&gpio_backlight>; + enable-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable>, <&lcd_rst>; + reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + rotation = <270>; + vdd-supply = <&vdd_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_in { + dsi_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi>; + }; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + /* synaptics,dsx-i2c touchscreen at 0x70 */ +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_3v8_sys>; + vcc2-supply = <&vcc_3v8_sys>; + vcc3-supply = <&vcc_3v8_sys>; + vcc4-supply = <&vcc_3v8_sys>; + vcc5-supply = <&vcc_3v8_sys>; + vcc6-supply = <&vcc_3v8_sys>; + vcc7-supply = <&vcc_3v8_sys>; + vcc8-supply = <&vcc_3v8_sys>; + vcc9-supply = <&vcc_3v8_sys>; + vcc10-supply = <&vcc_3v8_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_3v8_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_3v8_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + /* inv,icm42607 IMU at 0x68 */ +}; + +&i2c3 { + status = "okay"; + + es8388: audio-codec@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + AVDD-supply = <&vcca_3v3_s0>; + clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + DVDD-supply = <&vcc_3v3_s3>; + HPVDD-supply = <&vcca_3v3_s0>; + pinctrl-0 = <&sai1m0_mclk>; + pinctrl-names = "default"; + PVDD-supply = <&vcc_3v3_s3>; + #sound-dai-cells = <0>; + }; + + aw87391_pa_l: audio-codec@58 { + compatible = "anbernic,rgds-amp", "awinic,aw87391"; + reg = <0x58>; + #sound-dai-cells = <0>; + sound-name-prefix = "Left Amp"; + }; + + aw87391_pa_r: audio-codec@5b { + compatible = "anbernic,rgds-amp", "awinic,aw87391"; + reg = <0x5b>; + #sound-dai-cells = <0>; + sound-name-prefix = "Right Amp"; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + pinctrl-names = "default"; + status = "okay"; + + sgm41542: charger@3b { + compatible = "sgmicro,sgm41542"; + reg = <0x3b>; + input-current-limit-microamp = <3000000>; + input-voltage-limit-microvolt = <4500000>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&charger_irq>; + pinctrl-names = "default"; + monitored-battery = <&battery>; + status = "okay"; + + regulators { + vbus5v0_typec: otg-vbus { + regulator-name = "vbus5v0_typec"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + /* Unused iSmartWare SW2001 encryption device at 0x3c */ + + husb311: typec-port@4e { + compatible = "hynetek,husb311", "richtek,rt1711h"; + reg = <0x4e>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&usbc_int>; + pinctrl-names = "default"; + status = "okay"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + sink-pdos = ; + source-pdos = ; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs_ep: endpoint { + remote-endpoint = <&usb_drd0_hs_ep>; + }; + }; + port@1 { + reg = <1>; + usbc0_ss_ep: endpoint { + remote-endpoint = <&usb_drd0_ss_ep>; + }; + }; + port@2 { + reg = <2>; + usbc0_dp_ep: endpoint { + remote-endpoint = <&usbdp_phy_ep>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; + + /* cellwise,cw221X battery manager at 0x64 */ +}; + +&mipidcphy { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_perstn>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_wifi>; + status = "okay"; +}; + +&pinctrl { + audio { + hp_amp_enable_h: hp-amp-enable { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hp_det: hp-det { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + bluetooth { + bt_reset_gpio: bt-reset-pin { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-pin { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + charger { + charger_irq: charger-irq { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + display { + lcd_enable: lcd-enable { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_rst: lcd-rst { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gpio-keys { + vol_keys_l: vol-keys_l { + rockchip,pins = + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + gamepad_keys_l: gamepad-keys-l { + rockchip,pins = + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + led_amber_h: led-amber-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_backlight_h: led-backlight-h { + rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_green_h: led-green-h { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_red_h: led-red-h { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie0_perstn: pcie0-perstn { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + regulator { + vcc_3v3_sd_s0_h: vcc-3v3-sd-s0-h { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_sdio_h: vcc-sdio-h { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_wifi_h: vcc-wifi-h { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vdd_lcd_h: vdd-lcd-h { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usbc_int: usbc-int { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usbc0_sbu1: usbc0-sbu1 { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + usbc0_sbu2: usbc0-sbu2 { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wifi { + wifi_en_h: wifi-en-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai1 { + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_pldo2_s0>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + pinctrl-0 = <&sdmmc1m0_bus4>, <&sdmmc1m0_clk>, + <&sdmmc1m0_cmd>, <&sdmmc1m0_det>; + pinctrl-names = "default"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd_s0>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + full-pwr-cycle-in-suspend; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + pinctrl-0 = <&sdmmc0_bus4>, <&sdmmc0_clk>, + <&sdmmc0_cmd>, <&sdmmc0_det>; + pinctrl-names = "default"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi1 { + num-cs = <1>; + pinctrl-0 = <&spi1m2_pins>, <&spi1m2_csn0>; + status = "okay"; + + /* SPI controlled MCU for joystick and joystick LEDs. */ +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi_in_vp1>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart6 { + pinctrl-0 = <&uart6m1_xfer>, <&uart6m1_ctsn>, <&uart6m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + device-wake-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>; + pinctrl-names = "default"; + }; +}; + +&usbdp_phy { + mode-switch; + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_sbu1 &usbc0_sbu2>; + sbu1-dc-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + usbdp_phy_ep: endpoint { + remote-endpoint = <&usbc0_dp_ep>; + }; + }; +}; + +&usb_drd0_dwc3 { + usb-role-switch; + dr_mode = "otg"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_drd0_hs_ep: endpoint { + remote-endpoint = <&usbc0_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + usb_drd0_ss_ep: endpoint { + remote-endpoint = <&usbc0_ss_ep>; + }; + }; + }; +}; From 9f23009c60a3787c9bdb1eedf725a691537dfd5c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 27 Jul 2026 14:55:02 -0300 Subject: [PATCH 662/864] arm64: dts: rockchip: Drop data-mapping from Engicam PX30 Core The panel-simple schema only allows data-mapping overrides for panels whose mapping is not fixed by their compatible. Consequently, the property on the Ampire AM-1280800N3TZQW-T00H panel fails validation: (ampire,am-1280800n3tzqw-t00h): False schema does not allow ['vesa-24'] The panel descriptor already selects 8 bits per color and MEDIA_BUS_FMT_RGB888_1X7X4_SPWG. The DRM OF helpers translate "vesa-24" to that exact bus format, and panel-simple falls back to the descriptor's format when the property is absent. Removing the property therefore has no functional effect. Drop the redundant property to satisfy the binding. Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260727175502.2585290-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts index 47aa30505a42..aa636ce45e3a 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts @@ -28,7 +28,6 @@ panel { compatible = "ampire,am-1280800n3tzqw-t00h"; backlight = <&backlight>; power-supply = <&vcc3v3_lcd>; - data-mapping = "vesa-24"; port { panel_in_lvds: endpoint { From fe67191030089b2653837489328ee2d18acaa149 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 27 Jul 2026 14:40:07 -0300 Subject: [PATCH 663/864] arm64: dts: rockchip: Add CSI-2 bus type to ROCK 5B+ camera overlays The Rockchip RK3568 MIPI CSI-2 receiver binding requires the bus-type property in its input endpoint. Specify that the Radxa CAM4K modules connected to CSI2 and CSI4 use a MIPI CSI-2 D-PHY bus. This fixes the following dtbs_check warning: endpoint: 'bus-type' is a required property Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260727174007.2581714-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso | 2 ++ .../boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso index ee9ecf68a886..5c7fb960b099 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam0.dtso @@ -9,6 +9,7 @@ #include #include +#include #include &{/} { @@ -80,6 +81,7 @@ &csi2 { &csi2_in { csi2_input: endpoint { + bus-type = ; data-lanes = <1 2 3 4>; link-frequencies = /bits/ 64 <445500000>; remote-endpoint = <&imx415_output>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso index 8a4cf3fdbf8e..1ee9036b9095 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus-radxa-cam4k-cam1.dtso @@ -9,6 +9,7 @@ #include #include +#include #include &{/} { @@ -80,6 +81,7 @@ &csi4 { &csi4_in { csi4_input: endpoint { + bus-type = ; data-lanes = <1 2 3 4>; link-frequencies = /bits/ 64 <445500000>; remote-endpoint = <&cam1_imx415_output>; From 4f7259ebe1eba4778768a4f5a0bbbe439d10f3f3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 16 Jul 2026 22:07:34 -0300 Subject: [PATCH 664/864] arm64: dts: rockchip: Fix rk3399-roc-pc-plus analog audio The ES8388 sound card on the rk3399-roc-pc-plus fails to probe because i2s1 cannot claim its MCLK pin: pinctrl: pin gpio4-0 already requested by ff880000.i2s; cannot claim for ff890000.i2s pinctrl: error -EINVAL: pin-128 (ff890000.i2s) pinctrl: error -EINVAL: could not request pin 128 (gpio4-0) from group i2s-8ch-mclk-pin on device rockchip-pinctrl GPIO4_A0 is routed as SCLK_I2S_8CH_OUT and is used by i2s1 as the external MCLK for the ES8388 codec. The board dts already removes GPIO4_A0 from the i2s0_8ch_bus pin group, but i2s0 still claims the same pin through its bclk_off state. Since the i2s driver requests both states, this blocks i2s1 pinctrl setup and leaves the simple-audio-card deferred with a parse error. Override i2s0_8ch_bus_bclk_off as well, matching the existing i2s0_8ch_bus override, so GPIO4_A0 is left for i2s1/ES8388 audio. Cc: stable@vger.kernel.org Fixes: 6d9a7bd6a13c ("arm64: dts: rockchip: add support for Firefly ROC-RK3399-PC-PLUS") Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260717010736.578419-1-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index 4f2831097624..f6d62ee51f1b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -136,6 +136,18 @@ &i2s0_8ch_bus { <3 RK_PD7 1 &pcfg_pull_none>; }; +&i2s0_8ch_bus_bclk_off { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>; +}; + &i2s1 { pinctrl-names = "default"; pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; From 2dfc88c13fb2db7f17c55f16b679cdfe4ded19c5 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 16 Jul 2026 22:07:35 -0300 Subject: [PATCH 665/864] arm64: dts: rockchip: Enable wireless on rk3399-roc-pc-plus The rk3399-roc-pc-plus board has an Ampak AP6256 Wi-Fi/Bluetooth module. Describe the Wi-Fi function on SDIO0 and the Bluetooth function on UART0. Add the Bluetooth wake and shutdown pinctrl entries, enable SDIO0 as a non-removable SDIO device, and add the power sequencing delays needed by the module. The module uses the RK808 CLKOUT2 output as its 32 kHz low-power clock. Drop the duplicate HYM8563 clock-output-names property and remove the same clock from the SDIO power sequencer so the Bluetooth node can request the shared LPO clock directly. Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260717010736.578419-2-festevam@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-roc-pc-plus.dts | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index f6d62ee51f1b..f87bc7b6afc1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -123,6 +123,10 @@ es8388: es8388@11 { }; }; +&hym8563 { + /delete-property/ clock-output-names; +}; + /* <4 RK_PA0 1 &pcfg_pull_none> is used as i2s_8ch_mclk_pin */ &i2s0_8ch_bus { rockchip,pins = @@ -157,6 +161,20 @@ &i2s1 { }; &pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + es8388 { ear_ctl_pin: ear-ctl-pin { rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; @@ -180,6 +198,28 @@ i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { }; }; +&sdio_pwrseq { + /delete-property/ clocks; + /delete-property/ clock-names; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + &u2phy0 { status = "okay"; @@ -212,6 +252,17 @@ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; }; &usbdrd_dwc3_0 { From b2007873ddfff223bb680c7ff60eaf675670f07a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 16 Jul 2026 22:07:36 -0300 Subject: [PATCH 666/864] arm64: dts: rockchip: Keep rk3399-roc-pc-plus work LED on The rk3399-roc-pc-plus inherits the work LED heartbeat trigger from the common rk3399-roc-pc.dtsi. On the rk3399-roc-pc-plus this LED is the prominent blue front-panel status LED. Blinking it continuously is distracting for a PC-style board. The usual default is a steady power/status indication while the system is running. Use the default-on trigger for this board instead. This keeps the LED useful as a simple running indicator and still lets userspace select a different trigger or turn it off after boot. Signed-off-by: Fabio Estevam Link: https://patch.msgid.link/20260717010736.578419-3-festevam@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index f87bc7b6afc1..960faef1bb29 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -281,3 +281,7 @@ &vcc5v0_host { pinctrl-names = "default"; pinctrl-0 = <&vcc5v0_host_en>; }; + +&work_led { + linux,default-trigger = "default-on"; +}; From 181a06fe549d0b2a805eb112c0f7494bdbeefecf Mon Sep 17 00:00:00 2001 From: Pufan Jin <2254650260@qq.com> Date: Fri, 17 Jul 2026 00:36:31 +0800 Subject: [PATCH 667/864] dt-bindings: arm: rockchip: Add EmbedFire LubanCat 4 board Add compatible string for the EmbedFire LubanCat 4 single board computer based on the Rockchip RK3588S SoC. Acked-by: Conor Dooley Signed-off-by: Pufan Jin <2254650260@qq.com> Link: https://patch.msgid.link/tencent_0DA92AE62C08A802ACC4FE9E47A0192C8E05@qq.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ff91063bf8c4..93e7cba943fa 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -204,6 +204,11 @@ properties: - const: embedfire,lubancat-2 - const: rockchip,rk3568 + - description: EmbedFire LubanCat 4 + items: + - const: embedfire,lubancat-4 + - const: rockchip,rk3588s + - description: Engicam PX30.Core C.TOUCH 2.0 items: - const: engicam,px30-core-ctouch2 From 6d9430d58714909071853c0949cdc93756aa3ad4 Mon Sep 17 00:00:00 2001 From: Pufan Jin <2254650260@qq.com> Date: Fri, 17 Jul 2026 00:36:32 +0800 Subject: [PATCH 668/864] arm64: dts: rockchip: Add EmbedFire LubanCat 4 board Add device tree for the EmbedFire LubanCat 4 single board computer, featuring the Rockchip RK3588S SoC. Supported peripherals: - UART2 debug console - RK806 SPI PMIC with the full regulator tree, and RK8602/RK8603 fan53555-family supplies for the big CPU cluster and NPU - eMMC (HS400 enhanced strobe) and SD card (UHS SDR104) - GMAC1 with RGMII PHY on MDIO1 (Realtek RTL8211F, described via the generic clause-22 compatible) - HDMI0 output through hdptxphy0 and VOP2 - PCIe 2.0 x1 (mini PCIe slot) via combphy0_ps - USB 2.0 host ports and one USB 3.0 host port - HYM8563 RTC on I2C0 - On-board heartbeat LED and PWM fan header Tested on hardware: gmac1 negotiates 1000Mbps/Full duplex with phy-mode = "rgmii" (Realtek RTL8211F PHY, PCB provides ~2ns clock skew on both TXC and RXC). Signed-off-by: Pufan Jin <2254650260@qq.com> Reviewed-by: Andrew Lunn #for gmac1 + mdio1 Link: https://patch.msgid.link/tencent_D22A164B3AEEA50562C1EC988862BA827A09@qq.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588s-lubancat-4.dts | 785 ++++++++++++++++++ 2 files changed, 786 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1799c1190c04..28cd17170e37 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-gameforce-ace.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-lubancat-4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts new file mode 100644 index 000000000000..586741ae7363 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-lubancat-4.dts @@ -0,0 +1,785 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree for EmbedFire LubanCat-4 SBC. + * + * Copyright (c) 2026 Pufan Jin <2254650260@qq.com> + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "EmbedFire LubanCat-4"; + compatible = "embedfire,lubancat-4", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_status_led_pin>; + + sys-led { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc5v0_dcin: regulator-vcc5v0-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_dcin>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie20: regulator-vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb20_host: regulator-vcc5v0-usb20-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb20_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_pwr_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: regulator-vcc5v0-usb30-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_pwr_en>; + vin-supply = <&vcc5v0_sys>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 100 150 200 255>; + pwms = <&pwm0 0 5000 0>; + #cooling-cells = <2>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + /* + * The PCB adds ~2ns of trace delay on both TXC and RXC, so the + * required RGMII clock skew is provided by the board itself. + * Neither the MAC nor the PHY should add any internal delay, + * hence "rgmii" (not "rgmii-id") is correct here. + */ + phy-mode = "rgmii"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi0 { + pinctrl-0 = <&hdmim0_tx0_cec + &hdmim0_tx0_hpd + &hdmim0_tx0_scl + &hdmim0_tx0_sda>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l2 { + pinctrl-0 = <&pcie2_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sys_status_led_pin: sys-status-led-pin { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac1 { + gmac1_phy_rst: gmac1-phy-rst { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie2_reset: pcie2-reset { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb20_host_pwr_en: usb20-host-pwr-en { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb30_host_pwr_en: usb30-host-pwr-en { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg1 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg2 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; From 4baf28ab6256259bbee8bfcd9611d590992186bc Mon Sep 17 00:00:00 2001 From: Haritha S K Date: Fri, 24 Jul 2026 10:46:27 +0530 Subject: [PATCH 669/864] arm64: dts: qcom: eliza: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Haritha S K Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260724-eliza-cpufreq-v1-1-38f01e47f0f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 357e8066c176..b331e3e1c2be 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -45,6 +45,7 @@ cpu0: cpu@0 { dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; l2_0: l2-cache { compatible = "cache"; @@ -76,6 +77,7 @@ cpu1: cpu@100 { dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; }; cpu2: cpu@200 { @@ -94,6 +96,7 @@ cpu2: cpu@200 { dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; l2_2: l2-cache { compatible = "cache"; @@ -119,6 +122,7 @@ cpu3: cpu@300 { dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; l2_3: l2-cache { compatible = "cache"; @@ -144,6 +148,7 @@ cpu4: cpu@400 { dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; l2_4: l2-cache { compatible = "cache"; @@ -169,6 +174,7 @@ cpu5: cpu@500 { dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; l2_5: l2-cache { compatible = "cache"; @@ -194,6 +200,7 @@ cpu6: cpu@600 { dynamic-power-coefficient = <238>; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; l2_6: l2-cache { compatible = "cache"; @@ -219,6 +226,7 @@ cpu7: cpu@700 { dynamic-power-coefficient = <588>; qcom,freq-domain = <&cpufreq_hw 2>; + #cooling-cells = <2>; l2_7: l2-cache { compatible = "cache"; From ec31c2fb9286ace04394e8ed98ef5f2b1b34cbdd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 21 Jul 2026 17:51:03 +0200 Subject: [PATCH 670/864] dt-bindings: arm: qcom-soc: Include Eliza, Kaanapali and others in SoC names Grow the schema checking for proper SoC compatible naming style with recently upstreamed new Qualcomm SoCs: Eliza, Kaanapali, Hawi, Mahua, Maili, Nord and Shikra. The list covers only SoC IP blocks, thus no Hamoa or Talos in the names, because these are codenames but not used for SoC IP block naming. Since switching from model numbers to codenames, this list with explicit codenames will have to grow and list them all in order for the schema to work. It feels like a churn, but the compatible naming is still mess, for example, the schema pci/qcom,pcie-x1e80100.yaml with a legacy naming vendor,IP-SoC (qcom,pcie-x1e80100) received a new compatible with new style (qcom,glymur-pcie). Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-1-8f275c9d3412@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index 27261039d56f..fecf9dc05b67 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -25,7 +25,7 @@ select: compatible: oneOf: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,.*(glymur|milos).*$" + - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra).*$" required: - compatible @@ -36,7 +36,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - - pattern: "^qcom,(glymur|milos)-.*$" + - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra)-.*$" # Legacy namings - variations of existing patterns/compatibles are OK, # but do not add completely new entries to these: From d00d2656884fb8cabc81543457d3dd2685532521 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 21 Jul 2026 17:51:04 +0200 Subject: [PATCH 671/864] dt-bindings: arm: qcom-soc: Document more of existing legacy style compatibles The schema misses several old style compatibles with SoC component trailing in the compatible (qcom,IP-SoC): - qcom,apss-wdt-x1e80100 - qcom,apss-wdt-xxx, qcom,rpm-xxx and qcom,scm-xxx for SoC with code names (like qcom,rpm-shikra) - qcom,kpss-gcc-xxx - qcom,rpmcc-xxx - qcom,tcsr-xxx - qcom,usb-hs-phy-xxx It also missed qcom,ipq806x-ahci. None of these were flagged by schema, because they were used with fallbacks and the schema checks only for single compatibles. Nevertheless document them for complete picture and for future change, which will apply the schema to fallbacks as well. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-2-8f275c9d3412@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/arm/qcom-soc.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index fecf9dc05b67..dbc7877ee30e 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -40,12 +40,19 @@ properties: # Legacy namings - variations of existing patterns/compatibles are OK, # but do not add completely new entries to these: - - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,apss-wdt-[a-z]+$" # Codenames variant + - pattern: "^qcom,kpss-gcc-(apq|ipq|mdm|msm)[0-9]+.*$" - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,rpmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,rpm(cc)?-[a-z]+$" # Codenames variant + - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sar?|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,scm-[a-z]+$" # Codenames variant + - pattern: "^qcom,tcsr-(apq|ipq|mdm|msm)[0-9]+.*$" + - pattern: "^qcom,usb-hs-phy-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - enum: - qcom,dsi-ctrl-6g-qcm2290 - qcom,gpucc-sdm630 @@ -55,12 +62,15 @@ properties: - qcom,lcc-mdm9615 - qcom,lcc-msm8960 - qcom,lpass-cpu-apq8016 - - qcom,usb-ss-ipq4019-phy - qcom,usb-hs-ipq4019-phy + - qcom,usb-hsic-phy-mdm9615 + - qcom,usb-hsic-phy-msm8974 + - qcom,usb-ss-ipq4019-phy - qcom,vqmmc-ipq4019-regulator # Legacy compatibles with wild-cards - list cannot grow with new bindings: - enum: + - qcom,ipq806x-ahci - qcom,ipq806x-gmac - qcom,ipq806x-nand - qcom,ipq806x-sata-phy From 8ed9b7baf47cc876fcf44944b79dc30b493c9374 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 21 Jul 2026 17:51:05 +0200 Subject: [PATCH 672/864] dt-bindings: arm: qcom-soc: Validate nodes with fallbacks The schema checking for expected naming patterns for SoC IP block nodes was really incomplete and was checking only nodes with single compatible. Fix this by changing "select:" to "contains:" so every node, except root nodes, having at least one matching compatible will be evaluated. This however will evaluate nodes which have some generic fallbacks (e.g. syscon), thus the schema for expected compatible should also have "contains:" (with "anyOf:"). These two above are the only functional changes in this commit and the rest of the diff is indentation change. None of the patterns are changed (neither in "Preferred naming style" group nor in "Legacy namings"), none of the compatibles are affected. Basically the second part of the diff is (simplifying): properties: compatible: - oneOf: - ...... + contains: + anyOf: + ...... Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-3-8f275c9d3412@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/arm/qcom-soc.yaml | 98 ++++++++++--------- 1 file changed, 52 insertions(+), 46 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index dbc7877ee30e..e72502f8df2c 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -22,59 +22,65 @@ description: | select: properties: + # Select all nodes which have SoC-based compatibles, but not the root + # "/" node, because its front compatibles do not follow any SoC patterns + $nodename: + pattern: "[^/]" compatible: - oneOf: - - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra).*$" + contains: + oneOf: + - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra).*$" required: - compatible properties: compatible: - oneOf: - # Preferred naming style for compatibles of SoC components: - - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra)-.*$" + contains: + anyOf: + # Preferred naming style for compatibles of SoC components: + - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" + - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" + - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" + - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$" - # Legacy namings - variations of existing patterns/compatibles are OK, - # but do not add completely new entries to these: - - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,apss-wdt-[a-z]+$" # Codenames variant - - pattern: "^qcom,kpss-gcc-(apq|ipq|mdm|msm)[0-9]+.*$" - - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,rpmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,rpm(cc)?-[a-z]+$" # Codenames variant - - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sar?|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,scm-[a-z]+$" # Codenames variant - - pattern: "^qcom,tcsr-(apq|ipq|mdm|msm)[0-9]+.*$" - - pattern: "^qcom,usb-hs-phy-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - enum: - - qcom,dsi-ctrl-6g-qcm2290 - - qcom,gpucc-sdm630 - - qcom,gpucc-sdm660 - - qcom,lcc-apq8064 - - qcom,lcc-ipq8064 - - qcom,lcc-mdm9615 - - qcom,lcc-msm8960 - - qcom,lpass-cpu-apq8016 - - qcom,usb-hs-ipq4019-phy - - qcom,usb-hsic-phy-mdm9615 - - qcom,usb-hsic-phy-msm8974 - - qcom,usb-ss-ipq4019-phy - - qcom,vqmmc-ipq4019-regulator + # Legacy namings - variations of existing patterns/compatibles are OK, + # but do not add completely new entries to these: + - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,apss-wdt-[a-z]+$" # Codenames variant + - pattern: "^qcom,kpss-gcc-(apq|ipq|mdm|msm)[0-9]+.*$" + - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,rpmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,rpm(cc)?-[a-z]+$" # Codenames variant + - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sar?|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,scm-[a-z]+$" # Codenames variant + - pattern: "^qcom,tcsr-(apq|ipq|mdm|msm)[0-9]+.*$" + - pattern: "^qcom,usb-hs-phy-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - enum: + - qcom,dsi-ctrl-6g-qcm2290 + - qcom,gpucc-sdm630 + - qcom,gpucc-sdm660 + - qcom,lcc-apq8064 + - qcom,lcc-ipq8064 + - qcom,lcc-mdm9615 + - qcom,lcc-msm8960 + - qcom,lpass-cpu-apq8016 + - qcom,usb-hs-ipq4019-phy + - qcom,usb-hsic-phy-mdm9615 + - qcom,usb-hsic-phy-msm8974 + - qcom,usb-ss-ipq4019-phy + - qcom,vqmmc-ipq4019-regulator - # Legacy compatibles with wild-cards - list cannot grow with new bindings: - - enum: - - qcom,ipq806x-ahci - - qcom,ipq806x-gmac - - qcom,ipq806x-nand - - qcom,ipq806x-sata-phy - - qcom,ipq806x-usb-phy-ss - - qcom,ipq806x-usb-phy-hs + # Legacy compatibles with wild-cards - list cannot grow with new bindings: + - enum: + - qcom,ipq806x-ahci + - qcom,ipq806x-gmac + - qcom,ipq806x-nand + - qcom,ipq806x-sata-phy + - qcom,ipq806x-usb-phy-ss + - qcom,ipq806x-usb-phy-hs additionalProperties: true From ab7b4c7b351809538698dfb1634510b5730b1a74 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 21 Jul 2026 17:51:06 +0200 Subject: [PATCH 673/864] dt-bindings: arm: qcom-soc: Allow WSA88xx speaker compatible One selects in this schema captures "^qcom,.*sa[0-9]+.*$" compatibles, because there are SAxxxx Qualcomm SoCs. Unfortunately there is also WSA8810 and WSA8855 I2C speakers, so they need listing too. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260721-dt-bindings-qcom-soc-naming-v3-4-8f275c9d3412@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index e72502f8df2c..ff4a0baefad9 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -83,4 +83,8 @@ properties: - qcom,ipq806x-usb-phy-ss - qcom,ipq806x-usb-phy-hs + # In general non-SoC Qualcomm devices do not need to be listed here, + # however in a few cases they got selected by patterns in "select": + - pattern: "^qcom,wsa[0-9]+$" + additionalProperties: true From 7108a3708c3310df62c95bea11065bcd7804ec37 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 24 Jul 2026 11:23:54 +0300 Subject: [PATCH 674/864] arm64: dts: qcom: eliza-evk: Add support for USB and SD card Even though the EVK comes with 3 Type-C ports, the Eliza EVK only has one USB controller and a single set of PHYs, which are connected to the port marked as JUSB. Also, the EVK comes with an SD card slot. So describe the PMIC GLINK node, the connector graph, the PHYs and repeater supplies and enable the USB controller. Also enable the second SD host controller, describe the card detect GPIO and the board specific supplies. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260724-dts-qcom-eliza-cqs-evk-enable-usb-sdcard-v3-1-eadf9da69226@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 92 +++++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi index e47b24f8b827..2fc945658300 100644 --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi @@ -11,6 +11,70 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + pmic-glink { + compatible = "qcom,eliza-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + }; +}; + +&pm7550ba_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; +}; + +&sdhc_2 { + vmmc-supply = <&vreg_l13b>; + vqmmc-supply = <&vreg_l23b>; + + cd-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdc2_default>, <&sd_cd>; + pinctrl-1 = <&sdc2_sleep>, <&sd_cd>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + sd_cd: sd-cd-state { + pins = "gpio58"; + function = "gpio"; + bias-pull-up; + }; }; &uart13 { @@ -18,3 +82,31 @@ &uart13 { status = "okay"; }; + +&usb { + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3g>; + vdda-pll-supply = <&vreg_l7k>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_hsphy { + vdd-supply = <&vreg_l7k>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pm7550ba_eusb2_repeater>; + + status = "okay"; +}; From 23da74833df803c5e8bea71feb878173764ef121 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 24 Jul 2026 11:25:45 +0300 Subject: [PATCH 675/864] arm64: dts: qcom: eliza: Describe the ADSP GPR node Describe the ADSP Generic Packet Router (GPR) devicetree node as part of audio subsystem on Qualcomm Eliza SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20260724-dts-qcom-eliza-add-gpr-v3-1-2595beb0cdec@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 41 +++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index b331e3e1c2be..83b8d80545e9 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -17,6 +17,7 @@ #include #include #include +#include #include / { @@ -2020,6 +2021,46 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = ; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1001 0x80>, + <&apps_smmu 0x1061 0x0>; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; From b496282ee4ad07311a13489e15b74fb7078d9a01 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 17:02:18 +0200 Subject: [PATCH 676/864] riscv: dts: spacemit: k1-bananapi-f3: fix maximum CPU core voltage On the Banana Pi BPI-F3 board, the buck1 and buck2 voltage regulators, which supply the CPU core voltage, are configured with a maximum output voltage of 3.45V, while the highest operating point requires only 1.050V. This means that a kernel bug, OPP misconfiguration, or privileged userspace could request a voltage above the safe operating limit, causing possible permanent CPU damage. Set the maximum regulator voltage to 1.050V instead. Fixes: 09a412d39748 ("riscv: dts: spacemit: define regulator constraints") Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net Cc: stable@vger.kernel.org Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729150722.1598630-2-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index e2961b7e0a3e..58035d886bf6 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -237,14 +237,14 @@ pmic@41 { regulators { buck1_0v9: buck1 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; buck2 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; From 56a77ddae794ca0516fc146f6e59bb8cdf4fd9d2 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 17:02:19 +0200 Subject: [PATCH 677/864] riscv: dts: spacemit: k1-milkv-jupiter: fix maximum CPU core voltage On the Milk-V Jupiter board, the buck1 and buck2 voltage regulators, which supply the CPU core voltage, are configured with a maximum output voltage of 3.45V, while the highest operating point requires only 1.050V. This means that a kernel bug, OPP misconfiguration, or privileged userspace could request a voltage above the safe operating limit, causing possible permanent CPU damage. Set the maximum regulator voltage to 1.050V instead. Fixes: 7d307daa12b1 ("riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter") Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net Cc: stable@vger.kernel.org Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729150722.1598630-3-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index b61f5995ec77..c76b91ecb914 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -211,14 +211,14 @@ pmic@41 { regulators { buck1 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; buck2 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; From ae0c38f0a24f95c8759b6b0eaaa5a0d36a7c6af2 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 17:02:20 +0200 Subject: [PATCH 678/864] riscv: dts: spacemit: k1-orangepi-rv2: fix maximum CPU core voltage On the OrangePi RV2 board, the buck1 and buck2 voltage regulators, which supply the CPU core voltage, are configured with a maximum output voltage of 3.45V, while the highest operating point requires only 1.050V. This means that a kernel bug, OPP misconfiguration, or privileged userspace could request a voltage above the safe operating limit, causing possible permanent CPU damage. Set the maximum regulator voltage to 1.050V instead. Fixes: c02c047b925c ("riscv: dts: spacemit: Define the P1 PMIC regulators for OrangePi RV2") Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net Cc: stable@vger.kernel.org Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729150722.1598630-4-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 7c49bce427f3..b907a1396b21 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -164,14 +164,14 @@ pmic@41 { regulators { buck1 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; buck2 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; From f045253a03589b2616332560b4120e584342a987 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 17:02:21 +0200 Subject: [PATCH 679/864] riscv: dts: spacemit: k1-musepi-pro: fix maximum CPU core voltage On the MusePi Pro board, the buck1 and buck2 voltage regulators, which supply the CPU core voltage, are configured with a maximum output voltage of 3.45V, while the highest operating point requires only 1.050V. This means that a kernel bug, OPP misconfiguration, or privileged userspace could request a voltage above the safe operating limit, causing possible permanent CPU damage. Set the maximum regulator voltage to 1.050V instead. Fixes: e2dac7c7a3a8 ("riscv: dts: spacemit: k1-musepi-pro: add PMIC and power infrastructure") Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net Cc: stable@vger.kernel.org Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729150722.1598630-5-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts index 3078ffb5cb87..246f8f2ab62b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -180,14 +180,14 @@ pmic@41 { regulators { buck1 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; buck2 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; From d66267c35032c46c18b675601d03c80239bcd913 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 17:02:22 +0200 Subject: [PATCH 680/864] riscv: dts: spacemit: k1-orangepi-r2s: fix maximum CPU core voltage On the OrangePi R2S board, the buck1 and buck2 voltage regulators, which supply the CPU core voltage, are configured with a maximum output voltage of 3.45V, while the highest operating point requires only 1.050V. This means that a kernel bug, OPP misconfiguration, or privileged userspace could request a voltage above the safe operating limit, causing possible permanent CPU damage. Set the maximum regulator voltage to 1.050V instead. Fixes: 793cc54475b4 ("riscv: dts: spacemit: enable PMIC on OrangePi R2S") Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net Cc: stable@vger.kernel.org Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729150722.1598630-6-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index 24591f7c3d23..2d1ba34cb00e 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -134,14 +134,14 @@ pmic@41 { regulators { buck1 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; buck2 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; From a65e9b73b0f0f33078b63f039b3ff64af051a11f Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 17:02:23 +0200 Subject: [PATCH 681/864] riscv: dts: spacemit: k1-bananapi-cm6: fix maximum CPU core voltage On the Banana Pi BPI-CM6 module, the buck1 and buck2 voltage regulators, which supply the CPU core voltage, are configured with a maximum output voltage of 3.45V, while the highest operating point requires only 1.050V. This means that a kernel bug, OPP misconfiguration, or privileged userspace could request a voltage above the safe operating limit, causing possible permanent CPU damage. Set the maximum regulator voltage to 1.050V instead. Fixes: 46a8c01700ac ("riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board") Link: https://sashiko.dev/#/message/20260728211020.1248676-2-aurelien%40aurel32.net Signed-off-by: Aurelien Jarno Reviewed-by: Yixun Lan Link: https://patch.msgid.link/20260729150722.1598630-7-aurelien@aurel32.net Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi index bf502c87040a..81c40df2a366 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi @@ -114,14 +114,14 @@ pmic@41 { regulators { buck1 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; buck2 { regulator-min-microvolt = <500000>; - regulator-max-microvolt = <3450000>; + regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; regulator-always-on; }; From e273d298b74ea63d5d586bd50240f919a9c33fb3 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 29 Jul 2026 18:00:28 +0200 Subject: [PATCH 682/864] riscv: dts: spacemit: Add cpu scaling for Milk-V Jupiter Enable CPU DVFS on Milk-V Jupiter by including the OPP tables and wiring the CPU nodes to the CPU regulator supply. Reviewed-by: Yixun Lan Signed-off-by: Aurelien Jarno Link: https://patch.msgid.link/20260729160749.1621415-2-aurelien@aurel32.net Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index c76b91ecb914..635e95aad14a 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -5,6 +5,7 @@ */ #include "k1.dtsi" +#include "k1-opp.dtsi" #include "k1-pinctrl.dtsi" / { @@ -107,6 +108,38 @@ &combo_phy { status = "okay"; }; +&cpu_0 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_1 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_2 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_3 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_4 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_5 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_6 { + cpu-supply = <&buck1_0v9>; +}; + +&cpu_7 { + cpu-supply = <&buck1_0v9>; +}; + &emmc { bus-width = <8>; mmc-hs400-1_8v; @@ -209,7 +242,7 @@ pmic@41 { dldoin2-supply = <&buck5>; regulators { - buck1 { + buck1_0v9: buck1 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; regulator-ramp-delay = <5000>; From c8748463283738aacf323eb3f7853e6533d941dc Mon Sep 17 00:00:00 2001 From: Stanislav Zaikin Date: Thu, 30 Jul 2026 10:54:21 +0200 Subject: [PATCH 683/864] arm64: dts: qcom: taoyao: Drop adsp_rpc_remote_heap_mem override taoyao originally redefined adsp_rpc_remote_heap_mem at a fixed address to avoid overlapping with cdsp_mem, since kodiak.dtsi's version was a fixed-address at the time. kodiak.dtsi now defines adsp_rpc_remote_heap_mem as a dynamically allocated "shared-dma-pool" region instead, which removes the fixed address entirely and so cannot overlap with cdsp_mem. This makes the override unnecessary. Remove the taoyao-local /delete-node/ and static reg-based redefinition, and inherit the definition from kodiak.dtsi instead. Fixes: 28705df5d0df ("arm64: dts: qcom: sm7325: Add Xiaomi 12 Lite 5G (taoyao) DTS") Signed-off-by: Stanislav Zaikin Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260730085422.631896-1-zstaseg@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts index 6f8bc65bb99b..87f267aaeec0 100644 --- a/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts +++ b/arch/arm64/boot/dts/qcom/sm7325-xiaomi-taoyao.dts @@ -27,7 +27,6 @@ /* The following reserved memory regions have different addresses or sizes */ /delete-node/ &adsp_mem; -/delete-node/ &adsp_rpc_remote_heap_mem; /delete-node/ &cdsp_mem; /delete-node/ &rmtfs_mem; @@ -203,11 +202,6 @@ neuron_block_1_mem: neuron-block@d7f80000 { no-map; }; - adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@e0400000 { - reg = <0x0 0xe0400000 0x0 0x800000>; - no-map; - }; - framebuffer_reserved: framebuffer@e1000000 { reg = <0x0 0xe1000000 0x0 (1080 * 2400 * 4)>; no-map; From 882bb27c61610f16e54caa2dc75bacf977f614c9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 17 Apr 2026 09:07:46 +0200 Subject: [PATCH 684/864] arm64: dts: qcom: milos: Add GX clock controller Add a node for the GX clock controller, which provides a power domain to consumers. Reviewed-by: Konrad Dybcio Reviewed-by: Jagadeesh Kona Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20260417-milos-gxclkctl-v3-3-08f5988c43a2@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi index e91c0cf5e093..aad8bf678916 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1591,6 +1591,16 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + gxclkctl: clock-controller@3d64000 { + compatible = "qcom,milos-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + + power-domains = <&rpmhpd RPMHPD_GFX>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells = <1>; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,milos-gpucc"; reg = <0x0 0x03d90000 0x0 0x9800>; From 58ce9a2b9099bb26aed55d4e350c32af94930532 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 12:59:58 +0200 Subject: [PATCH 685/864] arm64: dts: qcom: msm8998: Don't pull-up I2C pins by default in sleep When the I2C controller is disabled, no communication is expected to take place. Without traffic on the bus, the pull-up is unnecessary. Both the vendor kernel for this platform and DTs of other SoCs in upstream concur this logic. Change the default and clean up now-NOP overrides. Fixes: 0fee55fc0de7 ("arm64: dts: qcom: msm8998: Add I2C pinctrl and fix BLSP2_I2C naming") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-1-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ---- .../boot/dts/qcom/msm8998-xiaomi-sagit.dts | 5 ---- arch/arm64/boot/dts/qcom/msm8998.dtsi | 24 +++++++++---------- 3 files changed, 12 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 3650f2501886..04d4741cdb5f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -229,10 +229,6 @@ rmi4-f11@11 { }; }; -&blsp1_i2c5_sleep { - bias-disable; -}; - &blsp1_uart3 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index 30222f6608da..69528771eda2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -217,11 +217,6 @@ rmi4-f1a@1a { }; }; -&blsp1_i2c5_sleep { - /delete-property/ bias-pull-up; - bias-disable; -}; - &blsp1_uart3 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 347706011637..5038d0009c1a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1183,7 +1183,7 @@ blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { pins = "gpio2", "gpio3"; function = "blsp_i2c1"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c2_default: blsp1-i2c2-default-state { @@ -1197,7 +1197,7 @@ blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { pins = "gpio32", "gpio33"; function = "blsp_i2c2"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c3_default: blsp1-i2c3-default-state { @@ -1211,7 +1211,7 @@ blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c4_default: blsp1-i2c4-default-state { @@ -1225,7 +1225,7 @@ blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { pins = "gpio10", "gpio11"; function = "blsp_i2c4"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c5_default: blsp1-i2c5-default-state { @@ -1239,7 +1239,7 @@ blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { pins = "gpio87", "gpio88"; function = "blsp_i2c5"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_i2c6_default: blsp1-i2c6-default-state { @@ -1253,7 +1253,7 @@ blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { pins = "gpio43", "gpio44"; function = "blsp_i2c6"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp1_spi_b_default: blsp1-spi-b-default-state { @@ -1318,7 +1318,7 @@ blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c2_default: blsp2-i2c2-default-state { @@ -1332,7 +1332,7 @@ blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c3_default: blsp2-i2c3-default-state { @@ -1346,7 +1346,7 @@ blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c4_default: blsp2-i2c4-default-state { @@ -1360,7 +1360,7 @@ blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { pins = "gpio67", "gpio68"; function = "blsp_i2c10"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c5_default: blsp2-i2c5-default-state { @@ -1374,7 +1374,7 @@ blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_i2c6_default: blsp2-i2c6-default-state { @@ -1388,7 +1388,7 @@ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { pins = "gpio83", "gpio84"; function = "blsp_i2c12"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; blsp2_spi1_default: blsp2-spi1-default-state { From bd0bb7d97773026c9f5d5f8ff1dcf987f8051045 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 12:59:59 +0200 Subject: [PATCH 686/864] arm64: dts: qcom: msm8976-longcheer-l9360: Fix accidental node override The active and sleep pinctrl states for the touchscreen interrupt pin shared the same node name, creating a single node, accidentally overridden immediately after the definition. Alter the names to make them distinct and to silence DT checker warnings. Fixes: 79b896e7da7e ("arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-2-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts index 18832a3b9a1c..57f549f06f73 100644 --- a/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts +++ b/arch/arm64/boot/dts/qcom/msm8976-longcheer-l9360.dts @@ -455,14 +455,14 @@ sdc2_cd_sleep: sdc2-cd-sleep-state { bias-disable; }; - ts_int_default: ts-int-state { + ts_int_default: ts-int-default-state { pins = "gpio65"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - ts_int_sleep: ts-int-state { + ts_int_sleep: ts-int-sleep-state { pins = "gpio65"; function = "gpio"; drive-strength = <2>; From c82ea31fb783d9ce4080eca1a7bb855f4648fc28 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 13:00:00 +0200 Subject: [PATCH 687/864] arm64: dts: qcom: sdm632-motorola-ocean: Fix LED default trigger property The correct property name is "linux,default-trigger", not "default-trigger". Fix it to avoid DT checker warnings and let the OSes consume the intended information. Fixes: 3176c4d6b9be ("arm64: dts: qcom: sdm632: Add device tree for Motorola G7 Power") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-3-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts index 2f55db0c8ce3..9ea3e5e76bf9 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dts @@ -130,7 +130,7 @@ led-controller@36 { led: led@1 { reg = <1>; - default-trigger = "backlight"; + linux,default-trigger = "backlight"; function = LED_FUNCTION_BACKLIGHT; led-sources = <0 1 2>; }; From a3b31d7e12e60f40cd4ea1f54126c38dd666fbe4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 13:00:01 +0200 Subject: [PATCH 688/864] arm64: dts: qcom: qcs8300-ride: Fix BT RFA supply name Fix up the supply name to align with qcom,wcn6855-bt bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-4-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index e9a8553a8d82..1ff39530ea3d 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -837,7 +837,7 @@ bluetooth: bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From c680d03c73d17235b8e5fdaa9086e35c15855146 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 17 Jul 2026 13:00:02 +0200 Subject: [PATCH 689/864] arm64: dts: qcom: talos-evk-som: Fix BT RFA supply name Fix up the supply name to align with qcom,wcn6855-bt bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260717-topic-june26_dts_fixes-v2-5-797cd46e5d9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 6d2cff3cf23c..a057a7271480 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -535,7 +535,7 @@ bluetooth { vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; }; }; From 9812d0a3077489f67afaca84dcc7e01a440ee106 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 23 Jul 2026 13:47:04 +0530 Subject: [PATCH 690/864] arm64: dts: qcom: qcs404: Fix DTBS Check errors in usb controller nodes The following errors pop up when DTBS check is done for qcs404 based platforms: arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@79b8800 (qcom,qcs404- dwc3): interrupt-names:1: 'qusb2_phy' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@79b8800 (qcom,qcs404- dwc3): interrupt-names:2: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@7678800 (qcom,qcs404- dwc3): interrupt-names:2: 'hs_phy_irq' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb: usb@7678800 (qcom,qcs404- dwc3): interrupt-names:1: 'qusb2_phy' was expected from schema $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml Modify ordering of hs_phy and qusb2_phy interrupts to fix the errors. Fixes: 927173bf8a0e ("arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332") Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260723-qcs404_dtbs_fix-v1-1-c9ca0dd69f23@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 4328c1dda898..736accfc34f9 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -677,11 +677,11 @@ usb3: usb@7678800 { assigned-clock-rates = <19200000>, <200000000>; interrupts = , - , - ; + , + ; interrupt-names = "pwr_event", - "hs_phy_irq", - "qusb2_phy"; + "qusb2_phy", + "hs_phy_irq"; status = "disabled"; @@ -716,11 +716,11 @@ usb2: usb@79b8800 { assigned-clock-rates = <19200000>, <133333333>; interrupts = , - , - ; + , + ; interrupt-names = "pwr_event", - "hs_phy_irq", - "qusb2_phy"; + "qusb2_phy", + "hs_phy_irq"; status = "disabled"; From 0cd1b39cf234321fb5c2450dc788ef296cb02cb2 Mon Sep 17 00:00:00 2001 From: Rakesh Kota Date: Wed, 22 Jul 2026 16:01:55 +0530 Subject: [PATCH 691/864] arm64: dts: qcom: Update spmi-pmic-arb interrupt trigger for shikra SPMI interrupts are not working after suspend/resume on Shikra. Update the spmi-pmic-arb top-level interrupt trigger type from IRQ_TYPE_EDGE_RISING to IRQ_TYPE_LEVEL_HIGH, as recommended by the hardware design team. Signed-off-by: Rakesh Kota Link: https://lore.kernel.org/r/20260722-fix_shikra_spmi_interrupt_trigger_type-v1-1-1f8a13528cd7@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4e5bc9e17c8e..80e8045282d8 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -511,7 +511,7 @@ spmi_bus: spmi@1c40000 { "obsrvr", "intr", "cnfg"; - interrupts-extended = <&mpm 86 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "periph_irq"; interrupt-controller; #interrupt-cells = <4>; From 67b5818ecadeb75e29c14add973b8cada2a73788 Mon Sep 17 00:00:00 2001 From: Pradyot Kumar Nayak Date: Fri, 17 Jul 2026 17:28:35 +0530 Subject: [PATCH 692/864] arm64: dts: qcom: glymur-crd: Add FocalTech ft3d81 touchscreen support The touchscreen module on Glymur/Mahua CRDs is different from the one used on Hamoa CRDs and requires the reset-gpios to be wired to the device. Without this in place the reset line will remain permanently asserted during resume leaving the device offline and causing all I2C transactions to fail with -ENXIO. i2c_hid_of 3-0038: failed to change power setting. i2c_hid_of 3-0038: PM: dpm_run_callback(): i2c_hid_core_pm_resume [i2c_hid] returns -6 i2c_hid_of 3-0038: PM: failed to resume async: error -6 The touchscreen on Glymur/Mahua-CRD is a focaltech ft3d81, which is hardware-compatible with the ft8112. we have added the required change in DT. Fixes: e6bf559f7eb9 ("arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen") Fixes: f64ef325f1d9 ("arm64: dts: glymur-crd: Add reset GPIO to touchscreen node") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Pradyot Kumar Nayak Link: https://lore.kernel.org/r/20260717-add_focaltech_ft3d81_touchscreen_support-v4-2-5dd091e25801@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index ddf9902e1c4f..22f8011eb447 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -679,14 +679,13 @@ &i2c8 { status = "okay"; touchscreen@38 { - compatible = "hid-over-i2c"; + compatible = "focaltech,ft3d81", "focaltech,ft8112"; reg = <0x38>; - hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; - vdd-supply = <&vreg_misc_3p3>; - vddl-supply = <&vreg_l15b_e0_1p8>; + vcc33-supply = <&vreg_misc_3p3>; + vccio-supply = <&vreg_l15b_e0_1p8>; reset-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; From e806c63ba51a70aa8e19f749eb36b4d81760f705 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 12:32:37 +0200 Subject: [PATCH 693/864] arm64: dts: qcom: Rename pci@ nodes to pcie@ PCIe hosts/devices commonly use the 'pcie' for their node name to reflect they're not legacy PCI. Every couple months someone comes around to clean this up because people keep introducing new uses of 'pci@'. Seems like it's my turn now, so do that for RCs and the downstream devices (switches etc.) defined in board files. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260701-topic-dts_pci_pcie-v1-1-aab8de213b39@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/hamoa.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts | 4 ++-- arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/monaco.dtsi | 4 ++-- .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 8 ++++---- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++-- 9 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 6356f977f720..72c23aef1207 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2827,7 +2827,7 @@ pcie_west_slv_noc: interconnect@1920000 { #interconnect-cells = <2>; }; - pcie4: pci@1bf0000 { + pcie4: pcie@1bf0000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01bf0000 0x0 0x3000>, @@ -3043,7 +3043,7 @@ pcie4_phy: phy@1bf6000 { status = "disabled"; }; - pcie5: pci@1b40000 { + pcie5: pcie@1b40000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01b40000 0x0 0x3000>, @@ -3315,7 +3315,7 @@ pcie5_phy: phy@1b50000 { status = "disabled"; }; - pcie6: pci@1c00000 { + pcie6: pcie@1c00000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01c00000 0x0 0x3000>, @@ -3531,7 +3531,7 @@ pcie6_phy: phy@1c06000 { status = "disabled"; }; - pcie3b: pci@1b80000 { + pcie3b: pcie@1b80000 { device_type = "pci"; compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; reg = <0x0 0x01b80000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 09527dcf9576..86168e445340 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3404,7 +3404,7 @@ pcie3_phy: phy@1be0000 { status = "disabled"; }; - pcie6a: pci@1bf8000 { + pcie6a: pcie@1bf8000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01bf8000 0 0x3000>, @@ -3547,7 +3547,7 @@ pcie6a_phy: phy@1bfc000 { status = "disabled"; }; - pcie5: pci@1c00000 { + pcie5: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01c00000 0 0x3000>, @@ -3684,7 +3684,7 @@ pcie5_phy: phy@1c06000 { status = "disabled"; }; - pcie4: pci@1c08000 { + pcie4: pcie@1c08000 { device_type = "pci"; compatible = "qcom,pcie-x1e80100"; reg = <0 0x01c08000 0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 44bd9b1a1765..4fc5f482a18f 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -271,7 +271,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -279,7 +279,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts index d1346ca5dd4e..299d0da15a15 100644 --- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts +++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts @@ -421,7 +421,7 @@ &pcie1 { &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pci@0,0 { + pcie@0,0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -429,7 +429,7 @@ pci@0,0 { ranges; reg = <0x010000 0x00 0x00 0x00 0x00>; - pci@2,0 { + pcie@2,0 { #address-cells = <3>; #size-cells = <2>; device_type = "pci"; diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index e6beb4393430..77c28c19d17a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -117,7 +117,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -125,7 +125,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index efe1e74fe509..a2daef463c3d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2256,7 +2256,7 @@ mmss_noc: interconnect@17a0000 { qcom,bcm-voters = <&apps_bcm_voter>; }; - pcie0: pci@1c00000 { + pcie0: pcie@1c00000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, @@ -2435,7 +2435,7 @@ pcie0_phy: phy@1c04000 { status = "disabled"; }; - pcie1: pci@1c10000 { + pcie1: pcie@1c10000 { device_type = "pci"; compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; reg = <0x0 0x01c10000 0x0 0x3000>, diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 83908db335af..937b63eae3ba 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -130,7 +130,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -138,7 +138,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -225,7 +225,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -233,7 +233,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e9a932c90d14..1acbfe7baa13 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -954,7 +954,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -962,7 +962,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index c8eed8ba93f5..4f6932dd1139 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -790,7 +790,7 @@ pcie@3,0 { ranges; bus-range = <0x5 0xff>; - pci@0,0 { + pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; @@ -798,7 +798,7 @@ pci@0,0 { ranges; }; - pci@0,1 { + pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; From 91721a3f37ab4caf8441f0205497bcd478315433 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 17:43:15 +0200 Subject: [PATCH 694/864] arm64: dts: qcom: sc8280xp-crd: Add pmic-glink orientation GPIOs The PMIC_GLINK USB-C setup on SC8280XP requires that an orientation GPIO is passed for each port, the value of which communicates the normal/reversed state of the plug. Add the missing references to let the OS access that information. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260701-topic-8280crd_fixups-v1-1-3fe92ee9636b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 67f0576f2824..b8b5cf217764 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -56,6 +56,8 @@ pmic-glink { #address-cells = <1>; #size-cells = <0>; + orientation-gpios = <&tlmm 166 GPIO_ACTIVE_HIGH>, + <&tlmm 49 GPIO_ACTIVE_HIGH>; connector@0 { compatible = "usb-c-connector"; From 0e05c183f3b97427f00d619132ba5984494f6886 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 1 Jul 2026 17:43:16 +0200 Subject: [PATCH 695/864] arm64: dts: qcom: sc8280xp-crd: Fix the pin index for misc_3p3_reg_en The correct pin is GPIO1. Fix it. Fixes: ccd3517faf18 ("arm64: dts: qcom: sc8280xp: Add reference device") Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260701-topic-8280crd_fixups-v1-2-3fe92ee9636b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index b8b5cf217764..1eea9d710d5b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -184,7 +184,7 @@ vreg_misc_3p3: regulator-misc-3p3 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>; + gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -921,7 +921,7 @@ kypd_vol_up_n: kypd-vol-up-n-state { }; misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio2"; + pins = "gpio1"; function = "normal"; }; }; From f1b63ded8bff1e6277a2b9f6e96c789ddcf90656 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:20 +0530 Subject: [PATCH 696/864] arm64: dts: qcom: ipq8074: move PCIe phys and PERST# to port node To align with the newer style of binding, move the phys, PERST# to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-1-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 10 ++++++++-- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 10 ++++++++-- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++-------- 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 5cf07caf4103..dea5ece600d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -54,12 +54,18 @@ &blsp1_uart5 { &pcie0 { status = "okay"; - perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie_qmp0 { diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 34e2f80514a3..f5c125e20ada 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -40,12 +40,18 @@ &blsp1_uart5 { &pcie0 { status = "okay"; - perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>; }; &pcie1 { status = "okay"; - perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; }; &pcie_qmp0 { diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 256e12cf6d54..75a5ae30d966 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -841,9 +841,6 @@ pcie1: pcie@10000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_qmp1>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ @@ -902,11 +899,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky"; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_qmp1>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -929,9 +928,6 @@ pcie0: pcie@20000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_qmp0>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ @@ -993,11 +989,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_s_sticky"; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_qmp0>; + #address-cells = <3>; #size-cells = <2>; ranges; From 1198b7ff1fdd2ae77ab2e5b3cddd4fa2aa9f38bd Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:21 +0530 Subject: [PATCH 697/864] arm64: dts: qcom: ipq6018: move PCIe phys to port node To align with the newer style of binding, move the phys property to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-2-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7866844cc09f..0701517275d4 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -889,9 +889,6 @@ pcie0: pcie@20000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_phy>; - phy-names = "pciephy"; - ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; @@ -956,6 +953,8 @@ pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From a95758e9718ad686e9e7e8addcc181bea853e5a2 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:22 +0530 Subject: [PATCH 698/864] arm64: dts: qcom: ipq5018: move PCIe phys and PERST# to port node To align with the newer style of binding, move the phys, PERST# to the port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-3-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 8 +++++--- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 12 +++++------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts index df3cbb7c79c4..33eef92b19b1 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -34,9 +34,6 @@ &pcie0 { pinctrl-0 = <&pcie0_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; - status = "okay"; }; @@ -44,6 +41,11 @@ &pcie0_phy { status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>; +}; + &sdhc_1 { pinctrl-0 = <&sdc_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index b5bfd5dcabad..4fc627b47fe7 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -758,9 +758,6 @@ pcie1: pcie@80000000 { /* The controller supports Gen3, but the connected PHY is Gen2-capable */ max-link-speed = <2>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - ranges = <0x01000000 0 0x00000000 0x80200000 0 0x00100000>, <0x02000000 0 0x80300000 0x80300000 0 0x10000000>; @@ -829,6 +826,8 @@ pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -859,9 +858,6 @@ pcie0: pcie@a0000000 { /* The controller supports Gen3, but the connected PHY is Gen2-capable */ max-link-speed = <2>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>, <0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>; @@ -925,11 +921,13 @@ pcie0: pcie@a0000000 { status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; From b99a594cfdd0862709ec54bdc356360e332377f6 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:23 +0530 Subject: [PATCH 699/864] arm64: dts: qcom: ipq9574: Add PCIe bridge node The PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, to align with the newer style of binding, move the phys and perst to port node. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-4-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/ipq9574-rdp433-common.dtsi | 39 ++++++++----- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 56 ++++++++++++++++--- 2 files changed, 72 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi index 3422058ac480..ad3a82c50e22 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433-common.dtsi @@ -6,16 +6,26 @@ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ -&pcie1_phy { - status = "okay"; -}; - &pcie1 { pinctrl-0 = <&pcie1_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1_port0 { + reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + pinctrl-0 = <&pcie2_default>; + pinctrl-names = "default"; + status = "okay"; }; @@ -23,12 +33,15 @@ &pcie2_phy { status = "okay"; }; -&pcie2 { - pinctrl-0 = <&pcie2_default>; +&pcie2_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; +}; + +&pcie3 { + pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; - perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -36,13 +49,9 @@ &pcie3_phy { status = "okay"; }; -&pcie3 { - pinctrl-0 = <&pcie3_default>; - pinctrl-names = "default"; - - perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; +&pcie3_port0 { + reset-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; - status = "okay"; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 451c2076f6a7..5a5bda5f21a1 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -1004,12 +1004,22 @@ pcie1: pcie@10000000 { "aux", "ahb"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie1_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie1_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3: pcie@18000000 { @@ -1092,12 +1102,22 @@ pcie3: pcie@18000000 { "aux", "ahb"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie3_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie3_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2: pcie@20000000 { @@ -1180,12 +1200,22 @@ pcie2: pcie@20000000 { "aux", "ahb"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie2_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie2_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0: pcie@28000000 { @@ -1267,12 +1297,22 @@ pcie0: pcie@28000000 { "aux", "ahb"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; interconnect-names = "pcie-mem", "cpu-pcie"; status = "disabled"; + + pcie0_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie0_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; nsscc: clock-controller@39b00000 { From 1290c03dc2d1e45928b427c616bc24a536e7601a Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 10:11:24 +0530 Subject: [PATCH 700/864] arm64: dts: qcom: ipq9574: enable the PCIe support on RDP454 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the PCIe0 (x1) and PCIe2 (x2) instances to connect QCN92xx Wi‑Fi cards. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260714-pcie_move_to_new_binding-v1-5-6bb25887a0dc@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts | 80 +++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts index f2334b9e0ed4..146422aede7d 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp454.dts @@ -18,3 +18,83 @@ / { &qpic_nand { status = "okay"; }; + +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0_port0 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + pinctrl-0 = <&pcie2_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie2_phy { + status = "okay"; +}; + +&pcie2_port0 { + reset-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; +}; + +&tlmm { + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio22"; + function = "pcie0_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio24"; + function = "pcie0_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie2_default: pcie2-default-state { + clkreq-n-pins { + pins = "gpio28"; + function = "pcie2_clk"; + drive-strength = <6>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio29"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; + + wake-n-pins { + pins = "gpio30"; + function = "pcie2_wake"; + drive-strength = <6>; + bias-pull-up; + }; + }; +}; From 95f827ceb21e2885f40eec5d93a340abbcc22d13 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 15 Jul 2026 18:31:30 +0530 Subject: [PATCH 701/864] arm64: dts: qcom: x1e80100: Add deepest idle state CPU subsystem deepest idle state can lead SoC to low power mode like CxPC (chip rail power collapse). SoC deepest low power mode requires the PDC interrupt controller to wake up the SoC as the GIC interrupt controller is on Cx (chip rail) and will not be functional to wake up the CPU. PDC monitors both direct SPI interrupts and GPIOs used as interrupts in SoC low power mode. Further all wake up capable interrupts gets routed via PDC to GIC when SoC is out of low power mode. The wake up capable GPIOs used as interrupts were by passing PDC on x1e with commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now") as a result CPU deepest idle state was not added so far. The blocker for enabling deepest idle state was GPIO IRQ wakeup support. The x1e80100 PDC can operate in two modes: pass-through mode (GPIO IRQs forwarded directly to GIC without latching at PDC) and secondary controller mode (PDC latches GPIO IRQs and sends them as level IRQs to GIC). All the SoCs on Linux so far worked in pass-through mode of PDC. On some x1e boards the firmware configures the PDC in secondary controller mode, which caused GPIO interrupt storms as the level latched at PDC gets never cleared. The secondary mode is originally a requirement for windows SW platforms (which could not work with all types of interrupts and require level interrupts for GPIOs). Initially shipped windows firmware did not have SCM interface to configure PDC back to pass-through mode if with such firmware Linux is booted up. PDC irqchip has got secondary mode and SCM interface support to configure PDC irqchip mode to pass-through mode on newer firmware where SCM interface is available and for older firmware on which SCM interface is not present PDC irqchip works in secondary irqchip mode [1]. Above mentioned commit is also reverted via [1]. With PDC now working on older firmware as well add the CPU deepest idle state domain_ss3. The newly added domain_ss3 state has entry/exit latencies of 2500 us. The shallower cluster_cl5 state had entry/exit latencies of 2200/4000 us which are higher than the deeper state. This create an inconsistency that would confuse the idle governor. Correct cluster_cl5 latencies to 2000 us each to match production configuration values. [1] https://lore.kernel.org/linux-arm-msm/20260707-hamoa_pdc_v3-v4-0-dfd1f4a3ae89@oss.qualcomm.com/#t Tested-by: Daniel J Blueman Signed-off-by: Maulik Shah Link: https://lore.kernel.org/r/20260715-hamoa_pdc_v3-v5-1-00440cfaf711@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 86168e445340..8a96ea1bdb9c 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -300,10 +300,18 @@ cluster_cl4: cluster-sleep-0 { cluster_cl5: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x01000054>; - entry-latency-us = <2200>; - exit-latency-us = <4000>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; min-residency-us = <7000>; }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2500>; + exit-latency-us = <2500>; + min-residency-us = <9000>; + }; }; }; @@ -462,7 +470,7 @@ cluster_pd2: power-domain-cpu-cluster2 { system_pd: power-domain-system { #power-domain-cells = <0>; - /* TODO: system-wide idle states */ + domain-idle-states = <&domain_ss3>; }; }; From a44338975cf80aa0aed629f5c6495aa18250897f Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Sat, 18 Jul 2026 15:21:25 +0000 Subject: [PATCH 702/864] arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add vbus-supply in Type-C connector VBUS supply property was moved from pmi632 typec node to USB-C connector. This fixes the following warning in kernel message. pmic@2:typec@1500: supply vdd-vbus not found, using dummy regulator Fixes: c1da9374c3e0 ("arm64: dts: qcom: sm6125-xiaomi-ginkgo: Add PMI632 Type-C property") Signed-off-by: Biswapriyo Nath Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260718-ginkgo-vbus-typec-v1-1-d5ed0aa6b78b@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi index a5458ab41629..59042a593753 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo-common.dtsi @@ -133,6 +133,8 @@ connector { typec-power-opmode = "default"; pd-disable; + vbus-supply = <&pmi632_vbus>; + port { pmi632_hs_in: endpoint { remote-endpoint = <&usb_dwc3_hs>; From 8ed8ee7499f2de55e3f63457936aaeb0ccbe0d72 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 21 Jul 2026 19:11:26 +0200 Subject: [PATCH 703/864] dt-bindings: arm: qcom: Add Asus Zenbook A16 (UX3607OA) UX3607OA is a variant of the Asus Zenbook A16 built on the Qualcomm Glymur platform. It comes with an 18-core X2 Elite Extreme SoC, 48GiB of RAM, NVMe storage, a 2880 x 1800 OLED screen, and the other typical Glymur platform capabilities. The hardware wiring is very different versus the 14" SKU. Add a compatible for this machine. [1] https://www.asus.com/us/laptops/for-home/zenbook/asus-zenbook-a16-ux3607/techspec/ Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260721-topic-a16_submission-v1-1-8ea213130d05@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f8c37096df46..f8ee354070d0 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -86,6 +86,7 @@ properties: - items: - enum: + - asus,zenbook-a16-ux3607oa - qcom,glymur-crd - const: qcom,glymur From 1c2935b75f78fa74ef9cc37d95c4f734cbc0c15f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 23 Jul 2026 13:48:44 +0200 Subject: [PATCH 704/864] arm64: dts: monaco: Fix CSI I2C controllers default bus frequency 1 MHz is quite fast for an I2C bus and not necessarly reliable, change this to 400 KHz which is a more reasonable default. Signed-off-by: Hans de Goede Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260723114844.63093-1-johannes.goede@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index a2daef463c3d..0e484b704fda 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -5475,14 +5475,14 @@ cci0: cci@ac13000 { cci0_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci0_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5512,14 +5512,14 @@ cci1: cci@ac14000 { cci1_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci1_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; @@ -5549,14 +5549,14 @@ cci2: cci@ac15000 { cci2_i2c0: i2c-bus@0 { reg = <0>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; cci2_i2c1: i2c-bus@1 { reg = <1>; - clock-frequency = <1000000>; + clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; }; From e78c5e9d79e3c024e9b80ec067e62477c29aa29f Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 23 Jul 2026 23:02:25 +0530 Subject: [PATCH 705/864] arm64: dts: qcom: glymur: Fix properties of usb_hs node The High-speed only controller is DRD capable. Hence move the dr_mode property to platform DTS and mark the controller as role switch capable. While at it, since its high-speed only controller, disable pipe clock requirement. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260723-glymur-usb-fixes-v1-1-816357d5319c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 2 ++ arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 22f8011eb447..47fa3ae301ac 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -1208,6 +1208,8 @@ &usb_1_qmpphy_out { }; &usb_hs { + dr_mode = "host"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 72c23aef1207..e6dfd196bd52 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4838,10 +4838,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - dr_mode = "host"; - maximum-speed = "high-speed"; + qcom,select-utmi-as-pipe-clk; + usb-role-switch; + status = "disabled"; }; From 5ac32106d3c2ea94abd236fe3ad3897925640289 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Thu, 23 Jul 2026 23:02:26 +0530 Subject: [PATCH 706/864] arm64: dts: qcom: glymur: Configure USB controllers are wakeup-capable All USB controller on Glymur are wakeup-capable device. Add wakeup-source property for each of them indicating the same. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260723-glymur-usb-fixes-v1-2-816357d5319c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index e6dfd196bd52..8708416451a4 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -4603,6 +4603,7 @@ usb_0: usb@a600000 { snps,dis_enblslpm_quirk; usb-role-switch; + wakeup-source; status = "disabled"; @@ -4678,6 +4679,7 @@ usb_1: usb@a800000 { snps,dis_enblslpm_quirk; usb-role-switch; + wakeup-source; status = "disabled"; @@ -4753,6 +4755,7 @@ usb_2: usb@a000000 { snps,dis_enblslpm_quirk; usb-role-switch; + wakeup-source; status = "disabled"; @@ -4842,6 +4845,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, qcom,select-utmi-as-pipe-clk; usb-role-switch; + wakeup-source; status = "disabled"; }; @@ -4913,6 +4917,7 @@ usb_mp: usb@a400000 { snps,dis_enblslpm_quirk; dr_mode = "host"; + wakeup-source; status = "disabled"; }; From e418346f4eb314a4b11fc7eb46cf2b4825d15aee Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 28 Jul 2026 21:19:41 +0530 Subject: [PATCH 707/864] arm64: dts: qcom: Add header file for ADC5 Gen3 channel macros Add macro definitions for virtual channels (combination of ADC channel number and PMIC SID number), to be used in devicetree by clients of ADC5 GEN3 device and in the "reg" property of ADC channels. Reviewed-by: Konrad Dybcio Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-1-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h diff --git a/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h new file mode 100644 index 000000000000..aa8e54d7e786 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcom-adc5-gen3.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_ARM64_QCOM_ADC5_GEN3_H__ +#define __DTS_ARM64_QCOM_ADC5_GEN3_H__ + +/* ADC channels for PMIC5 Gen3 */ + +#define VIRT_CHAN(sid, chan) ((sid) << 8 | (chan)) + +#define ADC5_GEN3_REF_GND(sid) VIRT_CHAN(sid, 0x00) +#define ADC5_GEN3_1P25VREF(sid) VIRT_CHAN(sid, 0x01) +#define ADC5_GEN3_VREF_VADC(sid) VIRT_CHAN(sid, 0x02) +#define ADC5_GEN3_DIE_TEMP(sid) VIRT_CHAN(sid, 0x03) + +#define ADC5_GEN3_AMUX1_THM(sid) VIRT_CHAN(sid, 0x04) +#define ADC5_GEN3_AMUX2_THM(sid) VIRT_CHAN(sid, 0x05) +#define ADC5_GEN3_AMUX3_THM(sid) VIRT_CHAN(sid, 0x06) +#define ADC5_GEN3_AMUX4_THM(sid) VIRT_CHAN(sid, 0x07) +#define ADC5_GEN3_AMUX5_THM(sid) VIRT_CHAN(sid, 0x08) +#define ADC5_GEN3_AMUX6_THM(sid) VIRT_CHAN(sid, 0x09) +#define ADC5_GEN3_AMUX1_GPIO(sid) VIRT_CHAN(sid, 0x0a) +#define ADC5_GEN3_AMUX2_GPIO(sid) VIRT_CHAN(sid, 0x0b) +#define ADC5_GEN3_AMUX3_GPIO(sid) VIRT_CHAN(sid, 0x0c) +#define ADC5_GEN3_AMUX4_GPIO(sid) VIRT_CHAN(sid, 0x0d) + +#define ADC5_GEN3_CHG_TEMP(sid) VIRT_CHAN(sid, 0x10) +#define ADC5_GEN3_USB_SNS_V_16(sid) VIRT_CHAN(sid, 0x11) +#define ADC5_GEN3_VIN_DIV16_MUX(sid) VIRT_CHAN(sid, 0x12) +#define ADC5_GEN3_VREF_BAT_THERM(sid) VIRT_CHAN(sid, 0x15) +#define ADC5_GEN3_IIN_FB(sid) VIRT_CHAN(sid, 0x17) +#define ADC5_GEN3_TEMP_ALARM_LITE(sid) VIRT_CHAN(sid, 0x18) +#define ADC5_GEN3_IIN_SMB(sid) VIRT_CHAN(sid, 0x19) +#define ADC5_GEN3_ICHG_SMB(sid) VIRT_CHAN(sid, 0x1b) +#define ADC5_GEN3_ICHG_FB(sid) VIRT_CHAN(sid, 0xa1) + +/* 30k pull-up */ +#define ADC5_GEN3_AMUX1_THM_30K_PU(sid) VIRT_CHAN(sid, 0x24) +#define ADC5_GEN3_AMUX2_THM_30K_PU(sid) VIRT_CHAN(sid, 0x25) +#define ADC5_GEN3_AMUX3_THM_30K_PU(sid) VIRT_CHAN(sid, 0x26) +#define ADC5_GEN3_AMUX4_THM_30K_PU(sid) VIRT_CHAN(sid, 0x27) +#define ADC5_GEN3_AMUX5_THM_30K_PU(sid) VIRT_CHAN(sid, 0x28) +#define ADC5_GEN3_AMUX6_THM_30K_PU(sid) VIRT_CHAN(sid, 0x29) +#define ADC5_GEN3_AMUX1_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2a) +#define ADC5_GEN3_AMUX2_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2b) +#define ADC5_GEN3_AMUX3_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2c) +#define ADC5_GEN3_AMUX4_GPIO_30K_PU(sid) VIRT_CHAN(sid, 0x2d) + +/* 100k pull-up */ +#define ADC5_GEN3_AMUX1_THM_100K_PU(sid) VIRT_CHAN(sid, 0x44) +#define ADC5_GEN3_AMUX2_THM_100K_PU(sid) VIRT_CHAN(sid, 0x45) +#define ADC5_GEN3_AMUX3_THM_100K_PU(sid) VIRT_CHAN(sid, 0x46) +#define ADC5_GEN3_AMUX4_THM_100K_PU(sid) VIRT_CHAN(sid, 0x47) +#define ADC5_GEN3_AMUX5_THM_100K_PU(sid) VIRT_CHAN(sid, 0x48) +#define ADC5_GEN3_AMUX6_THM_100K_PU(sid) VIRT_CHAN(sid, 0x49) +#define ADC5_GEN3_AMUX1_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4a) +#define ADC5_GEN3_AMUX2_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4b) +#define ADC5_GEN3_AMUX3_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4c) +#define ADC5_GEN3_AMUX4_GPIO_100K_PU(sid) VIRT_CHAN(sid, 0x4d) + +/* 400k pull-up */ +#define ADC5_GEN3_AMUX1_THM_400K_PU(sid) VIRT_CHAN(sid, 0x64) +#define ADC5_GEN3_AMUX2_THM_400K_PU(sid) VIRT_CHAN(sid, 0x65) +#define ADC5_GEN3_AMUX3_THM_400K_PU(sid) VIRT_CHAN(sid, 0x66) +#define ADC5_GEN3_AMUX4_THM_400K_PU(sid) VIRT_CHAN(sid, 0x67) +#define ADC5_GEN3_AMUX5_THM_400K_PU(sid) VIRT_CHAN(sid, 0x68) +#define ADC5_GEN3_AMUX6_THM_400K_PU(sid) VIRT_CHAN(sid, 0x69) +#define ADC5_GEN3_AMUX1_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6a) +#define ADC5_GEN3_AMUX2_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6b) +#define ADC5_GEN3_AMUX3_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6c) +#define ADC5_GEN3_AMUX4_GPIO_400K_PU(sid) VIRT_CHAN(sid, 0x6d) + +/* 1/3 Divider */ +#define ADC5_GEN3_AMUX1_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8a) +#define ADC5_GEN3_AMUX2_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8b) +#define ADC5_GEN3_AMUX3_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8c) +#define ADC5_GEN3_AMUX4_GPIO_DIV3(sid) VIRT_CHAN(sid, 0x8d) + +#define ADC5_GEN3_VPH_PWR(sid) VIRT_CHAN(sid, 0x8e) +#define ADC5_GEN3_VBAT_SNS_QBG(sid) VIRT_CHAN(sid, 0x8f) + +#define ADC5_GEN3_VBAT_SNS_CHGR(sid) VIRT_CHAN(sid, 0x94) +#define ADC5_GEN3_VBAT_2S_MID_QBG(sid) VIRT_CHAN(sid, 0x96) +#define ADC5_GEN3_VBAT_2S_MID_CHGR(sid) VIRT_CHAN(sid, 0x9d) + +#endif /* __DTS_ARM64_QCOM_ADC5_GEN3_H__ */ From 4a118c175bdd93198961320111642c66693ed26c Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 28 Jul 2026 21:19:42 +0530 Subject: [PATCH 708/864] arm64: dts: qcom: lemans-pmics: Add ADC support for PMM8654au Add ADC nodes for the four PMM8654au PMICs (pmm8654au_0 through pmm8654au_3) on the Lemans platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Also add the io-channels and io-channel-names properties under the temp-alarm nodes so that they can get temperature reading from the ADC die_temp channels. Signed-off-by: Ayyagari Ushasreevalli Reviewed-by: Konrad Dybcio Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-2-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-pmics.dtsi | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi index 341119fc8244..500f715931aa 100644 --- a/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-pmics.dtsi @@ -5,6 +5,7 @@ #include #include +#include "qcom-adc5-gen3.h" / { thermal-zones { @@ -110,6 +111,8 @@ pmm8654au_0_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_0_adc ADC5_GEN3_DIE_TEMP(0)>; + io-channel-names = "thermal"; }; pmm8654au_0_pon: pon@1200 { @@ -141,6 +144,27 @@ pmm8654au_0_rtc: rtc@6100 { interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; + pmm8654au_0_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@3 { + reg = ; + label = "pmm8654au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@8e { + reg = ; + label = "pmm8654au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8654au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -176,6 +200,29 @@ pmm8654au_1_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_1_adc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; + }; + + pmm8654au_1_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@203 { + reg = ; + label = "pmm8654au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@28e { + reg = ; + label = "pmm8654au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_1_gpios: gpio@8800 { @@ -200,6 +247,29 @@ pmm8654au_2_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_2_adc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; + }; + + pmm8654au_2_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x4 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@403 { + reg = ; + label = "pmm8654au_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@48e { + reg = ; + label = "pmm8654au_2_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_2_gpios: gpio@8800 { @@ -224,6 +294,29 @@ pmm8654au_3_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmm8654au_3_adc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; + }; + + pmm8654au_3_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x6 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@603 { + reg = ; + label = "pmm8654au_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@68e { + reg = ; + label = "pmm8654au_3_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; }; pmm8654au_3_gpios: gpio@8800 { From 198bb8bf8b9053cad7dfc6553c46d112ae2a9a34 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 28 Jul 2026 21:19:43 +0530 Subject: [PATCH 709/864] arm64: dts: qcom: monaco-pmics: Add ADC support for PMM8620AU Add ADC nodes for PMM8620AU PMIC instances (SID 0 and SID 2) present on the Monaco platform. Each ADC node exposes the following ADC channels: - DIE_TEMP: PMIC die temperature channel - VPH_PWR: Battery/supply voltage channel Signed-off-by: Ayyagari Ushasreevalli Tested-by: Loic Poulain Reviewed-by: Konrad Dybcio Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-3-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-pmics.dtsi | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi index e990d7367719..6e096b9b7546 100644 --- a/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-pmics.dtsi @@ -5,6 +5,7 @@ #include #include +#include "qcom-adc5-gen3.h" &spmi_bus { pmm8620au_0: pmic@0 { @@ -20,6 +21,27 @@ pmm8620au_0_rtc: rtc@6100 { interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; }; + pmm8620au_0_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x0 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@3 { + reg = ; + label = "pmm8620au_0_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@8e { + reg = ; + label = "pmm8620au_0_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8620au_0_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; @@ -37,6 +59,27 @@ pmm8650au_1: pmic@2 { #address-cells = <1>; #size-cells = <0>; + pmm8650au_1_adc: adc@8000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x8000>; + interrupts-extended = <&spmi_bus 0x2 0x80 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + channel@203 { + reg = ; + label = "pmm8650au_1_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@28e { + reg = ; + label = "pmm8650au_1_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + }; + pmm8650au_1_gpios: gpio@8800 { compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; reg = <0x8800>; From f969097d49663c1943b39c04f8e8b7c57bf8a456 Mon Sep 17 00:00:00 2001 From: Ayyagari Ushasreevalli Date: Tue, 28 Jul 2026 21:19:44 +0530 Subject: [PATCH 710/864] arm64: dts: qcom: hamoa-pmics: Add ADC support Add ADC node and define channels for: - Die temperature for PMK8550, PM8550VE* and PMC8380* PMICs. - PM8550: Die temperature, VPH power, and system thermistors. Add io-channels and io-channel-names properties to the temp_alarm nodes so that they can get temperature reading from the ADC die_temp channels. Remove die_temp channel of PMC8380_6 for Purwa boards where this PMIC is not present. Signed-off-by: Ayyagari Ushasreevalli Signed-off-by: Jishnu Prakash Link: https://lore.kernel.org/r/20260728-adc5_gen3_dt-v4-4-355f0edece77@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi | 158 ++++++++++++++++++ arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 1 + .../dts/qcom/x1p42100-asus-vivobook-s15.dts | 1 + .../dts/qcom/x1p42100-asus-zenbook-a14.dtsi | 1 + arch/arm64/boot/dts/qcom/x1p42100-crd.dts | 1 + .../dts/qcom/x1p42100-hp-omnibook-x14.dts | 1 + .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 1 + 7 files changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi index 6a31a0adf8be..17d754d57e18 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-pmics.dtsi @@ -6,7 +6,9 @@ #include #include #include +#include #include +#include "qcom-adc5-gen3.h" / { thermal-zones { @@ -277,6 +279,134 @@ pmk8550_pwm: pwm { status = "disabled"; }; + + pmk8550_vadc: adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts-extended = <&spmi_bus0 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <&spmi_bus0 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + pinctrl-0 = <&sys_therm_0_gpio3>, <&sys_therm_1_gpio4>; + pinctrl-names = "default"; + + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_therm_2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@145 { + reg = ; + label = "pm8550_therm_3"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@146 { + reg = ; + label = "pm8550_therm_4"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@147 { + reg = ; + label = "pm8550_therm_5"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@148 { + reg = ; + label = "pm8550_therm_6"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@14a { + reg = ; + label = "pm8550_gpio_01"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@14b { + reg = ; + label = "pm8550_gpio_02"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@203 { + reg = ; + label = "pm8550ve_2_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@303 { + reg = ; + label = "pmc8380_3_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@403 { + reg = ; + label = "pmc8380_4_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@503 { + reg = ; + label = "pmc8380_5_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmc8380_6_die_temp: channel@603 { + reg = ; + label = "pmc8380_6_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@803 { + reg = ; + label = "pm8550ve_8_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@903 { + reg = ; + label = "pm8550ve_9_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; }; /* PMC8380C */ @@ -291,6 +421,8 @@ pm8550_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; }; pm8550_gpios: gpio@8800 { @@ -301,6 +433,18 @@ pm8550_gpios: gpio@8800 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + sys_therm_0_gpio3: sys-therm-0-gpio3-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + sys_therm_1_gpio4: sys-therm-1-gpio4-state { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; }; pm8550_flash: led-controller@ee00 { @@ -329,6 +473,8 @@ pm8550ve_2_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; }; pm8550ve_2_gpios: gpio@8800 { @@ -354,6 +500,8 @@ pmc8380_3_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; }; pmc8380_3_gpios: gpio@8800 { @@ -378,6 +526,8 @@ pmc8380_4_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; }; pmc8380_4_gpios: gpio@8800 { @@ -402,6 +552,8 @@ pmc8380_5_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(5)>; + io-channel-names = "thermal"; }; pmc8380_5_gpios: gpio@8800 { @@ -426,6 +578,8 @@ pmc8380_6_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; }; pmc8380_6_gpios: gpio@8800 { @@ -451,6 +605,8 @@ pm8550ve_8_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x8 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(8)>; + io-channel-names = "thermal"; }; pm8550ve_8_gpios: gpio@8800 { @@ -476,6 +632,8 @@ pm8550ve_9_temp_alarm: temp-alarm@a00 { reg = <0xa00>; interrupts = <0x9 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(9)>; + io-channel-names = "thermal"; }; pm8550ve_9_gpios: gpio@8800 { diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index ff8621f87505..fb2dcbc7c393 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -10,6 +10,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { reserved-memory { diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts index 63e29d2cc4ab..c754104adac7 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-vivobook-s15.dts @@ -11,6 +11,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "ASUS Vivobook S 15 X1P-42-100"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi index 7f5860d2b6cc..b5226c1ae370 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1p42100-asus-zenbook-a14.dtsi @@ -11,6 +11,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { wcn6855-pmu { diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts index 7ed4116b9590..5de91bca3fd5 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts @@ -10,6 +10,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "Qualcomm Technologies, Inc. X1P42100 CRD"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts index 0f338e457abd..0e4dfb0f0a2a 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-hp-omnibook-x14.dts @@ -7,6 +7,7 @@ #include "x1-hp-omnibook-x14.dtsi" /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "HP Omnibook X 14-fe1"; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 500809772097..9e6f679758a9 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -18,6 +18,7 @@ /delete-node/ &pmc8380_6; /delete-node/ &pmc8380_6_thermal; +/delete-node/ &pmc8380_6_die_temp; / { model = "Lenovo ThinkBook 16 Gen 7 QOY"; From da0343ba8c1f4275b1ce8127d5b6cee24d988868 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:24 +0200 Subject: [PATCH 711/864] arm64: dts: qcom: pmk8550: add VADC node Add the VADC node and the initial pmk8550 adc channels. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-1-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmk8550.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmk8550.dtsi b/arch/arm64/boot/dts/qcom/pmk8550.dtsi index 3049eb6b46d7..3a9d9f7c3742 100644 --- a/arch/arm64/boot/dts/qcom/pmk8550.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8550.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include "qcom-adc5-gen3.h" / { reboot-mode { @@ -64,6 +65,35 @@ reboot_reason: reboot-reason@48 { }; }; + pmk8550_vadc: adc@9000 { + compatible = "qcom,spmi-adc5-gen3"; + reg = <0x9000>, <0x9100>; + interrupts-extended = <&spmi_bus 0x0 0x90 0x1 IRQ_TYPE_EDGE_RISING>, + <&spmi_bus 0x0 0x91 0x1 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + #thermal-sensor-cells = <1>; + + channel@0 { + reg = ; + label = "pmk8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@1 { + reg = ; + label = "pmk8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@3 { + reg = ; + label = "pmk8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + }; + pmk8550_gpios: gpio@b800 { compatible = "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg = <0xb800>; From c50667eab2d6482f6397c00735d429428e2b3c81 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:25 +0200 Subject: [PATCH 712/864] arm64: dts: qcom: sm8550-qrd: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-2-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index f2effa55d819..144e105b734f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -205,6 +205,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -995,27 +1081,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &pon_pwrkey { status = "okay"; }; From 972848c36912ec8cbe79d68e5b2875a889375ebf Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:26 +0200 Subject: [PATCH 713/864] arm64: dts: qcom: sm8550-hdk: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-3-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index b79558938552..58c71ac67da5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -280,6 +280,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + wcn7850-pmu { compatible = "qcom,wcn7850-pmu"; @@ -1100,27 +1186,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &pon_pwrkey { status = "okay"; }; From b857a25ce399b9f49a2152d78d1a3893751e7cc4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:27 +0200 Subject: [PATCH 714/864] arm64: dts: qcom: sm8650-qrd: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-4-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index a28d70c85fa3..5709cfea1bfd 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -158,6 +158,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -1039,27 +1125,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; From 09d35331b7a94e30e30afb36b37a98513a2f60f7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Jul 2026 17:31:28 +0200 Subject: [PATCH 715/864] arm64: dts: qcom: sm8650-hdk: add SPMI ADC channels and thermal nodes Add the SPMI ADC channels on the PMK8550 SPMI5 ADC3 for the other PMICS on the system. The thermal nodes are sorted by the sensor channel to be coherent with the system thermal nodes ordering. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260721-topic-sm8x50-adc5-gen3-v6-5-a507f4a1e537@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 277 ++++++++++++++++++++++++ 1 file changed, 277 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 80bd2437f154..71c0355ece4b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -220,6 +220,92 @@ platform { }; }; + thermal-zones { + skin-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX1_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + cam-flash-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX2_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wlan-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX3_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + pa-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX5_THM_100K_PU(1)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + usb-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX4_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + wls-thermal { + thermal-sensors = <&pmk8550_vadc ADC5_GEN3_AMUX6_THM_100K_PU(7)>; + + trips { + trip-point0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -1040,27 +1126,218 @@ led@3 { }; }; +&pm8550_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550b_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(7)>; + io-channel-names = "thermal"; +}; + &pm8550vs_c { status = "okay"; }; +&pm8550vs_c_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(2)>; + io-channel-names = "thermal"; +}; + &pm8550vs_d { status = "okay"; }; +&pm8550vs_d_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(3)>; + io-channel-names = "thermal"; +}; + &pm8550vs_e { status = "okay"; }; +&pm8550vs_e_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(4)>; + io-channel-names = "thermal"; +}; + &pm8550vs_g { status = "okay"; }; +&pm8550vs_g_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(6)>; + io-channel-names = "thermal"; +}; + +&pm8550ve_temp_alarm { + io-channels = <&pmk8550_vadc ADC5_GEN3_DIE_TEMP(PMK8550VE_SID)>; + io-channel-names = "thermal"; +}; + +&pmk8550_vadc { + /* PM8550 Channel nodes */ + channel@100 { + reg = ; + label = "pm8550_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@101 { + reg = ; + label = "pm8550_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@103 { + reg = ; + label = "pm8550_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + label = "pm8550_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@145 { + reg = ; + label = "pm8550_cam_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@146 { + reg = ; + label = "pm8550_wlan_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@147 { + reg = ; + label = "pm8550_pa_therm_1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@148 { + reg = ; + label = "pm8550_rear_tof_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@18e { + reg = ; + label = "pm8550_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + /* PM8550VS_C Channel nodes */ + channel@203 { + reg = ; + label = "pm8550vs_c_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_D Channel nodes */ + channel@303 { + reg = ; + label = "pm8550vs_d_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_E Channel nodes */ + channel@403 { + reg = ; + label = "pm8550vs_e_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VE Channel nodes */ + channel@503 { + reg = ; + label = "pm8550ve_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550VS_G Channel nodes */ + channel@603 { + reg = ; + label = "pm8550vs_g_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + /* PM8550B Channel nodes */ + channel@700 { + reg = ; + label = "pm8550b_offset_ref"; + qcom,pre-scaling = <1 1>; + }; + + channel@701 { + reg = ; + label = "pm8550b_vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + channel@703 { + reg = ; + label = "pm8550b_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@747 { + reg = ; + label = "pm8550b_usb_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@749 { + reg = ; + label = "pm8550b_wls_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <15>; + qcom,pre-scaling = <1 1>; + qcom,adc-tm; + }; + + channel@78e { + reg = ; + label = "pm8550b_vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + channel@78f { + reg = ; + label = "pm8550b_vbat_sns_qbg"; + qcom,pre-scaling = <1 6>; + }; +}; + &pon_pwrkey { status = "okay"; }; From b3938d240803b2b114f19f8375493033376d5dba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 30 Jul 2026 11:23:57 +0200 Subject: [PATCH 716/864] arm64: dts: qcom: eliza-cqs-som: Add eUSB2 repeater supplies Hardware works better when it's powered. Wire up the associated regulators. Fixes: 85a1eb421dfa ("arm64: dts: qcom: eliza: Add Eliza CQS SoM platform") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260730-topic-eliza_som_eusb2-v1-1-288bcda1fee2@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi index 318ae3c22351..5ef6c51618bf 100644 --- a/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-som.dtsi @@ -369,6 +369,11 @@ vreg_l7k: ldo7 { }; }; +&pm7550ba_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; +}; + &remoteproc_adsp { firmware-name = "qcom/eliza/adsp.mbn", "qcom/eliza/adsp_dtb.mbn"; From 1b0b6ddd0299efa29d18f68a2d7152ad67cb9576 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Jul 2026 16:08:32 +0200 Subject: [PATCH 717/864] arm64: dts: qcom: glymur: Fix PDC IRQ mapping Some of the sub-ranges are inconsistent with HW docs. Fix them. They are valid for both Glymur and Mahua. Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi") Signed-off-by: Konrad Dybcio Reviewed-by: Gopikrishna Garmidi Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260729-topic-glymur_pdc-v1-1-8747789e35aa@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur.dtsi | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 8708416451a4..400ad218a459 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -5428,9 +5428,13 @@ dispcc: clock-controller@af00000 { pdc: interrupt-controller@b220000 { compatible = "qcom,glymur-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>; - qcom,pdc-ranges = <0 745 51>, - <51 527 47>, - <98 609 32>, + qcom,pdc-ranges = <0 745 38>, + <40 785 11>, + <51 527 4>, + <57 533 10>, + <70 546 4>, + <75 551 18>, + <108 619 22>, <130 717 12>, <142 251 5>, <147 796 16>, From f2eb18c66b98fbfcbab4daef42c04f4becba7d79 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 30 Jul 2026 15:45:10 +0530 Subject: [PATCH 718/864] arm64: dts: qcom: talos: Fix cpu6 1094.4MHz OPP frequency typo opp-1094400000 in cpu6_opp_table has a typo in opp-hz, missing a trailing zero. Fix it to resolve the following OPP update failures: cpu cpu6: Voltage update failed freq=1094400 cpu cpu6: failed to update OPP for freq=1094400 Fixes: 44562f591890 ("arm64: dts: qcom: qcs615: Add OSM l3 interconnect provider node and CPU OPP tables to scale DDR/L3") Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260730-talos-cpu6-opp-fix-v1-1-f4886fdff13f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index bdfb70ca9740..bef3e2e5fcdc 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -352,7 +352,7 @@ opp-1017600000 { }; opp-1094400000 { - opp-hz = /bits/ 64 <109440000>; + opp-hz = /bits/ 64 <1094400000>; opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; }; From 299731d4fbeaaa141ce2e8226ca00cb30d6ab647 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Dawid=20Wro=CC=81bel?= Date: Thu, 30 Jul 2026 15:44:07 +0200 Subject: [PATCH 719/864] arm64: dts: qcom: sm8250-xiaomi-elish: correct the board ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit elish declares the same qcom,msm-id and qcom,board-id pair as sm8250-sony-xperia-edo.dtsi, so a bootloader choosing between appended device trees cannot tell the two boards apart. 0x10008 is Sony's value. The downstream device tree for this board, elish-sm8250-overlay.dts, uses qcom,board-id = <47 0>, i.e. platform type 0x2f. Fixes: a41b617530bf ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro") Signed-off-by: Dawid Wróbel Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-elish-board-id-v1-1-92f99e9722ec@dawidwrobel.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 19aff83ecf7b..945127dacc82 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -29,7 +29,7 @@ / { /* required for bootloader to select correct board */ qcom,msm-id = ; /* SM8250 v2.1 */ - qcom,board-id = <0x10008 0>; + qcom,board-id = <0x2f 0>; aliases { serial0 = &uart6; From 35eda0e5f87d52ed9f015f8a44155e8ab2ad9c5a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:42 +0200 Subject: [PATCH 720/864] arm64: dts: qcom: kaanapali: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-1-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 74699bc3eadb..128d46a39e22 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -2385,8 +2385,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, operating-points-v2 = <&pcie0_opp_table>; - iommu-map = <0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, From 52dac5bda29a3acd896fab2567605683d34970db Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:43 +0200 Subject: [PATCH 721/864] arm64: dts: qcom: kodiak: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: f8328b7549e1 ("arm64: dts: qcom: sc7280: Describe the first PCIe controller and PHY") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-2-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 7e73348fe0d0..f74fa66f1a67 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2281,8 +2281,8 @@ pcie0: pcie@1c00000 { "aggre0", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2423,8 +2423,8 @@ pcie1: pcie@1c08000 { dma-coherent; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; status = "disabled"; From f605087abc70ecac53757a7ae0d2d8068342ec4b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:44 +0200 Subject: [PATCH 722/864] arm64: dts: qcom: sar2130p: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: be9115bfe5bf ("arm64: dts: qcom: sar2130p: add support for SAR2130P") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-3-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 767f7cc218f1..a2d93fd68299 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1329,8 +1329,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1455,8 +1455,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>, + <0x100 &apps_smmu 0x1e01 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From a4548204821a56c23cd711cfad2a637ca055ff47 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:45 +0200 Subject: [PATCH 723/864] arm64: dts: qcom: sc8180x: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-4-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b532e33a2639..de1b72b64d96 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1767,8 +1767,8 @@ pcie0: pcie@1c00000 { assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, - <0x100 &apps_smmu 0x1d81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x0 0x1>, + <0x100 &apps_smmu 0x1d81 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1886,8 +1886,8 @@ pcie3: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>, + <0x100 &apps_smmu 0x1e01 0x0 0x1>; resets = <&gcc GCC_PCIE_3_BCR>; reset-names = "pci"; @@ -2006,8 +2006,8 @@ pcie1: pcie@1c10000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; @@ -2126,8 +2126,8 @@ pcie2: pcie@1c18000 { assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, - <0x100 &apps_smmu 0x1d01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x0 0x1>, + <0x100 &apps_smmu 0x1d01 0x0 0x1>; resets = <&gcc GCC_PCIE_2_BCR>; reset-names = "pci"; From deaea7e982bc353c8d3c406774970f16ed901adb Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:46 +0200 Subject: [PATCH 724/864] arm64: dts: qcom: sdm845: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-5-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 64 ++++++++++++++-------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 745ca60fc8ed..562d411ed256 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2372,22 +2372,22 @@ pcie0: pcie@1c00000 { "slave_q2a", "tbu"; - iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, - <0x100 &apps_smmu 0x1c11 0x1>, - <0x200 &apps_smmu 0x1c12 0x1>, - <0x300 &apps_smmu 0x1c13 0x1>, - <0x400 &apps_smmu 0x1c14 0x1>, - <0x500 &apps_smmu 0x1c15 0x1>, - <0x600 &apps_smmu 0x1c16 0x1>, - <0x700 &apps_smmu 0x1c17 0x1>, - <0x800 &apps_smmu 0x1c18 0x1>, - <0x900 &apps_smmu 0x1c19 0x1>, - <0xa00 &apps_smmu 0x1c1a 0x1>, - <0xb00 &apps_smmu 0x1c1b 0x1>, - <0xc00 &apps_smmu 0x1c1c 0x1>, - <0xd00 &apps_smmu 0x1c1d 0x1>, - <0xe00 &apps_smmu 0x1c1e 0x1>, - <0xf00 &apps_smmu 0x1c1f 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c10 0x0 0x1>, + <0x100 &apps_smmu 0x1c11 0x0 0x1>, + <0x200 &apps_smmu 0x1c12 0x0 0x1>, + <0x300 &apps_smmu 0x1c13 0x0 0x1>, + <0x400 &apps_smmu 0x1c14 0x0 0x1>, + <0x500 &apps_smmu 0x1c15 0x0 0x1>, + <0x600 &apps_smmu 0x1c16 0x0 0x1>, + <0x700 &apps_smmu 0x1c17 0x0 0x1>, + <0x800 &apps_smmu 0x1c18 0x0 0x1>, + <0x900 &apps_smmu 0x1c19 0x0 0x1>, + <0xa00 &apps_smmu 0x1c1a 0x0 0x1>, + <0xb00 &apps_smmu 0x1c1b 0x0 0x1>, + <0xc00 &apps_smmu 0x1c1c 0x0 0x1>, + <0xd00 &apps_smmu 0x1c1d 0x0 0x1>, + <0xe00 &apps_smmu 0x1c1e 0x0 0x1>, + <0xf00 &apps_smmu 0x1c1f 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2502,22 +2502,22 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>, - <0x200 &apps_smmu 0x1c02 0x1>, - <0x300 &apps_smmu 0x1c03 0x1>, - <0x400 &apps_smmu 0x1c04 0x1>, - <0x500 &apps_smmu 0x1c05 0x1>, - <0x600 &apps_smmu 0x1c06 0x1>, - <0x700 &apps_smmu 0x1c07 0x1>, - <0x800 &apps_smmu 0x1c08 0x1>, - <0x900 &apps_smmu 0x1c09 0x1>, - <0xa00 &apps_smmu 0x1c0a 0x1>, - <0xb00 &apps_smmu 0x1c0b 0x1>, - <0xc00 &apps_smmu 0x1c0c 0x1>, - <0xd00 &apps_smmu 0x1c0d 0x1>, - <0xe00 &apps_smmu 0x1c0e 0x1>, - <0xf00 &apps_smmu 0x1c0f 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>, + <0x200 &apps_smmu 0x1c02 0x0 0x1>, + <0x300 &apps_smmu 0x1c03 0x0 0x1>, + <0x400 &apps_smmu 0x1c04 0x0 0x1>, + <0x500 &apps_smmu 0x1c05 0x0 0x1>, + <0x600 &apps_smmu 0x1c06 0x0 0x1>, + <0x700 &apps_smmu 0x1c07 0x0 0x1>, + <0x800 &apps_smmu 0x1c08 0x0 0x1>, + <0x900 &apps_smmu 0x1c09 0x0 0x1>, + <0xa00 &apps_smmu 0x1c0a 0x0 0x1>, + <0xb00 &apps_smmu 0x1c0b 0x0 0x1>, + <0xc00 &apps_smmu 0x1c0c 0x0 0x1>, + <0xd00 &apps_smmu 0x1c0d 0x0 0x1>, + <0xe00 &apps_smmu 0x1c0e 0x0 0x1>, + <0xf00 &apps_smmu 0x1c0f 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From d2e56fb42e3d10d7e711063cdc00523ddb31d544 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:47 +0200 Subject: [PATCH 725/864] arm64: dts: qcom: sm8150: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-6-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 661848ef5eee..94a3b02cb289 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1893,8 +1893,8 @@ pcie0: pcie@1c00000 { "bus_slave", "slave_q2a"; - iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, - <0x100 &apps_smmu 0x1d81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x0 0x1>, + <0x100 &apps_smmu 0x1d81 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2011,8 +2011,8 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, - <0x100 &apps_smmu 0x1e01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x0 0x1>, + <0x100 &apps_smmu 0x1e01 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From c41749e9554d4e03e7074f5d1e46140bc4ac77bd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:48 +0200 Subject: [PATCH 726/864] arm64: dts: qcom: sm8250: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-7-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index f11da2ca4181..90f8b091634e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2199,8 +2199,8 @@ pcie0: pcie@1c00000 { "tbu", "ddrss_sf_tbu"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2326,8 +2326,8 @@ pcie1: pcie@1c08000 { assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; @@ -2453,8 +2453,8 @@ pcie2: pcie@1c10000 { assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; assigned-clock-rates = <19200000>; - iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, - <0x100 &apps_smmu 0x1d01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1d00 0x0 0x1>, + <0x100 &apps_smmu 0x1d01 0x0 0x1>; resets = <&gcc GCC_PCIE_2_BCR>; reset-names = "pci"; From 80337ea3a154230621c0b4e3c831f5d81712ba18 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:49 +0200 Subject: [PATCH 727/864] arm64: dts: qcom: sm8350: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-8-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 72ecfaeefdd3..524693ec31c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1577,8 +1577,8 @@ pcie0: pcie@1c00000 { "aggre1", "aggre0"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -1686,8 +1686,8 @@ pcie1: pcie@1c08000 { "ddrss_sf_tbu", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From 9b10e56647fa8f7ab62c7e45ebf4b168f7befa7f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:50 +0200 Subject: [PATCH 728/864] arm64: dts: qcom: sm8450: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 7b09b1b47335 ("arm64: dts: qcom: sm8450: add PCIe0 RC device") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-9-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2488928656d9..c3e22f6a69e4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2008,8 +2008,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "aggre0", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2173,8 +2173,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "ddrss_sf_tbu", "aggre1"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; From 16d98ee918d63018eaa6cc260791b71319aa4faa Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:51 +0200 Subject: [PATCH 729/864] arm64: dts: qcom: sm8550: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-10-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7599b7b7e645..2888ec109ef7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2388,8 +2388,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, msi-map = <0x0 &gic_its 0x1400 0x1>, <0x100 &gic_its 0x1401 0x1>; - iommu-map = <0x0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0x0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; @@ -2573,8 +2573,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, msi-map = <0x0 &gic_its 0x1480 0x1>, <0x100 &gic_its 0x1481 0x1>; - iommu-map = <0x0 &apps_smmu 0x1480 0x1>, - <0x100 &apps_smmu 0x1481 0x1>; + iommu-map = <0x0 &apps_smmu 0x1480 0x0 0x1>, + <0x100 &apps_smmu 0x1481 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From 8ccba7b44609d58db088447a771f6f30cfa8739e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:52 +0200 Subject: [PATCH 730/864] arm64: dts: qcom: sm8650: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 10e024671295 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-11-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index d9b2c88a130a..799d549a9019 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3682,8 +3682,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, operating-points-v2 = <&pcie0_opp_table>; - iommu-map = <0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, @@ -3875,8 +3875,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, operating-points-v2 = <&pcie1_opp_table>; - iommu-map = <0 &apps_smmu 0x1480 0x1>, - <0x100 &apps_smmu 0x1481 0x1>; + iommu-map = <0 &apps_smmu 0x1480 0x0 0x1>, + <0x100 &apps_smmu 0x1481 0x0 0x1>; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, From 366a540432a38c1c1533a319bc07b333f53752b6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:53 +0200 Subject: [PATCH 731/864] arm64: dts: qcom: sm8750: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 19f1395333f8 ("arm64: dts: qcom: sm8750: Add PCIe PHY and controller node") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-12-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3496f00ac4f5..dd738d13df8e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5516,8 +5516,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x1400 0x1>, - <0x100 &apps_smmu 0x1401 0x1>; + iommu-map = <0x0 &apps_smmu 0x1400 0x0 0x1>, + <0x100 &apps_smmu 0x1401 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; From f7e687d6050f27a03847abadc12d6821576d06ee Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:54 +0200 Subject: [PATCH 732/864] arm64: dts: qcom: talos: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 718cc7542a00 ("arm64: dts: qcom: qcs615: enable pcie") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-13-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index bef3e2e5fcdc..07ba5733ca92 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1358,8 +1358,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &apps_smmu 0x400 0x1>, - <0x100 &apps_smmu 0x401 0x1>; + iommu-map = <0x0 &apps_smmu 0x400 0x0 0x1>, + <0x100 &apps_smmu 0x401 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>; reset-names = "pci"; From 19b4c47fc9733a953e9586bc0906a3be378b4cd5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:55 +0200 Subject: [PATCH 733/864] arm64: dts: qcom: lemans: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-14-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 3b0539e27b51..17bc5bcd9d09 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2742,8 +2742,8 @@ pcie0: pcie@1c00000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; @@ -2916,8 +2916,8 @@ pcie1: pcie@1c10000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, + <0x100 &pcie_smmu 0x0081 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From 2e455d9278550c8886a94e30a906437a26c79581 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:56 +0200 Subject: [PATCH 734/864] arm64: dts: qcom: monaco: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 46a7c01e7e9d ("arm64: dts: qcom: qcs8300: enable pcie0") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-15-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 0e484b704fda..d839f3683535 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2329,8 +2329,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>; resets = <&gcc GCC_PCIE_0_BCR>, <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; @@ -2506,8 +2506,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, - <0x100 &pcie_smmu 0x0081 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, + <0x100 &pcie_smmu 0x0081 0x0 0x1>; resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; From d7ae79013e6c9b2374948d70856045cc84c9261d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:57 +0200 Subject: [PATCH 735/864] arm64: dts: qcom: monaco-monza-som: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5238f4e7169f ("arm64: dts: qcom: Add Monaco Monza SoM") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-16-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi index 9b5ed55939b8..36af1ad2105d 100644 --- a/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi @@ -196,14 +196,14 @@ &iris { /* PCIe0 Gen4 x2 */ &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, - <0x100 &pcie_smmu 0x0001 0x1>, - <0x200 &pcie_smmu 0x0007 0x1>, - <0x208 &pcie_smmu 0x0002 0x1>, - <0x210 &pcie_smmu 0x0003 0x1>, - <0x218 &pcie_smmu 0x0004 0x1>, - <0x300 &pcie_smmu 0x0005 0x1>, - <0x400 &pcie_smmu 0x0006 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, + <0x100 &pcie_smmu 0x0001 0x0 0x1>, + <0x200 &pcie_smmu 0x0007 0x0 0x1>, + <0x208 &pcie_smmu 0x0002 0x0 0x1>, + <0x210 &pcie_smmu 0x0003 0x0 0x1>, + <0x218 &pcie_smmu 0x0004 0x0 0x1>, + <0x300 &pcie_smmu 0x0005 0x0 0x1>, + <0x400 &pcie_smmu 0x0006 0x0 0x1>; status = "okay"; }; From b35b58535b45441a4521d50215b5668731857c7d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:58 +0200 Subject: [PATCH 736/864] arm64: dts: qcom: monaco-evk-ifp-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 5a67924d2fc5 ("arm64: dts: qcom: monaco-evk: Add IFP Mezzanine") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-17-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/monaco-evk-ifp-mezzanine.dtso | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso index 77c28c19d17a..ca5bf0fe5ec6 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso @@ -50,15 +50,15 @@ nvmem-layout { }; &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0 0x1>, - <0x100 &pcie_smmu 0x1 0x1>, - <0x208 &pcie_smmu 0x2 0x1>, - <0x210 &pcie_smmu 0x3 0x1>, - <0x218 &pcie_smmu 0x4 0x1>, - <0x300 &pcie_smmu 0x5 0x1>, - <0x400 &pcie_smmu 0x6 0x1>, - <0x500 &pcie_smmu 0x7 0x1>, - <0x501 &pcie_smmu 0x8 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x0 0x1>, + <0x208 &pcie_smmu 0x2 0x0 0x1>, + <0x210 &pcie_smmu 0x3 0x0 0x1>, + <0x218 &pcie_smmu 0x4 0x0 0x1>, + <0x300 &pcie_smmu 0x5 0x0 0x1>, + <0x400 &pcie_smmu 0x6 0x0 0x1>, + <0x500 &pcie_smmu 0x7 0x0 0x1>, + <0x501 &pcie_smmu 0x8 0x0 0x1>; }; &pcieport0 { From 6ee8ab6ca91dcea05793809df8a1dcfa94bcf3f0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:55:59 +0200 Subject: [PATCH 737/864] arm64: dts: qcom: lemans-evk-ifp-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider pcie_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: b64abb26a291 ("arm64: dts: qcom: lemans-evk: Add IFP Mezzanine") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-18-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/lemans-evk-ifp-mezzanine.dtso | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso index 4fc5f482a18f..6cfa0bc1440e 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso @@ -204,15 +204,15 @@ &mdss1_dp1_phy { }; &pcie0 { - iommu-map = <0x0 &pcie_smmu 0x0 0x1>, - <0x100 &pcie_smmu 0x1 0x1>, - <0x208 &pcie_smmu 0x2 0x1>, - <0x210 &pcie_smmu 0x3 0x1>, - <0x218 &pcie_smmu 0x4 0x1>, - <0x300 &pcie_smmu 0x5 0x1>, - <0x400 &pcie_smmu 0x6 0x1>, - <0x500 &pcie_smmu 0x7 0x1>, - <0x501 &pcie_smmu 0x8 0x1>; + iommu-map = <0x0 &pcie_smmu 0x0 0x0 0x1>, + <0x100 &pcie_smmu 0x1 0x0 0x1>, + <0x208 &pcie_smmu 0x2 0x0 0x1>, + <0x210 &pcie_smmu 0x3 0x0 0x1>, + <0x218 &pcie_smmu 0x4 0x0 0x1>, + <0x300 &pcie_smmu 0x5 0x0 0x1>, + <0x400 &pcie_smmu 0x6 0x0 0x1>, + <0x500 &pcie_smmu 0x7 0x0 0x1>, + <0x501 &pcie_smmu 0x8 0x0 0x1>; }; &pcieport0 { From 82a10eb6aeab412abd83a57cc3a605213d1dc1d5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:00 +0200 Subject: [PATCH 738/864] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: ef254b12ec60 ("arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-19-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 82ebd88f9aba..41d60c87f5bd 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -549,15 +549,15 @@ &pcie1 { pinctrl-names = "default"; /* Support for QPS615 PCIe switch */ - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x400 &apps_smmu 0x1c88 0x1>, - <0x500 &apps_smmu 0x1c89 0x1>, - <0x501 &apps_smmu 0x1c90 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x400 &apps_smmu 0x1c88 0x0 0x1>, + <0x500 &apps_smmu 0x1c89 0x0 0x1>, + <0x501 &apps_smmu 0x1c90 0x0 0x1>; status = "okay"; }; From fc3c550b3847636f6c0732dc6c94e879ab5ff578 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:01 +0200 Subject: [PATCH 739/864] arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 1cde54c54b83 ("arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-20-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 4f6932dd1139..172dc0cbb532 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -714,15 +714,15 @@ &pcie1 { <&pcie1_wake_n>; pinctrl-names = "default"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x400 &apps_smmu 0x1c88 0x1>, - <0x500 &apps_smmu 0x1c89 0x1>, - <0x501 &apps_smmu 0x1c90 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x400 &apps_smmu 0x1c88 0x0 0x1>, + <0x500 &apps_smmu 0x1c89 0x0 0x1>, + <0x501 &apps_smmu 0x1c90 0x0 0x1>; status = "okay"; }; From 485dc5e557a8fef1374669f4ebe027c947187325 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:02 +0200 Subject: [PATCH 740/864] arm64: dts: qcom: qcs6490-rb3gen2: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 267643b3e3a4 ("arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-21-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 1acbfe7baa13..90f2eebc349f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -844,15 +844,15 @@ &pcie1 { pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x400 &apps_smmu 0x1c88 0x1>, - <0x500 &apps_smmu 0x1c89 0x1>, - <0x501 &apps_smmu 0x1c90 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x400 &apps_smmu 0x1c88 0x0 0x1>, + <0x500 &apps_smmu 0x1c89 0x0 0x1>, + <0x501 &apps_smmu 0x1c90 0x0 0x1>; status = "okay"; }; From 770d1448435bca2b1cd00854dc9401320b584d5b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 30 Jul 2026 13:56:03 +0200 Subject: [PATCH 741/864] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Fix the PCIe iommu-map entries The IOMMU provider apps_smmu uses '#iommu-cells = <2>', but the PCIe iommu-map entries specify only one cell for the SID, omitting the SID mask. This went unnoticed until the OF core started warning with commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps"): iommu-map has 1-cell entries targeting 2-cell #iommu-cells, treating as 1-cell output So fix the entries to match the provider's '#iommu-cells' property. Fixes: 4559b435f741 ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260730-iommu-map-fix-v1-22-83405d37ba41@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 937b63eae3ba..46bb52c667a4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -54,15 +54,15 @@ &pcie0 { pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>, - <0x208 &apps_smmu 0x1c04 0x1>, - <0x210 &apps_smmu 0x1c05 0x1>, - <0x218 &apps_smmu 0x1c06 0x1>, - <0x300 &apps_smmu 0x1c07 0x1>, - <0x400 &apps_smmu 0x1c08 0x1>, - <0x500 &apps_smmu 0x1c09 0x1>, - <0x501 &apps_smmu 0x1c10 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x0 0x1>, + <0x100 &apps_smmu 0x1c01 0x0 0x1>, + <0x208 &apps_smmu 0x1c04 0x0 0x1>, + <0x210 &apps_smmu 0x1c05 0x0 0x1>, + <0x218 &apps_smmu 0x1c06 0x0 0x1>, + <0x300 &apps_smmu 0x1c07 0x0 0x1>, + <0x400 &apps_smmu 0x1c08 0x0 0x1>, + <0x500 &apps_smmu 0x1c09 0x0 0x1>, + <0x501 &apps_smmu 0x1c10 0x0 0x1>; status = "okay"; }; @@ -151,22 +151,22 @@ pcie@0,1 { }; &pcie1 { - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>, - <0x208 &apps_smmu 0x1c84 0x1>, - <0x210 &apps_smmu 0x1c85 0x1>, - <0x218 &apps_smmu 0x1c86 0x1>, - <0x300 &apps_smmu 0x1c87 0x1>, - <0x408 &apps_smmu 0x1c90 0x1>, - <0x410 &apps_smmu 0x1c91 0x1>, - <0x418 &apps_smmu 0x1c92 0x1>, - <0x500 &apps_smmu 0x1c93 0x1>, - <0x600 &apps_smmu 0x1c94 0x1>, - <0x700 &apps_smmu 0x1c95 0x1>, - <0x701 &apps_smmu 0x1c96 0x1>, - <0x800 &apps_smmu 0x1c97 0x1>, - <0x900 &apps_smmu 0x1c98 0x1>, - <0x901 &apps_smmu 0x1c99 0x1>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x0 0x1>, + <0x100 &apps_smmu 0x1c81 0x0 0x1>, + <0x208 &apps_smmu 0x1c84 0x0 0x1>, + <0x210 &apps_smmu 0x1c85 0x0 0x1>, + <0x218 &apps_smmu 0x1c86 0x0 0x1>, + <0x300 &apps_smmu 0x1c87 0x0 0x1>, + <0x408 &apps_smmu 0x1c90 0x0 0x1>, + <0x410 &apps_smmu 0x1c91 0x0 0x1>, + <0x418 &apps_smmu 0x1c92 0x0 0x1>, + <0x500 &apps_smmu 0x1c93 0x0 0x1>, + <0x600 &apps_smmu 0x1c94 0x0 0x1>, + <0x700 &apps_smmu 0x1c95 0x0 0x1>, + <0x701 &apps_smmu 0x1c96 0x0 0x1>, + <0x800 &apps_smmu 0x1c97 0x0 0x1>, + <0x900 &apps_smmu 0x1c98 0x0 0x1>, + <0x901 &apps_smmu 0x1c99 0x0 0x1>; }; &pcie1_switch0_dsp1 { From f63ecc70c341682f2f78403be84069876d3eac0c Mon Sep 17 00:00:00 2001 From: Jiqi Li Date: Fri, 31 Jul 2026 17:50:08 +0800 Subject: [PATCH 742/864] dt-bindings: arm: tegra: Add lenovo,thinkedge-se70 compatible string Lenovo ThinkEdge SE70 is a fanless industrial edge gateway carrier board based on NVIDIA Tegra194 (Xavier NX) SOM. Add the corresponding compatible string for device tree validation. Acked-by: Conor Dooley Signed-off-by: Jiqi Li Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 033a63f6c068..a54d0024e636 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -268,6 +268,11 @@ properties: items: - const: nvidia,p3509-0000+p3668-0001 - const: nvidia,tegra194 + - description: Lenovo ThinkEdge SE70 + items: + - const: lenovo,thinkedge-se70 + - const: nvidia,p3668-0001 + - const: nvidia,tegra194 - items: - const: nvidia,tegra234-vdk - const: nvidia,tegra234 From 7de0c114f06744444853b13e4faf231297370cc4 Mon Sep 17 00:00:00 2001 From: Akhil R Date: Tue, 31 Mar 2026 15:53:03 +0530 Subject: [PATCH 743/864] arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map Enable GPCDMA in Tegra264 and add the iommu-map property so that each channel uses a separate stream ID and gets its own IOMMU domain for memory. Signed-off-by: Akhil R Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 ++++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 1 + 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi index 7e2c3e66c2ab..58cd81bc33d7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -9,6 +9,10 @@ aliases { }; bus@0 { + dma-controller@8400000 { + status = "okay"; + }; + serial@c4e0000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 2d2cb1a3d95c..a8d534435a9b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3244,6 +3244,7 @@ gpcdma: dma-controller@8400000 { ; #dma-cells = <1>; iommus = <&smmu1 0x00000800>; + iommu-map = <1 &smmu1 0x801 31>; dma-coherent; dma-channel-mask = <0xfffffffe>; status = "disabled"; From 0e925a882e7c0d01b4f93ee3940c778874474b91 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jan 2026 16:15:36 +0530 Subject: [PATCH 744/864] arm64: tegra: Populate CPU and L2 cache nodes on Tegra264 Add the remaining 12 CPU nodes and all 14 L2 cache nodes for the Tegra264 CPU Complex, which comprises up to 14 ARM Neoverse V3AE CPUs. Each CPU has its own private 1MB L2 cache. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 321 +++++++++++++++++++++++ 1 file changed, 321 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index a8d534435a9b..8af8bfb95ba3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -4069,6 +4069,7 @@ cpu0: cpu@0 { d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; + next-level-cache = <&l2c0>; }; cpu1: cpu@10000 { @@ -4084,7 +4085,327 @@ cpu1: cpu@10000 { d-cache-size = <65536>; d-cache-line-size = <64>; d-cache-sets = <256>; + next-level-cache = <&l2c1>; }; + + cpu2: cpu@20000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x20000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c2>; + }; + + cpu3: cpu@30000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x30000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c3>; + }; + + cpu4: cpu@40000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x40000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c4>; + }; + + cpu5: cpu@50000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x50000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c5>; + }; + + cpu6: cpu@60000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x60000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c6>; + }; + + cpu7: cpu@70000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x70000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c7>; + }; + + cpu8: cpu@80000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x80000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c8>; + }; + + cpu9: cpu@90000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0x90000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c9>; + }; + + cpu10: cpu@a0000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0xa0000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c10>; + }; + + cpu11: cpu@b0000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0xb0000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c11>; + }; + + cpu12: cpu@c0000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0xc0000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c12>; + }; + + cpu13: cpu@d0000 { + compatible = "arm,neoverse-v3ae"; + device_type = "cpu"; + reg = <0xd0000>; + + enable-method = "psci"; + + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2c13>; + }; + + l2c0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c4: l2-cache-4 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c5: l2-cache-5 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c6: l2-cache-6 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c7: l2-cache-7 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c8: l2-cache-8 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c9: l2-cache-9 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c10: l2-cache-10 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c11: l2-cache-11 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c12: l2-cache-12 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + + l2c13: l2-cache-13 { + compatible = "cache"; + cache-level = <2>; + cache-size = <1048576>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + }; + }; bpmp: bpmp { From d51928a36fa43fa05f87c5e309f26c6db1effae2 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Mon, 22 Jun 2026 15:57:44 +0900 Subject: [PATCH 745/864] arm64: tegra: Add Host1x and VIC on Tegra264 Tegra264 has a host1x instance with a VIC (video image compositor). Other multimedia engines have moved outside host1x. Stream IDs are now namespaced by device rather than being defined globally -- however, the only engine we have using context isolation is VIC so we only define VIC's range of context devices. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 63 ++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 8af8bfb95ba3..0ad3ab802f0b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3808,6 +3808,69 @@ its: msi-controller@40000 { }; }; + /* VISION MMIO */ + bus@8180000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x000 0x00000000 0x81 0x80000000 0x00 0x10000000>, /* MMIO (256 MiB) */ + <0x100 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */ + <0x200 0x00000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ + + host1x@1200000 { + compatible = "nvidia,tegra264-host1x"; + reg = <0x0 0x1200000 0x0 0x10000>, + <0x0 0x1210000 0x0 0x10000>, + <0x0 0x1240000 0x0 0x10000>; + reg-names = "common", "hypervisor", "vm"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", + "syncpt5", "syncpt6", "syncpt7", "host1x"; + clocks = <&bpmp TEGRA264_CLK_HOST1X>; + clock-names = "host1x"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x000 0x00000000 0x00 0x08000000 0x00 0x01000000>, + <0x000 0x02800000 0x00 0x0a800000 0x00 0x00800000>; + + interconnects = <&mc TEGRA264_MEMORY_CLIENT_HOST1XR &emc>; + interconnect-names = "dma-mem"; + iommus = <&smmu1 TEGRA264_SID_HOST1X>; + dma-coherent; + + /* Context isolation domains */ + iommu-map = <0 &smmu1 (TEGRA264_SID_VIC + 1) 16>; + + vic@50000 { + compatible = "nvidia,tegra264-vic"; + reg = <0x0 0x50000 0x0 0x40000>; + interrupts = ; + clocks = <&bpmp TEGRA264_CLK_VIC>; + clock-names = "vic"; + resets = <&bpmp TEGRA264_RESET_VIC>; + reset-names = "vic"; + power-domains = <&bpmp TEGRA264_POWER_DOMAIN_VIC>; + interconnects = <&mc TEGRA264_MEMORY_CLIENT_VICR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_VICW &emc>; + interconnect-names = "dma-mem", "write"; + + iommus = <&smmu1 TEGRA264_SID_VIC>; + dma-coherent; + }; + }; + }; + /* DISP_USB MMIO */ bus@8800000000 { compatible = "simple-bus"; From 2863b8f38f5e344334d960c7341b4acd1a61197b Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Wed, 8 Apr 2026 21:24:13 +0000 Subject: [PATCH 746/864] arm64: tegra: Add GTE nodes for Tegra264 Add AON GPIO and system LIC GTE instances for Tegra264. Signed-off-by: Suneel Garapati Acked-by: Dipen Patel Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 0ad3ab802f0b..af748df3e2b9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -50,6 +50,15 @@ timer@8000000 { status = "disabled"; }; + hte_lic: hardware-timestamp@8380000 { + compatible = "nvidia,tegra264-gte-lic"; + reg = <0x0 0x08380000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + status = "disabled"; + }; + aconnect@9000000 { compatible = "nvidia,tegra264-aconnect", "nvidia,tegra210-aconnect"; @@ -3268,6 +3277,16 @@ hsp_top: hsp@8800000 { #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c2b0000 { + compatible = "nvidia,tegra264-gte-aon"; + reg = <0x0 0x0c2b0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + nvidia,gpio-controller = <&gpio_aon>; + status = "disabled"; + }; + rtc: rtc@c2c0000 { compatible = "nvidia,tegra264-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x0c2c0000 0x0 0x10000>; From 96c5696a58fa527873c261f74d74f81303e756fe Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 16 Jul 2026 23:44:24 +0200 Subject: [PATCH 747/864] arm64: tegra: Properly sort devices on Tegra264 We always sort by unit-address and fallback to alphanumeric sorting for nodes that don't have a unit-address. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 166 +++++++++++------------ 1 file changed, 83 insertions(+), 83 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index af748df3e2b9..42b143155ed4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -59,6 +59,67 @@ hte_lic: hardware-timestamp@8380000 { status = "disabled"; }; + gpcdma: dma-controller@8400000 { + compatible = "nvidia,tegra264-gpcdma"; + reg = <0x0 0x08400000 0x0 0x210000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu1 0x00000800>; + iommu-map = <1 &smmu1 0x801 31>; + dma-coherent; + dma-channel-mask = <0xfffffffe>; + status = "disabled"; + }; + + hsp_top: hsp@8800000 { + compatible = "nvidia,tegra264-hsp"; + reg = <0x0 0x08800000 0x0 0xd0000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + aconnect@9000000 { compatible = "nvidia,tegra264-aconnect", "nvidia,tegra210-aconnect"; @@ -3216,67 +3277,6 @@ agic_page5: interrupt-controller@99b0000 { }; }; - gpcdma: dma-controller@8400000 { - compatible = "nvidia,tegra264-gpcdma"; - reg = <0x0 0x08400000 0x0 0x210000>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - #dma-cells = <1>; - iommus = <&smmu1 0x00000800>; - iommu-map = <1 &smmu1 0x801 31>; - dma-coherent; - dma-channel-mask = <0xfffffffe>; - status = "disabled"; - }; - - hsp_top: hsp@8800000 { - compatible = "nvidia,tegra264-hsp"; - reg = <0x0 0x08800000 0x0 0xd0000>; - interrupts = , - , - , - , - , - , - , - , - ; - interrupt-names = "doorbell", "shared0", "shared1", "shared2", - "shared3", "shared4", "shared5", "shared6", - "shared7"; - #mbox-cells = <2>; - }; - hte_aon: hardware-timestamp@c2b0000 { compatible = "nvidia,tegra264-gte-aon"; reg = <0x0 0x0c2b0000 0x0 0x10000>; @@ -4134,6 +4134,28 @@ pci@8480000 { }; }; + bpmp: bpmp { + compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + memory-region = <&shmem_bpmp>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + thermal { + compatible = "nvidia,tegra186-bpmp-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -4490,28 +4512,6 @@ l2c13: l2-cache-13 { }; - bpmp: bpmp { - compatible = "nvidia,tegra264-bpmp", "nvidia,tegra186-bpmp"; - mboxes = <&hsp_top TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; - memory-region = <&shmem_bpmp>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - - i2c { - compatible = "nvidia,tegra186-bpmp-i2c"; - nvidia,bpmp-bus-id = <5>; - #address-cells = <1>; - #size-cells = <0>; - }; - - thermal { - compatible = "nvidia,tegra186-bpmp-thermal"; - #thermal-sensor-cells = <1>; - }; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; From 5af7a8a522f61ae2a3e5038c889e231e56d63526 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Mon, 22 Jun 2026 06:54:10 +0000 Subject: [PATCH 748/864] arm64: tegra: Fix CMDQV interrupt type on Tegra264 The CMDQV interrupts on Tegra264 are described as level-triggered, but per the hardware interrupt documentation these interrupts are actually edge-triggered. Correct the interrupt type for all CMDQV nodes from IRQ_TYPE_LEVEL_HIGH to IRQ_TYPE_EDGE_RISING. Fixes: fe57d0ac4835 ("arm64: tegra: Add nodes for CMDQV") Reported-by: Nicolin Chen Signed-off-by: Ashish Mhetre Acked-by: Jon Hunter Acked-by: Nicolin Chen Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 42b143155ed4..4073e3905f81 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3413,7 +3413,7 @@ smmu1: iommu@5000000 { cmdqv1: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x5200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3433,7 +3433,7 @@ smmu2: iommu@6000000 { cmdqv2: cmdqv@6200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x6200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3506,7 +3506,7 @@ smmu0: iommu@a000000 { cmdqv0: cmdqv@a200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0xa200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3526,7 +3526,7 @@ smmu4: iommu@b000000 { cmdqv4: cmdqv@b200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0xb200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; @@ -3914,7 +3914,7 @@ smmu3: iommu@6000000 { cmdqv3: cmdqv@6200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x00 0x6200000 0x0 0x830000>; - interrupts = ; + interrupts = ; status = "disabled"; }; From a112f2f5171ddd6362873e31777016b40f324854 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 27 Apr 2026 13:42:31 +0000 Subject: [PATCH 749/864] arm64: tegra: Add pinctrl nodes for Tegra264 Add the three pin controller (MAIN, UPHY, AON) device-tree nodes found on Tegra264. Signed-off-by: Prathamesh Shete Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 4073e3905f81..b141e8f884fe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3356,6 +3356,11 @@ i2c3: i2c@c610000 { status = "disabled"; }; + pinmux_aon: pinmux@c7a2000 { + compatible = "nvidia,tegra264-pinmux-aon"; + reg = <0x0 0x0c7a2000 0x0 0x2000>; + }; + pmc: pmc@c800000 { compatible = "nvidia,tegra264-pmc"; reg = <0x0 0x0c800000 0x0 0x100000>, @@ -3562,6 +3567,11 @@ pci@c000000 { status = "disabled"; }; + pinmux_main: pinmux@c281000 { + compatible = "nvidia,tegra264-pinmux-main"; + reg = <0x00 0x0c281000 0x0 0xc000>; + }; + gpio_main: gpio@c300000 { compatible = "nvidia,tegra264-gpio"; reg = <0x00 0x0c300000 0x0 0x4000>, @@ -3945,6 +3955,11 @@ bus@a800000000 { <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */ <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */ + pinmux_uphy: pinmux@82e0000 { + compatible = "nvidia,tegra264-pinmux-uphy"; + reg = <0x00 0x082e0000 0x0 0x4000>; + }; + gpio_uphy: gpio@8300000 { compatible = "nvidia,tegra264-gpio-uphy"; reg = <0x00 0x08300000 0x0 0x2000>, From 30a140dabeb20eea38c183da5fef764a9442e309 Mon Sep 17 00:00:00 2001 From: Jiqi Li Date: Fri, 31 Jul 2026 17:50:09 +0800 Subject: [PATCH 750/864] arm64: tegra: Add Lenovo ThinkEdge SE70 device tree Add initial device tree support for the Lenovo ThinkEdge SE70, an industrial edge gateway based on the NVIDIA Jetson Xavier NX module (P3668-0001) with a custom carrier board. This initial submission includes: - 40-pin expansion header pinmux configuration - External Micro SD card slot with dedicated 3.3V regulator - I2C bus for 40-pin header Static verification passed: dt_binding_check and dtbs compilation complete without errors. Reviewed-by: Mikko Perttunen Signed-off-by: Jiqi Li Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../nvidia/tegra194-lenovo-thinkedge-se70.dts | 111 ++++++++++++++++++ 2 files changed, 112 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 72c0cb5efa47..736a3f8a923f 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p3509-0000+p3636-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb +dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-lenovo-thinkedge-se70.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts new file mode 100644 index 000000000000..185ec60d85c1 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra194-lenovo-thinkedge-se70.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra194-p3668-0001.dtsi" + +#include + +/ { + model = "Lenovo ThinkEdge SE70"; + compatible = "lenovo,thinkedge-se70", "nvidia,p3668-0001", "nvidia,tegra194"; + + aliases { + mmc1 = "/bus@0/mmc@3440000"; + }; + + bus@0 { + /* 40-pin expansion header custom pinmux configuration */ + pinmux@2430000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_hdr40>; + + pinmux_hdr40: pinmux-hdr40 { + pin7 { + nvidia,pins = "aud_mclk_ps4"; + nvidia,function = "aud"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pin11 { + nvidia,pins = "uart1_rts_pr4"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pin12 { + nvidia,pins = "dap5_sclk_pt5"; + nvidia,function = "i2s5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pin35 { + nvidia,pins = "dap5_fs_pu0"; + nvidia,function = "i2s5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pin36 { + nvidia,pins = "uart1_cts_pr5"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pin38 { + nvidia,pins = "dap5_din_pt7"; + nvidia,function = "i2s5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pin40 { + nvidia,pins = "dap5_dout_pt6"; + nvidia,function = "i2s5"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; + + /* Configure i2c bus clock to 400kHz for carrier board peripherals */ + i2c@3160000 { + clock-frequency = <400000>; + }; + + /* SDMMC3: External Micro SD card slot */ + mmc@3440000 { + bus-width = <4>; + cd-gpios = <&gpio_aon TEGRA194_AON_GPIO(CC, 4) GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + vmmc-supply = <&vdd_3v3_sd>; + status = "okay"; + }; + }; + + /* Fixed 3.3V power supply regulator for external Micro SD slot */ + vdd_3v3_sd: regulator-vdd-3v3-sd { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA194_MAIN_GPIO(Q, 5) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; + + /* System 5V main supply, referenced by SOM and USB nodes */ + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; From 3f856cf050cb45e5921ebabf32ecde4f135c04e9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 Jun 2026 17:09:54 +0200 Subject: [PATCH 751/864] arm64: tegra: Drop CPU masks from GICv3 PPI interrupts Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven Reviewed-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 820670dd6042..ffdaf9d8d947 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4083,7 +4083,7 @@ gic: interrupt-controller@f400000 { reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ <0x0 0x0f440000 0x0 0x200000>; /* GICR */ interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; #redistributor-regions = <1>; #interrupt-cells = <3>; @@ -5885,10 +5885,10 @@ tj-thermal { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&gic>; always-on; }; From 93fd84cee4546ea6475b1c4e1250a7ddbd3d5e7f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 29 Apr 2026 18:56:27 +0200 Subject: [PATCH 752/864] arm64: tegra: Correct Tegra194 p2972 interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING Realtek RT5658 codec driver requests interrupt on both edges, so correct the interrupt flags, assuming the author of the code wanted the similar logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index ea6f397a2792..5462200f1176 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -2170,7 +2170,7 @@ rt5658: audio-codec@1a { compatible = "realtek,rt5658"; reg = <0x1a>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; clocks = <&bpmp TEGRA194_CLK_AUD_MCLK>; clock-names = "mclk"; realtek,jd-src = <2>; From bf2d4b582eb8bd5f3ab78c59fe2f6738b6c7ab2a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 29 Apr 2026 18:56:28 +0200 Subject: [PATCH 753/864] arm64: tegra: Correct Tegra234 p3737 interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING Realtek RT5640 codec driver requests interrupt on rising edge, so correct the interrupt flags, assuming the author of the code wanted the similar logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi index f6cad29355e6..420858a8f4a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi @@ -67,7 +67,7 @@ audio-codec@1c { compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>; clock-names = "mclk"; realtek,dmic1-data-pin = ; From 2aedc7afffc61449ddd44bf2a4b3195729cb46ac Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 29 Apr 2026 18:56:29 +0200 Subject: [PATCH 754/864] arm64: tegra: Correct Tegra234 p3740 interrupt flags GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 => IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 => IRQ_TYPE_EDGE_RISING Realtek RT5640 codec driver requests interrupt on rising edge, so correct the interrupt flags, assuming the author of the code wanted the similar logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_HIGH => IRQ_TYPE_EDGE_RISING Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts index 9ce55b4d2de8..97cede1fcb70 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -75,7 +75,7 @@ rt5640: audio-codec@1c { compatible = "realtek,rt5640"; reg = <0x1c>; interrupt-parent = <&gpio>; - interrupts = ; + interrupts = ; clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>; clock-names = "mclk"; From bf1aee1ad1c087ffda617207890dc92042a28c96 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:06:56 +0200 Subject: [PATCH 755/864] arm64: dts: exynos: Move 'status' to the end to match coding style 'status' property is special, thus DTS coding style expects it to be always the last property preceded with a blank line, as reported by dt-check-style: [property-order] property 'iommus' out of canonical order (should sort before 'status') [required-blank-lines] "status" must be preceded by a blank line Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-1-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos2200-g0s.dts | 2 + arch/arm64/boot/dts/exynos/exynos2200.dtsi | 98 +++++++++++++++++++ .../arm64/boot/dts/exynos/exynos5433-bus.dtsi | 10 ++ .../dts/exynos/exynos5433-tm2-common.dtsi | 47 +++++++-- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 55 ++++++++++- .../boot/dts/exynos/exynos7-espresso.dts | 10 +- arch/arm64/boot/dts/exynos/exynos7.dtsi | 24 +++++ .../boot/dts/exynos/exynos7885-jackpotlte.dts | 3 +- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 +++ .../boot/dts/exynos/exynos850-e850-96.dts | 13 ++- arch/arm64/boot/dts/exynos/exynos850.dtsi | 31 ++++++ .../boot/dts/exynos/exynos8895-dreamlte.dts | 1 + arch/arm64/boot/dts/exynos/exynos8895.dtsi | 47 +++++++++ arch/arm64/boot/dts/exynos/exynos990-c1s.dts | 3 +- arch/arm64/boot/dts/exynos/exynos990-r8s.dts | 3 +- .../boot/dts/exynos/exynos990-x1s-common.dtsi | 3 +- arch/arm64/boot/dts/exynos/exynos990.dtsi | 2 + .../boot/dts/exynos/exynosautov9-sadk.dts | 9 +- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 77 +++++++++++++++ .../boot/dts/exynos/exynosautov920-sadk.dts | 2 + .../arm64/boot/dts/exynos/exynosautov920.dtsi | 57 +++++++++++ 21 files changed, 485 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts b/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts index 0e348c5cf7df..458f1bc6f5d0 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts +++ b/arch/arm64/boot/dts/exynos/exynos2200-g0s.dts @@ -143,6 +143,7 @@ &usb { /* TODO: Replace these once PMIC is implemented */ vdd10-supply = <®_dummy>; vdd33-supply = <®_dummy>; + status = "okay"; }; @@ -161,6 +162,7 @@ &usb_hsphy { /* TODO: Replace these once PMIC is implemented */ vdda12-supply = <®_dummy>; vdd-supply = <®_dummy>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 59662f9bdb98..b1c134f22324 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -266,6 +266,7 @@ mct_peris: timer@10040000 { , , ; + status = "disabled"; }; @@ -326,6 +327,7 @@ usi4: usi@105000c0 { <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; hsi2c_8: i2c@10500000 { @@ -340,6 +342,7 @@ hsi2c_8: i2c@10500000 { interrupts = ; pinctrl-0 = <&hsi2c8_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -353,6 +356,7 @@ serial_6: serial@10500000 { pinctrl-0 = <&uart6_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -368,6 +372,7 @@ usi4_i2c: usi@105100c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; hsi2c_9: i2c@10510000 { @@ -382,6 +387,7 @@ hsi2c_9: i2c@10510000 { interrupts = ; pinctrl-0 = <&hsi2c9_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -418,6 +424,7 @@ usi7: usi@109000c0 { <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric1 0x2030>; + status = "disabled"; hsi2c_14: i2c@10900000 { @@ -432,6 +439,7 @@ hsi2c_14: i2c@10900000 { interrupts = ; pinctrl-0 = <&hsi2c14_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -445,6 +453,7 @@ serial_9: serial@10900000 { pinctrl-0 = <&uart9_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -460,6 +469,7 @@ usi7_i2c: usi@109100c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric1 0x2034>; + status = "disabled"; hsi2c_15: i2c@10910000 { @@ -474,6 +484,7 @@ hsi2c_15: i2c@10910000 { interrupts = ; pinctrl-0 = <&hsi2c15_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -488,6 +499,7 @@ usi8: usi@109200c0 { <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric1 0x2038>; + status = "disabled"; hsi2c_16: i2c@10920000 { @@ -502,6 +514,7 @@ hsi2c_16: i2c@10920000 { interrupts = ; pinctrl-0 = <&hsi2c16_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -515,6 +528,7 @@ serial_10: serial@10920000 { pinctrl-0 = <&uart10_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -530,6 +544,7 @@ usi8_i2c: usi@109300c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric1 0x203c>; + status = "disabled"; hsi2c_17: i2c@10930000 { @@ -544,6 +559,7 @@ hsi2c_17: i2c@10930000 { interrupts = ; pinctrl-0 = <&hsi2c17_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -558,6 +574,7 @@ usi9: usi@109400c0 { <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric1 0x2040>; + status = "disabled"; hsi2c_18: i2c@10940000 { @@ -572,6 +589,7 @@ hsi2c_18: i2c@10940000 { interrupts = ; pinctrl-0 = <&hsi2c18_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -585,6 +603,7 @@ serial_11: serial@10940000 { pinctrl-0 = <&uart11_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -600,6 +619,7 @@ usi9_i2c: usi@109500c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric1 0x2044>; + status = "disabled"; hsi2c_19: i2c@10950000 { @@ -614,6 +634,7 @@ hsi2c_19: i2c@10950000 { interrupts = ; pinctrl-0 = <&hsi2c19_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -628,6 +649,7 @@ usi10: usi@109600c0 { <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric1 0x2048>; + status = "disabled"; hsi2c_20: i2c@10960000 { @@ -642,6 +664,7 @@ hsi2c_20: i2c@10960000 { interrupts = ; pinctrl-0 = <&hsi2c20_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -655,6 +678,7 @@ serial_12: serial@10960000 { pinctrl-0 = <&uart12_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -670,6 +694,7 @@ usi10_i2c: usi@109700c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric1 0x204c>; + status = "disabled"; hsi2c_21: i2c@10970000 { @@ -684,6 +709,7 @@ hsi2c_21: i2c@10970000 { interrupts = ; pinctrl-0 = <&hsi2c21_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -821,6 +847,7 @@ usi0: usi@11d000c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x2000>; + status = "disabled"; hsi2c_0: i2c@11d00000 { @@ -835,6 +862,7 @@ hsi2c_0: i2c@11d00000 { interrupts = ; pinctrl-0 = <&hsi2c0_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -848,6 +876,7 @@ serial_2: serial@11d00000 { pinctrl-0 = <&uart2_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -863,6 +892,7 @@ usi0_i2c: usi@11d100c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x2004>; + status = "disabled"; hsi2c_1: i2c@11d10000 { @@ -877,6 +907,7 @@ hsi2c_1: i2c@11d10000 { interrupts = ; pinctrl-0 = <&hsi2c1_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -891,6 +922,7 @@ usi1: usi@11d200c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x2008>; + status = "disabled"; hsi2c_2: i2c@11d20000 { @@ -905,6 +937,7 @@ hsi2c_2: i2c@11d20000 { interrupts = ; pinctrl-0 = <&hsi2c2_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -918,6 +951,7 @@ serial_3: serial@11d20000 { pinctrl-0 = <&uart3_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -933,6 +967,7 @@ usi1_i2c: usi@11d300c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x200c>; + status = "disabled"; hsi2c_3: i2c@11d30000 { @@ -947,6 +982,7 @@ hsi2c_3: i2c@11d30000 { interrupts = ; pinctrl-0 = <&hsi2c3_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -961,6 +997,7 @@ usi2: usi@11d400c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x2010>; + status = "disabled"; hsi2c_4: i2c@11d40000 { @@ -975,6 +1012,7 @@ hsi2c_4: i2c@11d40000 { interrupts = ; pinctrl-0 = <&hsi2c4_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -988,6 +1026,7 @@ serial_4: serial@11d40000 { pinctrl-0 = <&uart4_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; + status = "disabled"; }; }; @@ -1003,6 +1042,7 @@ usi2_i2c: usi@11d500c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x2014>; + status = "disabled"; hsi2c_5: i2c@11d50000 { @@ -1017,6 +1057,7 @@ hsi2c_5: i2c@11d50000 { interrupts = ; pinctrl-0 = <&hsi2c5_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1031,6 +1072,7 @@ usi3: usi@11d600c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x2018>; + status = "disabled"; hsi2c_6: i2c@11d60000 { @@ -1045,6 +1087,7 @@ hsi2c_6: i2c@11d60000 { interrupts = ; pinctrl-0 = <&hsi2c6_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1058,6 +1101,7 @@ serial_5: serial@11d60000 { pinctrl-0 = <&uart5_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; + status = "disabled"; }; }; @@ -1073,6 +1117,7 @@ usi3_i2c: usi@11d700c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x201c>; + status = "disabled"; hsi2c_7: i2c@11d70000 { @@ -1087,6 +1132,7 @@ hsi2c_7: i2c@11d70000 { interrupts = ; pinctrl-0 = <&hsi2c7_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1102,6 +1148,7 @@ usi5_i2c: usi@11d800c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x102c>; + status = "disabled"; hsi2c_11: i2c@11d80000 { @@ -1116,6 +1163,7 @@ hsi2c_11: i2c@11d80000 { interrupts = ; pinctrl-0 = <&hsi2c11_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1131,6 +1179,7 @@ usi6_i2c: usi@11d900c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x1004>; + status = "disabled"; hsi2c_13: i2c@11d90000 { @@ -1145,6 +1194,7 @@ hsi2c_13: i2c@11d90000 { interrupts = ; pinctrl-0 = <&hsi2c13_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1159,6 +1209,7 @@ usi11: usi@11da00c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x1058>; + status = "disabled"; hsi2c_22: i2c@11da0000 { @@ -1173,6 +1224,7 @@ hsi2c_22: i2c@11da0000 { interrupts = ; pinctrl-0 = <&hsi2c22_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1186,6 +1238,7 @@ serial_13: serial@11da0000 { pinctrl-0 = <&uart13_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1201,6 +1254,7 @@ usi11_i2c: usi@11db00c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_peric2 0x105c>; + status = "disabled"; hsi2c_23: i2c@11db0000 { @@ -1215,6 +1269,7 @@ hsi2c_23: i2c@11db0000 { interrupts = ; pinctrl-0 = <&hsi2c23_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1229,6 +1284,7 @@ usi5: usi@11dd00c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x117c>; + status = "disabled"; hsi2c_10: i2c@11dd0000 { @@ -1243,6 +1299,7 @@ hsi2c_10: i2c@11dd0000 { interrupts = ; pinctrl-0 = <&hsi2c10_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1256,6 +1313,7 @@ serial_7: serial@11dd0000 { pinctrl-0 = <&uart7_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; + status = "disabled"; }; }; @@ -1270,6 +1328,7 @@ usi6: usi@11de00c0 { <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_peric2 0x1180>; + status = "disabled"; hsi2c_12: i2c@11de0000 { @@ -1284,6 +1343,7 @@ hsi2c_12: i2c@11de0000 { interrupts = ; pinctrl-0 = <&hsi2c12_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1297,6 +1357,7 @@ serial_8: serial@11de0000 { pinctrl-0 = <&uart8_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1338,6 +1399,7 @@ usi_cmgp0: usi@14f000c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2000>; + status = "disabled"; hsi2c_24: i2c@14f00000 { @@ -1352,6 +1414,7 @@ hsi2c_24: i2c@14f00000 { interrupts = ; pinctrl-0 = <&hsi2c24_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1365,6 +1428,7 @@ serial_14: serial@14f00000 { pinctrl-0 = <&uart14_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1380,6 +1444,7 @@ usi_i2c_cmgp0: usi@14f100c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2070>; + status = "disabled"; hsi2c_25: i2c@14f10000 { @@ -1394,6 +1459,7 @@ hsi2c_25: i2c@14f10000 { interrupts = ; pinctrl-0 = <&hsi2c25_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1408,6 +1474,7 @@ usi_cmgp1: usi@14f200c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI1>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2010>; + status = "disabled"; hsi2c_26: i2c@14f20000 { @@ -1422,6 +1489,7 @@ hsi2c_26: i2c@14f20000 { interrupts = ; pinctrl-0 = <&hsi2c26_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1435,6 +1503,7 @@ serial_15: serial@14f20000 { pinctrl-0 = <&uart15_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1450,6 +1519,7 @@ usi_i2c_cmgp1: usi@14f300c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2074>; + status = "disabled"; hsi2c_27: i2c@14f30000 { @@ -1464,6 +1534,7 @@ hsi2c_27: i2c@14f30000 { interrupts = ; pinctrl-0 = <&hsi2c27_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1478,6 +1549,7 @@ usi_cmgp2: usi@14f400c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI2>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2020>; + status = "disabled"; hsi2c_28: i2c@14f40000 { @@ -1492,6 +1564,7 @@ hsi2c_28: i2c@14f40000 { interrupts = ; pinctrl-0 = <&hsi2c28_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1505,6 +1578,7 @@ serial_16: serial@14f40000 { pinctrl-0 = <&uart16_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1520,6 +1594,7 @@ usi_i2c_cmgp2: usi@14f500c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2024>; + status = "disabled"; hsi2c_29: i2c@14f50000 { @@ -1534,6 +1609,7 @@ hsi2c_29: i2c@14f50000 { interrupts = ; pinctrl-0 = <&hsi2c29_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1548,6 +1624,7 @@ usi_cmgp3: usi@14f600c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI3>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2030>; + status = "disabled"; hsi2c_30: i2c@14f60000 { @@ -1562,6 +1639,7 @@ hsi2c_30: i2c@14f60000 { interrupts = ; pinctrl-0 = <&hsi2c30_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1575,6 +1653,7 @@ serial_17: serial@14f60000 { pinctrl-0 = <&uart17_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1590,6 +1669,7 @@ usi_i2c_cmgp3: usi@14f700c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2034>; + status = "disabled"; hsi2c_31: i2c@14f70000 { @@ -1604,6 +1684,7 @@ hsi2c_31: i2c@14f70000 { interrupts = ; pinctrl-0 = <&hsi2c31_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1618,6 +1699,7 @@ usi_cmgp4: usi@14f800c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI4>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2040>; + status = "disabled"; hsi2c_32: i2c@14f80000 { @@ -1632,6 +1714,7 @@ hsi2c_32: i2c@14f80000 { interrupts = ; pinctrl-0 = <&hsi2c32_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1645,6 +1728,7 @@ serial_18: serial@14f80000 { pinctrl-0 = <&uart18_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1660,6 +1744,7 @@ usi_i2c_cmgp4: usi@14f900c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2044>; + status = "disabled"; hsi2c_33: i2c@14f90000 { @@ -1674,6 +1759,7 @@ hsi2c_33: i2c@14f90000 { interrupts = ; pinctrl-0 = <&hsi2c33_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1688,6 +1774,7 @@ usi_cmgp5: usi@14fa00c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI5>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2050>; + status = "disabled"; hsi2c_34: i2c@14fa0000 { @@ -1702,6 +1789,7 @@ hsi2c_34: i2c@14fa0000 { interrupts = ; pinctrl-0 = <&hsi2c34_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1715,6 +1803,7 @@ serial_19: serial@14fa0000 { pinctrl-0 = <&uart19_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1730,6 +1819,7 @@ usi_i2c_cmgp5: usi@14fb00c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2054>; + status = "disabled"; hsi2c_35: i2c@14fb0000 { @@ -1744,6 +1834,7 @@ hsi2c_35: i2c@14fb0000 { interrupts = ; pinctrl-0 = <&hsi2c35_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1758,6 +1849,7 @@ usi_cmgp6: usi@14fc00c0 { <&cmu_cmgp CLK_DOUT_CMGP_USI6>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&syscon_cmgp 0x2060>; + status = "disabled"; hsi2c_36: i2c@14fc0000 { @@ -1772,6 +1864,7 @@ hsi2c_36: i2c@14fc0000 { interrupts = ; pinctrl-0 = <&hsi2c36_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1785,6 +1878,7 @@ serial_20: serial@14fc0000 { pinctrl-0 = <&uart20_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; }; @@ -1800,6 +1894,7 @@ usi_i2c_cmgp6: usi@14fd00c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2064>; + status = "disabled"; hsi2c_37: i2c@14fd0000 { @@ -1814,6 +1909,7 @@ hsi2c_37: i2c@14fd0000 { interrupts = ; pinctrl-0 = <&hsi2c37_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1829,6 +1925,7 @@ usi_i2c_cmgp7: usi@14fe00c0 { clock-names = "pclk", "ipclk"; samsung,mode = ; samsung,sysreg = <&syscon_cmgp 0x2080>; + status = "disabled"; hsi2c_38: i2c@14fe0000 { @@ -1843,6 +1940,7 @@ hsi2c_38: i2c@14fe0000 { interrupts = ; pinctrl-0 = <&hsi2c38_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi index 540b4d6c9067..0c200df9996f 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi @@ -12,6 +12,7 @@ bus_g2d_400: bus0 { clocks = <&cmu_top CLK_ACLK_G2D_400>; clock-names = "bus"; operating-points-v2 = <&bus_g2d_400_opp_table>; + status = "disabled"; }; @@ -20,6 +21,7 @@ bus_g2d_266: bus1 { clocks = <&cmu_top CLK_ACLK_G2D_266>; clock-names = "bus"; operating-points-v2 = <&bus_g2d_266_opp_table>; + status = "disabled"; }; @@ -28,6 +30,7 @@ bus_gscl: bus2 { clocks = <&cmu_top CLK_ACLK_GSCL_333>; clock-names = "bus"; operating-points-v2 = <&bus_gscl_opp_table>; + status = "disabled"; }; @@ -36,6 +39,7 @@ bus_hevc: bus3 { clocks = <&cmu_top CLK_ACLK_HEVC_400>; clock-names = "bus"; operating-points-v2 = <&bus_hevc_opp_table>; + status = "disabled"; }; @@ -44,6 +48,7 @@ bus_jpeg: bus4 { clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>; clock-names = "bus"; operating-points-v2 = <&bus_g2d_400_opp_table>; + status = "disabled"; }; @@ -52,6 +57,7 @@ bus_mfc: bus5 { clocks = <&cmu_top CLK_ACLK_MFC_400>; clock-names = "bus"; operating-points-v2 = <&bus_g2d_400_opp_table>; + status = "disabled"; }; @@ -60,6 +66,7 @@ bus_mscl: bus6 { clocks = <&cmu_top CLK_ACLK_MSCL_400>; clock-names = "bus"; operating-points-v2 = <&bus_g2d_400_opp_table>; + status = "disabled"; }; @@ -68,6 +75,7 @@ bus_noc0: bus7 { clocks = <&cmu_top CLK_ACLK_BUS0_400>; clock-names = "bus"; operating-points-v2 = <&bus_hevc_opp_table>; + status = "disabled"; }; @@ -76,6 +84,7 @@ bus_noc1: bus8 { clocks = <&cmu_top CLK_ACLK_BUS1_400>; clock-names = "bus"; operating-points-v2 = <&bus_hevc_opp_table>; + status = "disabled"; }; @@ -84,6 +93,7 @@ bus_noc2: bus9 { clocks = <&cmu_mif CLK_ACLK_BUS2_400>; clock-names = "bus"; operating-points-v2 = <&bus_noc2_opp_table>; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index a1fb354dea9f..bc5ff66d8455 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -141,6 +141,7 @@ sound { &adc { vdd-supply = <&ldo3_reg>; + status = "okay"; thermistor-ap { @@ -173,51 +174,61 @@ &bus_g2d_400 { devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>; vdd-supply = <&buck4_reg>; exynos,saturation-ratio = <10>; + status = "okay"; }; &bus_g2d_266 { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_gscl { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_hevc { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_jpeg { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_mfc { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_mscl { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_noc0 { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_noc1 { devfreq = <&bus_g2d_400>; + status = "okay"; }; &bus_noc2 { devfreq = <&bus_g2d_400>; + status = "okay"; }; @@ -344,7 +355,6 @@ tv_to_hdmi: endpoint { }; &dsi { - status = "okay"; vddcore-supply = <&ldo6_reg>; vddio-supply = <&ldo7_reg>; samsung,burst-clock-frequency = <512000000>; @@ -352,20 +362,24 @@ &dsi { samsung,pll-clock-frequency = <24000000>; pinctrl-names = "default"; pinctrl-0 = <&te_irq>; + + status = "okay"; }; &gpu { mali-supply = <&buck6_reg>; + status = "okay"; }; &hdmi { hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; - status = "okay"; vdd-supply = <&ldo6_reg>; vdd_osc-supply = <&ldo7_reg>; vdd_pll-supply = <&ldo6_reg>; + status = "okay"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -387,9 +401,10 @@ hdmi_to_mhl: endpoint { }; &hsi2c_0 { - status = "okay"; clock-frequency = <2500000>; + status = "okay"; + pmic@66 { compatible = "samsung,s2mps13-pmic"; interrupt-parent = <&gpa0>; @@ -819,9 +834,10 @@ stmfts: touchscreen@49 { }; &hsi2c_7 { - status = "okay"; clock-frequency = <1000000>; + status = "okay"; + bridge@39 { reg = <0x39>; compatible = "sil,sii8620"; @@ -884,6 +900,7 @@ port@0 { * Add a disabled port just to satisfy dtschema. */ reg = <0>; + status = "disabled"; }; @@ -945,11 +962,11 @@ &i2s0 { &i2s1 { assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>; assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>; + status = "okay"; }; &mshc_0 { - status = "okay"; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; @@ -968,10 +985,11 @@ &mshc_0 { bus-width = <8>; assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; assigned-clock-rates = <800000000>; + + status = "okay"; }; &mshc_2 { - status = "okay"; cap-sd-highspeed; disable-wp; cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; @@ -983,10 +1001,11 @@ &mshc_2 { pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>; bus-width = <4>; + + status = "okay"; }; &pcie { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pcie_bus &pcie_wlanen>; vdd10-supply = <&ldo6_reg>; @@ -998,6 +1017,8 @@ &pcie { assigned-clock-rates = <0>, <100000000>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; + + status = "okay"; }; &pcie_phy { @@ -1006,6 +1027,7 @@ &pcie_phy { &ppmu_d0_general { status = "okay"; + events { ppmu_event0_d0_general: ppmu-event0-d0-general { event-name = "ppmu-event0-d0-general"; @@ -1015,6 +1037,7 @@ ppmu_event0_d0_general: ppmu-event0-d0-general { &ppmu_d1_general { status = "okay"; + events { ppmu_event0_d1_general: ppmu-event0-d1-general { event-name = "ppmu-event0-d1-general"; @@ -1238,6 +1261,7 @@ initial_touch: initial-state { &pwm { pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; + status = "okay"; }; @@ -1270,6 +1294,7 @@ bluetooth { &spi_1 { cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>; + status = "okay"; wm5110: audio-codec@0 { @@ -1316,9 +1341,10 @@ controller-data { }; &spi_3 { - status = "okay"; no-cs-readback; + status = "okay"; + irled@0 { compatible = "ir-spi-led"; reg = <0x0>; @@ -1339,22 +1365,26 @@ &timer { &tmu_atlas0 { vtmu-supply = <&ldo3_reg>; + status = "okay"; }; &tmu_apollo { vtmu-supply = <&ldo3_reg>; + status = "okay"; }; &tmu_g3d { vtmu-supply = <&ldo3_reg>; + status = "okay"; }; &usbdrd30 { vdd33-supply = <&ldo10_reg>; vdd10-supply = <&ldo6_reg>; + status = "okay"; }; @@ -1364,6 +1394,7 @@ &usbdrd_dwc3 { &usbdrd30_phy { vbus-supply = <&safeout1_reg>; + status = "okay"; port { diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index fa2029e280a5..bc061b57caff 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -755,6 +755,7 @@ tmu_atlas0: tmu@10060000 { <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; + status = "disabled"; }; @@ -766,6 +767,7 @@ tmu_atlas1: tmu@10068000 { <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; + status = "disabled"; }; @@ -777,6 +779,7 @@ tmu_g3d: tmu@10070000 { <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; + status = "disabled"; }; @@ -788,6 +791,7 @@ tmu_apollo: tmu@10078000 { <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; + status = "disabled"; }; @@ -799,6 +803,7 @@ tmu_isp: tmu@1007c000 { <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; + status = "disabled"; }; @@ -825,24 +830,28 @@ timer@101c0000 { ppmu_d0_cpu: ppmu@10480000 { compatible = "samsung,exynos-ppmu-v2"; reg = <0x10480000 0x2000>; + status = "disabled"; }; ppmu_d0_general: ppmu@10490000 { compatible = "samsung,exynos-ppmu-v2"; reg = <0x10490000 0x2000>; + status = "disabled"; }; ppmu_d1_cpu: ppmu@104b0000 { compatible = "samsung,exynos-ppmu-v2"; reg = <0x104b0000 0x2000>; + status = "disabled"; }; ppmu_d1_general: ppmu@104c0000 { compatible = "samsung,exynos-ppmu-v2"; reg = <0x104c0000 0x2000>; + status = "disabled"; }; @@ -972,10 +981,11 @@ decon: decon@13800000 { , ; samsung,disp-sysreg = <&syscon_disp>; - status = "disabled"; iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; iommu-names = "m0", "m1"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1015,9 +1025,10 @@ decon_tv: decon@13880000 { interrupts = , , ; - status = "disabled"; iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>; iommu-names = "m0", "m1"; + + status = "disabled"; }; dsi: dsi@13900000 { @@ -1037,10 +1048,11 @@ dsi: dsi@13900000 { "sclk_rgb_vclk_to_dsim0", "sclk_mipi"; power-domains = <&pd_disp>; - status = "disabled"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1062,6 +1074,7 @@ mic: mic@13930000 { clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; power-domains = <&pd_disp>; samsung,disp-syscon = <&syscon_disp>; + status = "disabled"; ports { @@ -1108,6 +1121,7 @@ hdmi: hdmi@13970000 { samsung,syscon-phandle = <&pmu_system_controller>; samsung,sysreg-phandle = <&syscon_disp>; #sound-dai-cells = <0>; + status = "disabled"; }; @@ -1195,6 +1209,7 @@ gpu: gpu@14ac0000 { clock-names = "core"; power-domains = <&pd_g3d>; operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; gpu_opp_table: opp-table { @@ -1426,6 +1441,7 @@ serial_0: serial@14c10000 { clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; + status = "disabled"; }; @@ -1438,6 +1454,7 @@ serial_1: serial@14c20000 { clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart1_bus>; + status = "disabled"; }; @@ -1450,6 +1467,7 @@ serial_2: serial@14c30000 { clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart2_bus>; + status = "disabled"; }; @@ -1470,6 +1488,7 @@ spi_0: spi@14d20000 { pinctrl-0 = <&spi0_bus>; num-cs = <1>; fifo-depth = <256>; + status = "disabled"; }; @@ -1490,6 +1509,7 @@ spi_1: spi@14d30000 { pinctrl-0 = <&spi1_bus>; num-cs = <1>; fifo-depth = <64>; + status = "disabled"; }; @@ -1510,6 +1530,7 @@ spi_2: spi@14d40000 { pinctrl-0 = <&spi2_bus>; num-cs = <1>; fifo-depth = <64>; + status = "disabled"; }; @@ -1530,6 +1551,7 @@ spi_3: spi@14d50000 { pinctrl-0 = <&spi3_bus>; num-cs = <1>; fifo-depth = <64>; + status = "disabled"; }; @@ -1550,6 +1572,7 @@ spi_4: spi@14d00000 { pinctrl-0 = <&spi4_bus>; num-cs = <1>; fifo-depth = <64>; + status = "disabled"; }; @@ -1560,6 +1583,7 @@ adc: adc@14d10000 { clock-names = "adc"; clocks = <&cmu_peric CLK_PCLK_ADCIF>; #io-channel-cells = <1>; + status = "disabled"; }; @@ -1575,6 +1599,7 @@ i2s1: i2s@14d60000 { clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; #clock-cells = <1>; #sound-dai-cells = <1>; + status = "disabled"; }; @@ -1590,6 +1615,7 @@ pwm: pwm@14dd0000 { clocks = <&cmu_peric CLK_PCLK_PWM>; clock-names = "timers"; #pwm-cells = <3>; + status = "disabled"; }; @@ -1604,6 +1630,7 @@ hsi2c_0: i2c@14e40000 { pinctrl-0 = <&hs_i2c0_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C0>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1618,6 +1645,7 @@ hsi2c_1: i2c@14e50000 { pinctrl-0 = <&hs_i2c1_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C1>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1632,6 +1660,7 @@ hsi2c_2: i2c@14e60000 { pinctrl-0 = <&hs_i2c2_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C2>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1646,6 +1675,7 @@ hsi2c_3: i2c@14e70000 { pinctrl-0 = <&hs_i2c3_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C3>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1660,6 +1690,7 @@ hsi2c_4: i2c@14ec0000 { pinctrl-0 = <&hs_i2c4_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C4>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1674,6 +1705,7 @@ hsi2c_5: i2c@14ed0000 { pinctrl-0 = <&hs_i2c5_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C5>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1688,6 +1720,7 @@ hsi2c_6: i2c@14ee0000 { pinctrl-0 = <&hs_i2c6_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C6>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1702,6 +1735,7 @@ hsi2c_7: i2c@14ef0000 { pinctrl-0 = <&hs_i2c7_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C7>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1716,6 +1750,7 @@ hsi2c_8: i2c@14d90000 { pinctrl-0 = <&hs_i2c8_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C8>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1730,6 +1765,7 @@ hsi2c_9: i2c@14da0000 { pinctrl-0 = <&hs_i2c9_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C9>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1744,6 +1780,7 @@ hsi2c_10: i2c@14de0000 { pinctrl-0 = <&hs_i2c10_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C10>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1758,6 +1795,7 @@ hsi2c_11: i2c@14df0000 { pinctrl-0 = <&hs_i2c11_bus>; clocks = <&cmu_peric CLK_PCLK_HSI2C11>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -1771,6 +1809,7 @@ usbdrd30: usb@15400000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x15400000 0x10000>; + status = "disabled"; usbdrd_dwc3: usb@0 { @@ -1797,6 +1836,7 @@ usbdrd30_phy: phy@15500000 { "itp"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; }; @@ -1811,6 +1851,7 @@ usbhost30_phy: phy@15580000 { "itp"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; }; @@ -1824,6 +1865,7 @@ usbhost30: usb@15a00000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x15a00000 0x10000>; + status = "disabled"; usbhost_dwc3: usb@0 { @@ -1850,6 +1892,7 @@ mshc_0: mmc@15540000 { <&cmu_fsys CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -1864,6 +1907,7 @@ mshc_1: mmc@15550000 { <&cmu_fsys CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -1878,6 +1922,7 @@ mshc_2: mmc@15560000 { <&cmu_fsys CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -1937,6 +1982,7 @@ i2s0: i2s@11440000 { pinctrl-0 = <&i2s0_bus>; power-domains = <&pd_aud>; #sound-dai-cells = <1>; + status = "disabled"; }; @@ -1950,6 +1996,7 @@ serial_3: serial@11460000 { pinctrl-names = "default"; pinctrl-0 = <&uart_aud_bus>; power-domains = <&pd_aud>; + status = "disabled"; }; }; @@ -1960,6 +2007,7 @@ pcie_phy: pcie-phy@15680000 { samsung,pmu-syscon = <&pmu_system_controller>; samsung,fsys-sysreg = <&syscon_fsys>; #phy-cells = <0>; + status = "disabled"; }; @@ -1982,6 +2030,7 @@ pcie: pcie@15700000 { phys = <&pcie_phy>; ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 1f2eddcebdd9..c8925f4076b5 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -68,9 +68,10 @@ &serial_2 { }; &rtc { - status = "okay"; clocks = <&clock_ccore PCLK_RTC>, <&s2mps15_osc S2MPS11_CLK_AP>; clock-names = "rtc", "rtc_src"; + + status = "okay"; }; &watchdog { @@ -79,6 +80,7 @@ &watchdog { &adc { vdd-supply = <&ldo3_reg>; + status = "okay"; }; @@ -360,7 +362,6 @@ pmic_irq: pmic-irq-pins { }; &mmc_0 { - status = "okay"; cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; @@ -373,10 +374,11 @@ &mmc_0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 &sd0_bus8>; bus-width = <8>; + + status = "okay"; }; &mmc_2 { - status = "okay"; cap-sd-highspeed; card-detect-delay = <200>; clock-frequency = <400000000>; @@ -389,6 +391,8 @@ &mmc_2 { vmmc-supply = <&ldo17_reg>; vqmmc-supply = <&ldo2_reg>; disable-wp; + + status = "okay"; }; &pinctrl_bus1 { diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 9cb6bd61262e..fa4e7d678423 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -286,6 +286,7 @@ serial_0: serial@13630000 { clocks = <&clock_peric0 PCLK_UART0>, <&clock_peric0 SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; @@ -296,6 +297,7 @@ serial_1: serial@14c20000 { clocks = <&clock_peric1 PCLK_UART1>, <&clock_peric1 SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; @@ -306,6 +308,7 @@ serial_2: serial@14c30000 { clocks = <&clock_peric1 PCLK_UART2>, <&clock_peric1 SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; @@ -316,6 +319,7 @@ serial_3: serial@14c40000 { clocks = <&clock_peric1 PCLK_UART3>, <&clock_peric1 SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; @@ -388,6 +392,7 @@ hsi2c_0: i2c@13640000 { pinctrl-0 = <&hs_i2c0_bus>; clocks = <&clock_peric0 PCLK_HSI2C0>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -401,6 +406,7 @@ hsi2c_1: i2c@13650000 { pinctrl-0 = <&hs_i2c1_bus>; clocks = <&clock_peric0 PCLK_HSI2C1>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -414,6 +420,7 @@ hsi2c_2: i2c@14e60000 { pinctrl-0 = <&hs_i2c2_bus>; clocks = <&clock_peric1 PCLK_HSI2C2>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -427,6 +434,7 @@ hsi2c_3: i2c@14e70000 { pinctrl-0 = <&hs_i2c3_bus>; clocks = <&clock_peric1 PCLK_HSI2C3>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -440,6 +448,7 @@ hsi2c_4: i2c@13660000 { pinctrl-0 = <&hs_i2c4_bus>; clocks = <&clock_peric0 PCLK_HSI2C4>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -453,6 +462,7 @@ hsi2c_5: i2c@13670000 { pinctrl-0 = <&hs_i2c5_bus>; clocks = <&clock_peric0 PCLK_HSI2C5>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -466,6 +476,7 @@ hsi2c_6: i2c@14e00000 { pinctrl-0 = <&hs_i2c6_bus>; clocks = <&clock_peric1 PCLK_HSI2C6>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -479,6 +490,7 @@ hsi2c_7: i2c@13e10000 { pinctrl-0 = <&hs_i2c7_bus>; clocks = <&clock_peric1 PCLK_HSI2C7>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -492,6 +504,7 @@ hsi2c_8: i2c@14e20000 { pinctrl-0 = <&hs_i2c8_bus>; clocks = <&clock_peric1 PCLK_HSI2C8>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -505,6 +518,7 @@ hsi2c_9: i2c@13680000 { pinctrl-0 = <&hs_i2c9_bus>; clocks = <&clock_peric0 PCLK_HSI2C9>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -518,6 +532,7 @@ hsi2c_10: i2c@13690000 { pinctrl-0 = <&hs_i2c10_bus>; clocks = <&clock_peric0 PCLK_HSI2C10>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -531,6 +546,7 @@ hsi2c_11: i2c@136a0000 { pinctrl-0 = <&hs_i2c11_bus>; clocks = <&clock_peric0 PCLK_HSI2C11>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -546,6 +562,7 @@ rtc: rtc@10590000 { ; clocks = <&clock_ccore PCLK_RTC>; clock-names = "rtc"; + status = "disabled"; }; @@ -556,6 +573,7 @@ watchdog: watchdog@101d0000 { clocks = <&clock_peris PCLK_WDT>; clock-names = "watchdog"; samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; }; @@ -567,6 +585,7 @@ gpu: gpu@14ac0000 { , ; interrupt-names = "job", "mmu", "gpu"; + status = "disabled"; /* TODO: operating points for DVFS, cooling device */ }; @@ -581,6 +600,7 @@ mmc_0: mmc@15740000 { <&clock_top1 CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -594,6 +614,7 @@ mmc_1: mmc@15750000 { <&clock_top1 CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -607,6 +628,7 @@ mmc_2: mmc@15560000 { <&clock_top1 CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -617,6 +639,7 @@ adc: adc@13620000 { clocks = <&clock_peric0 PCLK_ADCIF>; clock-names = "adc"; #io-channel-cells = <1>; + status = "disabled"; }; @@ -660,6 +683,7 @@ ufs: ufs@15570000 { pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; phys = <&ufs_phy>; phy-names = "ufs-phy"; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts index 9d74fa6bfed9..4b1961ca365b 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -62,7 +62,6 @@ power-key { }; &mmc_0 { - status = "okay"; mmc-hs200-1_8v; mmc-hs400-1_8v; cap-mmc-highspeed; @@ -79,6 +78,8 @@ &mmc_0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk_fast_slew_rate_3x &sd0_cmd &sd0_rdqs &sd0_bus1 &sd0_bus4 &sd0_bus8>; + + status = "okay"; }; &oscclk { diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 008228fb319a..7d7d56206b86 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -307,6 +307,7 @@ mmc_0: mmc@13500000 { <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -321,6 +322,7 @@ serial_0: serial@13800000 { <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -335,6 +337,7 @@ serial_1: serial@13810000 { <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -349,6 +352,7 @@ serial_2: serial@13820000 { <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -363,6 +367,7 @@ i2c_0: i2c@13830000 { pinctrl-0 = <&i2c0_bus>; clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -377,6 +382,7 @@ i2c_1: i2c@13840000 { pinctrl-0 = <&i2c1_bus>; clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -391,6 +397,7 @@ i2c_2: i2c@13850000 { pinctrl-0 = <&i2c2_bus>; clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -405,6 +412,7 @@ i2c_3: i2c@13860000 { pinctrl-0 = <&i2c3_bus>; clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -419,6 +427,7 @@ i2c_4: i2c@13870000 { pinctrl-0 = <&i2c4_bus>; clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -433,6 +442,7 @@ i2c_5: i2c@13880000 { pinctrl-0 = <&i2c5_bus>; clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -447,6 +457,7 @@ i2c_6: i2c@13890000 { pinctrl-0 = <&i2c6_bus>; clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -461,6 +472,7 @@ i2c_7: i2c@11cd0000 { pinctrl-0 = <&i2c7_bus>; clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>; clock-names = "i2c"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index ab076d326a49..afef32ad4ee2 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -178,7 +178,6 @@ &cmu_hsi { }; &mmc_0 { - status = "okay"; mmc-hs200-1_8v; mmc-hs400-1_8v; cap-mmc-highspeed; @@ -195,6 +194,8 @@ &mmc_0 { pinctrl-names = "default"; pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; + + status = "okay"; }; &oscclk { @@ -224,21 +225,24 @@ micro_usb_det_pins: micro-usb-det-pins { }; &rtc { - status = "okay"; clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; clock-names = "rtc", "rtc_src"; + + status = "okay"; }; &serial_0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; + + status = "okay"; }; &usbdrd { - status = "okay"; vdd10-supply = <®_dummy>; vdd33-supply = <®_dummy>; + + status = "okay"; }; &usbdrd_dwc3 { @@ -273,6 +277,7 @@ &usbdrd_phy { &usi_uart { samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 3881f573ec08..8abf7c9eac9e 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -239,6 +239,7 @@ watchdog_cl0: watchdog@10050000 { clock-names = "watchdog", "watchdog_src"; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <0>; + status = "disabled"; }; @@ -250,6 +251,7 @@ watchdog_cl1: watchdog@10060000 { clock-names = "watchdog", "watchdog_src"; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; + status = "disabled"; }; @@ -455,6 +457,7 @@ rtc: rtc@11a30000 { ; clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; clock-names = "rtc"; + status = "disabled"; }; @@ -469,6 +472,7 @@ mmc_0: mmc@12100000 { <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; + status = "disabled"; }; @@ -482,6 +486,7 @@ i2c_0: i2c@13830000 { pinctrl-0 = <&i2c0_pins>; clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -495,6 +500,7 @@ i2c_1: i2c@13840000 { pinctrl-0 = <&i2c1_pins>; clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -508,6 +514,7 @@ i2c_2: i2c@13850000 { pinctrl-0 = <&i2c2_pins>; clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -521,6 +528,7 @@ i2c_3: i2c@13860000 { pinctrl-0 = <&i2c3_pins>; clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -534,6 +542,7 @@ i2c_4: i2c@13870000 { pinctrl-0 = <&i2c4_pins>; clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -548,6 +557,7 @@ i2c_5: i2c@13880000 { pinctrl-0 = <&i2c5_pins>; clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -562,6 +572,7 @@ i2c_6: i2c@13890000 { pinctrl-0 = <&i2c6_pins>; clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; clock-names = "i2c"; + status = "disabled"; }; @@ -632,6 +643,7 @@ usbdrd: usb@13600000 { clock-names = "bus_early", "ref"; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; usbdrd_dwc3: usb@0 { @@ -651,6 +663,7 @@ usbdrd_phy: phy@135d0000 { clock-names = "phy", "ref"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; + status = "disabled"; }; @@ -665,6 +678,7 @@ usi_uart: usi@138200c0 { clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, <&cmu_peri CLK_GOUT_UART_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_0: serial@13820000 { @@ -676,6 +690,7 @@ serial_0: serial@13820000 { clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, <&cmu_peri CLK_GOUT_UART_IPCLK>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; }; @@ -691,6 +706,7 @@ usi_hsi2c_0: usi@138a00c0 { clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_0: i2c@138a0000 { @@ -705,6 +721,7 @@ hsi2c_0: i2c@138a0000 { clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; }; }; @@ -720,6 +737,7 @@ usi_hsi2c_1: usi@138b00c0 { clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_1: i2c@138b0000 { @@ -734,6 +752,7 @@ hsi2c_1: i2c@138b0000 { clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; }; }; @@ -749,6 +768,7 @@ usi_hsi2c_2: usi@138c00c0 { clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_2: i2c@138c0000 { @@ -763,6 +783,7 @@ hsi2c_2: i2c@138c0000 { clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; }; }; @@ -778,6 +799,7 @@ usi_spi_0: usi@139400c0 { clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, <&cmu_peri CLK_GOUT_SPI0_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; spi_0: spi@13940000 { @@ -795,6 +817,7 @@ spi_0: spi@13940000 { samsung,spi-src-clk = <0>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -810,6 +833,7 @@ usi_cmgp0: usi@11d000c0 { clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_3: i2c@11d00000 { @@ -824,6 +848,7 @@ hsi2c_3: i2c@11d00000 { clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; }; @@ -836,6 +861,7 @@ serial_1: serial@11d00000 { clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; @@ -854,6 +880,7 @@ spi_1: spi@11d00000 { samsung,spi-src-clk = <0>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -869,6 +896,7 @@ usi_cmgp1: usi@11d200c0 { clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_4: i2c@11d20000 { @@ -883,6 +911,7 @@ hsi2c_4: i2c@11d20000 { clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; }; @@ -895,6 +924,7 @@ serial_2: serial@11d20000 { clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; }; @@ -913,6 +943,7 @@ spi_2: spi@11d20000 { samsung,spi-src-clk = <0>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts index 305dc72f93d8..da02b557a8f2 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts @@ -192,5 +192,6 @@ ts_int: ts-int-pins { &usi9 { samsung,mode = ; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index ff114cd6c9ea..e3b6d37aac09 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -244,6 +244,7 @@ serial_0: serial@10430000 { pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -256,6 +257,7 @@ usi0: usi@10440000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric0 0x1000>; + status = "disabled"; hsi2c_5: i2c@0 { @@ -283,6 +285,7 @@ serial_2: serial@0 { pinctrl-0 = <&uart2_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -298,6 +301,7 @@ spi_2: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -326,6 +330,7 @@ usi1: usi@10460000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric0 0x1004>; + status = "disabled"; hsi2c_7: i2c@0 { @@ -353,6 +358,7 @@ serial_3: serial@0 { pinctrl-0 = <&uart3_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -368,6 +374,7 @@ spi_3: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -396,6 +403,7 @@ usi2: usi@10480000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric0 0x1008>; + status = "disabled"; hsi2c_9: i2c@0 { @@ -423,6 +431,7 @@ serial_4: serial@0 { pinctrl-0 = <&uart4_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -438,6 +447,7 @@ spi_4: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -466,6 +476,7 @@ usi3: usi@104a0000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric0 0x100c>; + status = "disabled"; hsi2c_11: i2c@0 { @@ -493,6 +504,7 @@ serial_5: serial@0 { pinctrl-0 = <&uart5_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -508,6 +520,7 @@ spi_5: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -575,6 +588,7 @@ serial_1: serial@10830000 { pinctrl-names = "default"; pinctrl-0 = <&uart1_bus>; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -587,6 +601,7 @@ usi4: usi@10840000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1008>; + status = "disabled"; hsi2c_13: i2c@0 { @@ -614,6 +629,7 @@ serial_6: serial@0 { pinctrl-0 = <&uart6_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -629,6 +645,7 @@ spi_6: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -657,6 +674,7 @@ usi5: usi@10860000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x100c>; + status = "disabled"; hsi2c_15: i2c@0 { @@ -684,6 +702,7 @@ serial_7: serial@0 { pinctrl-0 = <&uart7_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -699,6 +718,7 @@ spi_7: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -727,6 +747,7 @@ usi6: usi@10880000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1010>; + status = "disabled"; hsi2c_17: i2c@0 { @@ -754,6 +775,7 @@ serial_8: serial@0 { pinctrl-0 = <&uart8_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -769,6 +791,7 @@ spi_8: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -797,6 +820,7 @@ usi7: usi@108a0000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1014>; + status = "disabled"; hsi2c_19: i2c@0 { @@ -824,6 +848,7 @@ serial_9: serial@0 { pinctrl-0 = <&uart9_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -839,6 +864,7 @@ spi_9: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -867,6 +893,7 @@ usi8: usi@108c0000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1018>; + status = "disabled"; hsi2c_21: i2c@0 { @@ -894,6 +921,7 @@ serial_10: serial@0 { pinctrl-0 = <&uart10_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -909,6 +937,7 @@ spi_10: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -937,6 +966,7 @@ usi9: usi@108e0000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x101c>; + status = "disabled"; hsi2c_23: i2c@0 { @@ -964,6 +994,7 @@ serial_11: serial@0 { pinctrl-0 = <&uart11_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -979,6 +1010,7 @@ spi_11: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -1007,6 +1039,7 @@ usi10: usi@10900000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1020>; + status = "disabled"; hsi2c_25: i2c@0 { @@ -1034,6 +1067,7 @@ serial_12: serial@0 { pinctrl-0 = <&uart12_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1049,6 +1083,7 @@ spi_12: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -1077,6 +1112,7 @@ usi11: usi@10920000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1024>; + status = "disabled"; hsi2c_27: i2c@0 { @@ -1104,6 +1140,7 @@ serial_13: serial@0 { pinctrl-0 = <&uart13_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1119,6 +1156,7 @@ spi_13: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -1147,6 +1185,7 @@ usi12: usi@10940000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x1028>; + status = "disabled"; hsi2c_29: i2c@0 { @@ -1174,6 +1213,7 @@ serial_14: serial@0 { pinctrl-0 = <&uart14_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1189,6 +1229,7 @@ spi_14: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -1217,6 +1258,7 @@ usi13: usi@10960000 { #address-cells = <1>; #size-cells = <1>; samsung,sysreg = <&syscon_peric1 0x102c>; + status = "disabled"; hsi2c_31: i2c@0 { @@ -1244,6 +1286,7 @@ serial_15: serial@0 { pinctrl-0 = <&uart15_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1259,6 +1302,7 @@ spi_15: spi@0 { pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; @@ -1356,6 +1400,7 @@ spi_0: spi@109d0000 { interrupts = ; pinctrl-0 = <&spi0_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1371,6 +1416,7 @@ spi_1: spi@109e0000 { interrupts = ; pinctrl-0 = <&spi1_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1437,6 +1483,7 @@ mmc: mmc@11500000 { interrupts = ; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts index 9f0ad4f9673a..a58923229128 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-c1s.dts +++ b/arch/arm64/boot/dts/exynos/exynos990-c1s.dts @@ -121,9 +121,10 @@ key_volup: key-volup-pins { }; &usbdrd { - status = "okay"; vdd10-supply = <®_dummy>; vdd33-supply = <®_dummy>; + + status = "okay"; }; &usbdrd_phy { diff --git a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts index 55342db61979..563dbde6abc7 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-r8s.dts +++ b/arch/arm64/boot/dts/exynos/exynos990-r8s.dts @@ -121,9 +121,10 @@ key_volup: key-volup-pins { }; &usbdrd { - status = "okay"; vdd10-supply = <®_dummy>; vdd33-supply = <®_dummy>; + + status = "okay"; }; &usbdrd_phy { diff --git a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi index 7b97220cccb7..01ecdf484dab 100644 --- a/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi @@ -104,9 +104,10 @@ key_volup: key-volup-pins { }; &usbdrd { - status = "okay"; vdd10-supply = <®_dummy>; vdd33-supply = <®_dummy>; + + status = "okay"; }; &usbdrd_phy { diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index 2e6fb24a3c92..c15ccaff2666 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -320,6 +320,7 @@ usbdrd_phy: phy@10c00000 { clock-names = "phy", "ref"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; + status = "disabled"; }; @@ -332,6 +333,7 @@ usbdrd: usb@10e00000 { clock-names = "bus_early", "ref"; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; usbdrd_dwc3: usb@0 { diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index de2c1de51a76..9912432c5961 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -103,11 +103,13 @@ key_volup: key-volup-pins { &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm_tout3>; + status = "okay"; }; &serial_0 { pinctrl-0 = <&uart0_bus_dual>; + status = "okay"; }; @@ -120,17 +122,20 @@ &ufs_1_phy { }; &ufs_0 { - status = "okay"; vcc-supply = <&ufs_0_fixed_vcc_reg>; + + status = "okay"; }; &ufs_1 { - status = "okay"; vcc-supply = <&ufs_1_fixed_vcc_reg>; + + status = "okay"; }; &usi_0 { samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 2c34a2b30ad0..94f8d1c47676 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -450,6 +450,7 @@ usi_0: usi@103000c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_0: serial@10300000 { @@ -463,6 +464,7 @@ serial_0: serial@10300000 { <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -483,6 +485,7 @@ spi_0: spi@10300000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <256>; + status = "disabled"; }; @@ -497,6 +500,7 @@ hsi2c_0: i2c@10300000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -513,6 +517,7 @@ usi_i2c_0: usi@103100c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_1: i2c@10310000 { @@ -526,6 +531,7 @@ hsi2c_1: i2c@10310000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -542,6 +548,7 @@ usi_1: usi@103200c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_1: serial@10320000 { @@ -555,6 +562,7 @@ serial_1: serial@10320000 { <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -575,6 +583,7 @@ spi_1: spi@10320000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <256>; + status = "disabled"; }; @@ -589,6 +598,7 @@ hsi2c_2: i2c@10320000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -605,6 +615,7 @@ usi_i2c_1: usi@103300c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_3: i2c@10330000 { @@ -618,6 +629,7 @@ hsi2c_3: i2c@10330000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -634,6 +646,7 @@ usi_2: usi@103400c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_2: serial@10340000 { @@ -647,6 +660,7 @@ serial_2: serial@10340000 { <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -667,6 +681,7 @@ spi_2: spi@10340000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -681,6 +696,7 @@ hsi2c_4: i2c@10340000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -697,6 +713,7 @@ usi_i2c_2: usi@103500c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_5: i2c@10350000 { @@ -710,6 +727,7 @@ hsi2c_5: i2c@10350000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -726,6 +744,7 @@ usi_3: usi@103600c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_3: serial@10360000 { @@ -739,6 +758,7 @@ serial_3: serial@10360000 { <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -759,6 +779,7 @@ spi_3: spi@10360000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -773,6 +794,7 @@ hsi2c_6: i2c@10360000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -789,6 +811,7 @@ usi_i2c_3: usi@103700c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_7: i2c@10370000 { @@ -802,6 +825,7 @@ hsi2c_7: i2c@10370000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -818,6 +842,7 @@ usi_4: usi@103800c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_4: serial@10380000 { @@ -831,6 +856,7 @@ serial_4: serial@10380000 { <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -851,6 +877,7 @@ spi_4: spi@10380000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -865,6 +892,7 @@ hsi2c_8: i2c@10380000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -881,6 +909,7 @@ usi_i2c_4: usi@103900c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_9: i2c@10390000 { @@ -894,6 +923,7 @@ hsi2c_9: i2c@10390000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -910,6 +940,7 @@ usi_5: usi@103a00c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_5: serial@103a0000 { @@ -923,6 +954,7 @@ serial_5: serial@103a0000 { <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -943,6 +975,7 @@ spi_5: spi@103a0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -957,6 +990,7 @@ hsi2c_10: i2c@103a0000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -973,6 +1007,7 @@ usi_i2c_5: usi@103b00c0 { clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_11: i2c@103b0000 { @@ -986,6 +1021,7 @@ hsi2c_11: i2c@103b0000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1002,6 +1038,7 @@ usi_6: usi@109000c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_6: serial@10900000 { @@ -1015,6 +1052,7 @@ serial_6: serial@10900000 { <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -1035,6 +1073,7 @@ spi_6: spi@10900000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <256>; + status = "disabled"; }; @@ -1049,6 +1088,7 @@ hsi2c_12: i2c@10900000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1065,6 +1105,7 @@ usi_i2c_6: usi@109100c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_13: i2c@10910000 { @@ -1078,6 +1119,7 @@ hsi2c_13: i2c@10910000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1094,6 +1136,7 @@ usi_7: usi@109200c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_7: serial@10920000 { @@ -1107,6 +1150,7 @@ serial_7: serial@10920000 { <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1127,6 +1171,7 @@ spi_7: spi@10920000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -1141,6 +1186,7 @@ hsi2c_14: i2c@10920000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1157,6 +1203,7 @@ usi_i2c_7: usi@109300c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_15: i2c@10930000 { @@ -1170,6 +1217,7 @@ hsi2c_15: i2c@10930000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1186,6 +1234,7 @@ usi_8: usi@109400c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_8: serial@10940000 { @@ -1199,6 +1248,7 @@ serial_8: serial@10940000 { <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1219,6 +1269,7 @@ spi_8: spi@10940000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -1233,6 +1284,7 @@ hsi2c_16: i2c@10940000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1249,6 +1301,7 @@ usi_i2c_8: usi@109500c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_17: i2c@10950000 { @@ -1262,6 +1315,7 @@ hsi2c_17: i2c@10950000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1278,6 +1332,7 @@ usi_9: usi@109600c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_9: serial@10960000 { @@ -1291,6 +1346,7 @@ serial_9: serial@10960000 { <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1311,6 +1367,7 @@ spi_9: spi@10960000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -1325,6 +1382,7 @@ hsi2c_18: i2c@10960000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1341,6 +1399,7 @@ usi_i2c_9: usi@109700c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_19: i2c@10970000 { @@ -1354,6 +1413,7 @@ hsi2c_19: i2c@10970000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1370,6 +1430,7 @@ usi_10: usi@109800c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_10: serial@10980000 { @@ -1383,6 +1444,7 @@ serial_10: serial@10980000 { <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1403,6 +1465,7 @@ spi_10: spi@10980000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -1417,6 +1480,7 @@ hsi2c_20: i2c@10980000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1433,6 +1497,7 @@ usi_i2c_10: usi@109900c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_21: i2c@10990000 { @@ -1446,6 +1511,7 @@ hsi2c_21: i2c@10990000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1462,6 +1528,7 @@ usi_11: usi@109a00c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_11: serial@109a0000 { @@ -1475,6 +1542,7 @@ serial_11: serial@109a0000 { <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1493,6 +1561,7 @@ spi_11: spi@109a0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -1507,6 +1576,7 @@ hsi2c_22: i2c@109a0000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1523,6 +1593,7 @@ usi_i2c_11: usi@109b00c0 { clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; clock-names = "pclk", "ipclk"; + status = "disabled"; hsi2c_23: i2c@109b0000 { @@ -1536,6 +1607,7 @@ hsi2c_23: i2c@109b0000 { clock-names = "hsi2c", "hsi2c_pclk"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -1548,6 +1620,7 @@ ufs_0_phy: phy@17e04000 { #phy-cells = <0>; clocks = <&xtcxo>; clock-names = "ref_clk"; + status = "disabled"; }; @@ -1569,6 +1642,7 @@ ufs_0: ufs@17e00000 { phys = <&ufs_0_phy>; phy-names = "ufs-phy"; samsung,sysreg = <&syscon_fsys2 0x710>; + status = "disabled"; }; @@ -1580,6 +1654,7 @@ ufs_1_phy: phy@17f04000 { #phy-cells = <0>; clocks = <&xtcxo>; clock-names = "ref_clk"; + status = "disabled"; }; @@ -1601,6 +1676,7 @@ ufs_1: ufs@17f00000 { phys = <&ufs_1_phy>; phy-names = "ufs-phy"; samsung,sysreg = <&syscon_fsys2 0x714>; + status = "disabled"; }; @@ -1632,6 +1708,7 @@ pwm: pwm@103f0000 { #pwm-cells = <3>; clocks = <&xtcxo>; clock-names = "timers"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts index 5873720c213e..a92e5751bf9b 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts @@ -71,6 +71,7 @@ key_back: key-back-pins { &pwm { pinctrl-names = "default"; pinctrl-0 = <&pwm_tout0>; + status = "okay"; }; @@ -80,6 +81,7 @@ &serial_0 { &usi_0 { samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index e2f962dc1b3d..f42207bdc701 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -440,6 +440,7 @@ usi_0: usi@108800c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_0: serial@10880000 { @@ -453,6 +454,7 @@ serial_0: serial@10880000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -473,6 +475,7 @@ spi_0: spi@10880000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <256>; + status = "disabled"; }; }; @@ -489,6 +492,7 @@ usi_1: usi@108a00c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_1: serial@108a0000 { @@ -502,6 +506,7 @@ serial_1: serial@108a0000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -522,6 +527,7 @@ spi_1: spi@108a0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <256>; + status = "disabled"; }; }; @@ -538,6 +544,7 @@ usi_2: usi@108c00c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_2: serial@108c0000 { @@ -551,6 +558,7 @@ serial_2: serial@108c0000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -571,6 +579,7 @@ spi_2: spi@108c0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -587,6 +596,7 @@ usi_3: usi@108e00c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_3: serial@108e0000 { @@ -600,6 +610,7 @@ serial_3: serial@108e0000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -620,6 +631,7 @@ spi_3: spi@108e0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -636,6 +648,7 @@ usi_4: usi@109000c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_4: serial@10900000 { @@ -649,6 +662,7 @@ serial_4: serial@10900000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -669,6 +683,7 @@ spi_4: spi@10900000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -685,6 +700,7 @@ usi_5: usi@109200c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_5: serial@10920000 { @@ -698,6 +714,7 @@ serial_5: serial@10920000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -718,6 +735,7 @@ spi_5: spi@10920000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -734,6 +752,7 @@ usi_6: usi@109400c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_6: serial@10940000 { @@ -747,6 +766,7 @@ serial_6: serial@10940000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI06_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -767,6 +787,7 @@ spi_6: spi@10940000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -783,6 +804,7 @@ usi_7: usi@109600c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_7: serial@10960000 { @@ -796,6 +818,7 @@ serial_7: serial@10960000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI07_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -816,6 +839,7 @@ spi_7: spi@10960000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -832,6 +856,7 @@ usi_8: usi@109800c0 { clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_8: serial@10980000 { @@ -845,6 +870,7 @@ serial_8: serial@10980000 { <&cmu_peric0 CLK_DOUT_PERIC0_USI08_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -865,6 +891,7 @@ spi_8: spi@10980000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; @@ -878,6 +905,7 @@ pwm: pwm@109b0000 { #pwm-cells = <3>; clocks = <&xtcxo>; clock-names = "timers"; + status = "disabled"; }; @@ -918,6 +946,7 @@ usi_9: usi@10c800c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_9: serial@10c8000 { @@ -931,6 +960,7 @@ serial_9: serial@10c8000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <256>; + status = "disabled"; }; @@ -951,6 +981,7 @@ spi_9: spi@10c80000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <256>; + status = "disabled"; }; }; @@ -967,6 +998,7 @@ usi_10: usi@10ca00c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_10: serial@10ca0000 { @@ -980,6 +1012,7 @@ serial_10: serial@10ca0000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1000,6 +1033,7 @@ spi_10: spi@10ca0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1016,6 +1050,7 @@ usi_11: usi@10cc00c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_11: serial@10cc0000 { @@ -1029,6 +1064,7 @@ serial_11: serial@10cc0000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1049,6 +1085,7 @@ spi_11: spi@10cc0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1065,6 +1102,7 @@ usi_12: usi@10ce00c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_12: serial@10ce0000 { @@ -1078,6 +1116,7 @@ serial_12: serial@10ce0000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI12_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1098,6 +1137,7 @@ spi_12: spi@10ce0000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1114,6 +1154,7 @@ usi_13: usi@10d000c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_13: serial@10d00000 { @@ -1127,6 +1168,7 @@ serial_13: serial@10d00000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI13_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1147,6 +1189,7 @@ spi_13: spi@10d00000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1163,6 +1206,7 @@ usi_14: usi@10d200c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_14: serial@10d20000 { @@ -1176,6 +1220,7 @@ serial_14: serial@10d20000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI14_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1196,6 +1241,7 @@ spi_14: spi@10d20000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1212,6 +1258,7 @@ usi_15: usi@10d400c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_15: serial@10d40000 { @@ -1225,6 +1272,7 @@ serial_15: serial@10d40000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI15_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1245,6 +1293,7 @@ spi_15: spi@10d40000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1261,6 +1310,7 @@ usi_16: usi@10d600c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_16: serial@10d60000 { @@ -1274,6 +1324,7 @@ serial_16: serial@10d60000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI16_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1294,6 +1345,7 @@ spi_16: spi@10d60000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1310,6 +1362,7 @@ usi_17: usi@10d800c0 { clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; clock-names = "pclk", "ipclk"; + status = "disabled"; serial_17: serial@10d80000 { @@ -1323,6 +1376,7 @@ serial_17: serial@10d80000 { <&cmu_peric1 CLK_DOUT_PERIC1_USI17_USI>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1343,6 +1397,7 @@ spi_17: spi@10d80000 { #address-cells = <1>; #size-cells = <0>; fifo-depth = <64>; + status = "disabled"; }; }; @@ -1468,6 +1523,7 @@ ufs_0: ufs@16e00000 { phy-names = "ufs-phy"; samsung,sysreg = <&syscon_hsi2 0x710>; dma-coherent; + status = "disabled"; }; @@ -1479,6 +1535,7 @@ ufs_0_phy: phy@16e04000 { clock-names = "ref_clk"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; + status = "disabled"; }; From 873fa6bd9a4f735575cd46a2824e0f0a454d8779 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:06:57 +0200 Subject: [PATCH 756/864] arm64: dts: exynos: Align continued properties and add missing blank lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Trivial white-space only changes to adjust to DTS coding style and fix dt-check-style strict warnings like: [required-blank-lines] child node must be preceded by a blank line [continuation-alignment] continuation should align to column 39 (under < or ") Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-2-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- .../arm64/boot/dts/exynos/exynos5433-bus.dtsi | 19 ++ .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 8 +- .../dts/exynos/exynos5433-tm2-common.dtsi | 120 +++++---- .../arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 45 ++++ arch/arm64/boot/dts/exynos/exynos5433.dtsi | 230 ++++++++++-------- .../boot/dts/exynos/exynos7-espresso.dts | 3 +- .../boot/dts/exynos/exynos7-trip-points.dtsi | 7 + arch/arm64/boot/dts/exynos/exynos7.dtsi | 34 ++- .../boot/dts/exynos/exynos7870-j6lte.dts | 4 +- arch/arm64/boot/dts/exynos/exynos7870.dtsi | 9 +- arch/arm64/boot/dts/exynos/exynos7885.dtsi | 9 +- .../boot/dts/exynos/exynos850-pinctrl.dtsi | 1 + arch/arm64/boot/dts/exynos/exynos850.dtsi | 16 +- arch/arm64/boot/dts/exynos/exynos8855.dtsi | 5 + arch/arm64/boot/dts/exynos/exynos8895.dtsi | 9 +- arch/arm64/boot/dts/exynos/exynos9810.dtsi | 9 +- arch/arm64/boot/dts/exynos/exynos990.dtsi | 3 +- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 9 +- .../arm64/boot/dts/exynos/exynosautov920.dtsi | 7 + 19 files changed, 359 insertions(+), 188 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi index 0c200df9996f..9bfa0474675c 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi @@ -105,22 +105,27 @@ opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1075000>; }; + opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-microvolt = <1000000>; }; + opp-200000000 { opp-hz = /bits/ 64 <200000000>; opp-microvolt = <975000>; }; + opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-microvolt = <962500>; }; + opp-134000000 { opp-hz = /bits/ 64 <134000000>; opp-microvolt = <950000>; }; + opp-100000000 { opp-hz = /bits/ 64 <100000000>; opp-microvolt = <937500>; @@ -133,15 +138,19 @@ bus_g2d_266_opp_table: opp-table-3 { opp-267000000 { opp-hz = /bits/ 64 <267000000>; }; + opp-200000000 { opp-hz = /bits/ 64 <200000000>; }; + opp-160000000 { opp-hz = /bits/ 64 <160000000>; }; + opp-134000000 { opp-hz = /bits/ 64 <134000000>; }; + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; @@ -153,9 +162,11 @@ bus_gscl_opp_table: opp-table-4 { opp-333000000 { opp-hz = /bits/ 64 <333000000>; }; + opp-222000000 { opp-hz = /bits/ 64 <222000000>; }; + opp-166500000 { opp-hz = /bits/ 64 <166500000>; }; @@ -168,18 +179,23 @@ bus_hevc_opp_table: opp-table-5 { opp-400000000 { opp-hz = /bits/ 64 <400000000>; }; + opp-267000000 { opp-hz = /bits/ 64 <267000000>; }; + opp-200000000 { opp-hz = /bits/ 64 <200000000>; }; + opp-160000000 { opp-hz = /bits/ 64 <160000000>; }; + opp-134000000 { opp-hz = /bits/ 64 <134000000>; }; + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; @@ -191,12 +207,15 @@ bus_noc2_opp_table: opp-table-6 { opp-400000000 { opp-hz = /bits/ 64 <400000000>; }; + opp-200000000 { opp-hz = /bits/ 64 <200000000>; }; + opp-134000000 { opp-hz = /bits/ 64 <134000000>; }; + opp-100000000 { opp-hz = /bits/ 64 <100000000>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 681553577ebc..d6850c51db26 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -139,7 +139,7 @@ gpz1: gpz1-gpio-bank { i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", - "gpz0-4", "gpz0-5", "gpz0-6"; + "gpz0-4", "gpz0-5", "gpz0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; @@ -572,16 +572,14 @@ hs_i2c9_bus: hs-i2c9-bus-pins { }; i2s1_bus: i2s1-bus-pins { - samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", - "gpd4-3", "gpd4-4"; + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", "gpd4-3", "gpd4-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; pcm1_bus: pcm1-bus-pins { - samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", - "gpd4-3", "gpd4-4"; + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", "gpd4-3", "gpd4-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index bc5ff66d8455..0ad02a098765 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -234,60 +234,60 @@ &bus_noc2 { &cmu_aud { assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, - <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, - <&cmu_top CLK_MOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_MOUT_SCLK_AUDIO0>, - <&cmu_top CLK_MOUT_SCLK_AUDIO1>, - <&cmu_top CLK_MOUT_SCLK_SPDIF>, + <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>, + <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>, + <&cmu_top CLK_MOUT_AUD_PLL>, + <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, + <&cmu_top CLK_MOUT_SCLK_AUDIO0>, + <&cmu_top CLK_MOUT_SCLK_AUDIO1>, + <&cmu_top CLK_MOUT_SCLK_SPDIF>, - <&cmu_aud CLK_DIV_AUD_CA5>, - <&cmu_aud CLK_DIV_ACLK_AUD>, - <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, - <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, - <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, - <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, - <&cmu_aud CLK_DIV_SCLK_AUD_UART>, - <&cmu_top CLK_DIV_SCLK_AUDIO0>, - <&cmu_top CLK_DIV_SCLK_AUDIO1>, - <&cmu_top CLK_DIV_SCLK_PCM1>, - <&cmu_top CLK_DIV_SCLK_I2S1>; + <&cmu_aud CLK_DIV_AUD_CA5>, + <&cmu_aud CLK_DIV_ACLK_AUD>, + <&cmu_aud CLK_DIV_PCLK_DBG_AUD>, + <&cmu_aud CLK_DIV_SCLK_AUD_I2S>, + <&cmu_aud CLK_DIV_SCLK_AUD_PCM>, + <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>, + <&cmu_aud CLK_DIV_SCLK_AUD_UART>, + <&cmu_top CLK_DIV_SCLK_AUDIO0>, + <&cmu_top CLK_DIV_SCLK_AUDIO1>, + <&cmu_top CLK_DIV_SCLK_PCM1>, + <&cmu_top CLK_DIV_SCLK_I2S1>; assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>, - <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_aud CLK_MOUT_AUD_PLL_USER>, - <&cmu_top CLK_FOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, - <&cmu_top CLK_SCLK_AUDIO0>; + <&cmu_aud CLK_MOUT_AUD_PLL_USER>, + <&cmu_aud CLK_MOUT_AUD_PLL_USER>, + <&cmu_top CLK_FOUT_AUD_PLL>, + <&cmu_top CLK_MOUT_AUD_PLL>, + <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, + <&cmu_top CLK_MOUT_AUD_PLL_USER_T>, + <&cmu_top CLK_SCLK_AUDIO0>; assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, - <196608001>, <65536001>, <32768001>, <49152001>, - <2048001>, <24576001>, <196608001>, - <24576001>, <98304001>, <2048001>, <49152001>; + <196608001>, <65536001>, <32768001>, <49152001>, + <2048001>, <24576001>, <196608001>, + <24576001>, <98304001>, <2048001>, <49152001>; }; &cmu_fsys { assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>, - <&cmu_top CLK_MOUT_SCLK_USBHOST30>, - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, - <&cmu_top CLK_DIV_SCLK_USBDRD30>, - <&cmu_top CLK_DIV_SCLK_USBHOST30>; + <&cmu_top CLK_MOUT_SCLK_USBHOST30>, + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>, + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>, + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>, + <&cmu_top CLK_DIV_SCLK_USBDRD30>, + <&cmu_top CLK_DIV_SCLK_USBHOST30>; assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>, - <&cmu_top CLK_MOUT_BUS_PLL_USER>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; + <&cmu_top CLK_MOUT_BUS_PLL_USER>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>; assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <66700000>, <66700000>; }; @@ -347,6 +347,7 @@ ports { port@0 { reg = <0>; + tv_to_hdmi: endpoint { remote-endpoint = <&hdmi_to_tv>; }; @@ -386,6 +387,7 @@ ports { port@0 { reg = <0>; + hdmi_to_tv: endpoint { remote-endpoint = <&tv_to_hdmi>; }; @@ -393,6 +395,7 @@ hdmi_to_tv: endpoint { port@1 { reg = <1>; + hdmi_to_mhl: endpoint { remote-endpoint = <&mhl_to_hdmi>; }; @@ -416,8 +419,7 @@ pmic@66 { s2mps13_osc: clocks { compatible = "samsung,s2mps13-clk"; #clock-cells = <1>; - clock-output-names = "s2mps13_ap", "s2mps13_cp", - "s2mps13_bt"; + clock-output-names = "s2mps13_ap", "s2mps13_cp", "s2mps13_bt"; }; regulators { @@ -433,6 +435,7 @@ ldo2_reg: LDO2 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -450,6 +453,7 @@ ldo4_reg: LDO4 { regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -460,6 +464,7 @@ ldo5_reg: LDO5 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -469,6 +474,7 @@ ldo6_reg: LDO6 { regulator-name = "VDD10_MIPI2L_1.0V_AP"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-state-mem { regulator-off-in-suspend; }; @@ -479,6 +485,7 @@ ldo7_reg: LDO7 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -489,6 +496,7 @@ ldo8_reg: LDO8 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -499,6 +507,7 @@ ldo9_reg: LDO9 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -508,6 +517,7 @@ ldo10_reg: LDO10 { regulator-name = "VDD33_USB30_3.0V_AP"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; + regulator-state-mem { regulator-off-in-suspend; }; @@ -518,6 +528,7 @@ ldo11_reg: LDO11 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -535,6 +546,7 @@ ldo13_reg: LDO13 { regulator-min-microvolt = <950000>; regulator-max-microvolt = <950000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -545,6 +557,7 @@ ldo14_reg: LDO14 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -555,6 +568,7 @@ ldo15_reg: LDO15 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -721,6 +735,7 @@ buck1_reg: BUCK1 { regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -731,6 +746,7 @@ buck2_reg: BUCK2 { regulator-min-microvolt = <900000>; regulator-max-microvolt = <1300000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -741,6 +757,7 @@ buck3_reg: BUCK3 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1200000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -751,6 +768,7 @@ buck4_reg: BUCK4 { regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -761,6 +779,7 @@ buck5_reg: BUCK5 { regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -771,6 +790,7 @@ buck6_reg: BUCK6 { regulator-min-microvolt = <600000>; regulator-max-microvolt = <1500000>; regulator-always-on; + regulator-state-mem { regulator-off-in-suspend; }; @@ -855,6 +875,7 @@ ports { port@0 { reg = <0>; + mhl_to_hdmi: endpoint { remote-endpoint = <&hdmi_to_mhl>; }; @@ -862,6 +883,7 @@ mhl_to_hdmi: endpoint { port@1 { reg = <1>; + mhl_to_musb_con: endpoint { remote-endpoint = <&musb_con_to_mhl>; }; @@ -906,6 +928,7 @@ port@0 { port@3 { reg = <3>; + musb_con_to_mhl: endpoint { remote-endpoint = <&mhl_to_musb_con>; }; @@ -924,6 +947,7 @@ muic_to_usb: endpoint { regulators { compatible = "maxim,max77843-regulator"; + safeout1_reg: SAFEOUT1 { regulator-name = "SAFEOUT1"; regulator-min-microvolt = <3300000>; @@ -981,7 +1005,7 @@ &mshc_0 { fifo-depth = <0x80>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4 - &sd0_bus8 &sd0_rdqs>; + &sd0_bus8 &sd0_rdqs>; bus-width = <8>; assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>; assigned-clock-rates = <800000000>; @@ -1304,7 +1328,7 @@ wm5110: audio-codec@0 { interrupt-parent = <&gpa0>; interrupts = <4 IRQ_TYPE_NONE>; clocks = <&pmu_system_controller 0>, - <&s2mps13_osc S2MPS11_CLK_BT>; + <&s2mps13_osc S2MPS11_CLK_BT>; clock-names = "mclk1", "mclk2"; gpio-controller; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi index 81b72393dd0d..57b335f579d8 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi @@ -13,37 +13,44 @@ atlas0_thermal: atlas0-thermal { thermal-sensors = <&tmu_atlas0>; polling-delay-passive = <0>; polling-delay = <0>; + trips { atlas0_alert_0: atlas0-alert-0 { temperature = <65000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas0_alert_1: atlas0-alert-1 { temperature = <70000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas0_alert_2: atlas0-alert-2 { temperature = <75000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas0_alert_3: atlas0-alert-3 { temperature = <80000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas0_alert_4: atlas0-alert-4 { temperature = <85000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas0_alert_5: atlas0-alert-5 { temperature = <90000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas0_alert_6: atlas0-alert-6 { temperature = <95000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ @@ -58,36 +65,42 @@ map0 { cooling-device = <&cpu4 1 2>, <&cpu5 1 2>, <&cpu6 1 2>, <&cpu7 1 2>; }; + map1 { /* Set maximum frequency as 1700MHz */ trip = <&atlas0_alert_1>; cooling-device = <&cpu4 2 3>, <&cpu5 2 3>, <&cpu6 2 3>, <&cpu7 2 3>; }; + map2 { /* Set maximum frequency as 1600MHz */ trip = <&atlas0_alert_2>; cooling-device = <&cpu4 3 4>, <&cpu5 3 4>, <&cpu6 3 4>, <&cpu7 3 4>; }; + map3 { /* Set maximum frequency as 1500MHz */ trip = <&atlas0_alert_3>; cooling-device = <&cpu4 4 5>, <&cpu5 4 5>, <&cpu6 4 5>, <&cpu7 4 5>; }; + map4 { /* Set maximum frequency as 1400MHz */ trip = <&atlas0_alert_4>; cooling-device = <&cpu4 5 7>, <&cpu5 5 7>, <&cpu6 5 7>, <&cpu7 5 7>; }; + map5 { /* Set maximum frequencyas 1200MHz */ trip = <&atlas0_alert_5>; cooling-device = <&cpu4 7 9>, <&cpu5 7 9>, <&cpu6 7 9>, <&cpu7 7 9>; }; + map6 { /* Set maximum frequency as 1000MHz */ trip = <&atlas0_alert_6>; @@ -101,37 +114,44 @@ atlas1_thermal: atlas1-thermal { thermal-sensors = <&tmu_atlas1>; polling-delay-passive = <0>; polling-delay = <0>; + trips { atlas1_alert_0: atlas1-alert-0 { temperature = <65000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas1_alert_1: atlas1-alert-1 { temperature = <70000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas1_alert_2: atlas1-alert-2 { temperature = <75000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas1_alert_3: atlas1-alert-3 { temperature = <80000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas1_alert_4: atlas1-alert-4 { temperature = <85000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas1_alert_5: atlas1-alert-5 { temperature = <90000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + atlas1_alert_6: atlas1-alert-6 { temperature = <95000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ @@ -144,37 +164,44 @@ g3d_thermal: g3d-thermal { thermal-sensors = <&tmu_g3d>; polling-delay-passive = <0>; polling-delay = <0>; + trips { g3d_alert_0: g3d-alert-0 { temperature = <70000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + g3d_alert_1: g3d-alert-1 { temperature = <75000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + g3d_alert_2: g3d-alert-2 { temperature = <80000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + g3d_alert_3: g3d-alert-3 { temperature = <85000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + g3d_alert_4: g3d-alert-4 { temperature = <90000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + g3d_alert_5: g3d-alert-5 { temperature = <95000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + g3d_alert_6: g3d-alert-6 { temperature = <100000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ @@ -187,37 +214,44 @@ apollo_thermal: apollo-thermal { thermal-sensors = <&tmu_apollo>; polling-delay-passive = <0>; polling-delay = <0>; + trips { apollo_alert_0: apollo-alert-0 { temperature = <65000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + apollo_alert_1: apollo-alert-1 { temperature = <70000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + apollo_alert_2: apollo-alert-2 { temperature = <75000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + apollo_alert_3: apollo-alert-3 { temperature = <80000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + apollo_alert_4: apollo-alert-4 { temperature = <85000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + apollo_alert_5: apollo-alert-5 { temperature = <90000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + apollo_alert_6: apollo-alert-6 { temperature = <95000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ @@ -232,24 +266,28 @@ map0 { cooling-device = <&cpu0 1 2>, <&cpu1 1 2>, <&cpu2 1 2>, <&cpu3 1 2>; }; + map1 { /* Set maximum frequency as 1100MHz */ trip = <&apollo_alert_3>; cooling-device = <&cpu0 2 3>, <&cpu1 2 3>, <&cpu2 2 3>, <&cpu3 2 3>; }; + map2 { /* Set maximum frequency as 1000MHz */ trip = <&apollo_alert_4>; cooling-device = <&cpu0 3 4>, <&cpu1 3 4>, <&cpu2 3 4>, <&cpu3 3 4>; }; + map3 { /* Set maximum frequency as 900MHz */ trip = <&apollo_alert_5>; cooling-device = <&cpu0 4 5>, <&cpu1 4 5>, <&cpu2 4 5>, <&cpu3 4 5>; }; + map4 { /* Set maximum frequency as 800MHz */ trip = <&apollo_alert_6>; @@ -263,37 +301,44 @@ isp_thermal: isp-thermal { thermal-sensors = <&tmu_isp>; polling-delay-passive = <0>; polling-delay = <0>; + trips { isp_alert_0: isp-alert-0 { temperature = <80000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + isp_alert_1: isp-alert-1 { temperature = <85000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + isp_alert_2: isp-alert-2 { temperature = <90000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + isp_alert_3: isp-alert-3 { temperature = <95000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + isp_alert_4: isp-alert-4 { temperature = <100000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + isp_alert_5: isp-alert-5 { temperature = <105000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ type = "active"; }; + isp_alert_6: isp-alert-6 { temperature = <110000>; /* millicelsius */ hysteresis = <1000>; /* millicelsius */ diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bc061b57caff..5fc3ca233ac6 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -57,12 +57,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -72,12 +75,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -243,38 +249,47 @@ opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-microvolt = <900000>; }; + opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <925000>; }; + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <950000>; }; + opp-700000000 { opp-hz = /bits/ 64 <700000000>; opp-microvolt = <975000>; }; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1000000>; }; + opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <1050000>; }; + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1075000>; }; + opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <1112500>; }; + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1112500>; }; + opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1150000>; @@ -289,58 +304,72 @@ opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <900000>; }; + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <900000>; }; + opp-700000000 { opp-hz = /bits/ 64 <700000000>; opp-microvolt = <912500>; }; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; opp-microvolt = <912500>; }; + opp-900000000 { opp-hz = /bits/ 64 <900000000>; opp-microvolt = <937500>; }; + opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <975000>; }; + opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; opp-microvolt = <1012500>; }; + opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1037500>; }; + opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; opp-microvolt = <1062500>; }; + opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; opp-microvolt = <1087500>; }; + opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <1125000>; }; + opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <1137500>; }; + opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <1175000>; }; + opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1212500>; }; + opp-1900000000 { opp-hz = /bits/ 64 <1900000000>; opp-microvolt = <1262500>; @@ -752,7 +781,7 @@ tmu_atlas0: tmu@10060000 { reg = <0x10060000 0x200>; interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, - <&cmu_peris CLK_SCLK_TMU0>; + <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; @@ -764,7 +793,7 @@ tmu_atlas1: tmu@10068000 { reg = <0x10068000 0x200>; interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>, - <&cmu_peris CLK_SCLK_TMU0>; + <&cmu_peris CLK_SCLK_TMU0>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; @@ -776,7 +805,7 @@ tmu_g3d: tmu@10070000 { reg = <0x10070000 0x200>; interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; + <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; @@ -788,7 +817,7 @@ tmu_apollo: tmu@10078000 { reg = <0x10078000 0x200>; interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; + <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; @@ -800,7 +829,7 @@ tmu_isp: tmu@1007c000 { reg = <0x1007c000 0x200>; interrupts = ; clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>, - <&cmu_peris CLK_SCLK_TMU1>; + <&cmu_peris CLK_SCLK_TMU1>; clock-names = "tmu_apbif", "tmu_sclk"; #thermal-sensor-cells = <0>; @@ -812,17 +841,17 @@ timer@101c0000 { "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + ; clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>; clock-names = "fin_pll", "mct"; }; @@ -960,21 +989,21 @@ decon: decon@13800000 { compatible = "samsung,exynos5433-decon"; reg = <0x13800000 0x2104>; clocks = <&cmu_disp CLK_PCLK_DECON>, - <&cmu_disp CLK_ACLK_DECON>, - <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_XIU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>, - <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_ACLK_XIU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>, - <&cmu_disp CLK_SCLK_DECON_VCLK>, - <&cmu_disp CLK_SCLK_DECON_ECLK>, - <&cmu_disp CLK_SCLK_DSD>; + <&cmu_disp CLK_ACLK_DECON>, + <&cmu_disp CLK_ACLK_SMMU_DECON0X>, + <&cmu_disp CLK_ACLK_XIU_DECON0X>, + <&cmu_disp CLK_PCLK_SMMU_DECON0X>, + <&cmu_disp CLK_ACLK_SMMU_DECON1X>, + <&cmu_disp CLK_ACLK_XIU_DECON1X>, + <&cmu_disp CLK_PCLK_SMMU_DECON1X>, + <&cmu_disp CLK_SCLK_DECON_VCLK>, + <&cmu_disp CLK_SCLK_DECON_ECLK>, + <&cmu_disp CLK_SCLK_DSD>; clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", - "aclk_xiu_decon0x", "pclk_smmu_decon0x", - "aclk_smmu_decon1x", "aclk_xiu_decon1x", - "pclk_smmu_decon1x", "sclk_decon_vclk", - "sclk_decon_eclk", "dsd"; + "aclk_xiu_decon0x", "pclk_smmu_decon0x", + "aclk_smmu_decon1x", "aclk_xiu_decon1x", + "pclk_smmu_decon1x", "sclk_decon_vclk", + "sclk_decon_eclk", "dsd"; power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , @@ -992,6 +1021,7 @@ ports { port@0 { reg = <0>; + decon_to_mic: endpoint { remote-endpoint = <&mic_to_decon>; @@ -1038,15 +1068,15 @@ dsi: dsi@13900000 { phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&cmu_disp CLK_PCLK_DSIM0>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, - <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, - <&cmu_disp CLK_SCLK_DSIM0>; + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>, + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>, + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>, + <&cmu_disp CLK_SCLK_DSIM0>; clock-names = "bus_clk", - "phyclk_mipidphy0_bitclkdiv8", - "phyclk_mipidphy0_rxclkesc0", - "sclk_rgb_vclk_to_dsim0", - "sclk_mipi"; + "phyclk_mipidphy0_bitclkdiv8", + "phyclk_mipidphy0_rxclkesc0", + "sclk_rgb_vclk_to_dsim0", + "sclk_mipi"; power-domains = <&pd_disp>; #address-cells = <1>; #size-cells = <0>; @@ -1059,6 +1089,7 @@ ports { port@0 { reg = <0>; + dsi_to_mic: endpoint { remote-endpoint = <&mic_to_dsi>; }; @@ -1070,7 +1101,7 @@ mic: mic@13930000 { compatible = "samsung,exynos5433-mic"; reg = <0x13930000 0x48>; clocks = <&cmu_disp CLK_PCLK_MIC0>, - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; power-domains = <&pd_disp>; samsung,disp-syscon = <&syscon_disp>; @@ -1083,6 +1114,7 @@ ports { port@0 { reg = <0>; + mic_to_decon: endpoint { remote-endpoint = <&decon_to_mic>; @@ -1091,6 +1123,7 @@ mic_to_decon: endpoint { port@1 { reg = <1>; + mic_to_dsi: endpoint { remote-endpoint = <&dsi_to_mic>; }; @@ -1103,19 +1136,19 @@ hdmi: hdmi@13970000 { reg = <0x13970000 0x70000>; interrupts = ; clocks = <&cmu_disp CLK_PCLK_HDMI>, - <&cmu_disp CLK_PCLK_HDMIPHY>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, - <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, - <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, - <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, - <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, - <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; + <&cmu_disp CLK_PCLK_HDMIPHY>, + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, + <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, + <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, + <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>; clock-names = "hdmi_pclk", "hdmi_i_pclk", - "i_tmds_clk", "i_pixel_clk", - "tmds_clko", "tmds_clko_user", - "pixel_clko", "pixel_clko_user", - "oscclk", "i_spdif_clk"; + "i_tmds_clk", "i_pixel_clk", + "tmds_clko", "tmds_clko_user", + "pixel_clko", "pixel_clko_user", + "oscclk", "i_spdif_clk"; phy = <&hdmiphy>; ddc = <&hsi2c_11>; samsung,syscon-phandle = <&pmu_system_controller>; @@ -1219,30 +1252,37 @@ opp-160000000 { opp-hz = /bits/ 64 <160000000>; opp-microvolt = <1000000>; }; + opp-267000000 { opp-hz = /bits/ 64 <267000000>; opp-microvolt = <1000000>; }; + opp-350000000 { opp-hz = /bits/ 64 <350000000>; opp-microvolt = <1025000>; }; + opp-420000000 { opp-hz = /bits/ 64 <420000000>; opp-microvolt = <1025000>; }; + opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1075000>; }; + opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-microvolt = <1125000>; }; + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1150000>; }; + opp-700000000 { opp-hz = /bits/ 64 <700000000>; opp-microvolt = <1150000>; @@ -1437,7 +1477,7 @@ serial_0: serial@14c10000 { reg = <0x14c10000 0x100>; interrupts = ; clocks = <&cmu_peric CLK_PCLK_UART0>, - <&cmu_peric CLK_SCLK_UART0>; + <&cmu_peric CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus>; @@ -1450,7 +1490,7 @@ serial_1: serial@14c20000 { reg = <0x14c20000 0x100>; interrupts = ; clocks = <&cmu_peric CLK_PCLK_UART1>, - <&cmu_peric CLK_SCLK_UART1>; + <&cmu_peric CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart1_bus>; @@ -1463,7 +1503,7 @@ serial_2: serial@14c30000 { reg = <0x14c30000 0x100>; interrupts = ; clocks = <&cmu_peric CLK_PCLK_UART2>, - <&cmu_peric CLK_SCLK_UART2>; + <&cmu_peric CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart2_bus>; @@ -1480,8 +1520,8 @@ spi_0: spi@14d20000 { #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric CLK_PCLK_SPI0>, - <&cmu_peric CLK_SCLK_SPI0>, - <&cmu_peric CLK_SCLK_IOCLK_SPI0>; + <&cmu_peric CLK_SCLK_SPI0>, + <&cmu_peric CLK_SCLK_IOCLK_SPI0>; clock-names = "spi", "spi_busclk0", "spi_ioclk"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -1501,8 +1541,8 @@ spi_1: spi@14d30000 { #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric CLK_PCLK_SPI1>, - <&cmu_peric CLK_SCLK_SPI1>, - <&cmu_peric CLK_SCLK_IOCLK_SPI1>; + <&cmu_peric CLK_SCLK_SPI1>, + <&cmu_peric CLK_SCLK_IOCLK_SPI1>; clock-names = "spi", "spi_busclk0", "spi_ioclk"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -1522,8 +1562,8 @@ spi_2: spi@14d40000 { #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric CLK_PCLK_SPI2>, - <&cmu_peric CLK_SCLK_SPI2>, - <&cmu_peric CLK_SCLK_IOCLK_SPI2>; + <&cmu_peric CLK_SCLK_SPI2>, + <&cmu_peric CLK_SCLK_IOCLK_SPI2>; clock-names = "spi", "spi_busclk0", "spi_ioclk"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -1543,8 +1583,8 @@ spi_3: spi@14d50000 { #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric CLK_PCLK_SPI3>, - <&cmu_peric CLK_SCLK_SPI3>, - <&cmu_peric CLK_SCLK_IOCLK_SPI3>; + <&cmu_peric CLK_SCLK_SPI3>, + <&cmu_peric CLK_SCLK_IOCLK_SPI3>; clock-names = "spi", "spi_busclk0", "spi_ioclk"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -1564,8 +1604,8 @@ spi_4: spi@14d00000 { #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_peric CLK_PCLK_SPI4>, - <&cmu_peric CLK_SCLK_SPI4>, - <&cmu_peric CLK_SCLK_IOCLK_SPI4>; + <&cmu_peric CLK_SCLK_SPI4>, + <&cmu_peric CLK_SCLK_IOCLK_SPI4>; clock-names = "spi", "spi_busclk0", "spi_ioclk"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -1802,9 +1842,9 @@ hsi2c_11: i2c@14df0000 { usbdrd30: usb@15400000 { compatible = "samsung,exynos5433-dwusb3"; clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; + <&cmu_fsys CLK_SCLK_USBDRD30>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>; clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; #address-cells = <1>; #size-cells = <1>; @@ -1815,8 +1855,8 @@ usbdrd30: usb@15400000 { usbdrd_dwc3: usb@0 { compatible = "snps,dwc3"; clocks = <&cmu_fsys CLK_SCLK_USBDRD30>, - <&cmu_fsys CLK_ACLK_USBDRD30>, - <&cmu_fsys CLK_SCLK_USBDRD30>; + <&cmu_fsys CLK_ACLK_USBDRD30>, + <&cmu_fsys CLK_SCLK_USBDRD30>; clock-names = "ref", "bus_early", "suspend"; reg = <0x0 0x10000>; interrupts = ; @@ -1829,11 +1869,10 @@ usbdrd30_phy: phy@15500000 { compatible = "samsung,exynos5433-usbdrd-phy"; reg = <0x15500000 0x100>; clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, - <&cmu_fsys CLK_SCLK_USBDRD30>; - clock-names = "phy", "ref", "phy_utmi", "phy_pipe", - "itp"; + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>, + <&cmu_fsys CLK_SCLK_USBDRD30>; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; @@ -1844,11 +1883,10 @@ usbhost30_phy: phy@15580000 { compatible = "samsung,exynos5433-usbdrd-phy"; reg = <0x15580000 0x100>; clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, - <&cmu_fsys CLK_SCLK_USBHOST30>; - clock-names = "phy", "ref", "phy_utmi", "phy_pipe", - "itp"; + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>, + <&cmu_fsys CLK_SCLK_USBHOST30>; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; @@ -1858,9 +1896,9 @@ usbhost30_phy: phy@15580000 { usbhost30: usb@15a00000 { compatible = "samsung,exynos5433-dwusb3"; clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; + <&cmu_fsys CLK_SCLK_USBHOST30>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>, + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>; clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk"; #address-cells = <1>; #size-cells = <1>; @@ -1871,8 +1909,8 @@ usbhost30: usb@15a00000 { usbhost_dwc3: usb@0 { compatible = "snps,dwc3"; clocks = <&cmu_fsys CLK_SCLK_USBHOST30>, - <&cmu_fsys CLK_ACLK_USBHOST30>, - <&cmu_fsys CLK_SCLK_USBHOST30>; + <&cmu_fsys CLK_ACLK_USBHOST30>, + <&cmu_fsys CLK_SCLK_USBHOST30>; clock-names = "ref", "bus_early", "suspend"; reg = <0x0 0x10000>; interrupts = ; @@ -1889,7 +1927,7 @@ mshc_0: mmc@15540000 { #size-cells = <0>; reg = <0x15540000 0x2000>; clocks = <&cmu_fsys CLK_ACLK_MMC0>, - <&cmu_fsys CLK_SCLK_MMC0>; + <&cmu_fsys CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; @@ -1904,7 +1942,7 @@ mshc_1: mmc@15550000 { #size-cells = <0>; reg = <0x15550000 0x2000>; clocks = <&cmu_fsys CLK_ACLK_MMC1>, - <&cmu_fsys CLK_SCLK_MMC1>; + <&cmu_fsys CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; @@ -1919,7 +1957,7 @@ mshc_2: mmc@15560000 { #size-cells = <0>; reg = <0x15560000 0x2000>; clocks = <&cmu_fsys CLK_ACLK_MMC2>, - <&cmu_fsys CLK_SCLK_MMC2>; + <&cmu_fsys CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x40>; @@ -1974,8 +2012,8 @@ i2s0: i2s@11440000 { #address-cells = <1>; #size-cells = <0>; clocks = <&cmu_aud CLK_PCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_AUD_I2S>, - <&cmu_aud CLK_SCLK_I2S_BCLK>; + <&cmu_aud CLK_SCLK_AUD_I2S>, + <&cmu_aud CLK_SCLK_I2S_BCLK>; clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; #clock-cells = <1>; pinctrl-names = "default"; @@ -1991,7 +2029,7 @@ serial_3: serial@11460000 { reg = <0x11460000 0x100>; interrupts = ; clocks = <&cmu_aud CLK_PCLK_AUD_UART>, - <&cmu_aud CLK_SCLK_AUD_UART>; + <&cmu_aud CLK_SCLK_AUD_UART>; clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart_aud_bus>; @@ -2037,14 +2075,10 @@ pcie: pcie@15700000 { timer: timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index c8925f4076b5..b3d5b447aeb6 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -99,8 +99,7 @@ pmic@66 { s2mps15_osc: clocks { compatible = "samsung,s2mps13-clk"; #clock-cells = <1>; - clock-output-names = "s2mps13_ap", "s2mps13_cp", - "s2mps13_bt"; + clock-output-names = "s2mps13_ap", "s2mps13_cp", "s2mps13_bt"; }; regulators { diff --git a/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi b/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi index d3301b8bd364..ecae9550801c 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi @@ -12,36 +12,43 @@ cpu-alert-0 { hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-alert-1 { temperature = <80000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-alert-2 { temperature = <85000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-alert-3 { temperature = <90000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-alert-4 { temperature = <95000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-alert-5 { temperature = <100000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-alert-6 { temperature = <110000>; /* millicelsius */ hysteresis = <10000>; /* millicelsius */ type = "passive"; }; + cpu-crit-0 { temperature = <115000>; /* millicelsius */ hysteresis = <0>; /* millicelsius */ diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index fa4e7d678423..20e24db952fa 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -670,13 +670,13 @@ tmuctrl_0: tmu@10060000 { ufs: ufs@15570000 { compatible = "samsung,exynos7-ufs"; reg = <0x15570000 0x100>, /* 0: HCI standard */ - <0x15570100 0x100>, /* 1: Vendor specificed */ - <0x15571000 0x200>, /* 2: UNIPRO */ - <0x15572000 0x300>; /* 3: UFS protector */ + <0x15570100 0x100>, /* 1: Vendor specified */ + <0x15571000 0x200>, /* 2: UNIPRO */ + <0x15572000 0x300>; /* 3: UFS protector */ reg-names = "hci", "vs_hci", "unipro", "ufsp"; interrupts = ; clocks = <&clock_fsys1 ACLK_UFS20_LINK>, - <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; + <&clock_fsys1 SCLK_UFSUNIPRO20_USER>; clock-names = "core_clk", "sclk_unipro_main"; freq-table-hz = <0 0>, <0 0>; pinctrl-names = "default"; @@ -706,10 +706,10 @@ usbdrd_phy: phy@15500000 { compatible = "samsung,exynos7-usbdrd-phy"; reg = <0x15500000 0x100>; clocks = <&clock_fsys0 ACLK_USBDRD300>, - <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, - <&clock_fsys0 SCLK_USBDRD300_REFCLK>; + <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, + <&clock_fsys0 SCLK_USBDRD300_REFCLK>; clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; @@ -718,10 +718,10 @@ usbdrd_phy: phy@15500000 { usbdrd: usb@15400000 { compatible = "samsung,exynos7-dwusb3"; clocks = <&clock_fsys0 ACLK_USBDRD300>, - <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, - <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; + <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, + <&clock_fsys0 ACLK_AXIUS_USBDRD30X_FSYS0X>; clock-names = "usbdrd30", "usbdrd30_susp_clk", - "usbdrd30_axius_clk"; + "usbdrd30_axius_clk"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x15400000 0x10000>; @@ -747,14 +747,10 @@ atlas_thermal: cluster0-thermal { timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts index de30d0970336..02bab3ab2711 100644 --- a/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts @@ -398,8 +398,8 @@ accelerometer@1d { pinctrl-0 = <&accel_irq>; mount-matrix = "-1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; + "0", "1", "0", + "0", "0", "-1"; st,drdy-int-pin = <1>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7870.dtsi b/arch/arm64/boot/dts/exynos/exynos7870.dtsi index 19f9ae783587..9e3ec6c952f0 100644 --- a/arch/arm64/boot/dts/exynos/exynos7870.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7870.dtsi @@ -36,12 +36,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -51,12 +54,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -201,8 +207,7 @@ gic: interrupt-controller@104e1000 { <0x104e2000 0x1000>, <0x104e4000 0x2000>, <0x104e6000 0x2000>; - interrupts = ; + interrupts = ; interrupt-controller; #address-cells = <0>; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi index 7d7d56206b86..6b994b487107 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -56,18 +56,23 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + core4 { cpu = <&cpu4>; }; + core5 { cpu = <&cpu5>; }; @@ -77,6 +82,7 @@ cluster1 { core0 { cpu = <&cpu6>; }; + core1 { cpu = <&cpu7>; }; @@ -186,8 +192,7 @@ gic: interrupt-controller@12301000 { <0x12302000 0x2000>, <0x12304000 0x2000>, <0x12306000 0x2000>; - interrupts = ; + interrupts = ; }; cmu_peri: clock-controller@10010000 { diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi index 424bc80bde68..e3f1ae8dedbf 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -509,6 +509,7 @@ gpp0: gpp0-gpio-bank { interrupt-controller; #interrupt-cells = <2>; }; + gpp1: gpp1-gpio-bank { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 8abf7c9eac9e..911643008b9f 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -61,12 +61,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -76,12 +79,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -96,24 +102,28 @@ cpu0: cpu@0 { clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>; clock-names = "cluster0_clk"; }; + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x1>; enable-method = "psci"; }; + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x2>; enable-method = "psci"; }; + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x3>; enable-method = "psci"; }; + cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; @@ -122,18 +132,21 @@ cpu4: cpu@100 { clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>; clock-names = "cluster1_clk"; }; + cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x101>; enable-method = "psci"; }; + cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x102>; enable-method = "psci"; }; + cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a55"; @@ -207,8 +220,7 @@ gic: interrupt-controller@12a01000 { <0x12a04000 0x2000>, <0x12a06000 0x2000>; interrupt-controller; - interrupts = ; + interrupts = ; }; pmu_system_controller: system-controller@11860000 { diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi index 9d82fceb5130..0333b80eba84 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -42,12 +42,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -57,9 +60,11 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index e3b6d37aac09..a9a6f6970d71 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -35,12 +35,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -50,12 +53,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -207,8 +213,7 @@ gic: interrupt-controller@10201000 { <0x10206000 0x2000>; #interrupt-cells = <3>; interrupt-controller; - interrupts = ; + interrupts = ; #address-cells = <0>; #size-cells = <1>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos9810.dtsi b/arch/arm64/boot/dts/exynos/exynos9810.dtsi index 01eba31f7ca3..4f1f1e9a41b2 100644 --- a/arch/arm64/boot/dts/exynos/exynos9810.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9810.dtsi @@ -36,12 +36,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -51,12 +54,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -179,8 +185,7 @@ gic: interrupt-controller@10101000 { <0x10106000 0x2000>; #interrupt-cells = <3>; interrupt-controller; - interrupts = ; + interrupts = ; #address-cells = <0>; #size-cells = <1>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi index c15ccaff2666..8115d581b173 100644 --- a/arch/arm64/boot/dts/exynos/exynos990.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi @@ -243,8 +243,7 @@ gic: interrupt-controller@10101000 { <0x10106000 0x2000>; #interrupt-cells = <3>; interrupt-controller; - interrupts = ; + interrupts = ; #address-cells = <0>; #size-cells = <1>; }; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 94f8d1c47676..9c140ca261a2 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -51,12 +51,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -66,12 +69,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -338,8 +344,7 @@ gic: interrupt-controller@10101000 { <0x10102000 0x2000>, <0x10104000 0x2000>, <0x10106000 0x2000>; - interrupts = ; + interrupts = ; }; pdma0: dma-controller@1b2e0000 { diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index f42207bdc701..399b56b4dbdd 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -48,12 +48,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -63,12 +66,15 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; @@ -78,6 +84,7 @@ cluster2 { core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; From b9014d9fb72b890254ff99b6b1d1c8a0f31ad9cb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:06:58 +0200 Subject: [PATCH 757/864] arm64: dts: exynos5433: Override thermal zones by phandle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix indentation of DTSI file with thermal zones (two opening { brackets, but only one indent) by using a safer choice of phandle/label override. Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-3-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 4 +--- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 +++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi index 57b335f579d8..a3ebc49fcd36 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi @@ -7,8 +7,7 @@ #include -/ { -thermal-zones { +&thermal_zones { atlas0_thermal: atlas0-thermal { thermal-sensors = <&tmu_atlas0>; polling-delay-passive = <0>; @@ -347,4 +346,3 @@ isp_alert_6: isp-alert-6 { }; }; }; -}; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 5fc3ca233ac6..ebd63b9e244d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -2073,6 +2073,9 @@ pcie: pcie@15700000 { }; }; + thermal_zones: thermal-zones { + }; + timer: timer { compatible = "arm,armv8-timer"; interrupts = , From 5128b3fbfbcabd55ca7a53f8a6182683287e28aa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:06:59 +0200 Subject: [PATCH 758/864] arm64: dts: exynos: Re-order clocks and align continued properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Trivial white-space only changes to adjust to DTS coding style (clocks-names should follow clocks) and fix dt-check-style strict warnings like: [property-order] property 'clocks' out of canonical order (should sort before 'clock-names') [continuation-alignment] continuation should align to column 39 (under < or ") Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-4-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 282 ++++++++++----------- 1 file changed, 141 insertions(+), 141 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index ebd63b9e244d..d318c87effaa 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -400,14 +400,14 @@ cmu_top: clock-controller@10030000 { reg = <0x10030000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_mphy_pll", - "sclk_mfc_pll", - "sclk_bus_pll"; clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>, - <&cmu_mif CLK_SCLK_MFC_PLL>, - <&cmu_mif CLK_SCLK_BUS_PLL>; + <&cmu_cpif CLK_SCLK_MPHY_PLL>, + <&cmu_mif CLK_SCLK_MFC_PLL>, + <&cmu_mif CLK_SCLK_BUS_PLL>; + clock-names = "oscclk", + "sclk_mphy_pll", + "sclk_mfc_pll", + "sclk_bus_pll"; }; cmu_cpif: clock-controller@10fc0000 { @@ -415,8 +415,8 @@ cmu_cpif: clock-controller@10fc0000 { reg = <0x10fc0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk"; clocks = <&xxti>; + clock-names = "oscclk"; }; cmu_mif: clock-controller@105b0000 { @@ -424,10 +424,10 @@ cmu_mif: clock-controller@105b0000 { reg = <0x105b0000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_mphy_pll"; clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_MPHY_PLL>; + <&cmu_cpif CLK_SCLK_MPHY_PLL>; + clock-names = "oscclk", + "sclk_mphy_pll"; }; cmu_peric: clock-controller@14c80000 { @@ -447,26 +447,26 @@ cmu_fsys: clock-controller@156e0000 { reg = <0x156e0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_ufs_mphy", - "aclk_fsys_200", - "sclk_pcie_100_fsys", - "sclk_ufsunipro_fsys", - "sclk_mmc2_fsys", - "sclk_mmc1_fsys", - "sclk_mmc0_fsys", - "sclk_usbhost30_fsys", - "sclk_usbdrd30_fsys"; clocks = <&xxti>, - <&cmu_cpif CLK_SCLK_UFS_MPHY>, - <&cmu_top CLK_ACLK_FSYS_200>, - <&cmu_top CLK_SCLK_PCIE_100_FSYS>, - <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, - <&cmu_top CLK_SCLK_MMC2_FSYS>, - <&cmu_top CLK_SCLK_MMC1_FSYS>, - <&cmu_top CLK_SCLK_MMC0_FSYS>, - <&cmu_top CLK_SCLK_USBHOST30_FSYS>, - <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + <&cmu_cpif CLK_SCLK_UFS_MPHY>, + <&cmu_top CLK_ACLK_FSYS_200>, + <&cmu_top CLK_SCLK_PCIE_100_FSYS>, + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>, + <&cmu_top CLK_SCLK_MMC2_FSYS>, + <&cmu_top CLK_SCLK_MMC1_FSYS>, + <&cmu_top CLK_SCLK_MMC0_FSYS>, + <&cmu_top CLK_SCLK_USBHOST30_FSYS>, + <&cmu_top CLK_SCLK_USBDRD30_FSYS>; + clock-names = "oscclk", + "sclk_ufs_mphy", + "aclk_fsys_200", + "sclk_pcie_100_fsys", + "sclk_ufsunipro_fsys", + "sclk_mmc2_fsys", + "sclk_mmc1_fsys", + "sclk_mmc0_fsys", + "sclk_usbhost30_fsys", + "sclk_usbdrd30_fsys"; }; cmu_g2d: clock-controller@12460000 { @@ -474,12 +474,12 @@ cmu_g2d: clock-controller@12460000 { reg = <0x12460000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_g2d_266", - "aclk_g2d_400"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_G2D_266>, - <&cmu_top CLK_ACLK_G2D_400>; + <&cmu_top CLK_ACLK_G2D_266>, + <&cmu_top CLK_ACLK_G2D_400>; + clock-names = "oscclk", + "aclk_g2d_266", + "aclk_g2d_400"; power-domains = <&pd_g2d>; }; @@ -488,24 +488,24 @@ cmu_disp: clock-controller@13b90000 { reg = <0x13b90000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_dsim1_disp", - "sclk_dsim0_disp", - "sclk_dsd_disp", - "sclk_decon_tv_eclk_disp", - "sclk_decon_vclk_disp", - "sclk_decon_eclk_disp", - "sclk_decon_tv_vclk_disp", - "aclk_disp_333"; clocks = <&xxti>, - <&cmu_mif CLK_SCLK_DSIM1_DISP>, - <&cmu_mif CLK_SCLK_DSIM0_DISP>, - <&cmu_mif CLK_SCLK_DSD_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, - <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, - <&cmu_mif CLK_ACLK_DISP_333>; + <&cmu_mif CLK_SCLK_DSIM1_DISP>, + <&cmu_mif CLK_SCLK_DSIM0_DISP>, + <&cmu_mif CLK_SCLK_DSD_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, + <&cmu_mif CLK_ACLK_DISP_333>; + clock-names = "oscclk", + "sclk_dsim1_disp", + "sclk_dsim0_disp", + "sclk_dsd_disp", + "sclk_decon_tv_eclk_disp", + "sclk_decon_vclk_disp", + "sclk_decon_eclk_disp", + "sclk_decon_tv_vclk_disp", + "aclk_disp_333"; power-domains = <&pd_disp>; }; @@ -513,8 +513,8 @@ cmu_aud: clock-controller@114c0000 { compatible = "samsung,exynos5433-cmu-aud"; reg = <0x114c0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "fout_aud_pll"; clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; + clock-names = "oscclk", "fout_aud_pll"; power-domains = <&pd_aud>; }; @@ -523,8 +523,8 @@ cmu_bus0: clock-controller@13600000 { reg = <0x13600000 0x1000>; #clock-cells = <1>; - clock-names = "aclk_bus0_400"; clocks = <&cmu_top CLK_ACLK_BUS0_400>; + clock-names = "aclk_bus0_400"; }; cmu_bus1: clock-controller@14800000 { @@ -532,8 +532,8 @@ cmu_bus1: clock-controller@14800000 { reg = <0x14800000 0x1000>; #clock-cells = <1>; - clock-names = "aclk_bus1_400"; clocks = <&cmu_top CLK_ACLK_BUS1_400>; + clock-names = "aclk_bus1_400"; }; cmu_bus2: clock-controller@13400000 { @@ -541,8 +541,8 @@ cmu_bus2: clock-controller@13400000 { reg = <0x13400000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_bus2_400"; clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>; + clock-names = "oscclk", "aclk_bus2_400"; }; cmu_g3d: clock-controller@14aa0000 { @@ -550,8 +550,8 @@ cmu_g3d: clock-controller@14aa0000 { reg = <0x14aa0000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_g3d_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; + clock-names = "oscclk", "aclk_g3d_400"; power-domains = <&pd_g3d>; }; @@ -560,12 +560,12 @@ cmu_gscl: clock-controller@13cf0000 { reg = <0x13cf0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_gscl_111", - "aclk_gscl_333"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_GSCL_111>, - <&cmu_top CLK_ACLK_GSCL_333>; + <&cmu_top CLK_ACLK_GSCL_111>, + <&cmu_top CLK_ACLK_GSCL_333>; + clock-names = "oscclk", + "aclk_gscl_111", + "aclk_gscl_333"; power-domains = <&pd_gscl>; }; @@ -574,8 +574,8 @@ cmu_apollo: clock-controller@11900000 { reg = <0x11900000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", "sclk_bus_pll_apollo"; clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>; + clock-names = "oscclk", "sclk_bus_pll_apollo"; }; cmu_atlas: clock-controller@11800000 { @@ -583,8 +583,8 @@ cmu_atlas: clock-controller@11800000 { reg = <0x11800000 0x2000>; #clock-cells = <1>; - clock-names = "oscclk", "sclk_bus_pll_atlas"; clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; + clock-names = "oscclk", "sclk_bus_pll_atlas"; }; cmu_mscl: clock-controller@150d0000 { @@ -592,12 +592,12 @@ cmu_mscl: clock-controller@150d0000 { reg = <0x150d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_jpeg_mscl", - "aclk_mscl_400"; clocks = <&xxti>, - <&cmu_top CLK_SCLK_JPEG_MSCL>, - <&cmu_top CLK_ACLK_MSCL_400>; + <&cmu_top CLK_SCLK_JPEG_MSCL>, + <&cmu_top CLK_ACLK_MSCL_400>; + clock-names = "oscclk", + "sclk_jpeg_mscl", + "aclk_mscl_400"; power-domains = <&pd_mscl>; }; @@ -606,8 +606,8 @@ cmu_mfc: clock-controller@15280000 { reg = <0x15280000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_mfc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; + clock-names = "oscclk", "aclk_mfc_400"; power-domains = <&pd_mfc>; }; @@ -616,8 +616,8 @@ cmu_hevc: clock-controller@14f80000 { reg = <0x14f80000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", "aclk_hevc_400"; clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; + clock-names = "oscclk", "aclk_hevc_400"; power-domains = <&pd_hevc>; }; @@ -626,12 +626,12 @@ cmu_isp: clock-controller@146d0000 { reg = <0x146d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_isp_dis_400", - "aclk_isp_400"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_ISP_DIS_400>, - <&cmu_top CLK_ACLK_ISP_400>; + <&cmu_top CLK_ACLK_ISP_DIS_400>, + <&cmu_top CLK_ACLK_ISP_400>; + clock-names = "oscclk", + "aclk_isp_dis_400", + "aclk_isp_400"; power-domains = <&pd_isp>; }; @@ -640,14 +640,14 @@ cmu_cam0: clock-controller@120d0000 { reg = <0x120d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_cam0_333", - "aclk_cam0_400", - "aclk_cam0_552"; clocks = <&xxti>, - <&cmu_top CLK_ACLK_CAM0_333>, - <&cmu_top CLK_ACLK_CAM0_400>, - <&cmu_top CLK_ACLK_CAM0_552>; + <&cmu_top CLK_ACLK_CAM0_333>, + <&cmu_top CLK_ACLK_CAM0_400>, + <&cmu_top CLK_ACLK_CAM0_552>; + clock-names = "oscclk", + "aclk_cam0_333", + "aclk_cam0_400", + "aclk_cam0_552"; power-domains = <&pd_cam0>; }; @@ -656,20 +656,20 @@ cmu_cam1: clock-controller@145d0000 { reg = <0x145d0000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "sclk_isp_uart_cam1", - "sclk_isp_spi1_cam1", - "sclk_isp_spi0_cam1", - "aclk_cam1_333", - "aclk_cam1_400", - "aclk_cam1_552"; clocks = <&xxti>, - <&cmu_top CLK_SCLK_ISP_UART_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, - <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, - <&cmu_top CLK_ACLK_CAM1_333>, - <&cmu_top CLK_ACLK_CAM1_400>, - <&cmu_top CLK_ACLK_CAM1_552>; + <&cmu_top CLK_SCLK_ISP_UART_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>, + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>, + <&cmu_top CLK_ACLK_CAM1_333>, + <&cmu_top CLK_ACLK_CAM1_400>, + <&cmu_top CLK_ACLK_CAM1_552>; + clock-names = "oscclk", + "sclk_isp_uart_cam1", + "sclk_isp_spi1_cam1", + "sclk_isp_spi0_cam1", + "aclk_cam1_333", + "aclk_cam1_400", + "aclk_cam1_552"; power-domains = <&pd_cam1>; }; @@ -678,23 +678,23 @@ cmu_imem: clock-controller@11060000 { reg = <0x11060000 0x1000>; #clock-cells = <1>; - clock-names = "oscclk", - "aclk_imem_sssx_266", - "aclk_imem_266", - "aclk_imem_200"; clocks = <&xxti>, - <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_266>, - <&cmu_top CLK_DIV_ACLK_IMEM_200>; + <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>, + <&cmu_top CLK_DIV_ACLK_IMEM_266>, + <&cmu_top CLK_DIV_ACLK_IMEM_200>; + clock-names = "oscclk", + "aclk_imem_sssx_266", + "aclk_imem_266", + "aclk_imem_200"; }; slim_sss: slim-sss@11140000 { compatible = "samsung,exynos5433-slim-sss"; reg = <0x11140000 0x1000>; interrupts = ; - clock-names = "pclk", "aclk"; clocks = <&cmu_imem CLK_PCLK_SLIMSSS>, <&cmu_imem CLK_ACLK_SLIMSSS>; + clock-names = "pclk", "aclk"; }; pd_gscl: power-domain@105c4000 { @@ -954,8 +954,8 @@ pmu_system_controller: system-controller@105c0000 { compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon"; reg = <0x105c0000 0x5008>; #clock-cells = <1>; - clock-names = "clkout16"; clocks = <&xxti>; + clock-names = "clkout16"; mipi_phy: mipi-phy { compatible = "samsung,exynos5433-mipi-video-phy"; @@ -975,13 +975,13 @@ reboot: syscon-reboot { gic: interrupt-controller@11001000 { compatible = "arm,gic-400"; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; interrupts = ; }; @@ -1190,13 +1190,13 @@ gsc_0: video-scaler@13c00000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c00000 0x1000>; interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL0>, <&cmu_gscl CLK_ACLK_GSCL0>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>, <&cmu_gscl CLK_ACLK_GSD>; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend", "gsd"; iommus = <&sysmmu_gscl0>; power-domains = <&pd_gscl>; }; @@ -1205,13 +1205,13 @@ gsc_1: video-scaler@13c10000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c10000 0x1000>; interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL1>, <&cmu_gscl CLK_ACLK_GSCL1>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>, <&cmu_gscl CLK_ACLK_GSD>; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend", "gsd"; iommus = <&sysmmu_gscl1>; power-domains = <&pd_gscl>; }; @@ -1220,13 +1220,13 @@ gsc_2: video-scaler@13c20000 { compatible = "samsung,exynos5433-gsc"; reg = <0x13c20000 0x1000>; interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", - "aclk_gsclbend", "gsd"; clocks = <&cmu_gscl CLK_PCLK_GSCL2>, <&cmu_gscl CLK_ACLK_GSCL2>, <&cmu_gscl CLK_ACLK_XIU_GSCLX>, <&cmu_gscl CLK_ACLK_GSCLBEND_333>, <&cmu_gscl CLK_ACLK_GSD>; + clock-names = "pclk", "aclk", "aclk_xiu", + "aclk_gsclbend", "gsd"; iommus = <&sysmmu_gscl2>; power-domains = <&pd_gscl>; }; @@ -1294,10 +1294,10 @@ scaler_0: scaler@15000000 { compatible = "samsung,exynos5433-scaler"; reg = <0x15000000 0x1294>; interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>, <&cmu_mscl CLK_ACLK_M2MSCALER0>, <&cmu_mscl CLK_ACLK_XIU_MSCLX>; + clock-names = "pclk", "aclk", "aclk_xiu"; iommus = <&sysmmu_scaler_0>; power-domains = <&pd_mscl>; }; @@ -1306,10 +1306,10 @@ scaler_1: scaler@15010000 { compatible = "samsung,exynos5433-scaler"; reg = <0x15010000 0x1294>; interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "pclk", "aclk", "aclk_xiu"; clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>, <&cmu_mscl CLK_ACLK_M2MSCALER1>, <&cmu_mscl CLK_ACLK_XIU_MSCLX>; + clock-names = "pclk", "aclk", "aclk_xiu"; iommus = <&sysmmu_scaler_1>; power-domains = <&pd_mscl>; }; @@ -1318,11 +1318,11 @@ jpeg: codec@15020000 { compatible = "samsung,exynos5433-jpeg"; reg = <0x15020000 0x10000>; interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; clocks = <&cmu_mscl CLK_PCLK_JPEG>, <&cmu_mscl CLK_ACLK_JPEG>, <&cmu_mscl CLK_ACLK_XIU_MSCLX>, <&cmu_mscl CLK_SCLK_JPEG>; + clock-names = "pclk", "aclk", "aclk_xiu", "sclk"; iommus = <&sysmmu_jpeg>; power-domains = <&pd_mscl>; }; @@ -1331,10 +1331,10 @@ mfc: codec@152e0000 { compatible = "samsung,exynos5433-mfc"; reg = <0x152e0000 0x10000>; interrupts = ; - clock-names = "pclk", "aclk", "aclk_xiu"; clocks = <&cmu_mfc CLK_PCLK_MFC>, <&cmu_mfc CLK_ACLK_MFC>, <&cmu_mfc CLK_ACLK_XIU_MFCX>; + clock-names = "pclk", "aclk", "aclk_xiu"; iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>; iommu-names = "left", "right"; power-domains = <&pd_mfc>; @@ -1344,9 +1344,9 @@ sysmmu_decon0x: sysmmu@13a00000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a00000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_DECON0X>, - <&cmu_disp CLK_PCLK_SMMU_DECON0X>; + <&cmu_disp CLK_PCLK_SMMU_DECON0X>; + clock-names = "aclk", "pclk"; power-domains = <&pd_disp>; #iommu-cells = <0>; }; @@ -1355,9 +1355,9 @@ sysmmu_decon1x: sysmmu@13a10000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a10000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_DECON1X>, - <&cmu_disp CLK_PCLK_SMMU_DECON1X>; + <&cmu_disp CLK_PCLK_SMMU_DECON1X>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_disp>; }; @@ -1366,9 +1366,9 @@ sysmmu_tv0x: sysmmu@13a20000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a20000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_TV0X>, - <&cmu_disp CLK_PCLK_SMMU_TV0X>; + <&cmu_disp CLK_PCLK_SMMU_TV0X>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_disp>; }; @@ -1377,9 +1377,9 @@ sysmmu_tv1x: sysmmu@13a30000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13a30000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_disp CLK_ACLK_SMMU_TV1X>, - <&cmu_disp CLK_PCLK_SMMU_TV1X>; + <&cmu_disp CLK_PCLK_SMMU_TV1X>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_disp>; }; @@ -1388,9 +1388,9 @@ sysmmu_gscl0: sysmmu@13c80000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13c80000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>, <&cmu_gscl CLK_PCLK_SMMU_GSCL0>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_gscl>; }; @@ -1399,9 +1399,9 @@ sysmmu_gscl1: sysmmu@13c90000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13c90000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>, <&cmu_gscl CLK_PCLK_SMMU_GSCL1>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_gscl>; }; @@ -1410,9 +1410,9 @@ sysmmu_gscl2: sysmmu@13ca0000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13ca0000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>, <&cmu_gscl CLK_PCLK_SMMU_GSCL2>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_gscl>; }; @@ -1421,9 +1421,9 @@ sysmmu_scaler_0: sysmmu@15040000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15040000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; + <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mscl>; }; @@ -1432,9 +1432,9 @@ sysmmu_scaler_1: sysmmu@15050000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15050000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>, - <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; + <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mscl>; }; @@ -1443,9 +1443,9 @@ sysmmu_jpeg: sysmmu@15060000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15060000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_mscl CLK_ACLK_SMMU_JPEG>, - <&cmu_mscl CLK_PCLK_SMMU_JPEG>; + <&cmu_mscl CLK_PCLK_SMMU_JPEG>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mscl>; }; @@ -1454,9 +1454,9 @@ sysmmu_mfc_0: sysmmu@15200000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15200000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_0>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; + <&cmu_mfc CLK_PCLK_SMMU_MFC_0>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mfc>; }; @@ -1465,9 +1465,9 @@ sysmmu_mfc_1: sysmmu@15210000 { compatible = "samsung,exynos-sysmmu"; reg = <0x15210000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; clocks = <&cmu_mfc CLK_ACLK_SMMU_MFC_1>, - <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; + <&cmu_mfc CLK_PCLK_SMMU_MFC_1>; + clock-names = "aclk", "pclk"; #iommu-cells = <0>; power-domains = <&pd_mfc>; }; @@ -1620,8 +1620,8 @@ adc: adc@14d10000 { compatible = "samsung,exynos5433-adc", "samsung,exynos7-adc"; reg = <0x14d10000 0x100>; interrupts = ; - clock-names = "adc"; clocks = <&cmu_peric CLK_PCLK_ADCIF>; + clock-names = "adc"; #io-channel-cells = <1>; status = "disabled"; From 56bca5626deb478ecb8d3981f415737557701327 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:07:00 +0200 Subject: [PATCH 759/864] arm64: dts: google: Move 'status' to the end to match coding style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 'status' property is special, thus DTS coding style expects it to be always the last property preceded with a blank line, as reported by dt-check-style: [required-blank-lines] "status" must be preceded by a blank line [property-order] property 'vcc-supply' out of canonical order (should sort before 'status') Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-5-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/exynos/google/gs101-oriole.dts | 2 + .../dts/exynos/google/gs101-pixel-common.dtsi | 12 +++- .../boot/dts/exynos/google/gs101-raven.dts | 2 + arch/arm64/boot/dts/exynos/google/gs101.dtsi | 70 +++++++++++++++++++ 4 files changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts index 36721adcaa23..c5a3958c2320 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts @@ -39,6 +39,7 @@ ldo31m { &cont_splash_mem { reg = <0x0 0xfac00000 (1080 * 2400 * 4)>; + status = "okay"; }; @@ -47,5 +48,6 @@ &framebuffer0 { height = <2400>; stride = <(1080 * 4)>; format = "a8r8g8b8"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi index 5227cd4e314b..a12f2b88d72d 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi @@ -32,6 +32,7 @@ framebuffer0: framebuffer-0 { vci-supply = <&s2mpg10_ldo22m>; vddi-supply = <&s2mpg11_bucka>; /* format properties to be added by actual board */ + status = "disabled"; }; }; @@ -98,6 +99,7 @@ cont_splash_mem: splash@fac00000 { /* size to be updated by actual board */ reg = <0x0 0xfac00000 0x0>; no-map; + status = "disabled"; }; }; @@ -856,8 +858,9 @@ &serial_0 { }; &ufs_0 { - status = "okay"; vcc-supply = <&ufs_0_fixed_vcc_reg>; + + status = "okay"; }; &ufs_0_phy { @@ -867,6 +870,7 @@ &ufs_0_phy { &usbdrd31 { vdd10-supply = <®_placeholder>; vdd33-supply = <®_placeholder>; + status = "okay"; }; @@ -875,6 +879,7 @@ &usbdrd31_dwc3 { usb-role-switch; role-switch-default-mode = "peripheral"; maximum-speed = "super-speed-plus"; + status = "okay"; port { @@ -893,6 +898,7 @@ &usbdrd31_phy { vdd33-usb20-supply = <®_placeholder>; vdda-usbdp-supply = <®_placeholder>; vddh-usbdp-supply = <®_placeholder>; + status = "okay"; port { @@ -904,20 +910,24 @@ usbdrd31_phy_orien_switch: endpoint { &usi_uart { samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; }; &usi8 { samsung,mode = ; + status = "okay"; }; &usi12 { samsung,mode = ; + status = "okay"; }; &watchdog_cl0 { timeout-sec = <30>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-raven.dts b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts index a422542715f2..7c4273796a22 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-raven.dts +++ b/arch/arm64/boot/dts/exynos/google/gs101-raven.dts @@ -35,6 +35,7 @@ ldo14s { &cont_splash_mem { reg = <0x0 0xfac00000 (1440 * 3120 * 4)>; + status = "okay"; }; @@ -43,5 +44,6 @@ &framebuffer0 { height = <3120>; stride = <(1440 * 4)>; format = "a8r8g8b8"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 86933f22647b..edc38f2d1183 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -624,6 +624,7 @@ watchdog_cl0: watchdog@10060000 { interrupts = ; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <0>; + status = "disabled"; }; @@ -636,6 +637,7 @@ watchdog_cl1: watchdog@10070000 { interrupts = ; samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; + status = "disabled"; }; @@ -707,6 +709,7 @@ usi1: usi@109000c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1000>; + status = "disabled"; hsi2c_1: i2c@10900000 { @@ -721,6 +724,7 @@ hsi2c_1: i2c@10900000 { interrupts = ; pinctrl-0 = <&hsi2c1_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -734,6 +738,7 @@ serial_1: serial@10900000 { pinctrl-0 = <&uart1_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -748,6 +753,7 @@ spi_1: spi@10900000 { interrupts = ; pinctrl-0 = <&spi1_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -762,6 +768,7 @@ usi2: usi@109100c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1004>; + status = "disabled"; hsi2c_2: i2c@10910000 { @@ -776,6 +783,7 @@ hsi2c_2: i2c@10910000 { interrupts = ; pinctrl-0 = <&hsi2c2_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -789,6 +797,7 @@ serial_2: serial@10910000 { pinctrl-0 = <&uart2_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -803,6 +812,7 @@ spi_2: spi@10910000 { interrupts = ; pinctrl-0 = <&spi2_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -817,6 +827,7 @@ usi3: usi@109200c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1008>; + status = "disabled"; hsi2c_3: i2c@10920000 { @@ -831,6 +842,7 @@ hsi2c_3: i2c@10920000 { interrupts = ; pinctrl-0 = <&hsi2c3_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -844,6 +856,7 @@ serial_3: serial@10920000 { pinctrl-0 = <&uart3_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -858,6 +871,7 @@ spi_3: spi@10920000 { interrupts = ; pinctrl-0 = <&spi3_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -872,6 +886,7 @@ usi4: usi@109300c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x100c>; + status = "disabled"; hsi2c_4: i2c@10930000 { @@ -886,6 +901,7 @@ hsi2c_4: i2c@10930000 { interrupts = ; pinctrl-0 = <&hsi2c4_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -899,6 +915,7 @@ serial_4: serial@10930000 { pinctrl-0 = <&uart4_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -913,6 +930,7 @@ spi_4: spi@10930000 { interrupts = ; pinctrl-0 = <&spi4_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -927,6 +945,7 @@ usi5: usi@109400c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1010>; + status = "disabled"; hsi2c_5: i2c@10940000 { @@ -941,6 +960,7 @@ hsi2c_5: i2c@10940000 { interrupts = ; pinctrl-0 = <&hsi2c5_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -954,6 +974,7 @@ serial_5: serial@10940000 { pinctrl-0 = <&uart5_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -968,6 +989,7 @@ spi_5: spi@10940000 { interrupts = ; pinctrl-0 = <&spi5_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -982,6 +1004,7 @@ usi6: usi@109500c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1014>; + status = "disabled"; hsi2c_6: i2c@10950000 { @@ -996,6 +1019,7 @@ hsi2c_6: i2c@10950000 { interrupts = ; pinctrl-0 = <&hsi2c6_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1009,6 +1033,7 @@ serial_6: serial@10950000 { pinctrl-0 = <&uart6_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1023,6 +1048,7 @@ spi_6: spi@10950000 { interrupts = ; pinctrl-0 = <&spi6_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1037,6 +1063,7 @@ usi7: usi@109600c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1018>; + status = "disabled"; hsi2c_7: i2c@10960000 { @@ -1051,6 +1078,7 @@ hsi2c_7: i2c@10960000 { interrupts = ; pinctrl-0 = <&hsi2c7_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1064,6 +1092,7 @@ serial_7: serial@10960000 { pinctrl-0 = <&uart7_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1078,6 +1107,7 @@ spi_7: spi@10960000 { interrupts = ; pinctrl-0 = <&spi7_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1092,6 +1122,7 @@ usi8: usi@109700c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x101c>; + status = "disabled"; hsi2c_8: i2c@10970000 { @@ -1106,6 +1137,7 @@ hsi2c_8: i2c@10970000 { interrupts = ; pinctrl-0 = <&hsi2c8_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1119,6 +1151,7 @@ serial_8: serial@10970000 { pinctrl-0 = <&uart8_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1133,6 +1166,7 @@ spi_8: spi@10970000 { interrupts = ; pinctrl-0 = <&spi8_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1148,6 +1182,7 @@ usi_uart: usi@10a000c0 { clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1020>; samsung,mode = ; + status = "disabled"; serial_0: serial@10a00000 { @@ -1160,6 +1195,7 @@ serial_0: serial@10a00000 { pinctrl-0 = <&uart0_bus>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; + status = "disabled"; }; }; @@ -1174,6 +1210,7 @@ usi14: usi@10a200c0 { <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric0 0x1028>; + status = "disabled"; hsi2c_14: i2c@10a20000 { @@ -1188,6 +1225,7 @@ hsi2c_14: i2c@10a20000 { interrupts = ; pinctrl-0 = <&hsi2c14_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1201,6 +1239,7 @@ serial_14: serial@10a20000 { pinctrl-0 = <&uart14_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1215,6 +1254,7 @@ spi_14: spi@10a20000 { interrupts = ; pinctrl-0 = <&spi14_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1254,6 +1294,7 @@ usi0: usi@10d100c0 { <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric1 0x1000>; + status = "disabled"; hsi2c_0: i2c@10d10000 { @@ -1268,6 +1309,7 @@ hsi2c_0: i2c@10d10000 { interrupts = ; pinctrl-0 = <&hsi2c0_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1281,6 +1323,7 @@ serial_usi0: serial@10d10000 { pinctrl-0 = <&uart0_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1295,6 +1338,7 @@ spi_0: spi@10d10000 { interrupts = ; pinctrl-0 = <&spi0_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1309,6 +1353,7 @@ usi9: usi@10d200c0 { <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric1 0x1004>; + status = "disabled"; hsi2c_9: i2c@10d20000 { @@ -1323,6 +1368,7 @@ hsi2c_9: i2c@10d20000 { interrupts = ; pinctrl-0 = <&hsi2c9_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1336,6 +1382,7 @@ serial_9: serial@10d20000 { pinctrl-0 = <&uart9_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1350,6 +1397,7 @@ spi_9: spi@10d20000 { interrupts = ; pinctrl-0 = <&spi9_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1364,6 +1412,7 @@ usi10: usi@10d300c0 { <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric1 0x1008>; + status = "disabled"; hsi2c_10: i2c@10d30000 { @@ -1378,6 +1427,7 @@ hsi2c_10: i2c@10d30000 { interrupts = ; pinctrl-0 = <&hsi2c10_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1391,6 +1441,7 @@ serial_10: serial@10d30000 { pinctrl-0 = <&uart10_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1405,6 +1456,7 @@ spi_10: spi@10d30000 { interrupts = ; pinctrl-0 = <&spi10_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1419,6 +1471,7 @@ usi11: usi@10d400c0 { <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric1 0x100c>; + status = "disabled"; hsi2c_11: i2c@10d40000 { @@ -1433,6 +1486,7 @@ hsi2c_11: i2c@10d40000 { interrupts = ; pinctrl-0 = <&hsi2c11_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1446,6 +1500,7 @@ serial_11: serial@10d40000 { pinctrl-0 = <&uart11_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1460,6 +1515,7 @@ spi_11: spi@10d40000 { interrupts = ; pinctrl-0 = <&spi11_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1474,6 +1530,7 @@ usi12: usi@10d500c0 { <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric1 0x1010>; + status = "disabled"; hsi2c_12: i2c@10d50000 { @@ -1488,6 +1545,7 @@ hsi2c_12: i2c@10d50000 { interrupts = ; pinctrl-0 = <&hsi2c12_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1501,6 +1559,7 @@ serial_12: serial@10d50000 { pinctrl-0 = <&uart12_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1515,6 +1574,7 @@ spi_12: spi@10d50000 { interrupts = ; pinctrl-0 = <&spi12_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1529,6 +1589,7 @@ usi13: usi@10d600c0 { <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6>; clock-names = "pclk", "ipclk"; samsung,sysreg = <&sysreg_peric1 0x1014>; + status = "disabled"; hsi2c_13: i2c@10d60000 { @@ -1543,6 +1604,7 @@ hsi2c_13: i2c@10d60000 { interrupts = ; pinctrl-0 = <&hsi2c13_bus>; pinctrl-names = "default"; + status = "disabled"; }; @@ -1556,6 +1618,7 @@ serial_13: serial@10d60000 { pinctrl-0 = <&uart13_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -1570,6 +1633,7 @@ spi_13: spi@10d60000 { interrupts = ; pinctrl-0 = <&spi13_bus>; pinctrl-names = "default"; + status = "disabled"; }; }; @@ -1609,6 +1673,7 @@ usbdrd31_phy: phy@11100000 { clock-names = "phy", "ref", "ctrl_aclk", "ctrl_pclk", "scl_pclk"; #phy-cells = <1>; samsung,pmu-syscon = <&pmu_system_controller>; + status = "disabled"; }; @@ -1622,6 +1687,7 @@ usbdrd31: usb@11110000 { clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; #address-cells = <1>; #size-cells = <1>; + status = "disabled"; usbdrd31_dwc3: usb@0 { @@ -1635,6 +1701,7 @@ usbdrd31_dwc3: usb@0 { snps,has-lpm-erratum; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; + status = "disabled"; }; }; @@ -1698,6 +1765,7 @@ ufs_0: ufs@14700000 { phys = <&ufs_0_phy>; phy-names = "ufs-phy"; samsung,sysreg = <&sysreg_hsi2 0x710>; + status = "disabled"; }; @@ -1709,6 +1777,7 @@ ufs_0_phy: phy@14704000 { #phy-cells = <0>; clocks = <&ext_24_5m>; clock-names = "ref_clk"; + status = "disabled"; }; @@ -1812,6 +1881,7 @@ pinctrl_gsacore: pinctrl@17a80000 { /* TODO: update once support for this CMU exists */ clocks = <0>; clock-names = "pclk"; + status = "disabled"; }; From 483e4332596477e3f4b6032a6f1fc2d2db668890 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:07:01 +0200 Subject: [PATCH 760/864] arm64: dts: google: Align continued properties and add missing blank lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Trivial white-space only changes to adjust to DTS coding style and fix dt-check-style strict warnings like: [required-blank-lines] child node must be preceded by a blank line [continuation-alignment] continuation should align to column 39 (under < or ") Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-6-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index edc38f2d1183..bfceea5486f4 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -39,12 +39,15 @@ cluster0 { core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; @@ -54,6 +57,7 @@ cluster1 { core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; @@ -63,6 +67,7 @@ cluster2 { core0 { cpu = <&cpu6>; }; + core1 { cpu = <&cpu7>; }; @@ -1681,9 +1686,9 @@ usbdrd31: usb@11110000 { compatible = "google,gs101-dwusb3"; ranges = <0x0 0x11110000 0x10000>; clocks = <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY>, - <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, - <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, - <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; + <&cmu_hsi0 CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK>, + <&cmu_hsi0 CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK>; clock-names = "bus_early", "susp_clk", "link_aclk", "link_pclk"; #address-cells = <1>; #size-cells = <1>; From 8356e0bc0e0b1f9c889dbcdd57f241b61c394fc3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:07:02 +0200 Subject: [PATCH 761/864] arm64: dts: fsd: Move 'status' to the end to match coding style MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 'status' property is special, thus DTS coding style expects it to be always the last property preceded with a blank line, as reported by dt-check-style: [required-blank-lines] "status" must be preceded by a blank line [property-order] property 'phy-mode' out of canonical order (should sort before 'status') Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-7-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 6 ++++-- arch/arm64/boot/dts/tesla/fsd.dtsi | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 9ff22e1c8723..73b6a25e0e4d 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -65,9 +65,10 @@ codec { }; ðernet0 { + phy-mode = "rgmii-id"; + status = "okay"; - phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; @@ -75,9 +76,10 @@ fixed-link { }; ðernet1 { + phy-mode = "rgmii-id"; + status = "okay"; - phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 5b06e2667b89..214d33ca7177 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -603,6 +603,7 @@ serial_0: serial@14180000 { <&clock_peric PERIC_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -616,6 +617,7 @@ serial_1: serial@14190000 { <&clock_peric PERIC_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; samsung,uart-fifosize = <64>; + status = "disabled"; }; @@ -658,6 +660,7 @@ pwm_0: pwm@14100000 { #pwm-cells = <3>; clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; clock-names = "timers"; + status = "disabled"; }; @@ -668,6 +671,7 @@ pwm_1: pwm@14110000 { #pwm-cells = <3>; clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; clock-names = "timers"; + status = "disabled"; }; @@ -681,6 +685,7 @@ hsi2c_0: i2c@14200000 { pinctrl-0 = <&hs_i2c0_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C0>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -694,6 +699,7 @@ hsi2c_1: i2c@14210000 { pinctrl-0 = <&hs_i2c1_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C1>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -707,6 +713,7 @@ hsi2c_2: i2c@14220000 { pinctrl-0 = <&hs_i2c2_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C2>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -720,6 +727,7 @@ hsi2c_3: i2c@14230000 { pinctrl-0 = <&hs_i2c3_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C3>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -733,6 +741,7 @@ hsi2c_4: i2c@14240000 { pinctrl-0 = <&hs_i2c4_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C4>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -746,6 +755,7 @@ hsi2c_5: i2c@14250000 { pinctrl-0 = <&hs_i2c5_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C5>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -759,6 +769,7 @@ hsi2c_6: i2c@14260000 { pinctrl-0 = <&hs_i2c6_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C6>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -772,6 +783,7 @@ hsi2c_7: i2c@14270000 { pinctrl-0 = <&hs_i2c7_bus>; clocks = <&clock_peric PERIC_PCLK_HSI2C7>; clock-names = "hsi2c"; + status = "disabled"; }; @@ -789,6 +801,7 @@ i2s_0: i2s@140e0000 { pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; #sound-dai-cells = <1>; + status = "disabled"; }; @@ -806,6 +819,7 @@ i2s_1: i2s@140f0000 { pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; #sound-dai-cells = <1>; + status = "disabled"; }; @@ -840,6 +854,7 @@ m_can0: can@14088000 { <&clock_peric PERIC_MCAN0_IPCLKPORT_CCLK>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; @@ -857,6 +872,7 @@ m_can1: can@14098000 { <&clock_peric PERIC_MCAN1_IPCLKPORT_CCLK>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; @@ -874,6 +890,7 @@ m_can2: can@140a8000 { <&clock_peric PERIC_MCAN2_IPCLKPORT_CCLK>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; @@ -891,6 +908,7 @@ m_can3: can@140b8000 { <&clock_peric PERIC_MCAN3_IPCLKPORT_CCLK>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; @@ -909,6 +927,7 @@ spi_0: spi@14140000 { pinctrl-names = "default"; pinctrl-0 = <&spi0_bus>; num-cs = <1>; + status = "disabled"; }; @@ -927,6 +946,7 @@ spi_1: spi@14150000 { pinctrl-names = "default"; pinctrl-0 = <&spi1_bus>; num-cs = <1>; + status = "disabled"; }; @@ -945,6 +965,7 @@ spi_2: spi@14160000 { pinctrl-names = "default"; pinctrl-0 = <&spi2_bus>; num-cs = <1>; + status = "disabled"; }; @@ -1007,6 +1028,7 @@ ethernet1: ethernet@14300000 { <ð1_rx_ctrl>, <ð1_mdio>; local-mac-address = [00 00 00 00 00 00]; iommus = <&smmu_peric 0x0 0x1>; + status = "disabled"; }; @@ -1026,6 +1048,7 @@ ufs: ufs@15120000 { pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; phys = <&ufs_phy>; phy-names = "ufs-phy"; + status = "disabled"; }; @@ -1056,6 +1079,7 @@ ethernet0: ethernet@15300000 { <ð0_rx_ctrl>, <ð0_mdio>; local-mac-address = [00 00 00 00 00 00]; iommus = <&smmu_fsys0 0x0 0x1>; + status = "disabled"; }; }; From 302937941c38b0e46c61ff5c77dd26d1ecaed524 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 17:07:03 +0200 Subject: [PATCH 762/864] arm64: dts: fsd: Align continued properties and add missing blank lines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Trivial white-space only changes to adjust to DTS coding style and fix dt-check-style strict warnings like: [required-blank-lines] child node must be preceded by a blank line [continuation-alignment] continuation should align to column 39 (under < or ") Reviewed-by: André Draszik Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801-b4-dts-coding-style-strict-v2-8-f09a659ab80d@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 2 + arch/arm64/boot/dts/tesla/fsd.dtsi | 97 +++++++++++++++------------ 2 files changed, 55 insertions(+), 44 deletions(-) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 73b6a25e0e4d..503abe52a81c 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -53,9 +53,11 @@ simple-audio-card,dai-link@0 { cpu-0 { sound-dai = <&i2s_0 0>; }; + cpu-1 { sound-dai = <&i2s_0 1>; }; + codec { sound-dai = <&tlv320aic3x>; system-clock-frequency = <33000000>; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 214d33ca7177..6766c78243a3 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -43,12 +43,15 @@ cluster0 { core0 { cpu = <&cpucl0_0>; }; + core1 { cpu = <&cpucl0_1>; }; + core2 { cpu = <&cpucl0_2>; }; + core3 { cpu = <&cpucl0_3>; }; @@ -58,12 +61,15 @@ cluster1 { core0 { cpu = <&cpucl1_0>; }; + core1 { cpu = <&cpucl1_1>; }; + core2 { cpu = <&cpucl1_2>; }; + core3 { cpu = <&cpucl1_3>; }; @@ -73,12 +79,15 @@ cluster2 { core0 { cpu = <&cpucl2_0>; }; + core1 { cpu = <&cpucl2_1>; }; + core2 { cpu = <&cpucl2_2>; }; + core3 { cpu = <&cpucl2_3>; }; @@ -456,13 +465,13 @@ clock_imem: clock-controller@10010000 { reg = <0x0 0x10010000 0x0 0x3000>; #clock-cells = <1>; clocks = <&fin_pll>, - <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, - <&clock_cmu DOUT_CMU_IMEM_ACLK>, - <&clock_cmu DOUT_CMU_IMEM_DMACLK>; + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, + <&clock_cmu DOUT_CMU_IMEM_ACLK>, + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; clock-names = "fin_pll", - "dout_cmu_imem_tcuclk", - "dout_cmu_imem_aclk", - "dout_cmu_imem_dmaclk"; + "dout_cmu_imem_tcuclk", + "dout_cmu_imem_aclk", + "dout_cmu_imem_dmaclk"; }; clock_cmu: clock-controller@11c10000 { @@ -499,17 +508,17 @@ clock_peric: clock-controller@14010000 { reg = <0x0 0x14010000 0x0 0x3000>; #clock-cells = <1>; clocks = <&fin_pll>, - <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, - <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, - <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, - <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, - <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; clock-names = "fin_pll", - "dout_cmu_pll_shared0_div4", - "dout_cmu_peric_shared1div36", - "dout_cmu_peric_shared0div3_tbuclk", - "dout_cmu_peric_shared0div20", - "dout_cmu_peric_shared1div4_dmaclk"; + "dout_cmu_pll_shared0_div4", + "dout_cmu_peric_shared1div36", + "dout_cmu_peric_shared0div3_tbuclk", + "dout_cmu_peric_shared0div20", + "dout_cmu_peric_shared1div4_dmaclk"; }; sysreg_peric: system-controller@14030000 { @@ -522,13 +531,13 @@ clock_fsys0: clock-controller@15010000 { reg = <0x0 0x15010000 0x0 0x3000>; #clock-cells = <1>; clocks = <&fin_pll>, - <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, - <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, - <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; clock-names = "fin_pll", - "dout_cmu_pll_shared0_div6", - "dout_cmu_fsys0_shared1div4", - "dout_cmu_fsys0_shared0div4"; + "dout_cmu_pll_shared0_div6", + "dout_cmu_fsys0_shared1div4", + "dout_cmu_fsys0_shared0div4"; }; sysreg_fsys0: system-controller@15030000 { @@ -541,11 +550,11 @@ clock_fsys1: clock-controller@16810000 { reg = <0x0 0x16810000 0x0 0x3000>; #clock-cells = <1>; clocks = <&fin_pll>, - <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, - <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; clock-names = "fin_pll", - "dout_cmu_fsys1_shared0div8", - "dout_cmu_fsys1_shared0div4"; + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; }; sysreg_fsys1: system-controller@16830000 { @@ -921,7 +930,7 @@ spi_0: spi@14140000 { #address-cells = <1>; #size-cells = <0>; clocks = <&clock_peric PERIC_PCLK_SPI0>, - <&clock_peric PERIC_SCLK_SPI0>; + <&clock_peric PERIC_SCLK_SPI0>; clock-names = "spi", "spi_busclk0"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -940,7 +949,7 @@ spi_1: spi@14150000 { #address-cells = <1>; #size-cells = <0>; clocks = <&clock_peric PERIC_PCLK_SPI1>, - <&clock_peric PERIC_SCLK_SPI1>; + <&clock_peric PERIC_SCLK_SPI1>; clock-names = "spi", "spi_busclk0"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -959,7 +968,7 @@ spi_2: spi@14160000 { #address-cells = <1>; #size-cells = <0>; clocks = <&clock_peric PERIC_PCLK_SPI2>, - <&clock_peric PERIC_SCLK_SPI2>; + <&clock_peric PERIC_SCLK_SPI2>; clock-names = "spi", "spi_busclk0"; samsung,spi-src-clk = <0>; pinctrl-names = "default"; @@ -973,21 +982,21 @@ timer@10040000 { compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x0 0x800>; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; clock-names = "fin_pll", "mct"; }; From 7a867322cd14ec54783fb2fdc3ce875c89ba3b16 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:41 +0200 Subject: [PATCH 763/864] dt-bindings: arm: apple: Add M3 Pro/Max/Ultra devices (T603x) The M3 Pro, Max and Ultra Apple silicon SoC family (T6030, T6031, T6032 and T6034) differs from its M1 and M2 predecessors. Most notable is that T6030 (M3 Pro) appears to be a separately designed SoC. MMIO address spaces, interrupt and pin numbers do not match. It has two CPU clusters with 6 efficiency or performance cores. T6031 (M3 Max) as one cluster with 4 effciency cores and two clusters with 6 performance cores each. T6032 (M3 Ultra) is like in the previous generations two T6031 dies connected with an high speed interface and appears from operation system perspective as a single SoC. T6034 is a separate identifier for smaller M3 Max variant. It has fewer performance CPU cores (10 instead of 12), fewer GPU cores (30 instead of 40) and less memory controllers (384-bit instead of 512-bit combined width). Apple has only released 14- and 16-inch Macbook Pros with T6030, T6031 and T6034 (M3 Pro and Max) and as only desktop device the Mac Studio with T6032 (M3 Ultra). Acked-by: Conor Dooley Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- .../devicetree/bindings/arm/apple.yaml | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index e49403c73f9d..fb277c96f341 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -123,6 +123,14 @@ description: | - Mac Studio (M2 Ultra, 2023) - Mac Pro (M2 Ultra, 2023) + Devices based on the "M3 Pro", "M3 Max" and "M3 Ultra" SoCs: + + - MacBook Pro (14-inch, M3 Pro, 2023) + - MacBook Pro (14-inch, M3 Max, 2023) + - MacBook Pro (16-inch, M3 Pro, 2023) + - MacBook Pro (16-inch, M3 Max, 2023) + - Mac Studio (M3 Ultra, 2025) + The compatible property should follow this format: compatible = "apple,", "apple,", "apple,arm-platform"; @@ -365,6 +373,35 @@ properties: - const: apple,t6022 - const: apple,arm-platform + - description: Apple M3 Pro SoC based platforms + items: + - enum: + - apple,j514s # MacBook Pro (14-inch, M3 Pro, 2023) + - apple,j516s # MacBook Pro (16-inch, M3 Pro, 2023) + - const: apple,t6030 + - const: apple,arm-platform + + - description: Apple M3 Max SoC based platforms + oneOf: + - items: + - enum: + - apple,j514c # MacBook Pro (14-inch, M3 Max, 16 cores, 2023) + - apple,j516c # MacBook Pro (16-inch, M3 Max, 16 cores, 2023) + - const: apple,t6031 + - const: apple,arm-platform + - items: + - enum: + - apple,j514m # MacBook Pro (14-inch, M3 Max, 14 cores, 2023) + - apple,j516m # MacBook Pro (16-inch, M3 Max, 14 cores, 2023) + - const: apple,t6034 + - const: apple,arm-platform + + - description: Apple M3 Ultra SoC based platforms + items: + - const: apple,j575d # Mac Studio (M3 Ultra, 2025) + - const: apple,t6032 + - const: apple,arm-platform + additionalProperties: true ... From 7482c380403e90299f4e99a2a128c3919227388a Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:42 +0200 Subject: [PATCH 764/864] dt-bindings: interrupt-controller: apple,aic2: Invert #interrupt-cells condition The condition for 3 or 4 #interrupt-cells list compatibles for the 3 cells variant (not used in SoCs consisting out of multiple dies). This includes the AICv3 base compatible "apple,t8122-aic3". This will match compatible = "apple,t6031-aic3", "apple,t8122-aic3"; shared for M3 Max and Ultra based devices which require the additional interrupt cell for the die number. Instead list the compatibles used for multi-die SoCs explicitly and use 4 #interrupt-cells for them. Acked-by: Conor Dooley Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- .../bindings/interrupt-controller/apple,aic2.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index d0d9a90e96e7..a94787939d34 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -128,16 +128,16 @@ allOf: compatible: contains: enum: - - apple,t8112-aic - - apple,t8122-aic3 + - apple,t6000-aic + - apple,t6020-aic then: properties: '#interrupt-cells': - const: 3 + const: 4 else: properties: '#interrupt-cells': - const: 4 + const: 3 examples: - | From 7869d8206476403b7326d6c66dad2bccd09aead0 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:43 +0200 Subject: [PATCH 765/864] dt-bindings: interrupt-controller: apple,aic2: Add apple,t6031-aic3 compatible The Apple M3 Max and Ultra SoCs use AICv3 as interrupt controller. It is compatible to the base M3 AICv3. Add "apple,t6031-aic3" as compatible and add it to the list for 4 #interrupt-cells used for multi-die SoCs. Acked-by: Conor Dooley Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- .../devicetree/bindings/interrupt-controller/apple,aic2.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index a94787939d34..726a6720e05f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - apple,t6030-aic3 + - apple,t6031-aic3 - const: apple,t8122-aic3 - const: apple,t8122-aic3 @@ -130,6 +131,7 @@ allOf: enum: - apple,t6000-aic - apple,t6020-aic + - apple,t6031-aic3 then: properties: '#interrupt-cells': From 61e938504e7ecf9e596b643d18524e9c826bbd3a Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:44 +0200 Subject: [PATCH 766/864] dt-bindings: arm: apple: apple,pmgr: Add t6030 and t6031 compatibles The block on Apple M3 Pro, Max and Ultra SoCs is compatible with "apple,t8103-pmgr". Add "apple,t6030-pmgr" and "apple,t6031-pmgr" as per-SoC compatibles for M3 Pro and M3 Max and Ultra. Acked-by: Conor Dooley Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index c67b67ba065a..1d2001836eb4 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -38,6 +38,8 @@ properties: - items: - enum: - apple,t6020-pmgr + - apple,t6030-pmgr + - apple,t6031-pmgr - apple,t8122-pmgr - const: apple,t8103-pmgr - const: syscon From d713bfe900d2935919118d9c8880c5d060d64cb9 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:45 +0200 Subject: [PATCH 767/864] dt-bindings: power: apple,pmgr-pwrstate: Add t6030 and t6031 compatibles The pmgr-powerstate registers on Apple M3 Pro, Max and Ultra SoCs are compatible with "apple,t8103-pmgr-pwrstate". Add "apple,t6030-pmgr-pwrstate" for M3 Pro and "apple,t6031-pmgr-pwrstate" for M3 Max and Ultra as per-SoC compatibles. Acked-by: Conor Dooley Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- .../devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index c9be097cfba0..e269f433524e 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -45,6 +45,8 @@ properties: - items: - enum: - apple,t6020-pmgr-pwrstate + - apple,t6030-pmgr-pwrstate + - apple,t6031-pmgr-pwrstate - apple,t8122-pmgr-pwrstate - const: apple,t8103-pmgr-pwrstate From c1b7bfab96da91021afbe7cde1539f4d715e9abc Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:46 +0200 Subject: [PATCH 768/864] dt-bindings: i2c: apple,i2c: Add t6030 and t6031 compatibles The i2c block on Apple silicon M3 Pro, Max and Ultra SoCs are compatible with the t8103 (M1) one. Add "apple,t6030-i2c" for M3 Pro and "apple,t6031-i2c" for M3 Max and Ultra as per-SoC compatibles. Acked-by: Conor Dooley Signed-off-by: Janne Grunau Acked-by: Andi Shyti Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 9e59200ad37b..d39f5e3f1df4 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -24,6 +24,8 @@ properties: - items: - enum: - apple,t6020-i2c + - apple,t6030-i2c + - apple,t6031-i2c - apple,t8122-i2c - const: apple,t8103-i2c - items: From a46622579a702964a9fccf02691d7e4921fd6a5f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:47 +0200 Subject: [PATCH 769/864] dt-bindings: pwm: apple,s5l-fpwm: Add t6030 and t6031 compatibles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PWM controller on Apple silicon M3 Pro, Max and Ultra SoCs is compatible with the t8103 (M1) one. Add "apple,t6030-fpwm" for M3 Pro and "apple,t6031-fpwm" for M3 Max and Ultra as per-SoC compatibles. Acked-by: Conor Dooley Acked-by: Uwe Kleine-König Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index 25ef04b60ca1..dd95037ea5ee 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -21,6 +21,8 @@ properties: - apple,t8122-fpwm - apple,t6000-fpwm - apple,t6020-fpwm + - apple,t6030-fpwm + - apple,t6031-fpwm - const: apple,s5l-fpwm reg: From 67d9574cf8ed1c81c472b932a9d9819f47fb5286 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:48 +0200 Subject: [PATCH 770/864] arm64: dts: apple: Initial T603[124] (M3 Max and Ultra) device trees Contains minimal device trees for all M3 Max and Ultra Apple silicon devices. Those are 14-inch and 16-inch MacBook Pros with M3 Max released in November 2023 and Mac Studio with M3 Ultra released in 2025. This does not include M3 Pro since it is separate SoC and not a smaller variant of the M3 Max contrary to the M1 and M2 generations. The smaller M3 Max variant (10 performance cores) has its own chip variant (T6034) but is clearly the same design as T6031. Besides fewer CPU performance cores and GPU cores it misses also on fourth of the memory controllers and thus has an aggregated bus width of 384 bit instead of 512 bit. Both M3 Ultra variants (28 or 32 CPU cores) are based on T6031 judging by the advertised memory bandwidth of 819GB/s. This uses the same multi-die macros as t600x*.dtsi and t602x.dtsi to support M3 Max and M3 Ultra without duplicating device nodes. Since the M3 Pro can't use the same .dtsi files "t6031*.dtsi" are used to define common nodes for T6031, T6032 and T6034. The device trees have devices nodes for CPU cores, timer, interrupt controller, power states, watchdog, serial, pin controller, i2c, PWM based keyboard LED illumination and the boot framebuffer. Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 5 + arch/arm64/boot/dts/apple/t6031-base.dtsi | 297 ++ arch/arm64/boot/dts/apple/t6031-die0.dtsi | 197 ++ arch/arm64/boot/dts/apple/t6031-dieX.dtsi | 107 + .../arm64/boot/dts/apple/t6031-gpio-pins.dtsi | 53 + arch/arm64/boot/dts/apple/t6031-j514c.dts | 18 + arch/arm64/boot/dts/apple/t6031-j516c.dts | 18 + arch/arm64/boot/dts/apple/t6031-pmgr.dtsi | 2400 +++++++++++++++++ arch/arm64/boot/dts/apple/t6031.dtsi | 48 + arch/arm64/boot/dts/apple/t6032-j575d.dts | 46 + arch/arm64/boot/dts/apple/t6032.dtsi | 416 +++ arch/arm64/boot/dts/apple/t6034-j514m.dts | 18 + arch/arm64/boot/dts/apple/t6034-j516m.dts | 18 + arch/arm64/boot/dts/apple/t6034.dtsi | 53 + .../arm64/boot/dts/apple/t603x-j514-j516.dtsi | 66 + 15 files changed, 3760 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6031-base.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6031-die0.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6031-dieX.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6031-j514c.dts create mode 100644 arch/arm64/boot/dts/apple/t6031-j516c.dts create mode 100644 arch/arm64/boot/dts/apple/t6031-pmgr.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6031.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6032-j575d.dts create mode 100644 arch/arm64/boot/dts/apple/t6032.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6034-j514m.dts create mode 100644 arch/arm64/boot/dts/apple/t6034-j516m.dts create mode 100644 arch/arm64/boot/dts/apple/t6034.dtsi create mode 100644 arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 6fc3349a5842..a22b4a8068b6 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -87,6 +87,11 @@ dtb-$(CONFIG_ARCH_APPLE) += t6021-j416c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6020-j474s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6021-j475c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6022-j475d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6031-j514c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6031-j516c.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6032-j575d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6034-j514m.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6034-j516m.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j415.dtb dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb diff --git a/arch/arm64/boot/dts/apple/t6031-base.dtsi b/arch/arm64/boot/dts/apple/t6031-base.dtsi new file mode 100644 index 000000000000..74e1fa51242d --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-base.dtsi @@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes common for T6031, T6032 and T6034 family SoCs (M3 Max/Ultra) + * + * Other names: H15J, H15S, "Palma" + * + * Copyright The Asahi Linux Contributors + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e00>; + }; + core1 { + cpu = <&cpu_e01>; + }; + core2 { + cpu = <&cpu_e02>; + }; + core3 { + cpu = <&cpu_e03>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p00>; + }; + core1 { + cpu = <&cpu_p01>; + }; + core2 { + cpu = <&cpu_p02>; + }; + core3 { + cpu = <&cpu_p03>; + }; + core4 { + cpu = <&cpu_p04>; + }; + core5 { + cpu = <&cpu_p05>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu_p10>; + }; + core1 { + cpu = <&cpu_p11>; + }; + core2 { + cpu = <&cpu_p12>; + }; + core3 { + cpu = <&cpu_p13>; + }; + core4 { + cpu = <&cpu_p14>; + }; + core5 { + cpu = <&cpu_p15>; + }; + }; + }; + + cpu_e00: cpu@0 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e01: cpu@1 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e02: cpu@2 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e03: cpu@3 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_p00: cpu@10100 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p01: cpu@10101 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p02: cpu@10102 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p03: cpu@10103 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p04: cpu@10104 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10104>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p05: cpu@10105 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10105>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p10: cpu@10200 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10200>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p11: cpu@10201 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10201>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p12: cpu@10202 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10202>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p13: cpu@10203 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10203>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p14: cpu@10204 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10204>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p15: cpu@10205 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10205>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_2>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + + l2_cache_2: l2-cache-2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = , + , + , + ; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t6031-die0.dtsi b/arch/arm64/boot/dts/apple/t6031-die0.dtsi new file mode 100644 index 000000000000..47d08672a047 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-die0.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Devices used on die 0 on the Apple T6032 "M3 Ultra" SoC and present on + * Apple T6030 ("M3 Pro") and T6031 / T6034 ("M3 Max"). + * + * Copyright The Asahi Linux Contributors + */ + + aic: interrupt-controller@292400000 { + compatible = "apple,t6031-aic3", "apple,t8122-aic3"; + #interrupt-cells = <4>; + interrupt-controller; + + reg = <0x00000002 0x92400000 0x00000000 0x1cc000>, + <0x00000002 0x92440000 0x00000000 0x4000>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + }; + + wdt: watchdog@2a02d4000 { + compatible = "apple,t6031-wdt", "apple,t8103-wdt"; + reg = <0x2 0xa02d4000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pinctrl_smc: pinctrl@2a4820000 { + compatible = "apple,t6031-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa4820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 30>; + apple,npins = <30>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + i2c0: i2c@391010000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91010000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c0>; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + i2c1: i2c@391014000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91014000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c1>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c2: i2c@391018000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91018000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c2>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c3: i2c@39101c000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9101c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c3>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c4: i2c@391020000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91020000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c4>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c5: i2c@391024000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91024000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c5_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c5>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c6: i2c@391028000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91028000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c6>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c7: i2c@39102c000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x9102c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c7>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + i2c8: i2c@391030000 { + compatible = "apple,t6031-i2c", "apple,t8103-i2c"; + reg = <0x3 0x91030000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + power-domains = <&ps_i2c8>; + #address-cells = <0x1>; + #size-cells = <0x0>; + status = "disabled"; + }; + + fpwm0: pwm@391040000 { + compatible = "apple,t6031-fpwm", "apple,s5l-fpwm"; + reg = <0x3 0x91040000 0x0 0x4000>; + power-domains = <&ps_fpwm0>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + + serial0: serial@391200000 { + compatible = "apple,s5l-uart"; + reg = <0x3 0x91200000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; diff --git a/arch/arm64/boot/dts/apple/t6031-dieX.dtsi b/arch/arm64/boot/dts/apple/t6031-dieX.dtsi new file mode 100644 index 000000000000..2e9d3d2e6dea --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-dieX.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Nodes present on both dies of T6032 (M3 Ultra) and present on T6031 / T6034 + * (M3 Max). + * + * Copyright The Asahi Linux Contributors + */ + + DIE_NODE(pmgr): power-management@292280000 { + compatible = "apple,t6031-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x92280000 0 0xc000>; + }; + + DIE_NODE(pmgr1): power-management@292800000 { + compatible = "apple,t6031-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x92800000 0 0x4000>; + }; + + DIE_NODE(pinctrl_nub): pinctrl@2a01f0000 { + compatible = "apple,t6031-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa01f0000 0x0 0x4000>; + power-domains = <&DIE_NODE(ps_nub_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_nub) 0 0 59>; + apple,npins = <59>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + DIE_NODE(pmgr_mini): power-management@2a0280000 { + compatible = "apple,t6031-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xa0280000 0 0x4000>; + }; + + DIE_NODE(pinctrl_aop): pinctrl@2a8824000 { + compatible = "apple,t6031-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xa8824000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_aop) 0 0 102>; + apple,npins = <102>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + DIE_NODE(pinctrl_ap): pinctrl@2b3000000 { + compatible = "apple,t6031-pinctrl", "apple,t8103-pinctrl"; + reg = <0x2 0xb3000000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + clocks = <&clkref>; + power-domains = <&DIE_NODE(ps_gpio)>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&DIE_NODE(pinctrl_ap) 0 0 200>; + apple,npins = <200>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + DIE_NODE(pmgr_gfx): power-management@408e80000 { + compatible = "apple,t6031-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x4 0x8e80000 0 0x4000>; + }; diff --git a/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi b/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi new file mode 100644 index 000000000000..5e4727e357d2 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-gpio-pins.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * GPIO pin mappings for Apple T6031/T6032/T6034 SoCs. + * + * Copyright The Asahi Linux Contributors + */ + +&pinctrl_ap { + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + + i2c5_pins: i2c5-pins { + pinmux = , + ; + }; + + i2c6_pins: i2c6-pins { + pinmux = , + ; + }; + + i2c7_pins: i2c7-pins { + pinmux = , + ; + }; + + i2c8_pins: i2c8-pins { + pinmux = , + ; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t6031-j514c.dts b/arch/arm64/boot/dts/apple/t6031-j514c.dts new file mode 100644 index 000000000000..c1507158325e --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-j514c.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M3 Max, 16 CPU cores, Nov 2023) + * + * target-type: J514c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6031.dtsi" +#include "t603x-j514-j516.dtsi" + +/ { + compatible = "apple,j514c", "apple,t6031", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M3 Max, 16 CPU cores, Nov 2023)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6031-j516c.dts b/arch/arm64/boot/dts/apple/t6031-j516c.dts new file mode 100644 index 000000000000..841b2bb10b06 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-j516c.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M3 Max, 16 CPU cores, Nov 2023) + * + * target-type: J516c + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6031.dtsi" +#include "t603x-j514-j516.dtsi" + +/ { + compatible = "apple,j516c", "apple,t6031", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M3 Max, 16 CPU cores, Nov 2023)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6031-pmgr.dtsi b/arch/arm64/boot/dts/apple/t6031-pmgr.dtsi new file mode 100644 index 000000000000..f80ee5f7ebcf --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031-pmgr.dtsi @@ -0,0 +1,2400 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for Apple T6031 "M3 Max/Ultra" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&DIE_NODE(pmgr) { + DIE_NODE(ps_ispsens0): power-controller@100 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ispsens0); + }; + + DIE_NODE(ps_apcie_gp): power-controller@108 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_gp); + }; + + DIE_NODE(ps_apcie_ge): power-controller@110 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_ge); + }; + + DIE_NODE(ps_apcie_st): power-controller@118 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_st); + }; + + DIE_NODE(ps_afnc3_ioa): power-controller@120 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ioa); + apple,always-on; + }; + + DIE_NODE(ps_afnc3_ls): power-controller@128 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ioa)>; + }; + + DIE_NODE(ps_afnc3_lw0): power-controller@138 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ls)>; + }; + + DIE_NODE(ps_afnc3_lw1): power-controller@148 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc3_lw1); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc3_ls)>; + }; + + DIE_NODE(ps_apcie_sys_gp): power-controller@158 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_sys_gp); + power-domains = <&DIE_NODE(ps_apcie_gp)>, <&DIE_NODE(ps_afnc3_lw0)>; + }; + + DIE_NODE(ps_afnc4_ioa): power-controller@168 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ioa); + apple,always-on; + }; + + DIE_NODE(ps_afnc4_ls): power-controller@178 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc4_ioa)>; + }; + + DIE_NODE(ps_afnc4_lw0): power-controller@188 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc4_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc4_ls)>; + }; + + DIE_NODE(ps_afnc5_ioa): power-controller@198 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ioa); + apple,always-on; + }; + + DIE_NODE(ps_afnc5_ls): power-controller@1a8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc5_ioa)>; + }; + + DIE_NODE(ps_afnc5_lw0): power-controller@1b8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc5_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc5_ls)>; + }; + + DIE_NODE(ps_afnc6_ioa): power-controller@1c8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_ioa); + apple,always-on; + }; + + DIE_NODE(ps_afnc6_ls): power-controller@1d8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc6_ioa)>; + }; + + DIE_NODE(ps_afnc6_lw0): power-controller@1e8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc6_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc6_ls)>; + }; + + DIE_NODE(ps_sio): power-controller@1f8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio); + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; + + DIE_NODE(ps_disp_sys): power-controller@200 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp_sys); + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; + + DIE_NODE(ps_isp_sys): power-controller@208 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_sys); + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; + + DIE_NODE(ps_sio_cpu): power-controller@210 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_cpu); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm0): power-controller@218 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm1): power-controller@220 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_fpwm2): power-controller@228 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(fpwm2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c0): power-controller@230 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c0); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c1): power-controller@238 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c1); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c2): power-controller@240 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c2); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c3): power-controller@248 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c3); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c4): power-controller@250 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c4); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c5): power-controller@258 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c5); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c6): power-controller@260 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c6); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c7): power-controller@268 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c7); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_i2c8): power-controller@270 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(i2c8); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_spi_p): power-controller@278 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_uart_p): power-controller@280 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_audio_p): power-controller@288 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(audio_p); + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_aes): power-controller@290 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aes); + apple,always-on; + power-domains = <&DIE_NODE(ps_sio)>; + }; + + DIE_NODE(ps_disp_fe): power-controller@298 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp_fe); + power-domains = <&DIE_NODE(ps_disp_cpu)>; + apple,min-state = <4>; + }; + + DIE_NODE(ps_disp_cpu): power-controller@2a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(disp_cpu); + power-domains = <&DIE_NODE(ps_disp_sys)>; + }; + + DIE_NODE(ps_spi0): power-controller@2a8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi0); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi1): power-controller@2b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi1); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi2): power-controller@2b8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi2); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi3): power-controller@2c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi3); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi4): power-controller@2c8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi4); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_spi5): power-controller@2d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(spi5); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_qspi): power-controller@2d8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(qspi); + power-domains = <&DIE_NODE(ps_spi_p)>; + }; + + DIE_NODE(ps_uart_n): power-controller@2e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart_n); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart0): power-controller@2e8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart0); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart1): power-controller@2f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart1); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart2): power-controller@2f8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart2); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart3): power-controller@300 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart3); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart4): power-controller@308 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart4); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart5): power-controller@310 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart5); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_uart6): power-controller@318 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(uart6); + power-domains = <&DIE_NODE(ps_uart_p)>; + }; + + DIE_NODE(ps_sio_adma): power-controller@320 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sio_adma); + power-domains = <&DIE_NODE(ps_sio)>, <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa0): power-controller@328 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa0); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa1): power-controller@330 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa1); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa2): power-controller@338 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa2); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa3): power-controller@340 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa3); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_dpa4): power-controller@348 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dpa4); + power-domains = <&DIE_NODE(ps_audio_p)>; + }; + + DIE_NODE(ps_amcc1): power-controller@350 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc1); + apple,always-on; + }; + + DIE_NODE(ps_amcc3): power-controller@360 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc3); + apple,always-on; + }; + + DIE_NODE(ps_amcc5): power-controller@370 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc5); + apple,always-on; + }; + + DIE_NODE(ps_amcc7): power-controller@380 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc7); + apple,always-on; + }; + + DIE_NODE(ps_dcs_04): power-controller@390 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_04); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc1)>; + }; + + DIE_NODE(ps_dcs_05): power-controller@3a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_05); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc1)>; + }; + + DIE_NODE(ps_dcs_06): power-controller@3b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_06); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc1)>; + }; + + DIE_NODE(ps_dcs_07): power-controller@3c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_07); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc1)>; + }; + + DIE_NODE(ps_dcs_12): power-controller@3d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_12); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc3)>; + }; + + DIE_NODE(ps_dcs_13): power-controller@3e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_13); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc3)>; + }; + + DIE_NODE(ps_dcs_14): power-controller@3f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_14); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc3)>; + }; + + DIE_NODE(ps_dcs_15): power-controller@400 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_15); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc3)>; + }; + + DIE_NODE(ps_dcs_20): power-controller@410 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_20); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc5)>; + }; + + DIE_NODE(ps_dcs_21): power-controller@420 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_21); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc5)>; + }; + + DIE_NODE(ps_dcs_22): power-controller@430 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x430 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_22); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc5)>; + }; + + DIE_NODE(ps_dcs_23): power-controller@440 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x440 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_23); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc5)>; + }; + + DIE_NODE(ps_dcs_28): power-controller@450 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x450 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_28); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc7)>; + }; + + DIE_NODE(ps_dcs_29): power-controller@460 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x460 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_29); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc7)>; + }; + + DIE_NODE(ps_dcs_30): power-controller@470 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x470 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_30); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc7)>; + }; + + DIE_NODE(ps_dcs_31): power-controller@480 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x480 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_31); + apple,always-on; /* LPDDR5 interface */ + power-domains = <&DIE_NODE(ps_amcc7)>; + }; + + DIE_NODE(ps_mca0): power-controller@4e8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca0); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca1): power-controller@4f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca1); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca2): power-controller@4f8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca2); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_mca3): power-controller@500 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x500 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mca3); + power-domains = <&DIE_NODE(ps_audio_p)>, <&DIE_NODE(ps_sio_adma)>; + }; + + DIE_NODE(ps_msr1): power-controller@508 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x508 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1); + power-domains = <&DIE_NODE(ps_afnc5_lw0)>; + }; + + DIE_NODE(ps_venc1_sys): power-controller@510 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x510 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_sys); + power-domains = <&DIE_NODE(ps_afnc5_lw0)>; + }; + + DIE_NODE(ps_msr0): power-controller@518 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x518 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0); + power-domains = <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_ane_sys): power-controller@520 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x520 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_sys); + power-domains = <&DIE_NODE(ps_afnc5_lw0)>, <&DIE_NODE(ps_afnc6_lw0)>; + }; + + DIE_NODE(ps_msr1_ase_core): power-controller@538 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x538 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr1_ase_core); + power-domains = <&DIE_NODE(ps_msr1)>; + }; + + DIE_NODE(ps_apcie_sys_ge): power-controller@540 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x540 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_sys_ge); + power-domains = <&DIE_NODE(ps_apcie_ge)>, <&DIE_NODE(ps_afnc3_lw0)>; + }; + + DIE_NODE(ps_ans): power-controller@550 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x550 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ans); + power-domains = <&DIE_NODE(ps_afnc3_lw1)>; + }; + + DIE_NODE(ps_apcie_sys_st): power-controller@560 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x560 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_sys_st); + power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans)>; + }; + + DIE_NODE(ps_apcie_sys_st1): power-controller@570 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x570 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_sys_st1); + power-domains = <&DIE_NODE(ps_apcie_st)>, <&DIE_NODE(ps_ans)>; + }; + + DIE_NODE(ps_apcie_phy_sw): power-controller@580 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x580 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(apcie_phy_sw); + apple,always-on; /* macOS does not turn this off */ + }; + + DIE_NODE(ps_msr0_ase_core): power-controller@590 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x590 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msr0_ase_core); + power-domains = <&DIE_NODE(ps_msr0)>; + }; + + DIE_NODE(ps_ane_mpm): power-controller@5a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_mpm); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_cpu): power-controller@5a8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_cpu); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_td): power-controller@5b8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_td); + power-domains = <&DIE_NODE(ps_ane_sys)>; + }; + + DIE_NODE(ps_ane_base): power-controller@5c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ane_base); + power-domains = <&DIE_NODE(ps_ane_td)>; + }; + + DIE_NODE(ps_sep): power-controller@c00 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sep); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc4_lw0)>; + }; + + DIE_NODE(ps_isp_cpu): power-controller@4008 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_cpu); + power-domains = <&DIE_NODE(ps_isp_sys)>; + }; + + DIE_NODE(ps_isp_fe): power-controller@4030 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_fe); + power-domains = <&DIE_NODE(ps_isp_sys)>; + }; + + DIE_NODE(ps_dprx): power-controller@4038 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4038 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dprx); + power-domains = <&DIE_NODE(ps_isp_fe)>; + }; + + DIE_NODE(ps_isp_secure): power-controller@4040 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_secure); + power-domains = <&DIE_NODE(ps_isp_fe)>; + }; + + DIE_NODE(ps_isp_be): power-controller@4048 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_be); + power-domains = <&DIE_NODE(ps_isp_fe)>; + }; + + DIE_NODE(ps_isp_clr): power-controller@4050 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(isp_clr); + power-domains = <&DIE_NODE(ps_isp_be)>; + }; + + DIE_NODE(ps_venc1_dma): power-controller@8000 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_dma); + power-domains = <&DIE_NODE(ps_venc1_sys)>; + }; + + DIE_NODE(ps_venc1_pipe4): power-controller@8008 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe4); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_pipe5): power-controller@8010 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_pipe5); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_me0): power-controller@8018 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me0); + power-domains = <&DIE_NODE(ps_venc1_dma)>; + }; + + DIE_NODE(ps_venc1_me1): power-controller@8020 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc1_me1); + power-domains = <&DIE_NODE(ps_venc1_me0)>; + }; +}; + +&DIE_NODE(pmgr1) { + DIE_NODE(ps_aic): power-controller@100 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(aic); + }; + + DIE_NODE(ps_dwi): power-controller@108 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dwi); + }; + + DIE_NODE(ps_sbr): power-controller@110 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(sbr); + apple,always-on; + }; + + DIE_NODE(ps_pms): power-controller@118 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms); + apple,always-on; + }; + + DIE_NODE(ps_soc_dpe): power-controller@120 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(soc_dpe); + apple,always-on; + }; + + DIE_NODE(ps_pms_c1ppt): power-controller@128 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_c1ppt); + apple,always-on; + power-domains = <&DIE_NODE(ps_soc_dpe)>; + }; + + DIE_NODE(ps_pmgr_soc_ocla): power-controller@130 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmgr_soc_ocla); + }; + + DIE_NODE(ps_pms_fpwm0): power-controller@138 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_fpwm0); + }; + + DIE_NODE(ps_pms_fpwm1): power-controller@140 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_fpwm1); + }; + + DIE_NODE(ps_pms_fpwm2): power-controller@148 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_fpwm2); + }; + + DIE_NODE(ps_pms_fpwm3): power-controller@150 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_fpwm3); + }; + + DIE_NODE(ps_pms_fpwm4): power-controller@158 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_fpwm4); + }; + + DIE_NODE(ps_gpio): power-controller@160 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpio); + power-domains = <&DIE_NODE(ps_sbr)>; + }; + + DIE_NODE(ps_msg): power-controller@168 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(msg); + }; + + DIE_NODE(ps_afc): power-controller@170 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afc); + apple,always-on; + }; + + DIE_NODE(ps_amcc0): power-controller@180 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afc)>; + }; + + DIE_NODE(ps_amcc2): power-controller@190 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc2); + apple,always-on; + power-domains = <&DIE_NODE(ps_afc)>; + }; + + DIE_NODE(ps_amcc4): power-controller@1a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc4); + apple,always-on; + power-domains = <&DIE_NODE(ps_afc)>; + }; + + DIE_NODE(ps_amcc6): power-controller@1b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(amcc6); + apple,always-on; + power-domains = <&DIE_NODE(ps_afc)>; + }; + + DIE_NODE(ps_dcs_00): power-controller@1c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_00); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc0)>; + }; + + DIE_NODE(ps_dcs_01): power-controller@1d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_01); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc0)>; + }; + + DIE_NODE(ps_dcs_02): power-controller@1e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_02); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc0)>; + }; + + DIE_NODE(ps_dcs_03): power-controller@1f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_03); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc0)>; + }; + + DIE_NODE(ps_dcs_08): power-controller@200 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_08); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc2)>; + }; + + DIE_NODE(ps_dcs_09): power-controller@210 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_09); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc2)>; + }; + + DIE_NODE(ps_dcs_10): power-controller@220 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_10); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc2)>; + }; + + DIE_NODE(ps_dcs_11): power-controller@230 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_11); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc2)>; + }; + + DIE_NODE(ps_dcs_16): power-controller@240 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_16); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc4)>; + }; + + DIE_NODE(ps_dcs_17): power-controller@250 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_17); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc4)>; + }; + + DIE_NODE(ps_dcs_18): power-controller@260 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_18); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc4)>; + }; + + DIE_NODE(ps_dcs_19): power-controller@270 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_19); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc4)>; + }; + + DIE_NODE(ps_dcs_24): power-controller@280 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_24); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc6)>; + }; + + DIE_NODE(ps_dcs_25): power-controller@290 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_25); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc6)>; + }; + + DIE_NODE(ps_dcs_26): power-controller@2a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_26); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc6)>; + }; + + DIE_NODE(ps_afi): power-controller@2b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afi); + apple,always-on; + }; + + DIE_NODE(ps_dcs_27): power-controller@2c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dcs_27); + apple,always-on; + power-domains = <&DIE_NODE(ps_amcc6)>; + }; + + DIE_NODE(ps_afi_d2d_0): power-controller@2d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afi_d2d_0); + apple,always-on; + status = "disabled"; + }; + + DIE_NODE(ps_afi_d2d_1): power-controller@2e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afi_d2d_1); + apple,always-on; + status = "disabled"; + }; + + DIE_NODE(ps_afc_d2d_0): power-controller@2f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afc_d2d_0); + apple,always-on; + status = "disabled"; + }; + + DIE_NODE(ps_afc_d2d_1): power-controller@300 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afc_d2d_1); + apple,always-on; + status = "disabled"; + }; + + DIE_NODE(ps_afr_d2d_0): power-controller@310 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afr_d2d_0); + apple,always-on; + status = "disabled"; + }; + + DIE_NODE(ps_afr_d2d_1): power-controller@320 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afr_d2d_1); + apple,always-on; + status = "disabled"; + }; + + DIE_NODE(ps_afnc1_ioa): power-controller@330 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc0_ioa): power-controller@340 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc2_ioa): power-controller@350 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc7_ioa): power-controller@360 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc7_ioa); + apple,always-on; + power-domains = <&DIE_NODE(ps_afi)>; + }; + + DIE_NODE(ps_afnc1_ls): power-controller@370 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc1_ioa)>; + }; + + DIE_NODE(ps_afnc0_ls): power-controller@380 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc0_ioa)>; + }; + + DIE_NODE(ps_afnc2_ls): power-controller@390 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ioa)>; + }; + + DIE_NODE(ps_afnc7_ls): power-controller@3a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc7_ls); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc7_ioa)>; + }; + + DIE_NODE(ps_afnc1_lw0): power-controller@3b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc1_lw1): power-controller@3c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc1_lw1); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc1_ls)>; + }; + + DIE_NODE(ps_afnc0_lw0): power-controller@3d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc0_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc0_ls)>; + }; + + DIE_NODE(ps_afnc2_lw0): power-controller@3e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw0); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc2_lw1): power-controller@3f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc2_lw1); + apple,always-on; + power-domains = <&DIE_NODE(ps_afnc2_ls)>; + }; + + DIE_NODE(ps_afnc7_lw0): power-controller@400 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afnc7_lw0); + apple,always-on; + }; + + DIE_NODE(ps_avd_sys): power-controller@410 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(avd_sys); + power-domains = <&DIE_NODE(ps_afnc1_lw0)>; + }; + + DIE_NODE(ps_jpg): power-controller@418 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(jpg); + power-domains = <&DIE_NODE(ps_afnc1_lw0)>; + }; + + DIE_NODE(ps_dispext3_sys): power-controller@420 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_sys); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_scodec): power-controller@428 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(scodec); + power-domains = <&DIE_NODE(ps_afnc1_lw1)>; + }; + + DIE_NODE(ps_venc0_sys): power-controller@430 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x430 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc0_sys); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_prores): power-controller@438 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x438 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(prores); + power-domains = <&DIE_NODE(ps_afnc0_lw0)>; + }; + + DIE_NODE(ps_dispext0_sys): power-controller@440 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x440 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_sys); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_atc0_common): power-controller@448 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x448 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_common); + power-domains = <&DIE_NODE(ps_afnc2_lw0)>; + }; + + DIE_NODE(ps_atc1_common): power-controller@450 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x450 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_common); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_atc2_common): power-controller@458 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x458 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_common); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_atc3_common): power-controller@460 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x460 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_common); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_trace_fab): power-controller@468 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x468 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(trace_fab); + power-domains = <&DIE_NODE(ps_afnc2_lw1)>; + }; + + DIE_NODE(ps_dispext1_sys): power-controller@470 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x470 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_sys); + power-domains = <&DIE_NODE(ps_afnc7_lw0)>; + }; + + DIE_NODE(ps_dispext2_sys): power-controller@478 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x478 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_sys); + power-domains = <&DIE_NODE(ps_afnc7_lw0)>; + }; + + DIE_NODE(ps_dispext3_fe): power-controller@480 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x480 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_fe); + power-domains = <&DIE_NODE(ps_dispext3_cpu)>; + }; + + DIE_NODE(ps_dispext3_cpu): power-controller@488 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x488 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext3_cpu); + power-domains = <&DIE_NODE(ps_dispext3_sys)>; + }; + + DIE_NODE(ps_scodec_streaming): power-controller@490 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x490 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(scodec_streaming); + power-domains = <&DIE_NODE(ps_scodec)>; + }; + + DIE_NODE(ps_venc0_dma): power-controller@498 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x498 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc0_dma); + power-domains = <&DIE_NODE(ps_venc0_sys)>; + }; + + DIE_NODE(ps_dispext0_fe): power-controller@4a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_fe); + power-domains = <&DIE_NODE(ps_dispext0_cpu)>; + }; + + DIE_NODE(ps_dispext0_cpu): power-controller@4a8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext0_cpu); + power-domains = <&DIE_NODE(ps_dispext0_sys)>; + }; + + DIE_NODE(ps_atc0_cio): power-controller@4b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc0_pcie): power-controller@4b8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_pcie); + power-domains = <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_cio): power-controller@4c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc1_pcie): power-controller@4c8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_pcie); + power-domains = <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_cio): power-controller@4d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc2_pcie): power-controller@4d8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_pcie); + power-domains = <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_cio): power-controller@4e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_atc3_pcie): power-controller@4e8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_pcie); + power-domains = <&DIE_NODE(ps_atc3_common)>; + }; + + DIE_NODE(ps_dispext1_fe): power-controller@4f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_fe); + power-domains = <&DIE_NODE(ps_dispext1_cpu)>; + }; + + DIE_NODE(ps_dispext1_cpu): power-controller@4f8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext1_cpu); + power-domains = <&DIE_NODE(ps_dispext1_sys)>; + }; + + DIE_NODE(ps_dispext2_fe): power-controller@500 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x500 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_fe); + power-domains = <&DIE_NODE(ps_dispext2_cpu)>; + }; + + DIE_NODE(ps_dispext2_cpu): power-controller@508 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x508 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(dispext2_cpu); + power-domains = <&DIE_NODE(ps_dispext2_sys)>; + }; + + DIE_NODE(ps_venc0_pipe4): power-controller@538 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x538 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc0_pipe4); + power-domains = <&DIE_NODE(ps_venc0_dma)>; + }; + + DIE_NODE(ps_venc0_pipe5): power-controller@540 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x540 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc0_pipe5); + power-domains = <&DIE_NODE(ps_venc0_dma)>; + }; + + DIE_NODE(ps_venc0_me0): power-controller@548 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x548 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc0_me0); + power-domains = <&DIE_NODE(ps_venc0_dma)>; + }; + + DIE_NODE(ps_pmp): power-controller@550 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x550 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pmp); + }; + + DIE_NODE(ps_pms_sram): power-controller@560 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x560 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(pms_sram); + }; + + DIE_NODE(ps_atc0_cio_pcie): power-controller@598 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x598 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_pcie); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc0_cio_usb): power-controller@5a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_cio_usb); + power-domains = <&DIE_NODE(ps_atc0_cio)>; + }; + + DIE_NODE(ps_atc1_cio_pcie): power-controller@5a8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_pcie); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc1_cio_usb): power-controller@5b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_cio_usb); + power-domains = <&DIE_NODE(ps_atc1_cio)>; + }; + + DIE_NODE(ps_atc2_cio_pcie): power-controller@5b8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_pcie); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc2_cio_usb): power-controller@5c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_cio_usb); + power-domains = <&DIE_NODE(ps_atc2_cio)>; + }; + + DIE_NODE(ps_atc3_cio_pcie): power-controller@5c8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_pcie); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_atc3_cio_usb): power-controller@5d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_cio_usb); + power-domains = <&DIE_NODE(ps_atc3_cio)>; + }; + + DIE_NODE(ps_venc0_me1): power-controller@638 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x638 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(venc0_me1); + power-domains = <&DIE_NODE(ps_venc0_me0)>; + }; + + DIE_NODE(ps_ap_tmm): power-controller@670 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x670 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(ap_tmm); + }; +}; + +&DIE_NODE(pmgr_mini) { + DIE_NODE(ps_debug_gated): power-controller@58 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug_gated); + apple,always-on; + }; + + DIE_NODE(ps_nub_spmi_ahb_fab): power-controller@60 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi_ahb_fab); + apple,always-on; + }; + + DIE_NODE(ps_nub_spmi0): power-controller@68 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi0); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_spmi_ahb_fab)>; + }; + + DIE_NODE(ps_nub_spmi_a0): power-controller@70 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi_a0); + apple,always-on; + }; + + DIE_NODE(ps_nub_spmi_a1): power-controller@78 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi_a1); + apple,always-on; + }; + + DIE_NODE(ps_nub_spmi_a2): power-controller@80 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi_a2); + apple,always-on; + }; + + DIE_NODE(ps_nub_aon): power-controller@90 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_aon); + apple,always-on; + }; + + DIE_NODE(ps_nub_gpio): power-controller@98 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_gpio); + apple,always-on; + }; + + DIE_NODE(ps_nub_ocla): power-controller@a0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_ocla); + apple,always-on; + }; + + DIE_NODE(ps_atc0_common_dp): power-controller@a8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_common_dp); + }; + + DIE_NODE(ps_atc1_common_dp): power-controller@b0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_common_dp); + }; + + DIE_NODE(ps_atc2_common_dp): power-controller@b8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_common_dp); + }; + + DIE_NODE(ps_atc3_common_dp): power-controller@c0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_common_dp); + }; + + DIE_NODE(ps_nub_spmi1): power-controller@c8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi1); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_spmi_ahb_fab)>; + }; + + DIE_NODE(ps_atc0_usb_aon): power-controller@d0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb_aon); + }; + + DIE_NODE(ps_atc1_usb_aon): power-controller@d8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb_aon); + }; + + DIE_NODE(ps_atc2_usb_aon): power-controller@e0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb_aon); + }; + + DIE_NODE(ps_atc3_usb_aon): power-controller@e8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb_aon); + }; + + DIE_NODE(ps_nub_spmi2): power-controller@f0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi2); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_spmi_ahb_fab)>; + }; + + DIE_NODE(ps_nub_spmi3): power-controller@f8 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi3); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_spmi_ahb_fab)>; + }; + + DIE_NODE(ps_nub_spmi4): power-controller@100 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi4); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_spmi_ahb_fab)>; + }; + + DIE_NODE(ps_nub_spmi5): power-controller@108 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_spmi5); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_spmi_ahb_fab)>; + }; + + DIE_NODE(ps_nub_fabric): power-controller@110 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_fabric); + apple,always-on; + }; + + DIE_NODE(ps_nub_sram): power-controller@120 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(nub_sram); + apple,always-on; + }; + + DIE_NODE(ps_debug_switch): power-controller@130 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(debug_switch); + apple,always-on; + }; + + DIE_NODE(ps_atc0_usb): power-controller@140 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc0_usb); + power-domains = <&DIE_NODE(ps_atc0_usb_aon)>, <&DIE_NODE(ps_atc0_common)>; + }; + + DIE_NODE(ps_atc1_usb): power-controller@148 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc1_usb); + power-domains = <&DIE_NODE(ps_atc1_usb_aon)>, <&DIE_NODE(ps_atc1_common)>; + }; + + DIE_NODE(ps_atc2_usb): power-controller@150 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc2_usb); + power-domains = <&DIE_NODE(ps_atc2_usb_aon)>, <&DIE_NODE(ps_atc2_common)>; + }; + + DIE_NODE(ps_atc3_usb): power-controller@158 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(atc3_usb); + power-domains = <&DIE_NODE(ps_atc3_usb_aon)>, <&DIE_NODE(ps_atc3_common)>; + }; + +#if 0 + /* MTP stuff is self-managed */ + DIE_NODE(ps_mtp_fabric): power-controller@2000 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_fabric); + apple,always-on; + power-domains = <&DIE_NODE(ps_nub_fabric)>; + }; + + DIE_NODE(ps_mtp_gpio): power-controller@2008 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_gpio); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_base): power-controller@2010 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_base); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_periph): power-controller@2018 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_periph); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_uart0): power-controller@2020 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_uart0); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_cpu): power-controller@2028 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_cpu); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>; + }; + + DIE_NODE(ps_mtp_scm_fabric): power-controller@2030 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_scm_fabric); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_periph)>; + }; + + DIE_NODE(ps_mtp_spi0): power-controller@2038 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2038 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_spi0); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>, <&DIE_NODE(ps_mtp_periph)>; + }; + + DIE_NODE(ps_mtp_i2cm0): power-controller@2040 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_i2cm0); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>, <&DIE_NODE(ps_mtp_periph)>; + }; + + DIE_NODE(ps_mtp_sram): power-controller@2048 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_sram); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_cpu)>, <&DIE_NODE(ps_mtp_scm_fabric)>; + }; + + DIE_NODE(ps_mtp_dma): power-controller@2050 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(mtp_dma); + apple,always-on; + power-domains = <&DIE_NODE(ps_mtp_fabric)>, <&DIE_NODE(ps_mtp_sram)>; + }; +#endif +}; + +&DIE_NODE(pmgr_gfx) { + DIE_NODE(ps_gpx): power-controller@0 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gpx); + apple,always-on; + }; + + DIE_NODE(ps_afr): power-controller@100 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(afr); + apple,always-on; + }; + + DIE_NODE(ps_gfx): power-controller@110 { + compatible = "apple,t6031-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = DIE_LABEL(gfx); + power-domains = <&DIE_NODE(ps_afr)>; + }; +}; diff --git a/arch/arm64/boot/dts/apple/t6031.dtsi b/arch/arm64/boot/dts/apple/t6031.dtsi new file mode 100644 index 000000000000..0059afe9a844 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6031.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6031 "M3 Max" SoC + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include + +#include "multi-die-cpp.h" + +#include "t6031-base.dtsi" + +/ { + compatible = "apple,t6031", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&soc { + #include "t6031-die0.dtsi" + #include "t6031-dieX.dtsi" +}; + +#include "t6031-gpio-pins.dtsi" +#include "t6031-pmgr.dtsi" + +#undef DIE +#undef DIE_NO diff --git a/arch/arm64/boot/dts/apple/t6032-j575d.dts b/arch/arm64/boot/dts/apple/t6032-j575d.dts new file mode 100644 index 000000000000..56edfb1139fb --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6032-j575d.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple Mac Studio (M3 Ultra, 2025) + * + * target-type: J575d + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6032.dtsi" + +/ { + compatible = "apple,j575d", "apple,t6032", "apple,arm-platform"; + model = "Apple Mac Studio (M3 Ultra, 2025)"; + + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + power-domains = <&ps_dispext0_cpu>; + }; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t6032.dtsi b/arch/arm64/boot/dts/apple/t6032.dtsi new file mode 100644 index 000000000000..bbf19ecdaaec --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6032.dtsi @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6032 "M3 Ultra" SoC + * + * Other names: H15J, "Palma 2C" + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include +#include + +#include "multi-die-cpp.h" + +#include "t6031-base.dtsi" + +/ { + compatible = "apple,t6032", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster3 { + core0 { + cpu = <&cpu_e10>; + }; + core1 { + cpu = <&cpu_e11>; + }; + core2 { + cpu = <&cpu_e12>; + }; + core3 { + cpu = <&cpu_e13>; + }; + }; + + cluster4 { + core0 { + cpu = <&cpu_p20>; + }; + core1 { + cpu = <&cpu_p21>; + }; + core2 { + cpu = <&cpu_p22>; + }; + core3 { + cpu = <&cpu_p23>; + }; + core4 { + cpu = <&cpu_p24>; + }; + core5 { + cpu = <&cpu_p25>; + }; + }; + + cluster5 { + core0 { + cpu = <&cpu_p30>; + }; + core1 { + cpu = <&cpu_p31>; + }; + core2 { + cpu = <&cpu_p32>; + }; + core3 { + cpu = <&cpu_p33>; + }; + core4 { + cpu = <&cpu_p34>; + }; + core5 { + cpu = <&cpu_p35>; + }; + }; + }; + + cpu_e10: cpu@800 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x800>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e11: cpu@801 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x801>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e12: cpu@802 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x802>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e13: cpu@803 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x803>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_3>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_p20: cpu@10900 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10900>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p21: cpu@10901 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10901>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p22: cpu@10902 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10902>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p23: cpu@10903 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10903>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p24: cpu@10904 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10904>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p25: cpu@10905 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10905>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_4>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p30: cpu@10a00 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10a00>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p31: cpu@10a01 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10a01>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p32: cpu@10a02 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10a02>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p33: cpu@10a03 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10a03>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p34: cpu@10a04 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10a04>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p35: cpu@10a05 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10a05>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_5>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_3: l2-cache-3 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_4: l2-cache-4 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + + l2_cache_5: l2-cache-5 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + die0: soc@200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x02 0x00000000 0x02 0x00000000 0x4 0x00000000>, + <0x05 0x80000000 0x05 0x80000000 0x1 0x80000000>, + <0x07 0x00000000 0x07 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x16 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; + + die1: soc@2200000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x02 0x00000000 0x22 0x00000000 0x4 0x00000000>, + <0x07 0x00000000 0x27 0x00000000 0xf 0x80000000>, + <0x16 0x80000000 0x36 0x80000000 0x5 0x80000000>; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + // filled via templated includes at the end of the file + }; +}; + +#define DIE +#define DIE_NO 0 + +&die0 { + #include "t6031-die0.dtsi" + #include "t6031-dieX.dtsi" +}; + +#include "t6031-pmgr.dtsi" +#include "t6031-gpio-pins.dtsi" + +#undef DIE +#undef DIE_NO + +#define DIE _die1 +#define DIE_NO 1 + +&die1 { + #include "t6031-dieX.dtsi" +}; + +#include "t6031-pmgr.dtsi" + +/delete-node/ &ps_pmp_die1; + +#undef DIE +#undef DIE_NO + +/* delete non-present DISP power-states */ +/delete-node/ &ps_disp_cpu; +/delete-node/ &ps_disp_cpu_die1; +/delete-node/ &ps_disp_fe; +/delete-node/ &ps_disp_fe_die1; +/delete-node/ &ps_disp_sys; +/delete-node/ &ps_disp_sys_die1; + +/* delete non-present ISP power-states */ +/delete-node/ &ps_dprx; +/delete-node/ &ps_dprx_die1; +/delete-node/ &ps_isp_be; +/delete-node/ &ps_isp_be_die1; +/delete-node/ &ps_isp_clr; +/delete-node/ &ps_isp_clr_die1; +/delete-node/ &ps_isp_cpu; +/delete-node/ &ps_isp_cpu_die1; +/delete-node/ &ps_isp_fe; +/delete-node/ &ps_isp_fe_die1; +/delete-node/ &ps_isp_secure; +/delete-node/ &ps_isp_secure_die1; +/delete-node/ &ps_isp_sys; +/delete-node/ &ps_isp_sys_die1; + +&ps_afi_d2d_0 { + status = "okay"; +}; + +&ps_afi_d2d_0_die1 { + status = "okay"; +}; + +&ps_afi_d2d_1 { + status = "okay"; +}; + +&ps_afi_d2d_1_die1 { + status = "okay"; +}; + +&ps_afc_d2d_0 { + status = "okay"; +}; + +&ps_afc_d2d_0_die1{ + status = "okay"; +}; + +&ps_afc_d2d_1 { + status = "okay"; +}; + +&ps_afc_d2d_1_die1 { + status = "okay"; +}; + +&ps_afr_d2d_0 { + status = "okay"; +}; + +&ps_afr_d2d_0_die1 { + status = "okay"; +}; + +&ps_afr_d2d_1 { + status = "okay"; +}; + +&ps_afr_d2d_1_die1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t6034-j514m.dts b/arch/arm64/boot/dts/apple/t6034-j514m.dts new file mode 100644 index 000000000000..e31bd0bc0592 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6034-j514m.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M3 Max, 14 CPU cores, Nov 2023) + * + * target-type: J514m + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6034.dtsi" +#include "t603x-j514-j516.dtsi" + +/ { + compatible = "apple,j514m", "apple,t6034", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M3 Max, 14 CPU cores, Nov 2023)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6034-j516m.dts b/arch/arm64/boot/dts/apple/t6034-j516m.dts new file mode 100644 index 000000000000..4d6513558597 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6034-j516m.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M3 Max, 14 CPU cores, Nov 2023) + * + * target-type: J516m + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6034.dtsi" +#include "t603x-j514-j516.dtsi" + +/ { + compatible = "apple,j516m", "apple,t6034", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M3 Max, 14 CPU cores, Nov 2023)"; +}; diff --git a/arch/arm64/boot/dts/apple/t6034.dtsi b/arch/arm64/boot/dts/apple/t6034.dtsi new file mode 100644 index 000000000000..ae8c27d7fa25 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6034.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6034 "M3 Max" SoC + * + * Copyright The Asahi Linux Contributors + */ + +#include "t6031.dtsi" + +/ { + compatible = "apple,t6034", "apple,arm-platform"; +}; + +// Disable power-states for memory channels not present on the 14-core variant. +&ps_amcc6 { + status = "disabled"; +}; + +&ps_amcc7 { + status = "disabled"; +}; + +&ps_dcs_24 { + status = "disabled"; +}; + +&ps_dcs_25 { + status = "disabled"; +}; + +&ps_dcs_26 { + status = "disabled"; +}; + +&ps_dcs_27 { + status = "disabled"; +}; + +&ps_dcs_28 { + status = "disabled"; +}; + +&ps_dcs_29 { + status = "disabled"; +}; + +&ps_dcs_30 { + status = "disabled"; +}; + +&ps_dcs_31 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi b/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi new file mode 100644 index 000000000000..517b84c183ca --- /dev/null +++ b/arch/arm64/boot/dts/apple/t603x-j514-j516.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14/16-inch, 2023) + * + * This file contains the parts common to J514 and J516 devices with t6030, + * t6031 and t6034. + * + * target-type: J514s / J514m / J514c / J516s / J516m / J516c + * + * Copyright The Asahi Linux Contributors + */ + +/* + * These models are essentially identical to the previous generations, other + * than the GPIO indices and using SPMI based USB Type-C port controllers. + */ + +#include + +/ { + chassis-type = "laptop"; + + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + power-domains = <&ps_disp_fe>; + }; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0 0x2 0>; /* To be filled by loader */ + }; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm0 0 40000>; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&fpwm0 { + status = "okay"; +}; From e81af013dbdd84c4e13f92c304eee555b1f9447a Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 24 Jul 2026 20:16:49 +0200 Subject: [PATCH 771/864] arm64: dts: apple: Initial T6030 (M3 Pro) device trees Minimal device trees for the M3 Pro based 14-inch and 16-inch MacBook Pro released in November 2023. The M3 Pro is a distinct SoC design and not a cut down version of the Max variant like for M1 and M2 Pro. The M3 Pro has only a single cluster with up to 6 performance cores and one cluster with 6 efficiency cores. While it no longer shares a common SoC .dtsi the devices itself are still similar to the ones with M3 Max. It is still useful to share the basic device composition in t603x-j514-j516.dtsi. For the M3 Pro based devices additional overrides for diverging pin and irq numbers are expected. The device trees have devices nodes for CPU cores, timer, interrupt controller, power states, watchdog, serial, pin controller, i2c, PWM based keyboard LED illumination and the boot framebuffer. Reviewed-by: Sven Peter Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/Makefile | 2 + arch/arm64/boot/dts/apple/t6030-j514s.dts | 22 + arch/arm64/boot/dts/apple/t6030-j516s.dts | 22 + arch/arm64/boot/dts/apple/t6030-pmgr.dtsi | 1437 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t6030.dtsi | 524 ++++++++ 5 files changed, 2007 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t6030-j514s.dts create mode 100644 arch/arm64/boot/dts/apple/t6030-j516s.dts create mode 100644 arch/arm64/boot/dts/apple/t6030-pmgr.dtsi create mode 100644 arch/arm64/boot/dts/apple/t6030.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index a22b4a8068b6..9fea43f760ec 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_APPLE) += t6021-j416c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6020-j474s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6021-j475c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6022-j475d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6030-j514s.dtb +dtb-$(CONFIG_ARCH_APPLE) += t6030-j516s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6031-j514c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6031-j516c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6032-j575d.dtb diff --git a/arch/arm64/boot/dts/apple/t6030-j514s.dts b/arch/arm64/boot/dts/apple/t6030-j514s.dts new file mode 100644 index 000000000000..3ba2c9ca4347 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6030-j514s.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (14-inch, M3 Pro, Nov 2023) + * + * target-type: J514s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6030.dtsi" +#include "t603x-j514-j516.dtsi" + +/ { + compatible = "apple,j514s", "apple,t6030", "apple,arm-platform"; + model = "Apple MacBook Pro (14-inch, M3 Pro, Nov 2023)"; +}; + +&framebuffer0 { + power-domains = <&ps_disp_cpu>; +}; diff --git a/arch/arm64/boot/dts/apple/t6030-j516s.dts b/arch/arm64/boot/dts/apple/t6030-j516s.dts new file mode 100644 index 000000000000..ab07bf7939ab --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6030-j516s.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * MacBook Pro (16-inch, M3 Pro, Nov 2023) + * + * target-type: J516s + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t6030.dtsi" +#include "t603x-j514-j516.dtsi" + +/ { + compatible = "apple,j516s", "apple,t6030", "apple,arm-platform"; + model = "Apple MacBook Pro (16-inch, M3 Pro, Nov 2023)"; +}; + +&framebuffer0 { + power-domains = <&ps_disp_cpu>; +}; diff --git a/arch/arm64/boot/dts/apple/t6030-pmgr.dtsi b/arch/arm64/boot/dts/apple/t6030-pmgr.dtsi new file mode 100644 index 000000000000..932388ea13c9 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6030-pmgr.dtsi @@ -0,0 +1,1437 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for Apple T6030 "M3 Pro" SoC + * + * Copyright The Asahi Linux Contributors + */ + +&pmgr_gfx { + ps_gpx: power-controller@0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpx"; + apple,always-on; + }; + + ps_afr: power-controller@100 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "afr"; + apple,always-on; + }; + + ps_gfx: power-controller@110 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + power-domains = <&ps_gpx>, <&ps_afr>; + }; +}; + +&pmgr { + ps_msg: power-controller@108 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msg"; + apple,always-on; + }; + + ps_aic: power-controller@110 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + }; + + ps_dwi: power-controller@118 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@120 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms_fpwm0: power-controller@138 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm0"; + }; + + ps_pms_fpwm1: power-controller@140 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm1"; + }; + + ps_pms_fpwm2: power-controller@148 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm2"; + }; + + ps_pms_fpwm3: power-controller@150 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm3"; + }; + + ps_pms_fpwm4: power-controller@158 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_fpwm4"; + }; + + ps_pms_c1ppt: power-controller@160 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_c1ppt"; + }; + + ps_soc_rc: power-controller@168 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_rc"; + }; + + ps_soc_dpe: power-controller@170 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_dpe"; + apple,always-on; + }; + + ps_pmgr_soc_ocla: power-controller@178 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmgr_soc_ocla"; + }; + + ps_ispsens0: power-controller@180 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_aft0: power-controller@190 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aft0"; + }; + + ps_ap_tmm: power-controller@1a8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ap_tmm"; + }; + + ps_sio: power-controller@1b8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + }; + + ps_disp_sys: power-controller@1c0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_sys"; + }; + + ps_jpg: power-controller@1c8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + }; + + ps_sio_cpu: power-controller@1d0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_cpu"; + power-domains = <&ps_sio>; + }; + + ps_fpwm0: power-controller@1d8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm0"; + power-domains = <&ps_sio>; + }; + + ps_fpwm1: power-controller@1e0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm1"; + power-domains = <&ps_sio>; + }; + + ps_fpwm2: power-controller@1e8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm2"; + power-domains = <&ps_sio>; + }; + + ps_i2c0: power-controller@1f0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio>; + }; + + ps_i2c1: power-controller@1f8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio>; + }; + + ps_i2c2: power-controller@200 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio>; + }; + + ps_i2c3: power-controller@208 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio>; + }; + + ps_i2c4: power-controller@210 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + power-domains = <&ps_sio>; + }; + + ps_i2c5: power-controller@218 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c5"; + power-domains = <&ps_sio>; + }; + + ps_i2c6: power-controller@220 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c6"; + power-domains = <&ps_sio>; + }; + + ps_i2c7: power-controller@228 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c7"; + power-domains = <&ps_sio>; + }; + + ps_i2c8: power-controller@230 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c8"; + power-domains = <&ps_sio>; + }; + + ps_spi_p: power-controller@238 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi_p"; + power-domains = <&ps_sio>; + }; + + ps_uart_p: power-controller@240 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_audio_p: power-controller@248 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "audio_p"; + power-domains = <&ps_sio>; + }; + + ps_aes: power-controller@250 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes"; + power-domains = <&ps_sio>; + }; + + ps_disp_fe: power-controller@258 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_fe"; + power-domains = <&ps_disp_sys>; + }; + + ps_spi0: power-controller@260 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_spi_p>; + }; + + ps_spi1: power-controller@268 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_spi_p>; + }; + + ps_spi2: power-controller@270 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_spi_p>; + }; + + ps_spi3: power-controller@278 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_spi_p>; + }; + + ps_spi4: power-controller@280 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_spi_p>; + }; + + ps_spi5: power-controller@288 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi5"; + power-domains = <&ps_spi_p>; + }; + + ps_qspi: power-controller@290 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "qspi"; + power-domains = <&ps_spi_p>; + }; + + ps_uart_n: power-controller@298 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_n"; + power-domains = <&ps_uart_p>; + }; + + ps_uart0: power-controller@2a0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + + ps_uart1: power-controller@2a8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@2b0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@2b8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_uart4: power-controller@2c0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_uart_p>; + }; + + ps_uart5: power-controller@2c8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_uart_p>; + }; + + ps_uart6: power-controller@2d0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_uart_p>; + }; + + ps_sio_adma: power-controller@2d8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_adma"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa0: power-controller@2e0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + apple,always-on; + power-domains = <&ps_audio_p>; + }; + + ps_dpa1: power-controller@2e8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + apple,always-on; + power-domains = <&ps_audio_p>; + }; + + ps_dpa2: power-controller@2f0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa2"; + apple,always-on; + power-domains = <&ps_audio_p>; + }; + + ps_dpa3: power-controller@2f8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa3"; + apple,always-on; + power-domains = <&ps_audio_p>; + }; + + ps_dpa4: power-controller@300 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa4"; + apple,always-on; + power-domains = <&ps_audio_p>; + }; + + ps_mca0: power-controller@308 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_dcs0: power-controller@320 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; + }; + + ps_dcs2: power-controller@328 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; + }; + + ps_dcs1: power-controller@330 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; + }; + + ps_dcs3: power-controller@338 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; + }; + + ps_dcs4: power-controller@340 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; + }; + + ps_dcs5: power-controller@348 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; + }; + + ps_dcs6: power-controller@358 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + apple,always-on; + }; + + ps_dcs7: power-controller@360 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + apple,always-on; + }; + + ps_dcs8: power-controller@368 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs8"; + apple,always-on; + }; + + ps_dcs9: power-controller@370 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs9"; + apple,always-on; + }; + + ps_dcs10: power-controller@378 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs10"; + apple,always-on; + }; + + ps_dcs11: power-controller@380 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs11"; + apple,always-on; + }; + + ps_mca1: power-controller@388 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca2: power-controller@390 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca3: power-controller@398 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_ioa1: power-controller@3a0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ioa1"; + apple,always-on; + }; + + ps_ls1: power-controller@3a8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ls1"; + apple,always-on; + power-domains = <&ps_ioa1>; + }; + + ps_lw10: power-controller@3b0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lw10"; + apple,always-on; + power-domains = <&ps_ls1>; + }; + + ps_dispext0_sys: power-controller@3b8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext0_sys"; + power-domains = <&ps_lw10>; + }; + + ps_dispext1_sys: power-controller@3c0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext1_sys"; + power-domains = <&ps_lw10>; + }; + + ps_isp_sys: power-controller@3c8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_lw10>; + }; + + ps_venc_sys: power-controller@3d0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_lw10>; + }; + + ps_dispext0_fe: power-controller@3d8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext0_fe"; + power-domains = <&ps_dispext0_sys>; + }; + + ps_dispext0_cpu: power-controller@3e0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext0_cpu"; + power-domains = <&ps_dispext0_fe>; + }; + + ps_trace_fab: power-controller@3e8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "trace_fab"; + }; + + ps_dispext1_fe: power-controller@3f0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext1_fe"; + power-domains = <&ps_dispext1_sys>; + }; + + ps_dispext1_cpu: power-controller@3f8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext1_cpu"; + power-domains = <&ps_dispext1_fe>; + }; + + ps_dptx_phy: power-controller@408 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dptx_phy"; + apple,always-on; + }; + + ps_avd_sys: power-controller@490 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x490 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + }; + + ps_ane_sys: power-controller@498 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x498 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys"; + }; + + ps_scodec: power-controller@4a0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "scodec"; + }; + + ps_scodec_stream: power-controller@4a8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "scodec_stream"; + power-domains = <&ps_scodec>; + }; + + ps_ioa3: power-controller@4b0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ioa3"; + apple,always-on; + }; + + ps_ls3: power-controller@4b8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ls3"; + apple,always-on; + power-domains = <&ps_ioa3>; + }; + + ps_lw30: power-controller@4c0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lw30"; + apple,always-on; + power-domains = <&ps_ls3>; + }; + + ps_pmp: power-controller@4c8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@4d0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_lw31: power-controller@4d8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lw31"; + apple,always-on; + power-domains = <&ps_ls3>; + }; + + ps_atc0_common: power-controller@4e0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_common"; + power-domains = <&ps_lw30>; + }; + + ps_atc1_common: power-controller@4e8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_common"; + power-domains = <&ps_lw30>; + }; + + ps_atc2_common: power-controller@4f0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_common"; + power-domains = <&ps_lw30>; + }; + + ps_atc3_common: power-controller@4f8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_common"; + power-domains = <&ps_lw30>; + }; + + ps_apcie_gp: power-controller@500 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x500 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_gp"; + power-domains = <&ps_lw31>; + }; + + ps_msr: power-controller@508 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x508 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_lw31>; + }; + + ps_ans: power-controller@510 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x510 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + power-domains = <&ps_lw31>; + }; + + ps_atc0_pcie: power-controller@518 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x518 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_pcie"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio: power-controller@520 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x520 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc1_pcie: power-controller@528 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x528 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_pcie"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio: power-controller@530 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x530 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc2_pcie: power-controller@538 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x538 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_pcie"; + power-domains = <&ps_atc2_common>; + }; + + ps_atc2_cio: power-controller@540 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x540 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_cio"; + power-domains = <&ps_atc2_common>; + }; + + ps_atc3_pcie: power-controller@548 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x548 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_pcie"; + power-domains = <&ps_atc3_common>; + }; + + ps_atc3_cio: power-controller@550 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x550 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_cio"; + power-domains = <&ps_atc3_common>; + }; + + ps_apcie_sys_gp: power-controller@558 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x558 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_sys_gp"; + power-domains = <&ps_apcie_gp>; + }; + + ps_msr_ase_core: power-controller@560 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x560 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr_ase_core"; + power-domains = <&ps_msr>; + }; + + ps_apcie_st: power-controller@568 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x568 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_st"; + power-domains = <&ps_ans>; + }; + + ps_atc0_cio_pcie: power-controller@570 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x570 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_pcie"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc0_cio_usb: power-controller@578 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x578 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_usb"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc1_cio_pcie: power-controller@580 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x580 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_pcie"; + power-domains = <&ps_atc1_cio>; + }; + + ps_atc1_cio_usb: power-controller@588 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x588 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_usb"; + power-domains = <&ps_atc1_cio>; + }; + + ps_atc2_cio_pcie: power-controller@590 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x590 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_cio_pcie"; + power-domains = <&ps_atc2_cio>; + }; + + ps_atc2_cio_usb: power-controller@598 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x598 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_cio_usb"; + power-domains = <&ps_atc2_cio>; + }; + + ps_atc3_cio_pcie: power-controller@5a0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_cio_pcie"; + power-domains = <&ps_atc3_cio>; + }; + + ps_atc3_cio_usb: power-controller@5a8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_cio_usb"; + power-domains = <&ps_atc3_cio>; + }; + + ps_apcie_sys_st: power-controller@5b0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_sys_st"; + power-domains = <&ps_apcie_st>, <&ps_ans>; + }; + + ps_apcie_phy_sw: power-controller@5b8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x5b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_phy_sw"; + apple,always-on; /* macOS does not turn this off */ + }; + + ps_sep: power-controller@c00 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; + }; + + ps_isp_cpu: power-controller@4000 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_cpu"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_fe: power-controller@4008 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_fe"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@4010 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_fe>; + }; + + ps_isp_secure: power-controller@4018 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_secure"; + power-domains = <&ps_isp_fe>; + }; + + ps_isp_be: power-controller@4020 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_fe>; + }; + + ps_isp_clr: power-controller@4028 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x4028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_clr"; + power-domains = <&ps_isp_be>; + }; + + ps_venc_dma: power-controller@8000 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe4: power-controller@8008 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_pipe5: power-controller@8010 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me0: power-controller@8018 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me1: power-controller@8020 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc_me0>; + }; + + ps_disp_cpu: power-controller@10000 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x10000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_cpu"; + power-domains = <&ps_disp_fe>; + apple,min-state = <4>; + }; +}; + +&pmgr_mini { + ps_debug_gated: power-controller@0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_gated"; + apple,always-on; + }; + + ps_nub_spmi0: power-controller@58 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi0"; + apple,always-on; + }; + + ps_nub_spmi1: power-controller@60 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi1"; + apple,always-on; + }; + + ps_nub_spmi2: power-controller@68 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi2"; + apple,always-on; + }; + + ps_nub_spmi_a0: power-controller@70 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi_a0"; + apple,always-on; + }; + + ps_nub_spmi_a1: power-controller@78 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi_a1"; + apple,always-on; + }; + + ps_nub_spi0: power-controller@88 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spi0"; + apple,always-on; + }; + + ps_nub_ocla: power-controller@90 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_ocla"; + apple,always-on; + }; + + ps_nub_gpio: power-controller@98 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_gpio"; + apple,always-on; + }; + + ps_nub_sram: power-controller@a8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; + }; + + ps_debug_switch: power-controller@b0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_switch"; + apple,always-on; + }; + + ps_atc0_usb_aon: power-controller@b8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb_aon"; + }; + + ps_atc1_usb_aon: power-controller@c0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb_aon"; + }; + + ps_atc2_usb_aon: power-controller@c8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xc8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_usb_aon"; + }; + + ps_atc3_usb_aon: power-controller@d0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_usb_aon"; + }; + + ps_atc0_usb: power-controller@d8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xd8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb"; + power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + ps_atc1_usb: power-controller@e0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb"; + power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; + + ps_atc2_usb: power-controller@e8 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xe8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc2_usb"; + power-domains = <&ps_atc2_usb_aon>, <&ps_atc2_common>; + }; + + ps_atc3_usb: power-controller@f0 { + compatible = "apple,t6030-pmgr-pwrstate", "apple,t8103-pmgr-pwrstate"; + reg = <0xf0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc3_usb"; + power-domains = <&ps_atc3_usb_aon>, <&ps_atc3_common>; + }; +}; + diff --git a/arch/arm64/boot/dts/apple/t6030.dtsi b/arch/arm64/boot/dts/apple/t6030.dtsi new file mode 100644 index 000000000000..dda9568af11f --- /dev/null +++ b/arch/arm64/boot/dts/apple/t6030.dtsi @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T6030 "M3 Pro" SoC + * + * Other names: H15J, "Lobos" + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e00>; + }; + core1 { + cpu = <&cpu_e01>; + }; + core2 { + cpu = <&cpu_e02>; + }; + core3 { + cpu = <&cpu_e03>; + }; + core4 { + cpu = <&cpu_e04>; + }; + core5 { + cpu = <&cpu_e05>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p00>; + }; + core1 { + cpu = <&cpu_p01>; + }; + core2 { + cpu = <&cpu_p02>; + }; + core3 { + cpu = <&cpu_p03>; + }; + core4 { + cpu = <&cpu_p04>; + }; + core5 { + cpu = <&cpu_p05>; + }; + }; + }; + + cpu_e00: cpu@0 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e01: cpu@1 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e02: cpu@2 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e03: cpu@3 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e04: cpu@4 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x4>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e05: cpu@5 { + compatible = "apple,sawtooth"; + device_type = "cpu"; + reg = <0x0 0x5>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* to be filled by loader */ + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_p00: cpu@10100 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p01: cpu@10101 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p02: cpu@10102 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p03: cpu@10103 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p04: cpu@10104 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10104>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p05: cpu@10105 { + compatible = "apple,everest"; + device_type = "cpu"; + reg = <0x0 0x10105>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = , + , + , + ; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + /* Required to get >32-bit DMA via DARTs */ + dma-ranges = <0 0 0 0 0xffffffff 0xffffc000>; + + i2c1: i2c@289014000 { + compatible = "apple,t6030-i2c", "apple,t8103-i2c"; + reg = <0x2 0x89014000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c1>; + status = "disabled"; + }; + + i2c2: i2c@289018000 { + compatible = "apple,t6030-i2c", "apple,t8103-i2c"; + reg = <0x2 0x89018000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c2>; + status = "disabled"; + }; + + i2c3: i2c@28901c000 { + compatible = "apple,t6030-i2c", "apple,t8103-i2c"; + reg = <0x2 0x8901c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c3>; + status = "disabled"; + }; + + i2c4: i2c@289020000 { + compatible = "apple,t6030-i2c", "apple,t8103-i2c"; + reg = <0x2 0x89020000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c4>; + status = "disabled"; + }; + + i2c6: i2c@289028000 { + compatible = "apple,t6030-i2c", "apple,t8103-i2c"; + reg = <0x2 0x89028000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c6>; + status = "disabled"; + }; + + i2c8: i2c@289030000 { + compatible = "apple,t6030-i2c", "apple,t8103-i2c"; + reg = <0x2 0x89030000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c8>; + status = "disabled"; + }; + + fpwm0: pwm@289040000 { + compatible = "apple,t6030-fpwm", "apple,s5l-fpwm"; + reg = <0x2 0x89040000 0x0 0x4000>; + power-domains = <&ps_fpwm0>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + + serial0: serial@289200000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x89200000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + pmgr_gfx: power-management@290e80000 { + compatible = "apple,t6030-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x90e80000 0 0x4000>; + /* child nodes are added in t6030-pmgr.dtsi */ + }; + + pinctrl_ap: pinctrl@347100000 { + compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; + reg = <0x3 0x47100000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 224>; + apple,npins = <224>; + + interrupt-controller; + #interrupt-cells = <2>; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + + i2c6_pins: i2c6-pins { + pinmux = , + ; + }; + + i2c8_pins: i2c8-pins { + pinmux = , + ; + }; + }; + + pmgr: power-management@350700000 { + compatible = "apple,t6030-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x3 0x50700000 0 0x14000>; + /* child nodes are added in t6030-pmgr.dtsi */ + }; + + aic: interrupt-controller@351000000 { + compatible = "apple,t6030-aic3", "apple,t8122-aic3"; + #interrupt-cells = <3>; + interrupt-controller; + + reg = <0x3 0x51000000 0x0 0x184000>, + <0x3 0x51040000 0x0 0x4000>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + }; + + pinctrl_nub: pinctrl@3641f0000 { + compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; + reg = <0x3 0x641f0000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 37>; + apple,npins = <37>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmgr_mini: power-management@364280000 { + compatible = "apple,t6030-pmgr", "apple,t8103-pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x3 0x64280000 0 0x4000>; + /* child nodes are added in t6030-pmgr.dtsi */ + }; + + wdt: watchdog@3642b0000 { + compatible = "apple,t6030-wdt", "apple,t8103-wdt"; + reg = <0x3 0x642b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pinctrl_smc: pinctrl@36c820000 { + compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; + reg = <0x3 0x6c820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 18>; + apple,npins = <18>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@374824000 { + compatible = "apple,t6030-pinctrl", "apple,t8103-pinctrl"; + reg = <0x3 0x74824000 0x0 0x4000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + clocks = <&clkref>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 54>; + apple,npins = <54>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "t6030-pmgr.dtsi" From 1a17f391c139567e2fac6894c6b43f5978e915c8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:02:48 +0200 Subject: [PATCH 772/864] ARM: dts: rockchip: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801210247.383632-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3188-radxarock.dts | 2 +- arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts | 2 +- arch/arm/boot/dts/rockchip/rk3288-evb.dtsi | 2 +- arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi | 2 +- arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi | 2 +- arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts | 2 +- arch/arm/boot/dts/rockchip/rv1126.dtsi | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts index 1f31c0a6774f..7ebbf9b932e1 100644 --- a/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rockchip/rk3188-radxarock.dts @@ -324,7 +324,7 @@ rtc_int: rtc-int { }; }; - lan8720a { + lan8720a { phy_int: phy-int { rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts index e1821fadbe7a..fb581b505101 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rockchip/rk3288-evb-act8846.dts @@ -175,7 +175,7 @@ &panel { &pinctrl { lcd { - lcd_en: lcd-en { + lcd_en: lcd-en { rockchip,pins = <7 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi b/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi index 11bb970c6112..ffa5a1257341 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-evb.dtsi @@ -40,7 +40,7 @@ button-esc { press-threshold-microvolt = <1000000>; }; - button-home { + button-home { label = "Home"; linux,code = ; press-threshold-microvolt = <1300000>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi index 59029483741b..e68bf31e816a 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly-reload-core.dtsi @@ -150,7 +150,7 @@ vdd10_lcd: REG6 { regulator-always-on; }; - vcca_18: REG7 { + vcca_18: REG7 { regulator-name = "vcca_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi b/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi index 187d4f0a52eb..13060a9ecbb6 100644 --- a/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288-firefly.dtsi @@ -79,7 +79,7 @@ power_led: led-1 { }; }; - vbat_wl: vcc_sys: regulator-vsys { + vbat_wl: vcc_sys: regulator-vsys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts index c6472f933aa5..b9ec812b4a86 100644 --- a/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts +++ b/arch/arm/boot/dts/rockchip/rv1103b-omega4-evb.dts @@ -26,7 +26,7 @@ chosen { leds { compatible = "gpio-leds"; - led-0 { + led-0 { color = ; default-state = "on"; function = LED_FUNCTION_STATUS; diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index d0cdc5f74212..74f238e13533 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -717,7 +717,7 @@ sdio: mmc@ffc70000 { status = "disabled"; }; - sfc: spi@ffc90000 { + sfc: spi@ffc90000 { compatible = "rockchip,sfc"; reg = <0xffc90000 0x4000>; interrupts = ; From 49ee9e9a51b85113b741bf97d9131d0416316f04 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:02:49 +0200 Subject: [PATCH 773/864] arm64: dts: rockchip: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801210247.383632-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts index 5e7181948992..74be8bcad7a9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts @@ -156,7 +156,7 @@ &pinctrl { pinctrl-0 = <&rtc_32k>; ir-receiver { - ir_recv_pin: ir-recv-pin { + ir_recv_pin: ir-recv-pin { rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts index 70979079923c..60ea9ff7fd75 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts @@ -85,7 +85,7 @@ simple-audio-card,cpu { }; }; - sgtl5000_clk: sgtl5000-oscillator { + sgtl5000_clk: sgtl5000-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts b/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts index b57bf7bf10f5..b17c7a43d54d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-onething-edge-cube.dts @@ -310,7 +310,7 @@ &usb_host1_ohci { status = "okay"; }; -&usb_host1_xhci { +&usb_host1_xhci { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts index 873fbeb8daa1..935c40c5a9ba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts @@ -90,7 +90,7 @@ simple-audio-card,cpu { }; }; - sgtl5000_clk: sgtl5000-oscillator { + sgtl5000_clk: sgtl5000-oscillator { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; From 264429dfe5294b76c7c3b4ed2c9e6cea1042255c Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 28 Jul 2026 17:55:40 -0500 Subject: [PATCH 774/864] arm64: dts: rockchip: Add icm42607p IMU for RG-DS Add the Invensense ICM42607P IMU for the Anbernic RG-DS. Mount-matrix was tested with iio-sensor-proxy and reports correct orientation. Signed-off-by: Chris Morgan Link: https://patch.msgid.link/20260728225542.174825-10-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts index 8d906ab02c5f..b770bfd5268d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts @@ -871,7 +871,13 @@ aw87391_pa_r: audio-codec@5b { sound-name-prefix = "Right Amp"; }; - /* invensense,icm42607p at 0x68 */ + icm42607p: imu@68 { + compatible = "invensense,icm42607p"; + reg = <0x68>; + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; }; &i2c3 { From 50208eafca2b1187079c0c5c54e5cf804c0ce0d1 Mon Sep 17 00:00:00 2001 From: Hrushiraj Gandhi Date: Thu, 30 Jul 2026 10:29:46 +0530 Subject: [PATCH 775/864] dt-bindings: arm: rockchip: Add Vicharak Vaaman board Document the compatible string for the Vicharak Vaaman, an RK3399-based single-board computer. Signed-off-by: Hrushiraj Gandhi Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260730045947.388660-2-hrushirajg23@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 93e7cba943fa..9c3e24d471c1 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1345,6 +1345,11 @@ properties: - const: vicharak,axon - const: rockchip,rk3588 + - description: Vicharak Vaaman + items: + - const: vicharak,vaaman + - const: rockchip,rk3399 + - description: Vicharak Vaaman2 items: - const: vicharak,vaaman2 From c0fe7b7226942eb4e405d3dd08671510510463f1 Mon Sep 17 00:00:00 2001 From: Hrushiraj Gandhi Date: Thu, 30 Jul 2026 10:29:47 +0530 Subject: [PATCH 776/864] arm64: dts: rockchip: Add Vicharak Vaaman board Add initial devicetree support for the Vicharak Vaaman, an RK3399-based single-board computer. Supported peripherals: - RK808 PMIC with core/logic/IO regulators - SYR827/SYR828 (vdd_cpu_b/vdd_gpu) CPU-big and GPU regulators - Mali GPU - Gigabit Ethernet (RGMII, RTL8211E PHY via &gmac with mdio subnode) - eMMC (HS400, enhanced strobe) - microSD card slot - SARADC and TSADC - PWM-based vdd_log regulator - UART2 serial console Signed-off-by: Hrushiraj Gandhi Link: https://patch.msgid.link/20260730045947.388660-3-hrushirajg23@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3399-vicharak-vaaman.dts | 458 ++++++++++++++++++ 2 files changed, 459 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-vicharak-vaaman.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 28cd17170e37..127517356dc8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -90,6 +90,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-screen.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-vicharak-vaaman.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-armsom-sige1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-h28k.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3399-vicharak-vaaman.dts b/arch/arm64/boot/dts/rockchip/rk3399-vicharak-vaaman.dts new file mode 100644 index 000000000000..e7bc8f2f12d2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-vicharak-vaaman.dts @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Vicharak Computers Pvt Ltd + */ + +/dts-v1/; +#include "rk3399.dtsi" + +/ { + model = "Vicharak Vaaman"; + compatible = "vicharak,vaaman", "rockchip,rk3399"; + + aliases { + ethernet0 = &gmac; + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc12v_dcin: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_lan: regulator-vcc3v3-lan { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vdd_log: regulator-vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + rockchip,enable-strobe-pulldown; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_lan>; + phy-mode = "rgmii"; + phy-handle = <&rtl8211e>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rstb>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_cam: SWITCH_REG1 { + regulator-name = "vcc_cam"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: SWITCH_REG2 { + regulator-name = "vcc_mipi"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pinctrl { + gmac { + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + max-frequency = <150000000>; + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; From 2b009df2afd0874080a1e2a893df5e4db39cc1c5 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 11 Jul 2026 14:28:27 -0500 Subject: [PATCH 777/864] dt-bindings: arm: rockchip: Add LincStation E1 LincStation E1 is an entry-level NAS device powered by the RK3568B2 SoC with two 3.5" HDD slots and two m.2 2280 slots for SSDs. It is marketed under the LincPlus[1] brand, but the OEM appears to be Techvision Intelligent Technology Co., Ltd[2]. The OEM model number is TVD8322R, which is referenced by the vendor devicetree, a sticker on the board, and a design patent (CN309443154S) matching the system chassis. Link: https://www.lincplustech.com/products/lincstation-e1-network-attached-storage.html [1] Link: https://cn.techvision.com.cn [2] Signed-off-by: Samuel Holland Acked-by: Conor Dooley Link: https://patch.msgid.link/20260711192842.845048-4-samuel@sholland.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 9c3e24d471c1..4454fff7d4bd 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -813,6 +813,11 @@ properties: - const: lckfb,tspi-3m-rk3576 - const: rockchip,rk3576 + - description: LincPlus LincStation E1 + items: + - const: techvision,tvd8322r + - const: rockchip,rk3568 + - description: LinkEase EasePi R1 items: - const: linkease,easepi-r1 From 0f4c49bb3e538d01bdec403052ba6c35858aa0cf Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 11 Jul 2026 14:28:28 -0500 Subject: [PATCH 778/864] arm64: dts: rockchip: Add LincStation E1 LincStation E1 is an entry-level NAS device powered by the RK3568B2 SoC with two 3.5" HDD slots (behind a SATA port multiplier) and two m.2 2280 slots for SSDs (each PCIe 3.0 x1). Other major features include: - 4 GiB DRAM / 64 GB eMMC - RTL8125 2.5 Gb Ethernet - Fn-Link 6222B-SRC Wi-Fi 5 / Bluetooth module - 1 USB 5 Gbps + 2 USB high speed ports - HDMI output Each HDD slot provides a GPIO input for disk presence detection and an output for power control. Since the disks are behind a port multiplier, there is no way to describe them in the devicetree, so the disk power is enabled at all times by GPIO hogs, and the detection inputs are used only as LED triggers. The board contains several pairs of amber/white LEDs for power, disk, m.2 slot, and network status. These are configured to use triggers when possible. The PWM fan uses a relatively aggressive fan curve to keep the hard disks within a safe temperature range. It may benefit from further tuning. The pinhole reset button is multiplexed between the SoC reset pin and an ADC input. The mux is configured here to drive the SoC reset pin, as this works reliably without polling by software. The adc-keys description is included for use by a devicetree overlay if desired. Signed-off-by: Samuel Holland Link: https://patch.msgid.link/20260711192842.845048-5-samuel@sholland.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-lincstation-e1.dts | 1000 +++++++++++++++++ 2 files changed, 1001 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 127517356dc8..e7936a21c118 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -149,6 +149,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-graperain-g3568-v2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lincstation-e1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts b/arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts new file mode 100644 index 000000000000..d6fed197099d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts @@ -0,0 +1,1000 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "rk3568.dtsi" + +/ { + model = "LincPlus LincStation E1"; + compatible = "techvision,tvd8322r", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc1; + rtc0 = &hym8563; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + /* This device is only available when reset-button-mux is driven high */ + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 5>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + status = "disabled"; + + button-reset { + label = "reset"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_leds &sata1_detect &sata2_detect>; + + led-2 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-4 { + color = ; + function = "m1"; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + color = ; + function = "m1"; + gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + color = ; + function = "m2"; + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + led-7 { + color = ; + function = "m2"; + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + color = ; + function = "s1"; + gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + + led-9 { + color = ; + function = "s1"; + gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + trigger-sources = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + }; + + led-a { + color = ; + function = "s2"; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + }; + + led-b { + color = ; + function = "s2"; + gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "gpio"; + trigger-sources = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + interrupt-parent = <&gpio0>; + interrupts = ; + #cooling-cells = <2>; + cooling-levels = <0 20 50 90 130 170 210 225 240 255>; + fan-supply = <&vcc12v0_sys>; + fan-stop-to-start-percent = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&fan_tach>; + pulses-per-revolution = <2>; + pwms = <&pwm0 0 50000 0>; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STANDBY; + max-brightness = <255>; + pwms = <&pwm4 0 25000 0>; + }; + + led-1 { + color = ; + default-brightness = <127>; + default-state = "on"; + function = LED_FUNCTION_POWER; + max-brightness = <255>; + pwms = <&pwm5 0 25000 0>; + }; + }; + + dc_12v: regulator-dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc12v0_sys: regulator-vcc12v0-sys { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc12v0_sys_en>; + regulator-name = "vcc12v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_lan: regulator-vcc3v3-lan { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_lan_en>; + regulator-name = "vcc3v3_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en>; + off-on-delay-us = <500000>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sata: regulator-vcc5v0-sata { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_sata_en>; + regulator-name = "vcc5v0_sata"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc_wl: regulator-vcc-wl { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_wl_en>; + regulator-name = "vcc_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_wl: regulator-vccio-wl { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vccio_wl_en>; + regulator-name = "vccio_wl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +/* + * The fan pulls hot air from the CPU and m.2 slot heat sinks and blows it + * across the hard disks. To keep the disks from overheating (below 50 °C), + * their ambient air, and thus the CPU heat sink, must be kept quite cool. + */ +&cpu_thermal { + trips { + sys_fan1: sys-fan1 { + hysteresis = <2000>; + temperature = <25000>; + type = "active"; + }; + + sys_fan2: sys-fan2 { + hysteresis = <2000>; + temperature = <35000>; + type = "active"; + }; + + sys_fan3: sys-fan3 { + hysteresis = <2000>; + temperature = <45000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + cooling-device = <&fan 1 3>; + trip = <&sys_fan1>; + }; + + map2 { + cooling-device = <&fan 4 5>; + trip = <&sys_fan2>; + }; + + map3 { + cooling-device = <&fan 6 THERMAL_NO_LIMIT>; + trip = <&sys_fan3>; + }; + }; +}; + +&gpio1 { + /* ata1.01 is the slot labeled HDD2 */ + sata1-power-control-hog { + gpio-hog; + gpios = ; + line-name = "sata1-power-control"; + output-high; + }; +}; + +&gpio2 { + /* ata1.02 is the slot labeled HDD1 */ + sata2-power-control-hog { + gpio-hog; + gpios = ; + line-name = "sata2-power-control"; + output-high; + }; +}; + +&gpio4 { + /* low = SoC reset, high = saradc input */ + reset-button-mux-hog { + gpio-hog; + gpios = ; + line-name = "reset-button-mux"; + output-low; + }; + + sata-pm-reset-hog { + gpio-hog; + gpios = ; + line-name = "sata-pm-reset"; + output-low; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2x1_rst>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_lan>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_device_wake_h: bt-device-wake-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_h: bt-host-wake-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gpio-leds { + gpio_leds: gpio-leds { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2x1_rst: pcie2x1-rst { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_lan_en: vcc3v3-lan-en { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pwm-fan { + fan_tach: fan-tach { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc12v0_sys_en: vcc12v0-sys-en { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + sata1_detect: sata1-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sata2_detect: sata2-detect { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_sata_en: vcc5v0-sata-en { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wlan { + vcc_wl_en: vcc-wl-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vccio_wl_en: vccio-wl-en { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_h: wifi-host-wake-h { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "disabled"; +}; + +&sata1 { + target-supply = <&vcc5v0_sata>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <208000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vccio_wl>; + status = "okay"; + + rtl8822cs: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_h>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_device_wake_h &bt_enable_h &bt_host_wake_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From e8fbbca94db752ab94d9dadf2f65872905eafecd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 21 Jul 2026 19:11:27 +0200 Subject: [PATCH 779/864] arm64: dts: qcom: glymur: Add Asus Zenbook A16 (UX3607OA) UX3607OA is a variant of the Asus Zenbook A16 built on the Qualcomm Glymur platform. It comes with an 18-core X2 Elite Extreme SoC, 48GiB of RAM, NVMe storage, a 2880 x 1800 OLED screen, and the other typical Glymur platform capabilities. The hardware wiring is very different versus the 14" SKU - the larger one is based on the System-In-Package reference design, unlike the smaller one, which derives from a more common Chip-On-Board base. Currently working: - Audio playback (4 speakers) - GPU, Display - HDMI port - Keyboard, touchpad, lid switch - Privacy LEDs (camera-use, camera-block, mic-mute) - Charging, Type-C, Type-A port - Onboard SD Card slot (RTS5329) - Wi-Fi, Bluetooth (QCC2072) - Touchscreen should work on the SKUs that have it, but it remains untested due to lack of access to such a device Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260721-topic-a16_submission-v1-2-8ea213130d05@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../qcom/glymur-asus-zenbook-a16-ux3607oa.dts | 1269 +++++++++++++++++ arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi | 2 +- 4 files changed, 1272 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e05414290d8e..1c86e7e98f55 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096sg-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += eliza-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += glymur-asus-zenbook-a16-ux3607oa.dtb dtb-$(CONFIG_ARCH_QCOM) += glymur-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += hamoa-iot-evk.dtb diff --git a/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts new file mode 100644 index 000000000000..939e1a927a79 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-asus-zenbook-a16-ux3607oa.dts @@ -0,0 +1,1269 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "glymur.dtsi" + +#include "pmcx0102.dtsi" +#include "pmh0101.dtsi" +#include "pmh0110-glymur.dtsi" +#include "pmh0104-glymur.dtsi" +#include "pmk8850.dtsi" +#include "smb2370.dtsi" + +#include +#include +#include +#include + +/delete-node/ &pmh0104_l_e1; +/delete-node/ &pmh0104_l1_thermal; +/delete-node/ &pmh0110_h_e0; +/delete-node/ &pmh0110_h0_thermal; + +/ { + compatible = "asus,zenbook-a16-ux3607oa", "qcom,glymur"; + model = "ASUS Zenbook A16 (UX3607OA)"; + + aliases { + i2c0 = &i2c0; + i2c5 = &i2c5; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c13 = &i2c13; + i2c19 = &i2c19; + + serial0 = &uart21; + serial1 = &uart14; + }; + + chosen { + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + label = "lid"; + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&usb2_dp_hot_plug_detect>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint = <&usb_2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&cam_indicator_en>, + <&keyboard_cam_led>, + <&keyboard_mic_led>; + pinctrl-names = "default"; + + keyboard-camera-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + + keyboard-mic-led { + function = LED_FUNCTION_MICMUTE; + color = ; + gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + default-state = "off"; + panic-indicator; + }; + + privacy-led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 111 GPIO_ACTIVE_HIGH>; + default-state = "off"; + panic-indicator; + }; + }; + + pmic-glink { + compatible = "qcom,glymur-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + /* Left side display-adjacent port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + }; + }; + + /* Left side user-adjacent port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + }; + }; + }; + + vreg_edp: regulator-edp { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_pwr_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_misc_3p3: regulator-misc-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_MISC_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0110_f_e0_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&misc_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,glymur-sndcard"; + model = "GLYMUR-ASUS-Zenbook-A16-UX3607OA"; + + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK1 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wlan-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_wcn_3p3>; + vpcie1v8-supply = <&vreg_l15b_e0>; + + w-disable1-gpios = <&tlmm 117 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie4_port0_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart14_ep>; + }; + }; + }; + }; +}; + +&apps_rsc { + /* PMCX0104 */ + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_l1b_e0: ldo1 { + regulator-name = "vreg_l1b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + /* Unused */ + vreg_l2b_e0: ldo2 { + regulator-name = "vreg_l2b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_l6b_e0: ldo6 { + regulator-name = "vreg_l6b_e0"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l7b_e0: ldo7 { + regulator-name = "vreg_l7b_e0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l8b_e0: ldo8 { + regulator-name = "vreg_l8b_e0"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + /* Unused */ + vreg_l9b_e0: ldo9 { + regulator-name = "vreg_l9b_e0"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + }; + + vreg_l10b_e0: ldo10 { + regulator-name = "vreg_l10b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b_e0: ldo11 { + regulator-name = "vreg_l11b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + /* Unused */ + vreg_l12b_e0: ldo12 { + regulator-name = "vreg_l12b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l15b_e0: ldo15 { + regulator-name = "vreg_l15b_e0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + /* Provides reference voltage for many undescribed components */ + regulator-always-on; + }; + + /* Unused */ + vreg_l17b_e0: ldo17 { + regulator-name = "vreg_l17b_e0"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + }; + + vreg_l18b_e0: ldo18 { + regulator-name = "vreg_l18b_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + + /* Provides reference voltage for many undescribed components */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E0"; + + vreg_l1c_e0: ldo1 { + regulator-name = "vreg_l1c_e0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e0: ldo2 { + regulator-name = "vreg_l2c_e0"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e0: ldo4 { + regulator-name = "vreg_l4c_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + /* PMCX0101 */ + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s7f_e0: smps7 { + regulator-name = "vreg_s7f_e0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_s8f_e0: smps8 { + regulator-name = "vreg_s8f_e0"; + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e0: ldo2 { + regulator-name = "vreg_l2f_e0"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + }; + + vreg_l3f_e0: ldo3 { + regulator-name = "vreg_l3f_e0"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmcx0102-rpmh-regulators"; + qcom,pmic-id = "C_E1"; + + vreg_l1c_e1: ldo1 { + regulator-name = "vreg_l1c_e1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2c_e1: ldo2 { + regulator-name = "vreg_l2c_e1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3c_e1: ldo3 { + regulator-name = "vreg_l3c_e1"; + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + }; + + vreg_l4c_e1: ldo4 { + regulator-name = "vreg_l4c_e1"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + /* PMCX0101 */ + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E1"; + + vreg_l1f_e1: ldo1 { + regulator-name = "vreg_l1f_e1"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l2f_e1: ldo2 { + regulator-name = "vreg_l2f_e1"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4f_e1: ldo4 { + regulator-name = "vreg_l4f_e1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + /* 2808:0219 */ + touchpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + ptn3222_1: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0>; + vdd1v8-supply = <&vreg_l15b_e0>; + + #phy-cells = <0>; + }; + + ptn3222_0: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply = <&vreg_l8b_e0>; + vdd1v8-supply = <&vreg_l15b_e0>; + + #phy-cells = <0>; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + + status = "okay"; + + touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + /* EC subdevice @ 0x5b */ + /* EC @ 0x76 */ +}; + +&i2c10 { + clock-frequency = <400000>; + + status = "okay"; + + /* ASUSTek 0B05:4543 */ + hid@17 { + compatible = "hid-over-i2c"; + reg = <0x17>; + interrupts-extended = <&tlmm 43 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x1>; + wakeup-source; + + pinctrl-0 = <&hid_int_a_default>; + pinctrl-names = "default"; + }; +}; + +&i2c13 { + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c19 { + clock-frequency = <400000>; + + status = "okay"; + + /* ASUSTek 0B05:4B42 */ + keyboard@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + wakeup-source; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + }; +}; + +&pmh0110_f_e0_gpios { + misc_3p3_reg_en: misc-3p3-reg-en-state { + pins = "gpio6"; + function = "normal"; + bias-disable; + input-disable; + output-enable; + drive-push-pull; + power-source = <1>; /* 1.8 V */ + qcom,drive-strength = ; + }; +}; + +&lpass_vamacro { + vdd-micb-supply = <&vreg_l1b_e0>; + + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "samsung,atna33xc20"; + enable-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; +}; + +&mdss_dp3_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l2f_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie4 { + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l1c_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + +&pcie4_port0_ep { + remote-endpoint = <&m2_e_pcie_ep>; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + + status = "okay"; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&pmk8850_rtc { + qcom,uefi-rtc-info; + qcom,no-alarm; +}; + +&remoteproc_adsp { + firmware-name = "qcom/glymur/ASUSTeK/UX3607OA/qcadsp8480.mbn", + "qcom/glymur/ASUSTeK/UX3607OA/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/glymur/ASUSTeK/UX3607OA/qccdsp8480.mbn", + "qcom/glymur/ASUSTeK/UX3607OA/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_soccp { + firmware-name = "qcom/glymur/ASUSTeK/UX3607OA/soccp.mbn", + "qcom/glymur/ASUSTeK/UX3607OA/soccp_dtb.mbn"; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply = <&vreg_l15b_e0>; + vdd3-supply = <&vreg_l7b_e0>; +}; + +&swr0 { + status = "okay"; + + /* WSA8845, left woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, left tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&swr3 { + status = "okay"; + + /* WSA8845, right woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <1 2 3 7 12 14>; + }; + + /* WSA8845, right tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_e0>; + vdd-io-supply = <&vreg_l18b_e0>; + qcom,port-mapping = <4 5 6 7 13 15>; + }; +}; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrpt3-0p9-supply = <&vreg_l2c_e0>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2c_e0>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1>; + vdda-qrefrx4-0p9-supply = <&vreg_l2c_e0>; + vdda-qrefrx5-0p9-supply = <&vreg_l3f_e0>; + vdda-qreftx0-0p9-supply = <&vreg_l3f_e0>; + vdda-qreftx0-1p2-supply = <&vreg_l4c_e0>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1>; + vdda-refgen3-0p9-supply = <&vreg_l2f_e0>; + vdda-refgen3-1p2-supply = <&vreg_l4c_e0>; + vdda-refgen4-0p9-supply = <&vreg_l1f_e1>; + vdda-refgen4-1p2-supply = <&vreg_l4f_e1>; +}; + +&tlmm { + gpio-reserved-ranges = <4 4>, /* EC Secure I3C */ + <10 2>, /* OOB UART */ + <44 4>, /* TPM */ + <65 1>, /* EC reset */ + <90 1>; /* TPM */ + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + edp_bl_en: edp-bl-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hid_int_a_default: hid-int-a-default-state { + pins = "gpio43"; + function = "gpio"; + bias-disable; + }; + + ts_default: ts-default-state { + reset-n-pins { + pins = "gpio48"; + function = "gpio"; + bias-disable; + }; + + int-pins { + pins = "gpio51"; + function = "gpio"; + bias-disable; + }; + }; + + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + edp_pwr_en: edp-pwr-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + keyboard_mic_led: keyboard-mic-led-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp0_hpd_default: edp0-hpd-default-state { + pins = "gpio119"; + function = "edp0_hot"; + bias-disable; + }; + + keyboard_cam_led: keyboard-cam-led-state { + pins = "gpio120"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + usb2_dp_hot_plug_detect: usb2-dp-hot-plug-detect-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&uart14 { + status = "okay"; + + port { + uart14_ep: endpoint { + remote-endpoint = <&m2_e_uart_ep>; + }; + }; +}; + +&uart21 { + status = "okay"; +}; + +&usb_0 { + status = "okay"; +}; + +&usb_0_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_0_hsphy { + vdd-supply = <&vreg_l3f_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&smb2370_j_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_0_qmpphy { + vdda-phy-supply = <&vreg_l3f_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l2f_e0>; + + status = "okay"; +}; + +&usb_0_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in1>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l3f_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&smb2370_k_e2_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l1c_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l2f_e0>; + + status = "okay"; +}; + +&usb_1_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in1>; +}; + +&usb_2_qmpphy { + vdda-phy-supply = <&vreg_l4c_e1>; + vdda-pll-supply = <&vreg_l4f_e1>; + refgen-supply = <&vreg_l4f_e1>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_in>; + }; + }; + }; +}; + +&usb_mp { + status = "okay"; +}; + +/* MP0 (eUSB3 + USBSS3) -> Type-A port */ +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2c_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&ptn3222_0>; + + status = "okay"; +}; + +/* MP1 (eUSB6 + USBSS4) -> RTS5329 SD Card reader */ +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2c_e0>; + vdda12-supply = <&vreg_l4c_e0>; + + phys = <&ptn3222_1>; + + status = "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l2c_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l2c_e0>; + vdda-pll-supply = <&vreg_l4c_e0>; + refgen-supply = <&vreg_l4f_e1>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi index 6b4747025b9f..30e2d8caa0ed 100644 --- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; - pmh0104-l1-thermal { + pmh0104_l1_thermal: pmh0104-l1-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0104_l_e1_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi index 7655bc030348..c2d0b9597818 100644 --- a/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/pmh0110-glymur.dtsi @@ -46,7 +46,7 @@ trip1 { }; }; - pmh0110-h0-thermal { + pmh0110_h0_thermal: pmh0110-h0-thermal { polling-delay-passive = <100>; thermal-sensors = <&pmh0110_h_e0_temp_alarm>; From d01693e992b8faebe61612208096e5937684aaf2 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:17 +0530 Subject: [PATCH 780/864] arm64: dts: qcom: kaanapali: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-7-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 128d46a39e22..131fd2a16c54 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -224,6 +224,7 @@ scm: scm { qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + sram = <&minidump_config>; }; scmi: scmi { @@ -5586,6 +5587,10 @@ sram@14680000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-sram@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 90a6f902c8de56a2e32f8c458c10e42b29a4394a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:18 +0530 Subject: [PATCH 781/864] arm64: dts: qcom: sm8450: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-8-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index c3e22f6a69e4..b8793482b181 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -479,6 +479,7 @@ scm: scm { compatible = "qcom,scm-sm8450", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -4964,6 +4965,10 @@ sram@146aa000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 1243108ae31de2de25ba08d08debad4bf8afe3ad Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:19 +0530 Subject: [PATCH 782/864] arm64: dts: qcom: sa8775p: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-9-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 17bc5bcd9d09..695eae1b7256 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -514,6 +514,7 @@ firmware { scm { compatible = "qcom,scm-sa8775p", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; }; }; @@ -6821,6 +6822,10 @@ sram: sram@146d8000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 8106cb30725baca6568cc8f54dffdbef792d52bf Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:20 +0530 Subject: [PATCH 783/864] arm64: dts: qcom: qcs8300: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-10-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d839f3683535..0812ed997381 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -614,6 +614,7 @@ firmware { scm: scm { compatible = "qcom,scm-qcs8300", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; }; }; @@ -7163,6 +7164,10 @@ sram: sram@146d8000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 27ba11afe4aeeed7d9aa31179fdc46656d6f335d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:21 +0530 Subject: [PATCH 784/864] arm64: dts: qcom: qdu1000: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-11-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 26cc86d12f72..af106aebd30d 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -171,6 +171,7 @@ cluster_sleep_1: cluster-sleep-1 { firmware { scm { compatible = "qcom,scm-qdu1000", "qcom,scm"; + sram = <&minidump_config>; }; }; @@ -1369,6 +1370,10 @@ sram@14680000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From a1db65c7980a5567396a74ce94272d26f0bcb86a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:22 +0530 Subject: [PATCH 785/864] arm64: dts: qcom: sm8550: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-12-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 2888ec109ef7..0e701e709235 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -391,6 +391,7 @@ scm: scm { qcom,dload-mode = <&tcsr 0x19000>; interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + sram = <&minidump_config>; }; }; @@ -5551,6 +5552,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2c000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@8000 { reg = <0x8000 0x2000>; }; From f0259f721e1870177a949d56fc6970454c452d23 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:24 +0530 Subject: [PATCH 786/864] arm64: dts: qcom: sc7280: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-14-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index f74fa66f1a67..f2da3706d5c8 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -723,6 +723,7 @@ firmware { scm: scm { compatible = "qcom,scm-sc7280", "qcom,scm"; qcom,dload-mode = <&tcsr_2 0x13000>; + sram = <&minidump_config>; }; }; @@ -6714,6 +6715,10 @@ sram@146a5000 { ranges = <0 0 0x146a5000 0x6000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@3000 { reg = <0x3000 0x2000>; }; From e030c56e38fcd5d30fb57f0db3388d13e29872b4 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:25 +0530 Subject: [PATCH 787/864] arm64: dts: qcom: sm8350: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-15-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 524693ec31c9..32b47f5ec1f6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -295,6 +295,7 @@ firmware { scm: scm { compatible = "qcom,scm-sm8350", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -3535,6 +3536,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x40000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@3d000 { reg = <0x3d000 0x2000>; }; From 9d2f33d8ceacde93631319f06243bfc5ed41e2d7 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:26 +0530 Subject: [PATCH 788/864] arm64: dts: qcom: sc7180: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-16-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 18f9cb82639a..70fbfb31d4a4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -385,6 +385,7 @@ cluster_aoss_sleep: cluster-sleep-2 { firmware { scm: scm { compatible = "qcom,scm-sc7180", "qcom,scm"; + sram = <&minidump_config>; }; }; @@ -3596,6 +3597,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2e000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@28000 { reg = <0x28000 0x2000>; }; From 4e9b6041bbdddde93369df47ba44c759e29c0972 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:27 +0530 Subject: [PATCH 789/864] arm64: dts: qcom: sm6350: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-17-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 51e0cb5cce66..15d38b7e803c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -363,6 +363,7 @@ big_cpu_sleep_1: cpu-sleep-1-1 { firmware { scm: scm { compatible = "qcom,scm-sm6350", "qcom,scm"; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -2820,6 +2821,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x2e000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@28000 { reg = <0x28000 0x2000>; }; From aadae3dbd5ae8c98ee1e6c8b6636f18b006cb905 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:28 +0530 Subject: [PATCH 790/864] arm64: dts: qcom: sm6375: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-18-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index ccf572bb1549..71a228597093 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -307,6 +307,7 @@ scm { compatible = "qcom,scm-sm6375", "qcom,scm"; clocks = <&rpmcc RPM_SMD_CE1_CLK>; clock-names = "core"; + sram = <&minidump_config>; #reset-cells = <1>; }; }; @@ -1645,6 +1646,10 @@ sram@c125000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@94c { compatible = "qcom,pil-reloc-info"; reg = <0x94c 0xc8>; From 32df14ece3e5c92bd2ddf1eebb3f193df3b7a701 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:29 +0530 Subject: [PATCH 791/864] arm64: dts: qcom: qcs615: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260624190830.3131112-19-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 07ba5733ca92..eedfdce3c479 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -474,6 +474,7 @@ firmware { scm { compatible = "qcom,scm-qcs615", "qcom,scm"; qcom,dload-mode = <&tcsr 0x13000>; + sram = <&minidump_config>; }; }; @@ -4722,6 +4723,10 @@ sram@14680000 { #address-cells = <1>; #size-cells = <1>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + pil-reloc@2a94c { compatible = "qcom,pil-reloc-info"; reg = <0x2a94c 0xc8>; From 6fb55156f44ae3fd8e2a308167ed8dad1249492a Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 25 Jun 2026 00:38:30 +0530 Subject: [PATCH 792/864] arm64: dts: qcom: sdm845: Add minidump SRAM config to SCM node Point the SCM node at the minidump config slot in the always-on SRAM. Boot firmware reads this word before DDR is initialised on a warm reset to decide where to deliver the minidump. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260624190830.3131112-20-mukesh.ojha@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 562d411ed256..b1f6782a3ad9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -363,6 +363,7 @@ cluster_sleep_0: cluster-sleep-0 { firmware { scm { compatible = "qcom,scm-sdm845", "qcom,scm"; + sram = <&minidump_config>; }; }; @@ -5195,6 +5196,10 @@ sram@14680000 { ranges = <0 0 0x14680000 0x40000>; + minidump_config: minidump-sram@1c { + reg = <0x1c 0x4>; + }; + ipa_modem_tables: modem-tables@3d000 { reg = <0x3d000 0x2000>; }; From b4387e476fb2fdcc2c4697bd607833ea567db747 Mon Sep 17 00:00:00 2001 From: William Bright Date: Thu, 23 Jul 2026 19:18:07 +0100 Subject: [PATCH 793/864] dt-bindings: vendor-prefixes: Add IMDT Add IMDT (IMD Technologies Ltd) to the vendor prefixes list. Acked-by: Rob Herring (Arm) Signed-off-by: William Bright Link: https://lore.kernel.org/r/20260723-imdt-qcs8550-sbc-rfc-v5-1-2fb988854623@imd-tec.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 7b0d79ebf9bd..5c74da791c13 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -791,6 +791,8 @@ patternProperties: description: ILI Technology Corporation (ILITEK) "^imagis,.*": description: Imagis Technologies Co., Ltd. + "^imdt,.*": + description: IMD Technologies Ltd. "^img,.*": description: Imagination Technologies Ltd. "^imi,.*": From d15c4f0eff1e7b6fc23ea2e37a32633642ce4b85 Mon Sep 17 00:00:00 2001 From: William Bright Date: Thu, 23 Jul 2026 19:18:08 +0100 Subject: [PATCH 794/864] dt-bindings: arm: qcom: Document IMDT QCS8550 SBC/SoM Document the IMDT QCS8550 SBC which consists of an IMDT QCS8550 SoM soldered onto an IMDT QCS8550 carrier board. Acked-by: Rob Herring (Arm) Signed-off-by: William Bright Link: https://lore.kernel.org/r/20260723-imdt-qcs8550-sbc-rfc-v5-2-2fb988854623@imd-tec.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f8ee354070d0..b035557283e1 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1138,6 +1138,13 @@ properties: - sony,pdx234 - const: qcom,sm8550 + - items: + - enum: + - imdt,qcs8550-sbc + - const: imdt,qcs8550-som + - const: qcom,qcs8550 + - const: qcom,sm8550 + - items: - enum: - qcom,qcs8550-aim300-aiot From b9f1f97846bcb1989bb52b6cbd1205ecc22c8e43 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Fri, 31 Jul 2026 14:10:31 +0530 Subject: [PATCH 795/864] arm64: dts: qcom: eliza: Add LPASS macro and SoundWire support Add SoC-level LPASS WSA macro, VA macro, SoundWire controller and LPASS LPI pin controller nodes. DMIC and WSA SoundWire pinctrl states are defined inside the LPASS LPI pin controller node. The hardware is similar to the SM8750 platform. The SoundWire controller is kept disabled so board DTS files can selectively enable and configure it. Signed-off-by: Ravi Hothi Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260731084032.3106477-2-ravi.hothi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza.dtsi | 189 ++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 83b8d80545e9..0d4629b2ded8 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -2064,6 +2065,77 @@ q6prmcc: clock-controller { }; }; + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,eliza-lpass-wsa-macro", + "qcom,sm8550-lpass-wsa-macro"; + reg = <0x0 0x06b00000 0x0 0x1000>; + + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", + "macro", + "dcodec", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + }; + + swr0: soundwire@6b10000 { + compatible = "qcom,soundwire-v2.1.0", + "qcom,soundwire-v2.0.0"; + reg = <0x0 0x06b10000 0x0 0x10000>; + interrupts = ; + + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + + label = "WSA"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = + /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f + 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = + /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 + 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = + /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f + 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = + /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 + 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = + /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + lpass_lpiaon_noc: interconnect@7400000 { compatible = "qcom,eliza-lpass-lpiaon-noc"; reg = <0x0 0x07400000 0x0 0x19080>; @@ -2078,6 +2150,123 @@ lpass_lpicx_noc: interconnect@7420000 { #interconnect-cells = <2>; }; + lpass_vamacro: codec@7660000 { + compatible = "qcom,eliza-lpass-va-macro", + "qcom,sm8550-lpass-va-macro"; + reg = <0x0 0x07660000 0x0 0x2000>; + + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", + "macro", + "dcodec"; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + + lpass_tlmm: pinctrl@7760000 { + compatible = "qcom,eliza-lpass-lpi-pinctrl"; + reg = <0x0 0x07760000 0x0 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic45_default: dmic45-default-state { + clk-pins { + pins = "gpio12"; + function = "dmic3_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio13"; + function = "dmic3_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic67_default: dmic67-default-state { + clk-pins { + pins = "gpio21"; + function = "dmic4_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio22"; + function = "dmic4_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + sdhc_2: mmc@8804000 { compatible = "qcom,eliza-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0 0x08804000 0x0 0x1000>; From f016b7e86137f6a83de84f660b6bb3d7b955de25 Mon Sep 17 00:00:00 2001 From: Ravi Hothi Date: Fri, 31 Jul 2026 14:10:32 +0530 Subject: [PATCH 796/864] arm64: dts: qcom: eliza-cqs-evk: Enable sound card support with WSA8845 and DMIC Enable the sound card on the Eliza CQS EVK platform, including the WSA8845 external speaker path and DMIC microphone capture via VA macro. Enable the required LPASS WSA macro, VA macro and SoundWire controller along with the necessary pinctrl configurations for DMIC and WSA SoundWire interfaces. Signed-off-by: Ravi Hothi Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260731084032.3106477-3-ravi.hothi@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts | 141 +++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts index 43d428a4ed2d..5e4175291f05 100644 --- a/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/eliza-cqs-evk.dts @@ -5,10 +5,151 @@ /dts-v1/; +#include + #include "eliza-cqs-som.dtsi" #include "eliza-evk.dtsi" / { model = "Qualcomm Technologies, Inc. Eliza CQS EVK"; compatible = "qcom,eliza-cqs-evk", "qcom,eliza-cqs-som", "qcom,eliza"; + + sound { + compatible = "qcom,eliza-sndcard", "qcom,sm8450-sndcard"; + model = "eliza-cqs-evk"; + + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb", + "VA DMIC4", "vdd-micb", + "VA DMIC5", "vdd-micb", + "VA DMIC6", "vdd-micb", + "VA DMIC7", "vdd-micb"; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + dmic_eldo: regulator-dmic-eldo { + compatible = "regulator-fixed"; + regulator-name = "dmic-eldo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm7550_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>, + <&dmic45_default>, <&dmic67_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&dmic_eldo>; + qcom,dmic-sample-rate = <4800000>; +}; + +&swr0 { + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + + status = "okay"; + + /* WSA8845, Speaker Left */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>; + vdd-1p8-supply = <&vreg_l7b>; + vdd-io-supply = <&vreg_l7b>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 1 (SPKR_L) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 2 (SPKR_L_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 3 (SPKR_L_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 10 (SPKR_L_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Speaker Right */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + pinctrl-0 = <&spkr_2_sd_n_active>; + pinctrl-names = "default"; + powerdown-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + vdd-1p8-supply = <&vreg_l7b>; + vdd-io-supply = <&vreg_l7b>; + + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + + /* + * WSA8845 Port 1 (DAC) <=> SWR0 Port 4 (SPKR_R) + * WSA8845 Port 2 (COMP) <=> SWR0 Port 5 (SPKR_R_COMP) + * WSA8845 Port 3 (BOOST) <=> SWR0 Port 6 (SPKR_R_BOOST) + * WSA8845 Port 4 (PBR) <=> SWR0 Port 7 (PBR) + * WSA8845 Port 5 (VISENSE) <=> SWR0 Port 11 (SPKR_R_VI) + * WSA8845 Port 6 (CPS) <=> SWR0 Port 13 (CPS) + */ + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio79"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; }; From 2cc1076501887746f20bdcca40ae703c8c13bc7a Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 29 Jul 2026 14:27:19 +0300 Subject: [PATCH 797/864] arm64: dts: qcom: sm8650: Assign CCI clock rates to 37.5MHz Setting CCI supply clock rate to higher value of 37.5MHz allows to program the controller to configure its I2C bus speed to Fast-mode plus. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Neil Armstrong Reviewed-by: Loic Poulain Link: https://lore.kernel.org/r/20260729112719.1151700-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 799d549a9019..893a7a6f0c28 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5351,6 +5351,8 @@ cci0: cci@ac15000 { clock-names = "camnoc_axi", "cpas_ahb", "cci"; + assigned-clocks = <&camcc CAM_CC_CCI_0_CLK>; + assigned-clock-rates = <37500000>; pinctrl-0 = <&cci0_0_default &cci0_1_default>; pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; pinctrl-names = "default", "sleep"; @@ -5384,6 +5386,8 @@ cci1: cci@ac16000 { clock-names = "camnoc_axi", "cpas_ahb", "cci"; + assigned-clocks = <&camcc CAM_CC_CCI_1_CLK>; + assigned-clock-rates = <37500000>; pinctrl-0 = <&cci1_0_default &cci1_1_default>; pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; pinctrl-names = "default", "sleep"; @@ -5417,6 +5421,8 @@ cci2: cci@ac17000 { clock-names = "camnoc_axi", "cpas_ahb", "cci"; + assigned-clocks = <&camcc CAM_CC_CCI_2_CLK>; + assigned-clock-rates = <37500000>; pinctrl-0 = <&cci2_0_default &cci2_1_default>; pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; pinctrl-names = "default", "sleep"; From ce470cc95b8932519d3b63744e6e3f4113e23b67 Mon Sep 17 00:00:00 2001 From: Dominik Haller Date: Wed, 15 Jul 2026 17:08:25 -0700 Subject: [PATCH 798/864] arm64: dts: ti: k3-am68-phyboard-izar: Add pwm fan Add an overlay to control the pwm fan[0] that comes with the kit. [0] https://www.sepa-europe.com/en/2023/06/16/axial-fan-lf40p/ Signed-off-by: Dominik Haller Link: https://patch.msgid.link/20260716000827.84982-1-d.haller@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 6 +- .../dts/ti/k3-am68-phyboard-izar-pwm-fan.dtso | 74 +++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-pwm-fan.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index dba641193144..114b144c7899 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -185,7 +185,10 @@ k3-am68-phyboard-izar-lvds-ph128800t006-dtbs := k3-am68-phyboard-izar.dtb \ k3-am68-phyboard-izar-lvds-ph128800t006.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar-peb-av-15.dtb k3-am68-phyboard-izar-peb-av-15-dtbs := k3-am68-phyboard-izar.dtb \ - k3-am68-phyboard-izar-peb-av-15.dtbo + k3-am68-phyboard-izar-peb-av-15.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar-pwm-fan.dtb +k3-am68-phyboard-izar-pwm-fan-dtbs := k3-am68-phyboard-izar.dtb \ + k3-am68-phyboard-izar-pwm-fan.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb @@ -467,6 +470,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ k3-am68-phyboard-izar-peb-av-15.dtb \ + k3-am68-phyboard-izar-pwm-fan.dtb \ k3-am68-sk-base-board-csi2-dual-imx219.dtb \ k3-am68-sk-base-board-pcie1-ep.dtb \ k3-am69-aquila-clover-panel-cap-touch-7inch-dsi.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-pwm-fan.dtso b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-pwm-fan.dtso new file mode 100644 index 000000000000..8c1a51216a90 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar-pwm-fan.dtso @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&main_pwmfan_default_pins>; + #cooling-cells = <2>; + cooling-levels = <0 90 150 255>; + /* frequency needs to be the same as lvds backlight */ + pwms = <&main_ehrpwm0 0 44000 PWM_POLARITY_INVERTED>; + }; +}; + +&main_pmx0 { + main_pwmfan_default_pins: main-pwmfan-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0cc, PIN_OUTPUT, 5) /* (AE27) SPI0_CS0.EHRPWM0_A */ + >; + }; +}; + +&main_ehrpwm0 { + status = "okay"; +}; + +&main3_thermal { + trips { + cpu_low: cpu-low { + hysteresis = <3000>; + temperature = <55000>; + type = "active"; + }; + + cpu_med: cpu-med { + hysteresis = <3000>; + temperature = <60000>; + type = "active"; + }; + + cpu_high: cpu-high { + hysteresis = <3000>; + temperature = <65000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + cooling-device = <&pwmfan 1 1>; + trip = <&cpu_low>; + }; + + map2 { + cooling-device = <&pwmfan 2 2>; + trip = <&cpu_med>; + }; + + map3 { + cooling-device = <&pwmfan 3 3>; + trip = <&cpu_high>; + }; + }; +}; From e5e88c26df2b4ce9fb5e0c5d40aae241872b89bc Mon Sep 17 00:00:00 2001 From: Aradhya Bhatia Date: Wed, 15 Jul 2026 13:05:31 +0530 Subject: [PATCH 799/864] arm64: dts: ti: Add LincolnTech OLDI LCD-185 Overlay for AM625-BeaglePlay The panel is Lincoln Technology Solutions LCD185-101CT[0]. It is a Dual-Link LVDS panel and supports WUXGA resolution (1920x1200). Furthermore, it has an i2c based touch controller: Goodix-GT928. Add DT overlay for the OLDI panel to connect with BeaglePlay platform. [0]: https://lincolntechsolutions.com/wp-content/uploads/2024/09/LCD185-101CTL1ARNTT_DS_R1.3.pdf Signed-off-by: Aradhya Bhatia Signed-off-by: Swamil Jain Link: https://patch.msgid.link/20260715073531.2346803-1-s-jain1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + ...5-beagleplay-lincolntech-lcd185-panel.dtso | 162 ++++++++++++++++++ 2 files changed, 166 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 114b144c7899..1623a816d961 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -26,6 +26,7 @@ k3-am625-verdin-wifi-dev-dsi-to-hdmi-dtbs := k3-am625-verdin-wifi-dev.dtb \ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-ov5640.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-csi2-tevi-ov5640.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay-lincolntech-lcd185-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk-microtips-mf101hie-panel.dtbo @@ -240,6 +241,8 @@ k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-ov5640.dtbo k3-am625-beagleplay-csi2-tevi-ov5640-dtbs := k3-am625-beagleplay.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtbo +k3-am625-beagleplay-lincolntech-lcd185-panel-dtbs := k3-am625-beagleplay.dtb \ + k3-am625-beagleplay-lincolntech-lcd185-panel.dtbo k3-am625-phyboard-lyra-disable-eth-phy-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ k3-am6xx-phycore-disable-eth-phy.dtbo k3-am625-phyboard-lyra-disable-rtc-dtbs := k3-am625-phyboard-lyra-rdk.dtb \ @@ -414,6 +417,7 @@ k3-j784s4-evm-usxgmii-exp1-exp2-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ + k3-am625-beagleplay-lincolntech-lcd185-panel.dtb \ k3-am625-phyboard-lyra-disable-eth-phy.dtb \ k3-am625-phyboard-lyra-disable-rtc.dtb \ k3-am625-phyboard-lyra-disable-spi-nor.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso b/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso new file mode 100644 index 000000000000..ac621c32de9b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay-lincolntech-lcd185-panel.dtso @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/** + * Lincoln tech Solutions OLDI panel (LCD185-101CT) and touch DT overlay for AM625-BeaglePlay + * + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "k3-pinctrl.h" + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins_default>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + enable-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + pwms = <&epwm0 1 20000 0>; + }; + + lcd { + compatible = "lincolntech,lcd185-101ct"; + backlight = <&backlight>; + /* + * Note that the OLDI TX 0 transmits the odd set of pixels + * while the OLDI TX 1 transmits the even set. This is a + * fixed configuration in the IP integration and is not + * changeable. The properties, "dual-lvds-odd-pixels" and + * "dual-lvds-even-pixels" have been used to merely + * identify if a Dual Link configuration is required. + * Swapping them will cause an error in the dss oldi driver. + */ + power-supply = <&vsys_5v0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + lcd_in0: endpoint { + remote-endpoint = <&oldi_0_out>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + lcd_in1: endpoint { + remote-endpoint = <&oldi_1_out>; + }; + }; + }; + }; +}; + +&main_pmx0 { + touchscreen_pins_default: touchscreen-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 7) /* (A13) SPI0_CS0.GPIO1_15 */ + AM62X_IOPAD(0x00a0, PIN_INPUT, 7) /* (K25) GPMC0_WPn.GPIO0_39 */ + >; + }; + + backlight_pins_default: bl-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ + >; + }; +}; + +&dss { + status = "okay"; +}; + +&oldi0 { + status = "okay"; + ti,companion-oldi = <&oldi1>; +}; + +&oldi1 { + status = "okay"; + ti,secondary-oldi; + ti,companion-oldi = <&oldi0>; +}; + +&oldi0_port0 { + oldi_0_in: endpoint { + remote-endpoint = <&dpi0_out0>; + }; +}; + +&oldi0_port1 { + oldi_0_out: endpoint { + remote-endpoint = <&lcd_in0>; + }; +}; + +&oldi1_port0 { + oldi_1_in: endpoint { + remote-endpoint = <&dpi0_out1>; + }; +}; + +&oldi1_port1 { + oldi_1_out: endpoint { + remote-endpoint = <&lcd_in1>; + }; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP1: Output to OLDI */ + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dpi0_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&oldi_0_in>; + }; + dpi0_out1: endpoint@1 { + reg = <1>; + remote-endpoint = <&oldi_1_in>; + }; + }; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + }; + + touchscreen@5d { + compatible = "goodix,gt928"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + irq-gpios = <&main_gpio0 39 GPIO_ACTIVE_HIGH>; + reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + }; +}; + +&epwm0 { + status = "okay"; +}; From f0d750aa4072d8e06a3133a852d48149d02cdd49 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 2 Jun 2026 18:29:27 +0530 Subject: [PATCH 800/864] arm64: dts: ti: k3-am67a-beagley-ai: Setup I2C for CSI/DSI connectors I2C0 is used by the 22-pin CSI1/DSI0 connector and I2C2 is used by the 22-pin CSI0 connector. Add the missing pinmux definition for the I2C2, and setup both nodes but keep them disabled. They will be enabled by the camera and display overlays. Signed-off-by: Jai Luthra Reviewed-by: Rishikesh Donadkar Link: https://patch.msgid.link/20260602-beagley-cameras-v3-1-fe6ae35b7eda@ideasonboard.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index 5255e04b9ac7..890d3a745375 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -157,6 +157,13 @@ J722S_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (B22) I2C0_SDA */ bootph-all; }; + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ @@ -399,4 +406,22 @@ &sdhci1 { status = "okay"; }; +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + /* Only used by the CSI1/DSI0 connector; enable it in the overlay */ + status = "disabled"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + /* Only used by the CSI0 connector; enable it in the overlay */ + status = "disabled"; +}; + #include "k3-j722s-ti-ipc-firmware.dtsi" From 7859b66bfaac20198805fa6d69f477888e14a09e Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 2 Jun 2026 18:29:28 +0530 Subject: [PATCH 801/864] arm64: dts: ti: k3-am67a-beagley-ai: Add DSI0/CSI1 mux The DSI0 connector is shared with the CSI1 and selectable via the TMUX646 switch present on the board. Model it using a gpio-mux so that camera sensor or DSI panel overlays can override it. Link: https://docs.beagle.cc/boards/beagley/ai/03-design.html#dsi Reviewed-by: Rishikesh Donadkar Signed-off-by: Jai Luthra Link: https://patch.msgid.link/20260602-beagley-cameras-v3-2-fe6ae35b7eda@ideasonboard.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index 890d3a745375..bb1db8c6a91f 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -146,6 +146,19 @@ led-1 { default-state = "on"; }; }; + + dsi_csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi_csi_mux_pins_default>; + + mux-gpios = <&main_gpio0 2 GPIO_ACTIVE_HIGH>, + <&main_gpio0 1 GPIO_ACTIVE_HIGH>; + + /* state = SEL + 2*OE : 0 = DSI0, 1 = CSI1, 2,3 = off */ + idle-state = <2>; + }; }; &main_pmx0 { @@ -199,6 +212,13 @@ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ >; }; + dsi_csi_mux_pins_default: dsi-csi-mux-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x0004, PIN_OUTPUT, 7) /* (L23) OSPI0_LBCLKO.GPIO0_1 */ + J722S_IOPAD(0x0008, PIN_OUTPUT, 7) /* (L22) OSPI0_DQS.GPIO0_2 */ + >; + }; + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x014c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ From e0c1c2492be4d3fad27a4cd2ff74c41d0f11b807 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 2 Jun 2026 18:29:29 +0530 Subject: [PATCH 802/864] arm64: dts: ti: k3-am67a-beagley-ai: Add overlay for IMX219 on CSI0 RPi v2 Camera (IMX219) is an 8MP camera that can be used with BeagleY AI through the 22-pin CSI-RX connectors. Add a DT overlay to enable use of this camera sensor through the CSI0 connector. Link: https://pip.raspberrypi.com/categories/1205-drawings-and-schematics Link: https://docs.beagle.cc/boards/beagley/ai/03-design.html#csi Signed-off-by: Jai Luthra Reviewed-by: Rishikesh Donadkar Link: https://patch.msgid.link/20260602-beagley-cameras-v3-3-fe6ae35b7eda@ideasonboard.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../ti/k3-am67a-beagley-ai-csi0-imx219.dtso | 118 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi0-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 1623a816d961..5e565c7d39de 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -201,6 +201,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai-csi0-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo @@ -359,6 +360,8 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am67a-beagley-ai-csi0-imx219-dtbs := k3-am67a-beagley-ai.dtb \ + k3-am67a-beagley-ai-csi0-imx219.dtbo k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ @@ -472,6 +475,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am67a-beagley-ai-csi0-imx219.dtb \ k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-phyboard-izar-pwm-fan.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi0-imx219.dtso b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi0-imx219.dtso new file mode 100644 index 000000000000..1b1c68f23cc3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi0-imx219.dtso @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * RPi Camera V2.1 on BeagleY AI CSI0 port + * + * Copyright (C) 2026 Ideas On Board Oy + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_csi0: imx219-csi0-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + reg_2p8v_csi0: regulator-2p8v-csi0 { + compatible = "regulator-fixed"; + regulator-name = "2P8V_CSI0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p8v_csi0: regulator-1p8v-csi0 { + compatible = "regulator-fixed"; + regulator-name = "1P8V_CSI0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p2v_csi0: regulator-1p2v-csi0 { + compatible = "regulator-fixed"; + regulator-name = "1P2V_CSI0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; +}; + +&mcu_pmx0 { + cam0_reset_pins_default: cam0-default-reset-pins { + pinctrl-single,pins = < + J722S_MCU_IOPAD(0x003c, PIN_OUTPUT, 7) /* (C1) MCU_MCAN1_TX.MCU_GPIO0_15 */ + >; + }; +}; + +&mcu_gpio0 { + status = "okay"; +}; + +&main_i2c2 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + imx219_0: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_csi0>; + + VANA-supply = <®_2p8v_csi0>; + VDIG-supply = <®_1p8v_csi0>; + VDDL-supply = <®_1p2v_csi0>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam0_reset_pins_default>; + + reset-gpios = <&mcu_gpio0 15 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&dphy0 { + status = "okay"; +}; From bb58f1c72c5c5920e87fd5af2faa914b5c66ae82 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Tue, 2 Jun 2026 18:29:30 +0530 Subject: [PATCH 803/864] arm64: dts: ti: k3-am67a-beagley-ai: Add overlay for IMX219 on CSI1 RPi v2 Camera (IMX219) is an 8MP camera that can be used with BeagleY AI through the 22-pin CSI-RX connectors. Add a DT overlay to enable use of this camera sensor through the CSI1 connector. The CSI1 connector is muxed with DSI0, so ensure that we route it to CSI1 (DSI_CSI_OE=0 and DSI_CSI_SEL=1). Link: https://pip.raspberrypi.com/categories/1205-drawings-and-schematics Link: https://docs.beagle.cc/boards/beagley/ai/03-design.html#id60 Signed-off-by: Jai Luthra Reviewed-by: Rishikesh Donadkar Link: https://patch.msgid.link/20260602-beagley-cameras-v3-4-fe6ae35b7eda@ideasonboard.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 4 + .../ti/k3-am67a-beagley-ai-csi1-imx219.dtso | 118 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi1-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 5e565c7d39de..795978e962ee 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -202,6 +202,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-usb0-type-a.dtbo # Boards with J722s SoC dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai.dtb dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai-csi0-imx219.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-am67a-beagley-ai-csi1-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo @@ -362,6 +363,8 @@ k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo k3-am67a-beagley-ai-csi0-imx219-dtbs := k3-am67a-beagley-ai.dtb \ k3-am67a-beagley-ai-csi0-imx219.dtbo +k3-am67a-beagley-ai-csi1-imx219-dtbs := k3-am67a-beagley-ai.dtb \ + k3-am67a-beagley-ai-csi1-imx219.dtbo k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ k3-j721e-sk-csi2-dual-imx219.dtbo k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \ @@ -476,6 +479,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-am67a-beagley-ai-csi0-imx219.dtb \ + k3-am67a-beagley-ai-csi1-imx219.dtb \ k3-am68-phyboard-izar-lvds-ph128800t006.dtb \ k3-am68-phyboard-izar-peb-av-15.dtb \ k3-am68-phyboard-izar-pwm-fan.dtb \ diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi1-imx219.dtso b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi1-imx219.dtso new file mode 100644 index 000000000000..cf3729f5ae60 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai-csi1-imx219.dtso @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * RPi Camera V2.1 on BeagleY AI CSI1 port + * + * Copyright (C) 2026 Ideas On Board Oy + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_csi1: imx219-csi1-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + reg_2p8v_csi1: regulator-2p8v-csi1 { + compatible = "regulator-fixed"; + regulator-name = "2P8V_CSI1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p8v_csi1: regulator-1p8v-csi1 { + compatible = "regulator-fixed"; + regulator-name = "1P8V_CSI1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; + + reg_1p2v_csi1: regulator-1p2v-csi1 { + compatible = "regulator-fixed"; + regulator-name = "1P2V_CSI1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdd_3v3>; + regulator-always-on; + }; +}; + +&main_pmx0 { + cam1_reset_pins_default: cam1-default-reset-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (D22) MCAN0_TX.GPIO1_24 */ + >; + }; +}; + +&dsi_csi_mux { + idle-state = <1>; +}; + +&main_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + imx219_1: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_csi1>; + + VANA-supply = <®_2p8v_csi1>; + VDIG-supply = <®_1p8v_csi1>; + VDDL-supply = <®_1p2v_csi1>; + + pinctrl-names = "default"; + pinctrl-0 = <&cam1_reset_pins_default>; + + reset-gpios = <&main_gpio1 24 GPIO_ACTIVE_HIGH>; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&ti_csi2rx1 { + status = "okay"; +}; + +&dphy1 { + status = "okay"; +}; From 41fe2049d282a86034acd24ca77016d4279a6b04 Mon Sep 17 00:00:00 2001 From: Chintan Vankar Date: Thu, 25 Jun 2026 17:02:23 +0530 Subject: [PATCH 804/864] arm64: dts: ti: k3-am62a7-sk: Add bootph-all property in cpsw_mac_syscon node Ethernet boot requires CPSW node to be present starting from R5 SPL stage. Add "bootph-all" property in CPSW MAC's eFuse node "cpsw_mac_syscon" to enable this node during SPL stage along with later boot stage so that CPSW port will get static MAC address. Signed-off-by: Chintan Vankar Acked-by: Andrew Davis Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 821a9705bb7d..d3b3675e7a8f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -230,6 +230,10 @@ AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ }; }; +&cpsw_mac_syscon { + bootph-all; +}; + /* WKUP UART0 is used for DM firmware logs */ &wkup_uart0 { pinctrl-names = "default"; From 6c76412dd575b57f54b3d9646503b2e9b2e390df Mon Sep 17 00:00:00 2001 From: "David Lechner (TI)" Date: Tue, 28 Jul 2026 14:44:37 -0500 Subject: [PATCH 805/864] arm64: dts: ti: k3-am67a-beagley-ai: Add gpio line names Add gpio-line-names properties to the BeagleY-AI .dts so that gpios can be requested by the documented name on the 40-pin header (and a few other board functions). Signed-off-by: David Lechner (TI) Acked-by: Robert Nelson Link: https://patch.msgid.link/20260728-arm-dts-beagleyai-gpio-info-v1-2-783ec90d54da@baylibre.com Signed-off-by: Vignesh Raghavendra --- .../arm64/boot/dts/ti/k3-am67a-beagley-ai.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts index bb1db8c6a91f..8b4b3b80a29d 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts @@ -281,9 +281,32 @@ &cpsw_port1 { status = "okay"; }; +&main_gpio0 { + gpio-line-names = "", "", "", "", "", /* 0-4 */ + "", "", "", "", "", /* 5-9 */ + "", "", "", "", "", /* 10-14 */ + "", "", "", "", "", /* 15-19 */ + "", "", "", "", "", /* 20-24 */ + "", "", "", "", "", /* 25-29 */ + "", "", "USB_RST", "GPIO27", "", /* 30-34 */ + "", "GPIO26", "", "GPIO4", "", /* 35-39 */ + "", "GPIO22", "GPIO25", "", ""; /* 40-44 */ +}; + &main_gpio1 { bootph-all; status = "okay"; + gpio-line-names = "", "", "", "", "", /* 0-4 */ + "", "", "GPIO16", "GPIO17", "GPIO21", /* 5-9 */ + "GPIO20", "GPIO18", "GPIO19", "GPIO15", "GPIO14", /* 10-14 */ + "GPIO5", "GPIO12", "GPIO6", "GPIO13", ""; /* 15-19 */ +}; + +&mcu_gpio0 { + gpio-line-names = "GPIO8", "", "GPIO11", "GPIO10", "GPIO9", /* 0-4 */ + "", "", "GPIO23", "", "GPIO7", /* 5-9 */ + "GPIO24", "", "", "HDMI_RSTn", "HDMI_INTn", /* 10-14 */ + "", "", "GPIO3", "GPIO2", ""; /* 15-19 */ }; &main_uart0 { From 4999ba58b600318a42672f6d2a54ed79876f277a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:04:51 +0200 Subject: [PATCH 806/864] ARM: dts: allwinner: Correct white-space style Correct a few white-space issues, like double before bracket '{' character, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801210450.384087-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts | 2 +- arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts | 4 ++-- arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts index ea7a59dcf8f9..f6d4babe6c1c 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-gemei-g9.dts @@ -179,7 +179,7 @@ ®_usb2_vbus { }; -&uart0 { +&uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; status = "okay"; diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts index 60e432a0ef1c..408d1f01412f 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-inet1.dts @@ -78,7 +78,7 @@ &cpu0 { cpu-supply = <®_dcdc2>; }; -&ehci0 { +&ehci0 { status = "okay"; }; @@ -157,7 +157,7 @@ &mmc0 { status = "okay"; }; -&ohci0 { +&ohci0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi index 544d60cfc32e..4879a437f415 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi @@ -42,7 +42,7 @@ reg_vcc_core: regulator-core { }; /* USB0 MUX to switch connect to Card-Edge only after BootROM */ - usb0_sec_mux: mux-controller{ + usb0_sec_mux: mux-controller { compatible = "gpio-mux"; #mux-control-cells = <0>; mux-gpios = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */ From be145483f8eee440d335ed794a2294fd55ff2a35 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:04:52 +0200 Subject: [PATCH 807/864] arm64: dts: allwinner: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801210450.384087-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 2 +- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 2 +- arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi index 6d78a1c98f10..3b9ded8375dc 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi @@ -49,7 +49,7 @@ axp803: pmic@3a3 { }; }; -&spi0 { +&spi0 { status = "okay"; flash@0 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts index 6e30a564c87f..5627d2828fc9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts @@ -48,7 +48,7 @@ ext_rgmii_phy: ethernet-phy@1 { }; }; -&spi0 { +&spi0 { status = "okay"; flash@0 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 0f29da7d51e6..6e57ee19e799 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -191,7 +191,7 @@ reg_vdd_cpux: regulator@65 { }; }; -&spi0 { +&spi0 { status = "okay"; flash@0 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts index 3322cc4d9aa4..f9fbaf6df237 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts @@ -103,7 +103,7 @@ rtl8189ftv: wifi@1 { }; }; -&spi0 { +&spi0 { status = "okay"; flash@0 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi index a8644fb52b04..0d3e761f6466 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi @@ -99,7 +99,7 @@ &ohci1 { status = "okay"; }; -&spi0 { +&spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts index b340bbcb710d..ff9b40352a54 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts @@ -149,7 +149,7 @@ reg_dcdc3: dcdc3 { }; }; -&spi0 { +&spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 994f1e4f0ce7..85247186461d 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -409,7 +409,7 @@ &rtc { assigned-clock-rates = <32768>; }; -&spi0 { +&spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pj_pins>, <&spi0_cs0_pj_pin>, <&spi0_hold_pj_pin>, <&spi0_wp_pj_pin>; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 055be86e5fae..26ce579b42bf 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -400,7 +400,7 @@ &rtc { assigned-clock-rates = <32768>; }; -&spi0 { +&spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>; status = "okay"; From db23b4aab4252f793d9fa97dc5d6f8d99c5e8e4b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:03:54 +0200 Subject: [PATCH 808/864] arm64: dts: exynos: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260801210353.383880-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi | 2 +- arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi index b65f1698cd74..439d7d7e319b 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855-pinctrl.dtsi @@ -462,7 +462,7 @@ gpm21: gpm21-gpio-bank { }; &pinctrl_hsi_ufs { - gpf3: gpf3-gpio-bank{ + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi index a675f822acec..646722da4e8c 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101-pinctrl.dtsi @@ -77,7 +77,7 @@ gpa4: gpa4-gpio-bank { ; }; - gpa5: gpa5-gpio-bank { + gpa5: gpa5-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -91,7 +91,7 @@ gpa5: gpa5-gpio-bank { ; }; - gpa9: gpa9-gpio-bank { + gpa9: gpa9-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -106,7 +106,7 @@ gpa9: gpa9-gpio-bank { ; }; - gpa10: gpa10-gpio-bank { + gpa10: gpa10-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -1030,7 +1030,7 @@ gpp27: gpp27-gpio-bank { #interrupt-cells = <2>; }; - hsi2c13_bus: hsi2c13-bus-pins { + hsi2c13_bus: hsi2c13-bus-pins { samsung,pins = "gpp25-0", "gpp25-1"; samsung,pin-function = ; samsung,pin-pud = ; From e2b3acf8c227beda488f00d06f1266f83b9b5c08 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:02:11 +0200 Subject: [PATCH 809/864] ARM: dts: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Michal Simek # Zynq Link: https://patch.msgid.link/20260801210210.383417-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/armv7-m.dtsi | 2 +- arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts | 2 +- arch/arm/boot/dts/marvell/kirkwood-nsa320.dts | 4 ++-- arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts | 8 ++++---- arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi | 2 +- arch/arm/boot/dts/microchip/at91rm9200ek.dts | 2 +- arch/arm/boot/dts/microchip/lan966x-pcb8291.dts | 2 +- arch/arm/boot/dts/st/stih407-family.dtsi | 2 +- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 2 +- arch/arm/boot/dts/xilinx/zynq-cc108.dts | 4 ++-- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi index 26f5443d85e1..6ee18d6a93ef 100644 --- a/arch/arm/boot/dts/armv7-m.dtsi +++ b/arch/arm/boot/dts/armv7-m.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 / { - nvic: interrupt-controller@e000e100 { + nvic: interrupt-controller@e000e100 { compatible = "arm,armv7m-nvic"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts index 74161b76008a..6c4131b846c1 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts @@ -141,7 +141,7 @@ mdio@200 { #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@0 { compatible = "brcm,bcm53125"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts index dd5c8ffc8781..56334b71152d 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts @@ -30,12 +30,12 @@ pinctrl: pin-controller@10000 { /* SATA Activity and Present pins are not connected */ pmx_sata0: pmx-sata0 { - marvell,pins ; + marvell,pins; marvell,function = "sata0"; }; pmx_sata1: pmx-sata1 { - marvell,pins ; + marvell,pins; marvell,function = "sata1"; }; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts index fec7269088d1..19a286dcc8a5 100644 --- a/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts +++ b/arch/arm/boot/dts/microchip/at91-kizbox3-hs.dts @@ -35,7 +35,7 @@ led-4 { }; }; - led-controller-2 { + led-controller-2 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led_red @@ -58,7 +58,7 @@ led-6 { gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default" , "default", "default", - "default", "default" ; + "default", "default"; pinctrl-0 = <&pinctrl_key_gpio_default>; pinctrl-1 = <&pinctrl_pio_rf &pinctrl_pio_wifi>; pinctrl-2 = <&pinctrl_pio_io_boot @@ -170,7 +170,7 @@ verbose_bootloader { input; }; - nail_bed_detection { + nail_bed_detection { label = "nail bed detection"; gpio = <&pioA PIN_PB12 GPIO_ACTIVE_HIGH>; input; @@ -276,7 +276,7 @@ &uart4 { &flx0 { status = "okay"; - uart5: serial@200 { + uart5: serial@200 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi index 465664628419..75d2e748a3db 100644 --- a/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi +++ b/arch/arm/boot/dts/microchip/at91-kizbox3_common.dtsi @@ -298,7 +298,7 @@ &flx0 { atmel,flexcom-mode = ; status = "disabled"; - uart5: serial@200 { + uart5: serial@200 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; atmel,use-dma-rx; diff --git a/arch/arm/boot/dts/microchip/at91rm9200ek.dts b/arch/arm/boot/dts/microchip/at91rm9200ek.dts index ce691c4692b9..b849bc7049d6 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200ek.dts +++ b/arch/arm/boot/dts/microchip/at91rm9200ek.dts @@ -117,7 +117,7 @@ kernel@50000 { reg = <0x50000 0x300000>; }; - root@350000 { + root@350000 { label = "root"; reg = <0x350000 0x4B0000>; }; diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts index 3a3d76af8612..1f0b0b647aa9 100644 --- a/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8291.dts @@ -64,7 +64,7 @@ fc3_b_pins: fc3-b-pins { function = "fc3_b"; }; - can0_b_pins: can0-b-pins { + can0_b_pins: can0-b-pins { /* RX, TX */ pins = "GPIO_35", "GPIO_36"; function = "can0_b"; diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 3e6a0542e3ae..59073e053549 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -812,7 +812,7 @@ ethernet0: dwmac@9630000 { <&clk_s_c0_flexgen CLK_ETH_PHY>; }; - mailbox0: mailbox@8f00000 { + mailbox0: mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 6022e73f58af..1d6435c59096 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -382,7 +382,7 @@ goodix: goodix-ts@5d { VDDIO-supply = <&scmi_v3v3_sw>; touchscreen-size-x = <480>; touchscreen-size-y = <272>; - status = "okay" ; + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/xilinx/zynq-cc108.dts b/arch/arm/boot/dts/xilinx/zynq-cc108.dts index f5525c048426..e7cb82c7b8e6 100644 --- a/arch/arm/boot/dts/xilinx/zynq-cc108.dts +++ b/arch/arm/boot/dts/xilinx/zynq-cc108.dts @@ -92,8 +92,8 @@ partition@f00000 { &sdhci1 { status = "okay"; - broken-cd ; - wp-inverted ; + broken-cd; + wp-inverted; }; &uart0 { From 7c78d6fa9aec67a72a498cda5cdbaced890cb038 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 1 Aug 2026 23:02:12 +0200 Subject: [PATCH 810/864] arm64: dts: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Michal Simek # Versal NET Acked-by: Sven Peter # for apple dts Link: https://patch.msgid.link/20260801210210.383417-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 2 +- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 +- arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi | 2 +- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 2 +- arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi | 4 ++-- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 2 +- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 4 ++-- arch/arm64/boot/dts/xilinx/versal-net.dtsi | 4 ++-- 13 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index a1c5d10f2f54..91df4793dd6e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -546,7 +546,7 @@ &spdifout_b { }; &tdmif_a { - pinctrl-0 = <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>, <&tdm_a_dout0_pins> ; + pinctrl-0 = <&tdm_a_fs_pins>, <&tdm_a_sclk_pins>, <&tdm_a_dout0_pins>; pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index e930f2f26f4b..e110792cdc76 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -293,7 +293,7 @@ socpll: socpll@17000120 { clock-output-names = "socpll"; }; - socplldiv2: socplldiv2 { + socplldiv2: socplldiv2 { compatible = "fixed-factor-clock"; #clock-cells = <0>; clocks = <&socpll 0>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 4c4938faffb1..d67f5ed985a2 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -174,7 +174,7 @@ socpll: socpll@17000120 { clock-output-names = "socpll"; }; - socplldiv2: socplldiv2 { + socplldiv2: socplldiv2 { compatible = "fixed-factor-clock"; #clock-cells = <0>; clocks = <&socpll 0>; diff --git a/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi index ee12fea5b12c..926bb4ab77af 100644 --- a/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-j474-j475.dtsi @@ -33,6 +33,6 @@ &hpm2 { interrupts = <44 IRQ_TYPE_LEVEL_LOW>; }; -&hpm3 { +&hpm3 { interrupts = <44 IRQ_TYPE_LEVEL_LOW>; }; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 761c59d90ffc..6a066c43d24a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -644,7 +644,7 @@ mip1: msi-controller@1000131000 { brcm,msi-offset = <8>; }; - isp: isp@1000880000 { + isp: isp@1000880000 { compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe"; reg = <0x10 0x00880000 0x0 0x4000>; interrupts = ; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index 82cd4115746e..afe4ef182ee7 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -107,7 +107,7 @@ qspi_boot: partition@0 { reg = <0x0 0x00c00000>; }; - root: partition@c00000 { + root: partition@c00000 { label = "root"; reg = <0x00c00000 0x03400000>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 06d4a3a93f84..efc32074bb11 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -109,7 +109,7 @@ gpio_exp: pca9555@22 { */ }; - rtc@68 { + rtc@68 { /* PT7C4337A from pericom fully compatible with the ds1337 */ compatible = "dallas,ds1337"; reg = <0x68>; diff --git a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi index 91ba5f7dc9b4..feffb9c299fd 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi @@ -353,7 +353,7 @@ cp0_mmc0_cd_pins: cp0-mmc0-cd-pins { marvell,function = "sdio_cd"; }; - cp0_pwrbtn_pins: cp0-pwrbtn-pins { + cp0_pwrbtn_pins: cp0-pwrbtn-pins { marvell,pins = "mpp31"; marvell,function = "gpio"; }; @@ -378,7 +378,7 @@ cp0_spi1_cs1_pins: cp0-spi1-cs1-pins { marvell,function = "spi1"; }; - cp0_uart2_pins: cp0-uart2-pins { + cp0_uart2_pins: cp0-uart2-pins { marvell,pins = "mpp50", "mpp51"; marvell,function = "uart2"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 16cf4414de59..6f4879c49da2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1159,7 +1159,7 @@ asrc_out5_ep: endpoint { }; }; - asrc_out6_port: port@c { + asrc_out6_port: port@c { reg = <0xc>; asrc_out6_ep: endpoint { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8e0c51e496e2..ff9b73d5db2a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1765,7 +1765,7 @@ asrc_out5_ep: endpoint { }; }; - asrc_out6_port: port@c { + asrc_out6_port: port@c { reg = <0xc>; asrc_out6_ep: endpoint { diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 2d8e7e37830f..8d52d9e7c711 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -1945,7 +1945,7 @@ asrc_out5_ep: endpoint { }; }; - asrc_out6_port: port@c { + asrc_out6_port: port@c { reg = <0xc>; asrc_out6_ep: endpoint { diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 14e033f365e3..b5db62a0a550 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -404,11 +404,11 @@ scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; - scmi_vddcore: regulator@11 { + scmi_vddcore: regulator@11 { reg = ; regulator-name = "vddcore"; }; - scmi_v1v8: regulator@14 { + scmi_v1v8: regulator@14 { reg = ; regulator-name = "v1v8"; }; diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index 15f767608e67..21bb917bcba1 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -1074,7 +1074,7 @@ usb0: usb@f1e00000 { #address-cells = <2>; #size-cells = <2>; - dwc3_0: usb@f1b00000 { + dwc3_0: usb@f1b00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0 0xf1b00000 0 0x10000>; @@ -1099,7 +1099,7 @@ usb1: usb@f1e10000 { #address-cells = <2>; #size-cells = <2>; - dwc3_1: usb@f1c00000 { + dwc3_1: usb@f1c00000 { compatible = "snps,dwc3"; status = "disabled"; reg = <0x0 0xf1c00000 0x0 0x10000>; From 5011466bade64483bb52bc4a926719d6794e6dab Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Mon, 11 May 2026 14:38:17 +0800 Subject: [PATCH 811/864] riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller Change the DMA controller compatible to the sophgo,cv1800b-axi-dma, which supports setting DMA channel number in DMA phandle args. This dts change does not break backward compatibility as a fallback compatiable string is added. Fixes: 514951a81a5e ("riscv: dts: sophgo: cv18xx: add DMA controller") Reported-by: Anton D. Stavinskii Closes: https://github.com/sophgo/linux/issues/9 Tested-by: Anton D. Stavinskii Link: https://patch.msgid.link/20260511063818.463877-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 06b0ce5a2db7..ecafdee79ac8 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -417,7 +417,7 @@ sdhci1: mmc@4320000 { }; dmac: dma-controller@4330000 { - compatible = "snps,axi-dma-1.01a"; + compatible = "sophgo,cv1800b-axi-dma", "snps,axi-dma-1.01a"; reg = <0x04330000 0x1000>; interrupts = ; clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; From 418bd91075ccee25828db79390848da1ab3ef0a7 Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Mon, 15 Jun 2026 08:03:23 -0400 Subject: [PATCH 812/864] riscv64: dts: sophgo: add SG2000 dtsi Adds sg2000.dtsi on the RISCV side. Signed-off-by: Joshua Milas Tested-by: Gui-Dong Han Reviewed-by: Gui-Dong Han Link: https://patch.msgid.link/20260615120324.1527881-3-josh.milas@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2000.dtsi | 53 ++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2000.dtsi diff --git a/arch/riscv/boot/dts/sophgo/sg2000.dtsi b/arch/riscv/boot/dts/sophgo/sg2000.dtsi new file mode 100644 index 000000000000..38462769574f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2000.dtsi @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16) + +#include +#include +#include "cv180x-cpus.dtsi" +#include "cv180x.dtsi" +#include "cv181x.dtsi" + +/ { + compatible = "sophgo,sg2000"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + soc { + interrupt-parent = <&plic>; + dma-noncoherent; + + pinctrl: pinctrl@3001000 { + compatible = "sophgo,sg2000-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + + clk: clock-controller@3002000 { + compatible = "sophgo,sg2000-clk"; + reg = <0x03002000 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,sg2000-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,sg2000-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; From 66153532fb18474c83f9bcbb27b039c7788e664f Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Mon, 15 Jun 2026 08:03:24 -0400 Subject: [PATCH 813/864] riscv64: dts: sophgo: add initial Milk-V Duo S board support This adds initial riscv support for the Milk-V Duo S board [1] making it possible to boot Linux to the command line. Link: https://milkv.io/duo-s [1] Signed-off-by: Joshua Milas Link: https://milkv.io/duo-s [1] Link: https://patch.msgid.link/20260615120324.1527881-4-josh.milas@gmail.com Signed-off-by: Inochi Amaoto # Trim empty line Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/Makefile | 1 + .../boot/dts/sophgo/sg2000-milkv-duo-s.dts | 244 ++++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 6f65526d4193..58cc6b70d8de 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-s.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts b/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts new file mode 100644 index 000000000000..78a257839f6f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2000-milkv-duo-s.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include +#include "sg2000.dtsi" + +/ { + model = "Milk-V Duo S"; + compatible = "milkv,duo-s", "sophgo,sg2000"; + + aliases { + i2c4 = &i2c4; + mmc0 = &sdhci0; + mmc1 = &emmc; + mmc2 = &sdhci1; + serial0 = &uart0; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&porta 15 GPIO_ACTIVE_LOW>; + power-off-delay-us = <50000>; + post-power-on-delay-ms = <200>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&pinctrl { + emmc_cfg: emmc-cfg { + emmc-rstn-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + emmc-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + emmc-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + emmc-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + }; + + i2c4_cfg: i2c4-cfg { + i2c4-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <4000>; + power-source = <1800>; + }; + }; + + sdhci0_cfg: sdhci0-cfg { + sdhci0-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <16100>; + power-source = <3300>; + }; + + sdhci0-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + sdhci1_cfg: sdhci1-cfg { + sdhci1-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + sdhci1-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + sdhci1-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + uart4_cfg: uart4-cfg { + uart4-data-pins { + pinmux = , + ; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + uart4-control-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; +}; + +&dmac { + status = "okay"; +}; + +&emmc { + bus-width = <4>; + no-1-8-v; + cap-mmc-hw-reset; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&sdhci0 { + bus-width = <4>; + disable-wp; + no-1-8-v; + pinctrl-0 = <&sdhci0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + no-mmc; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-pwrseq = <&wifi_pwrseq>; + pinctrl-0 = <&sdhci1_cfg>; + pinctrl-names = "default"; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4_cfg>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; From 06c236909705fcc92f59b0f2dd05a45b22902769 Mon Sep 17 00:00:00 2001 From: Chen-Yu Yeh Date: Sun, 26 Jul 2026 01:53:43 +0800 Subject: [PATCH 814/864] dt-bindings: soc: sophgo: add Milk-V Duo 256M board Add compatible string for the Milk-V Duo 256M board. Signed-off-by: Chen-Yu Yeh Acked-by: Conor Dooley Link: https://patch.msgid.link/20260725175346.139173-2-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index 0b6fbab48b74..99194d8721ef 100644 --- a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -35,6 +35,10 @@ properties: - enum: - milkv,duo-s - const: sophgo,sg2000 + - items: + - enum: + - milkv,duo256m + - const: sophgo,sg2002 - items: - enum: - sipeed,licheerv-nano-b From 76237a509a0e91665c4d9c96b72a78ec66ea3fe4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Yeh Date: Sun, 26 Jul 2026 01:53:44 +0800 Subject: [PATCH 815/864] riscv: dts: sophgo: cv180x: Add PWR_GPIO controller The CV180x/CV181x family has an additional DesignWare APB GPIO controller (PWR_GPIO) located in the always-on power domain at 0x5021000. Add the node so that boards can reference GPIOs in this bank, such as status LEDs. Signed-off-by: Chen-Yu Yeh Link: https://patch.msgid.link/20260725175346.139173-3-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index ecafdee79ac8..ec3bf305274a 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -448,6 +448,24 @@ usb: usb@4340000 { status = "disabled"; }; + gpio4: gpio@5021000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; + rtc@5025000 { compatible = "sophgo,cv1800b-rtc", "syscon"; reg = <0x5025000 0x2000>; From 59c682ffc76ebda27ecbbbd1423e23ec482d61b9 Mon Sep 17 00:00:00 2001 From: Chen-Yu Yeh Date: Sun, 26 Jul 2026 01:53:45 +0800 Subject: [PATCH 816/864] riscv: dts: sophgo: Add Milk-V Duo 256M board support The Milk-V Duo 256M is a small form factor development board based on the Sophgo SG2002 SoC. This patch adds basic device tree support for the board, including: - UART console - SD/MMC controller - USB host - Onboard blue status LED (connected to PWR_GPIO[2] / porte 2) Tested on actual Milk-V Duo 256M hardware, verified boot to shell and heartbeat LED functionality. Signed-off-by: Chen-Yu Yeh Link: https://patch.msgid.link/20260725175346.139173-4-chenyou910331@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/Makefile | 1 + .../boot/dts/sophgo/sg2002-milkv-duo256m.dts | 121 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 58cc6b70d8de..d5c80d4ff005 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-s.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-milkv-duo256m.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v1.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-evb-v2.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts b/arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts new file mode 100644 index 000000000000..a2797c0bd767 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2002-milkv-duo256m.dts @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2026 Chen-Yu Yeh + */ + +/dts-v1/; + +#include "sg2002.dtsi" +#include +#include + +/ { + model = "Milk-V Duo 256M"; + compatible = "milkv,duo256m", "sophgo,sg2002"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&porte 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + coprocessor_rtos: region@8fe00000 { + reg = <0x8fe00000 0x200000>; + no-map; + }; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&pinctrl { + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + sdhci0_cfg: sdhci0-cfg { + sdhci0-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <16100>; + power-source = <3300>; + }; + + sdhci0-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; +}; + +&sdhci0 { + pinctrl-0 = <&sdhci0_cfg>; + pinctrl-names = "default"; + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + disable-wp; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; From d5e1ea5b05fe62c296701251c628ced6c68a6a80 Mon Sep 17 00:00:00 2001 From: Joshua Milas Date: Mon, 15 Jun 2026 08:03:22 -0400 Subject: [PATCH 817/864] arm64: dts: sophgo: add initial Milk-V Duo S board support Adds initial arm64 support for the Milk-V Duo S board [1] making it possible to boot Linux to the command line. Link: https://milkv.io/duo-s [1] Signed-off-by: Joshua Milas Link: https://milkv.io/duo-s [1] Link: https://patch.msgid.link/20260615120324.1527881-2-josh.milas@gmail.com Signed-off-by: Inochi Amaoto # Trim empty line Signed-off-by: Chen Wang --- arch/arm64/boot/dts/sophgo/Makefile | 1 + .../boot/dts/sophgo/sg2000-milkv-duo-s.dts | 244 ++++++++++++++++++ 2 files changed, 245 insertions(+) create mode 100644 arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts diff --git a/arch/arm64/boot/dts/sophgo/Makefile b/arch/arm64/boot/dts/sophgo/Makefile index 94f52cd7d994..68aace728223 100644 --- a/arch/arm64/boot/dts/sophgo/Makefile +++ b/arch/arm64/boot/dts/sophgo/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-module-01-evb.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2000-milkv-duo-s.dtb diff --git a/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts new file mode 100644 index 000000000000..78a257839f6f --- /dev/null +++ b/arch/arm64/boot/dts/sophgo/sg2000-milkv-duo-s.dts @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include +#include "sg2000.dtsi" + +/ { + model = "Milk-V Duo S"; + compatible = "milkv,duo-s", "sophgo,sg2000"; + + aliases { + i2c4 = &i2c4; + mmc0 = &sdhci0; + mmc1 = &emmc; + mmc2 = &sdhci1; + serial0 = &uart0; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&porta 15 GPIO_ACTIVE_LOW>; + power-off-delay-us = <50000>; + post-power-on-delay-ms = <200>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&pinctrl { + emmc_cfg: emmc-cfg { + emmc-rstn-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + emmc-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + emmc-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + emmc-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + }; + + i2c4_cfg: i2c4-cfg { + i2c4-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <4000>; + power-source = <1800>; + }; + }; + + sdhci0_cfg: sdhci0-cfg { + sdhci0-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <16100>; + power-source = <3300>; + }; + + sdhci0-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + sdhci1_cfg: sdhci1-cfg { + sdhci1-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + sdhci1-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + + sdhci1-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <1800>; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + uart4_cfg: uart4-cfg { + uart4-data-pins { + pinmux = , + ; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + uart4-control-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; +}; + +&dmac { + status = "okay"; +}; + +&emmc { + bus-width = <4>; + no-1-8-v; + cap-mmc-hw-reset; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&emmc_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&sdhci0 { + bus-width = <4>; + disable-wp; + no-1-8-v; + pinctrl-0 = <&sdhci0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + no-mmc; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-pwrseq = <&wifi_pwrseq>; + pinctrl-0 = <&sdhci1_cfg>; + pinctrl-names = "default"; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&uart4_cfg>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&usb { + dr_mode = "host"; + status = "okay"; +}; From 3e6a70436d363dec92b3e6c089ab3d2d5f11d8b9 Mon Sep 17 00:00:00 2001 From: Xueyao An Date: Mon, 3 Aug 2026 16:56:30 +0530 Subject: [PATCH 818/864] arm64: dts: qcom: shikra: Add QUPv3 configuration Add device tree support for QUPv3 serial engine protocols on Shikra. Shikra has 10 QUP serial engines under a single QUP wrapper, all with support of GPI DMA engines. Signed-off-by: Xueyao An Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-1-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++ 1 file changed, 951 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 80e8045282d8..524c88615d08 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -348,6 +349,161 @@ tlmm: pinctrl@500000 { gpio-ranges = <&tlmm 0 0 165>; wakeup-parent = <&mpm>; + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio2", "gpio3"; + function = "qup0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio6", "gpio7"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio10", "gpio11"; + function = "qup0_se3_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup0_se4_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio14", "gpio15"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio18", "gpio19"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup0_se7_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio22", "gpio23"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio27", "gpio26"; + function = "qup0_se9_01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio1"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio2", "gpio3", "gpio0"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio9"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio6", "gpio7", "gpio8"; + function = "qup0_se2"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio17"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio14", "gpio15", "gpio16"; + function = "qup0_se5"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio29"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio18", "gpio19", "gpio28"; + function = "qup0_se6"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio25"; + function = "qup0_se8"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio22", "gpio23", "gpio24"; + function = "qup0_se8"; + drive-strength = <6>; + bias-disable; + }; + qup_uart0_default: qup-uart0-default-state { pins = "gpio0", "gpio1"; function = "qup0_se0"; @@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state { bias-disable; }; + qup_uart1_default: qup-uart1-default-state { + pins = "gpio4", "gpio5"; + function = "qup0_se1_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart2_default: qup-uart2-default-state { + /* TX, RX */ + pins = "gpio8", "gpio9"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart2_cts_rts: qup-uart2-cts-rts-state { + /* CTS, RTS */ + pins = "gpio6", "gpio7"; + function = "qup0_se2"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart3_default: qup-uart3-default-state { + pins = "gpio10", "gpio11"; + function = "qup0_se3_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup0_se4_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio16", "gpio17"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart5_cts_rts: qup-uart5-cts-rts-state { + /* CTS, RTS */ + pins = "gpio14", "gpio15"; + function = "qup0_se5"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart6_default: qup-uart6-default-state { + /* TX, RX */ + pins = "gpio28", "gpio29"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart6_cts_rts: qup-uart6-cts-rts-state { + /* CTS, RTS */ + pins = "gpio18", "gpio19"; + function = "qup0_se6"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart7_default: qup-uart7-default-state { + pins = "gpio20", "gpio21"; + function = "qup0_se7_23"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart8_default: qup-uart8-default-state { + /* TX, RX */ + pins = "gpio24", "gpio25"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart8_cts_rts: qup-uart8-cts-rts-state { + /* CTS, RTS */ + pins = "gpio22", "gpio23"; + function = "qup0_se8"; + drive-strength = <2>; + bias-pull-down; + }; + + qup_uart9_default: qup-uart9-default-state { + pins = "gpio26", "gpio27"; + function = "qup0_se9_23"; + drive-strength = <2>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -604,6 +859,34 @@ opp-384000000 { }; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x04a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <16>; + dma-channel-mask = <0xff>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xf6 0x0>; + }; + qupv3_0: geniqup@4ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x04ac0000 0x0 0x2000>; @@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 { clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; #size-cells = <2>; ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart0: serial@4a80000 { compatible = "qcom,geni-debug-uart"; reg = <0x0 0x04a80000 0x0 0x4000>; @@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, status = "disabled"; }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart1: serial@4a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart1_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a88000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart2: serial@4a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a88000 0x0 0x4000>; + + interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>, + <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart3: serial@4a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart3_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@4a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c6: i2c@4a98000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@4a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart6: serial@4a98000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a98000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c7: i2c@4a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart7: serial@4a9c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c8: i2c@4aa0000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>, + <&gpi_dma0 1 8 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi8: spi@4aa0000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x4aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>, + <&gpi_dma0 1 8 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart8: serial@4aa0000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04aa0000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + i2c9: i2c@4aa4000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x4aa4000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, + <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>, + <&gpi_dma0 1 9 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart9: serial@4aa4000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04aa4000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; }; sram@c11e000 { From 9e5bbfecb523aef0d01241b13d705ca8a48d7d7d Mon Sep 17 00:00:00 2001 From: Sayantan Chakraborty Date: Mon, 3 Aug 2026 16:56:31 +0530 Subject: [PATCH 819/864] arm64: dts: qcom: shikra: Add DDR BWMON support Add CPU-to-DDR BWMON nodes and their corresponding opp tables for Shikra SoC. This is necessary to enable power management and optimize system performance from the perspective of dynamically changing DDR frequencies. Signed-off-by: Sayantan Chakraborty Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-2-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 524c88615d08..3582352dcff7 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -661,6 +661,46 @@ rclk-pins { }; }; + pmu@c91000 { + compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x00c91000 0x0 0x1000>; + + interrupts = ; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <1200000>; + }; + + opp-1 { + opp-peak-kBps = <2188000>; + }; + + opp-2 { + opp-peak-kBps = <3072000>; + }; + + opp-3 { + opp-peak-kBps = <4068000>; + }; + + opp-4 { + opp-peak-kBps = <6220000>; + }; + + opp-5 { + opp-peak-kBps = <7216000>; + }; + }; + }; + mem_noc: interconnect@d00000 { compatible = "qcom,shikra-mem-noc-core"; reg = <0x0 0x00d00000 0x0 0x43080>; From aadafe002c9836da43a890f3bcba0a7ab8a69a1e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:32 +0530 Subject: [PATCH 820/864] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs. Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables required to scale DDR and L3 per freq-domain on Shikra SoC. Co-developed-by: Aastha Pandey Signed-off-by: Aastha Pandey Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sayantan Chakraborty Signed-off-by: Sayantan Chakraborty Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-3-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 140 +++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 3582352dcff7..a01e26d9ee6d 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,14 @@ cpu0: cpu@0 { next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu1: cpu@100 { @@ -54,6 +63,14 @@ cpu1: cpu@100 { next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu2: cpu@200 { @@ -64,6 +81,14 @@ cpu2: cpu@200 { next-level-cache = <&l3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + clocks = <&cpufreq_hw 0>; + qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; }; cpu3: cpu@300 { @@ -74,6 +99,14 @@ cpu3: cpu@300 { next-level-cache = <&l2_3>; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <489>; + clocks = <&cpufreq_hw 1>; + qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; + operating-points-v2 = <&cpu3_opp_table>; + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; l2_3: l2-cache { compatible = "cache"; @@ -132,6 +165,86 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <1200000 17817600>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + opp-peak-kBps = <3072000 30105600>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 38707200>; + }; + + opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <7216000 43622400>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <7216000 43622400>; + }; + }; + + cpu3_opp_table: opp-table-cpu3 { + compatible = "operating-points-v2"; + opp-shared; + + opp-768000000 { + opp-hz = /bits/ 64 <768000000>; + opp-peak-kBps = <1200000 17817600>; + }; + + opp-1017600000 { + opp-hz = /bits/ 64 <1017600000>; + opp-peak-kBps = <2188000 25804800>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + opp-peak-kBps = <3072000 30105600>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <4068000 38707200>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <6220000 43008000>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <7216000 43622400>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <7216000 43622400>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = ; @@ -1820,6 +1933,33 @@ frame@f42d000 { status = "disabled"; }; }; + + epss_l3: interconnect@fd90000 { + compatible = "qcom,shikra-epss-l3"; + reg = <0x0 0x0fd90000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@fd91000 { + compatible = "qcom,shikra-epss"; + reg = <0x0 0x0fd91000 0x0 0x1000>, + <0x0 0x0fd92000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; }; timer { From 4a0123734f43acef97cf4e7e05ec33f530e2dbe5 Mon Sep 17 00:00:00 2001 From: Vishnu Santhosh Date: Mon, 3 Aug 2026 16:56:33 +0530 Subject: [PATCH 821/864] arm64: dts: qcom: shikra: Add SMP2P nodes Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable inter-processor signalling for remoteproc state management. Signed-off-by: Vishnu Santhosh Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-4-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a01e26d9ee6d..42a17ffc040f 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -428,6 +428,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 { }; }; + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + + interrupts = ; + + mboxes = <&apcs_glb 6>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-lmcu { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + + interrupts = ; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <26>; + + lmcu_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + lmcu_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; From 8b6f81f7801a44c0ad141c3bda5537daa5611993 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 3 Aug 2026 16:56:34 +0530 Subject: [PATCH 822/864] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem. Signed-off-by: Bibek Kumar Patro Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-5-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 42a17ffc040f..570505c927bb 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1813,6 +1813,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, }; }; + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,shikra-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&mpss_wlan_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 12>; + qcom,remote-pid = <1>; + label = "mpss"; + }; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + + fastrpc { + compatible = "qcom,fastrpc"; + #address-cells = <1>; + #size-cells = <0>; + label = "cdsp"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0201 0x0000>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0202 0x0000>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0203 0x0000>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0204 0x0000>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0205 0x0000>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0206 0x0000>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&apps_smmu 0x0209 0x0000>; + }; + }; + }; + }; + + remoteproc_lpaicp: remoteproc@b800000 { + compatible = "qcom,shikra-lpaicp-pas"; + reg = <0x0 0x0b800000 0x0 0x200000>; + + interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>, + <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>, + <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>; + + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&lmcu_mem &lmcu_dtb_mem>; + + qcom,smem-states = <&lmcu_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 9>; + qcom,remote-pid = <26>; + label = "lpaicp"; + }; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "mmio-sram"; reg = <0x0 0x0c11e000 0x0 0x1000>; From 1db66deb4af8c4121172dfd13aff4cabfacf4534 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Mon, 3 Aug 2026 16:56:35 +0530 Subject: [PATCH 823/864] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and IQS EVK board. Signed-off-by: Bibek Kumar Patro Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-6-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts index 0a52ab9b7a4c..b112b21b1d79 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index b3f19a64d7ae..e62ba5aef71f 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm4125_l20>; vqmmc-supply = <&pm4125_l14>; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index 3003a47bd759..727809430fd1 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -23,6 +23,25 @@ chosen { }; }; +&remoteproc_cdsp { + firmware-name = "qcom/shikra/cdsp.mbn"; + + status = "okay"; +}; + +&remoteproc_lpaicp { + firmware-name = "qcom/shikra/lpaicp.mbn", + "qcom/shikra/lpaicp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn"; + + status = "okay"; +}; + &sdhc_1 { vmmc-supply = <&pm8150_l17>; vqmmc-supply = <&pm8150_s4>; From adf87a37cfc9bbdcac4951bdccfb258a1a44ac0f Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Mon, 3 Aug 2026 16:56:36 +0530 Subject: [PATCH 824/864] arm64: dts: qcom: shikra: Enable TSENS and thermal zones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The shikra includes one TSENS instance, with a total of 14 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 120°C in the hardware. Enable all TSENS instances, and define the thermal zones with a hot trip at 110°C and critical trip at 115°C. Signed-off-by: Gaurav Kohli Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-7-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++ 1 file changed, 267 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 570505c927bb..fb0391bef460 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -998,6 +999,18 @@ spmi_bus: spmi@1c40000 { qcom,ee = <0>; }; + tsens0: thermal-sensor@4411000 { + compatible = "qcom,shikra-tsens", "qcom,tsens-v2"; + reg = <0x0 0x04411000 0x0 0x1000>, + <0x0 0x04410000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", + "critical"; + #qcom,sensors = <14>; + #thermal-sensor-cells = <1>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0x0 0x045f0000 0x0 0x7000>; @@ -2195,6 +2208,260 @@ cpufreq_hw: cpufreq@fd91000 { }; }; + thermal_zones: thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu00-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu01-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu10-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-1-1-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu11-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + gpuss-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsp-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + nsp-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss0-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + mdmss1-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + mdmss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + camera-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + video-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu-0-2-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpu02-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <110000>; + hysteresis = <5000>; + type = "hot"; + }; + + cpuss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; From a04957d5ef041059d26fabe8d1a754e6c408fe2a Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:37 +0530 Subject: [PATCH 825/864] arm64: dts: qcom: shikra: add WiFi node support Introduce the WiFi hardware description in shikra.dtsi, including register space, interrupts, IOMMU configuration and reserved memory. The node is kept disabled by default and is intended to be enabled by board-specific device trees. Signed-off-by: Miaoqing Pan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-8-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index fb0391bef460..efb02e8719e9 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2079,6 +2079,29 @@ apps_smmu: iommu@c600000 { ; }; + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x0c800000 0x0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + + status = "disabled"; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0xf200000 0x0 0x10000>, From 320670a802179ac0851f010f78053da0731c6da8 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:38 +0530 Subject: [PATCH 826/864] arm64: dts: qcom: shikra: Enable WiFi/BT on SoMs Shikra SoM cards include WCN3988 WiFi/Bluetooth chip, with supplies provided by on-card PMICs. Enable both interfaces and provide the required supply and calibration data. Co-developed-by: Yepuri Siddu Signed-off-by: Yepuri Siddu Co-developed-by: Miaoqing Pan Signed-off-by: Miaoqing Pan Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-9-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 74 ++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 82 ++++++++++++++++++++ 2 files changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index dc3861489f64..2fff5fe9f6d2 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -11,6 +11,10 @@ #include "pm8005.dtsi" / { + aliases { + serial1 = &uart8; + }; + gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; @@ -27,6 +31,42 @@ key-volume-up { linux,can-disable; }; }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm4125_l7>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &pm4125_gpios { @@ -154,3 +194,37 @@ pm4125_l22: l22 { }; }; }; + +&tlmm { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart8 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + max-speed = <3200000>; + + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "shikra"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index 73945bf42112..657a14ca9606 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -10,6 +10,10 @@ #include "pm8150.dtsi" / { + aliases { + serial1 = &uart8; + }; + gpio-key { compatible = "gpio-keys"; label = "gpio-keys"; @@ -26,6 +30,50 @@ key-volume-up { linux,can-disable; }; }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + regulator-name = "wcn_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + wcn3988-pmu { + compatible = "qcom,wcn3988-pmu"; + + pinctrl-0 = <&sw_ctrl_default>; + pinctrl-names = "default"; + + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + + vddio-supply = <&pm8150_s4>; + vddxo-supply = <&pm8150_l12>; + vddrf-supply = <&pm8150_l8>; + vddch0-supply = <&vreg_wcn_3p3>; + + regulators { + vreg_pmu_io: ldo0 { + regulator-name = "vreg_pmu_io"; + }; + + vreg_pmu_xo: ldo1 { + regulator-name = "vreg_pmu_xo"; + }; + + vreg_pmu_rf: ldo2 { + regulator-name = "vreg_pmu_rf"; + }; + + vreg_pmu_ch0: ldo3 { + regulator-name = "vreg_pmu_ch0"; + }; + + vreg_pmu_ch1: ldo4 { + regulator-name = "vreg_pmu_ch1"; + }; + }; + }; }; &pm8150_gpios { @@ -168,3 +216,37 @@ pm8150_l18: l18 { }; }; }; + +&tlmm { + sw_ctrl_default: sw-ctrl-default-state { + pins = "gpio88"; + function = "gpio"; + bias-pull-down; + }; +}; + +&uart8 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + max-speed = <3200000>; + + vddio-supply = <&vreg_pmu_io>; + vddxo-supply = <&vreg_pmu_xo>; + vddrf-supply = <&vreg_pmu_rf>; + vddch0-supply = <&vreg_pmu_ch0>; + }; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm8150_s4>; + vdd-1.8-xo-supply = <&vreg_pmu_xo>; + vdd-1.3-rfa-supply = <&vreg_pmu_rf>; + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>; + + qcom,calibration-variant = "Shikra_EVK"; + firmware-name = "shikra"; + + status = "okay"; +}; From 779aead2dace11c7a514c0b94f87c0f2dcf59ca3 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 3 Aug 2026 16:56:39 +0530 Subject: [PATCH 827/864] arm64: dts: qcom: shikra: Add gpio-reserved-ranges to tlmm Add gpio-reserved-ranges property to the TLMM node for both Shikra SoM variants (CQM and IQS). These reserved GPIOs are inaccessible from the non-secure world and dedicated to fixed functions. Co-developed-by: Anurag Pateriya Signed-off-by: Anurag Pateriya Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20260803-shikra-dt-m1-v7-10-7fec8e777076@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 6 ++++++ arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi index 2fff5fe9f6d2..8ac42ff625a0 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -196,6 +196,12 @@ pm4125_l22: l22 { }; &tlmm { + gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */ + <14 4>, /* eSE SPI */ + <30 2>, /* NFC SPI */ + <138 1>, /* NFC Secure IO */ + <155 11>; /* eMMC Boot */ + sw_ctrl_default: sw-ctrl-default-state { pins = "gpio88"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi index 657a14ca9606..4ff97945274d 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -218,6 +218,12 @@ pm8150_l18: l18 { }; &tlmm { + gpio-reserved-ranges = <6 4>, /* Fingerprint SPI */ + <14 4>, /* eSE SPI */ + <30 2>, /* NFC SPI */ + <138 1>, /* NFC Secure IO */ + <155 11>; /* eMMC Boot */ + sw_ctrl_default: sw-ctrl-default-state { pins = "gpio88"; function = "gpio"; From 26d7b23caa4b1d8208e28c5981a85cf83e658e7c Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Sat, 18 Jul 2026 18:26:19 +0530 Subject: [PATCH 828/864] arm64: dts: qcom: agatti: Add missing CX power domain to DISPCC Add the missing power-domains property to associate DISPCC with CX rail. This is to ensure the genpd performance state votes on the GDSC to get propagated to the CX rail and to avoid the rail under-voltage conditions. Fixes: a2b32096709d ("arm64: dts: qcom: qcm2290: Add display nodes") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-12-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index f0b6ae9b8152..590bd2432d85 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2197,6 +2197,7 @@ dispcc: clock-controller@5f00000 { "gcc_disp_gpll0_div_clk_src", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk"; + power-domains = <&rpmpd QCM2290_VDDCX>; #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; From 58a273157af32b7d8e6fbd7930db3a5044c2ad10 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Sat, 18 Jul 2026 18:26:23 +0530 Subject: [PATCH 829/864] arm64: dts: qcom: shikra: Add support for DISPCC/GPUCC nodes Add support for Display clock controller and GPU clock controller nodes on Qualcomm Shikra SoCs. Reviewed-by: Dmitry Baryshkov Signed-off-by: Imran Shaik Link: https://lore.kernel.org/r/20260718-shikra-dispcc-gpucc-v6-16-62703e05ef0f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/shikra.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index efb02e8719e9..92d22e3b6931 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -3,6 +3,8 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include +#include #include #include #include @@ -1990,6 +1992,40 @@ glink-edge { }; }; + gpucc: clock-controller@5990000 { + compatible = "qcom,shikra-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@5f00000 { + compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; + reg = <0x0 0x05f00000 0x0 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_CLK_SRC>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, + <0>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "gcc_disp_gpll0_clk_src", + "gcc_disp_gpll0_div_clk_src", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk"; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + sram@c11e000 { compatible = "qcom,shikra-imem", "mmio-sram"; reg = <0x0 0x0c11e000 0x0 0x1000>; From ff7155df9a9543af1eb9722563e6dcda33c1a97d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:00 +0200 Subject: [PATCH 830/864] arm64: dts: qcom: sc8280xp-blackrock: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 16a7fed11714 ("arm64: dts: qcom: sc8280xp-blackrock: dt definition for WDK2023") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-2-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 9da2ffb318d0..4f4b5f4285ec 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -996,8 +996,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4d>; - vdda-pll-supply = <&vreg_l9d>; + vdda-phy-supply = <&vreg_l9d>; + vdda-pll-supply = <&vreg_l4d>; orientation-switch; @@ -1033,8 +1033,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3b>; - vdda-pll-supply = <&vreg_l4b>; + vdda-phy-supply = <&vreg_l4b>; + vdda-pll-supply = <&vreg_l3b>; orientation-switch; From 1960614611142e4b57f8a4e276f36ff8b6db2a1d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:01 +0200 Subject: [PATCH 831/864] arm64: dts: qcom: sa8540p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 519183af39b2 ("arm64: dts: qcom: add SA8540P and ADP") Fixes: 6be310347c9c ("arm64: dts: qcom: add SA8540P ride(Qdrive-3)") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-3-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 16 ++++++++-------- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 512de3597581..6ea60cdf1823 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -612,8 +612,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; @@ -636,8 +636,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l4c>; - vdda-pll-supply = <&vreg_l1c>; + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4c>; status = "okay"; }; @@ -679,15 +679,15 @@ &usb_2_hsphy3 { }; &usb_2_qmpphy0 { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; &usb_2_qmpphy1 { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 83d5f1d9e79b..c72faaa0ae7a 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -482,8 +482,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; @@ -497,8 +497,8 @@ &usb_2_hsphy0 { }; &usb_2_qmpphy0 { - vdda-phy-supply = <&vreg_l3a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l3a>; status = "okay"; }; From ce18e4c1cfc77c2eda5f0b9839edac1b0e929c54 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:02 +0200 Subject: [PATCH 832/864] arm64: dts: qcom: sdm845: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Fixes: a678adbf2d22 ("arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL") Fixes: 28ae8aa3923c ("arm64: dts: qcom: add device tree for LG G7 and LG V35") Fixes: cfe10d38aa1a ("arm64: dts: qcom: sdm845-mtp: Add nodes for USB") Fixes: d711b22eee55 ("arm64: dts: qcom: starqltechn: add initial device tree for starqltechn") Fixes: 45882459159d ("arm64: dts: qcom: sdm845: add device tree for SHIFT6mq") Fixes: dd6459a0890a ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts") Fixes: be497abe19bf ("arm64: dts: qcom: Add support for Xiaomi Mi Mix2s") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-4-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 4 ++-- .../boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 4 ++-- 8 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 02416812b6a7..846138149b2c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1121,8 +1121,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &usb_2 { @@ -1147,8 +1147,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi index 9368fd6b8751..9e952f9862f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -571,8 +571,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi index 5ac2e058827c..b030a10009c5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-lg-common.dtsi @@ -674,8 +674,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 97c79b51ff42..c66df45eee64 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -727,8 +727,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; }; &usb_2 { @@ -759,8 +759,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index a404a23086d4..bd59f1dcd96d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -947,8 +947,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index e31c784eff3d..1b0eaeafbd51 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -874,8 +874,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index cc14d9fa3b05..080f5294988d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -643,8 +643,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l26a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p875>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 96d4f7496f2f..d3162e444453 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -666,8 +666,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-pll-supply = <&vreg_l1a_0p875>; - vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l26a_1p2>; + vdda-phy-supply = <&vreg_l1a_0p875>; status = "okay"; }; From ef7b567f54c72a91dec3fb0bd5d80b8e956f7cd8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:03 +0200 Subject: [PATCH 833/864] arm64: dts: qcom: sdm850: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: aab69794b55d ("arm64: dts: qcom: Add support for Huawei MateBook E 2019") Fixes: 44acee207844 ("arm64: dts: qcom: Add Lenovo Yoga C630") Fixes: d4b341269efb ("arm64: dts: qcom: Add support for Samsung Galaxy Book2") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-5-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index e38b768d16a1..9b217580e1d5 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -870,8 +870,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; status = "okay"; }; @@ -896,8 +896,8 @@ &usb_2_hsphy { }; &usb_2_qmpphy { - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 981074a40e38..2bad7297cb7f 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -858,8 +858,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; }; &usb_1_qmpphy_out { @@ -951,8 +951,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 1dab0582eae6..d6a1d2542c1d 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -608,8 +608,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb1_ss_1p2>; - vdda-pll-supply = <&vdda_usb1_ss_core>; + vdda-phy-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_usb1_ss_1p2>; }; &usb_2 { @@ -634,8 +634,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb2_ss_1p2>; - vdda-pll-supply = <&vdda_usb2_ss_core>; + vdda-phy-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_usb2_ss_1p2>; }; &venus { From 3a0c5af9fb0e835e90c4f2439dc4534301be8856 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:04 +0200 Subject: [PATCH 834/864] arm64: dts: qcom: sm8150: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0ab1b2d10afe ("arm64: dts: qcom: add sm8150 hdk dts") Fixes: b33d2868e8d3 ("arm64: dts: qcom: sm8150: Add USB and PHY device nodes") Fixes: d1f781db47a8 ("arm64: dts: qcom: add initial device-tree for Microsoft Surface Duo") Fixes: d0a6ce59ea4e ("arm64: dts: qcom: sm8150: Add support for SONY Xperia 1 / 5 (Kumano platform)") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-6-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 4 ++-- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 8fb04ce72f91..cdced5c848d3 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -801,8 +801,8 @@ &usb_2_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l18a_0p8>; + vdda-phy-supply = <&vreg_l18a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; }; @@ -812,8 +812,8 @@ &usb_1_qmpphy_out { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p875>; + vdda-phy-supply = <&vreg_l5a_0p875>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 835ef929ff2d..f37e11bde067 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -520,8 +520,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + vdda-phy-supply = <&vdda_usb_ss_dp_core_1>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 0f2d511624a8..6a6564d8d7f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -438,8 +438,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + vdda-phy-supply = <&vdda_usb_ss_dp_core_1>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index 70fd6455518b..6c2e2bf869d0 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -869,6 +869,6 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l18a_0p8>; + vdda-phy-supply = <&vreg_l18a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; From d57a10f2ebcf327bdecf8bb26e9f330b17b0b1a6 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:05 +0200 Subject: [PATCH 835/864] arm64: dts: qcom: sm8250: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 91ed0e90fc49 ("arm64: dts: qcom: add sm8250 hdk dts") Fixes: 221f0ef37f55 ("arm64: dts: sm8250-mtp: enable USB host nodes") Fixes: 69cdb97ef652 ("arm64: dts: qcom: sm8250: Add support for SONY Xperia 1 II / 5 II (Edo platform)") Fixes: 264beb3cbd0d ("arm64: dts: qcom: sm8250-xiaomi-pipa: Add initial device tree") Fixes: 52c90664f122 ("arm64: dts: qcom: qrb5165-rb5: Add USB support") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-7-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts | 4 ++-- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 690b484352ed..d6af679abe1a 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -1424,8 +1424,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_1_qmpphy_out { @@ -1451,8 +1451,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &vamacro { diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 3ea9d2b1a7d5..c1c673086df5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -438,14 +438,14 @@ &usb_2_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p92>; + vdda-phy-supply = <&vreg_l18a_0p92>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_1 { diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 51779b99176d..14c8ca602110 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -862,8 +862,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &usb_2 { @@ -885,8 +885,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index d8289b2698f3..51c0caaf4ea1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -715,8 +715,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts index 078ba13f8762..f11e4e244dff 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-pipa.dts @@ -515,8 +515,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l9a_1p2>; - vdda-pll-supply = <&vreg_l18a_0p9>; + vdda-phy-supply = <&vreg_l18a_0p9>; + vdda-pll-supply = <&vreg_l9a_1p2>; }; &ufs_mem_hc { From 65cd57115c379ff0d0a200ad5a857afb8042a63c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:06 +0200 Subject: [PATCH 836/864] arm64: dts: qcom: sm8350: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 9208c19f2124 ("arm64: dts: qcom: Introduce SM8350 HDK") Fixes: c16160cfa565 ("arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2") Fixes: 054b40a6111f ("arm64: dts: qcom: sm8350-mtp: enable USB nodes") Fixes: 5a077120bcf6 ("arm64: dts: qcom: sm8350-sagami: Wire up USB regulators and fix USB3") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-8-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 8 ++++---- .../arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 8 ++++---- arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 4 ++-- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index d98ec4bcfd87..bb93c3e9417b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -866,8 +866,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p88>; + vdda-phy-supply = <&vreg_l1b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_1_qmpphy_out { @@ -896,8 +896,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l5b_0p88>; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; /* PINCTRL - additions to nodes defined in sm8350.dtsi */ diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 6b10464e8774..442405ba5f6a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -356,8 +356,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p88>; + vdda-phy-supply = <&vreg_l1b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_2 { @@ -375,6 +375,6 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l5b_0p88>; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index b25f223d6190..410bb0befeea 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -354,8 +354,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p88>; + vdda-phy-supply = <&vreg_l1b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_2 { @@ -373,8 +373,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l5b_0p88>; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &ipa { diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index ba862b4f9890..4b62ee50da7b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -916,6 +916,6 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&pm8350_l6>; - vdda-pll-supply = <&pm8350_l1>; + vdda-phy-supply = <&pm8350_l1>; + vdda-pll-supply = <&pm8350_l6>; }; From 6469731fb66f40ab873bf4c9fd97d295b390e87f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:07 +0200 Subject: [PATCH 837/864] arm64: dts: qcom: sm8450: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.91V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 067b2b3616cd ("arm64: dts: qcom: Add SM8450 HDK DTS") Fixes: 27a0d0b846d9 ("arm64: dts: qcom: sm8450-qrd: Enable USB nodes") Fixes: 1620676b85f1 ("arm64: dts: qcom: sm8450-nagara: Separate out Nagara platform dtsi") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-9-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index b37998cd9a2c..4ade28f40cae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -1214,8 +1214,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p91>; + vdda-phy-supply = <&vreg_l1b_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 56db5f79f59d..4993059483e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -527,8 +527,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p91>; + vdda-phy-supply = <&vreg_l1b_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &usb_1_qmpphy_out { diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 6bd315e10992..4fb5627d8126 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -793,7 +793,7 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&pm8350_l6>; - vdda-pll-supply = <&pm8350_l1>; + vdda-phy-supply = <&pm8350_l1>; + vdda-pll-supply = <&pm8350_l6>; status = "okay"; }; From f35723d6b6a2f6d6fc3cf2fc3ff556436f76ebd4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:08 +0200 Subject: [PATCH 838/864] arm64: dts: qcom: sm8550: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: b5e25ded2721 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Fixes: 772e6bc4a0a9 ("arm64: dts: qcom: sm8550-mtp: Add USB PHYs and HC nodes") Fixes: d228efe88469 ("arm64: dts: qcom: sm8550-qrd: add QRD8550") Fixes: 39c596304e44 ("arm64: dts: qcom: Add SM8550 Xperia 1 V") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-10-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 58c71ac67da5..82fb10ed6b6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1649,8 +1649,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p88>; + vdda-phy-supply = <&vreg_l3f_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5769be83cfbd..7c634572c6b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -971,8 +971,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p91>; + vdda-phy-supply = <&vreg_l3f_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 144e105b734f..473ec4e27daf 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1549,8 +1549,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p88>; + vdda-phy-supply = <&vreg_l3f_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 0e6ed6fce614..367f6eae5e65 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -766,8 +766,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&pm8550vs_2_l3>; - vdda-pll-supply = <&pm8550ve_l3>; + vdda-phy-supply = <&pm8550ve_l3>; + vdda-pll-supply = <&pm8550vs_2_l3>; status = "okay"; }; From c0ea3b6339881c2a5fff0830557b1279d9681036 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:09 +0200 Subject: [PATCH 839/864] arm64: dts: qcom: qcs8550-aim300: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0b12da4e28d8 ("arm64: dts: qcom: add base AIM300 dtsi") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-11-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ebb643203b..ae301d78e071 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -412,8 +412,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3f_0p88>; + vdda-phy-supply = <&vreg_l3f_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; }; &xo_board { From f6a787a5e238599f3543c3dccf0abd6030dd48e3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:10 +0200 Subject: [PATCH 840/864] arm64: dts: qcom: qcm6490: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 9af6a9f32ad0 ("arm64: dts: qcom: Add base qcm6490 idp board dts") Fixes: a319cf4a4b09 ("arm64: dts: qcom: qcm6490: Introduce the Particle Tachyon") Fixes: eee9602ad649 ("arm64: dts: qcom: qcm6490: Add device-tree for Fairphone 5") Fixes: 249666e34c24 ("arm64: dts: qcom: add QCM6490 SHIFTphone 8") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-12-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index f072bd96c7d4..f41ad446a39e 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -1554,8 +1554,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b>; - vdda-pll-supply = <&vreg_l1b>; + vdda-phy-supply = <&vreg_l1b>; + vdda-pll-supply = <&vreg_l6b>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index bdc02260f902..58cce89a0c1c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -1141,8 +1141,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index 94eebb7de7b9..5bb33a8a9830 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -841,8 +841,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts index e5366cfd3a02..cf74b3664cf5 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-shift-otter.dts @@ -975,8 +975,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b>; - vdda-pll-supply = <&vreg_l1b>; + vdda-phy-supply = <&vreg_l1b>; + vdda-pll-supply = <&vreg_l6b>; status = "okay"; }; From 83185fc5f51e7fa2d02f02e2504ad7b002c2d1d8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:11 +0200 Subject: [PATCH 841/864] arm64: dts: qcom: qcs6490: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 04cf333afc75 ("arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts") Fixes: 1cde54c54b83 ("arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT") Fixes: f055a39f6874 ("arm64: dts: qcom: Add qcs6490-rubikpi3 board dts") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-13-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 90f2eebc349f..a13315bf0fb0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1419,8 +1419,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; mode-switch; orientation-switch; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 172dc0cbb532..31bafa2cf51d 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -1065,8 +1065,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index d8a9a7e47bdc..13e8e62f6205 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -1111,8 +1111,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p912>; + vdda-phy-supply = <&vreg_l1b_0p912>; + vdda-pll-supply = <&vreg_l6b_1p2>; status = "okay"; }; From a3b3a060b696d964c769a7d9dc5835c79e4fe964 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:12 +0200 Subject: [PATCH 842/864] arm64: dts: qcom: sm7225-fairphone-fp4: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 4cbea668767d ("arm64: dts: qcom: sm7225: Add device tree for Fairphone 4") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-14-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 711a120753ad..5d20ad93b0c5 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -1246,8 +1246,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l22a>; - vdda-pll-supply = <&vreg_l16a>; + vdda-phy-supply = <&vreg_l16a>; + vdda-pll-supply = <&vreg_l22a>; status = "okay"; }; From 2c45c4df3079acba14920b14286cebfea24ec603 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:13 +0200 Subject: [PATCH 843/864] arm64: dts: qcom: sc7180: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0b766e7fe5a2 ("arm64: dts: qcom: sc7180: Add USB related nodes") Fixes: 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") Fixes: 4a9f8f8f2ada ("arm64: dts: qcom: Add Acer Aspire 1") Fixes: de8eed359759 ("arm64: dts: qcom: Add support for ECS LIVA QC710") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-15-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index 1514da636269..d9c70897b6f1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -631,8 +631,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; + vdda-phy-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts index b84da371581b..3100fab18787 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-ecs-liva-qc710.dts @@ -563,8 +563,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; + vdda-phy-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index 0bce3eefca2e..acfb9937651d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -461,8 +461,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l4a_0p8>; + vdda-phy-supply = <&vreg_l4a_0p8>; + vdda-pll-supply = <&vreg_l3c_1p2>; }; &venus { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index cd4a0e281cf8..0e0bc8543f71 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -998,8 +998,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; + vdda-phy-supply = <&vdda_usb_ss_dp_core>; + vdda-pll-supply = <&vdda_usb_ss_dp_1p2>; }; &venus { From b3038aac412d14538f135e6509e657997fd6825d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:14 +0200 Subject: [PATCH 844/864] arm64: dts: qcom: sc7280: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 97a5b73b7058 ("arm64: dts: qcom: sc7280-idp: Add device tree files for IDP2") Fixes: 116f7cc43d28 ("arm64: dts: qcom: sc7280: Add herobrine-r1") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-16-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 6bb806931b79..96a7327f00a8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -545,8 +545,8 @@ &usb_1_hsphy { &usb_1_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l6b_1p2>; - vdda-pll-supply = <&vreg_l1b_0p8>; + vdda-phy-supply = <&vreg_l1b_0p8>; + vdda-pll-supply = <&vreg_l6b_1p2>; }; &uart7 { diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 9ae9af40f4d2..264029ff3f90 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -465,8 +465,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>; - vdda-pll-supply = <&vdd_a_usbssdp_0_core>; + vdda-phy-supply = <&vdd_a_usbssdp_0_core>; + vdda-pll-supply = <&vdd_a_usbssdp_0_1p2>; }; &usb_2_hsphy { From 8e1877c41c2ee4ad245e1c26c98f3b4cb2585162 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:15 +0200 Subject: [PATCH 845/864] arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 2ce38cc1e8fe ("arm64: dts: qcom: sc8180x: Introduce Primus") Fixes: 20dea72a393c ("arm64: dts: qcom: sc8180x: Introduce Lenovo Flex 5G") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-17-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 16 ++++++++-------- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 7601afc3d7bf..565e5a9979b1 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -611,15 +611,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; @@ -633,8 +633,8 @@ &usb_prim_hsphy { }; &usb_prim_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; @@ -674,8 +674,8 @@ &usb_sec_hsphy { }; &usb_sec_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index e34f4758ebe2..c10a936b320a 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -703,15 +703,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; status = "okay"; }; @@ -725,8 +725,8 @@ &usb_prim_hsphy { }; &usb_prim_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; @@ -762,8 +762,8 @@ &usb_sec_hsphy { }; &usb_sec_qmpphy { - vdda-phy-supply = <&vreg_l3c_1p2>; - vdda-pll-supply = <&vreg_l5e_0p88>; + vdda-phy-supply = <&vreg_l5e_0p88>; + vdda-pll-supply = <&vreg_l3c_1p2>; orientation-switch; From 4458dcd38295c8bd13957637ba98132ba3f089b0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:16 +0200 Subject: [PATCH 846/864] arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 5098ae93ce44 ("arm64: dts: qcom: Add HAMOA-IOT-SOM platform") Fixes: af241225893a ("arm64: dts: qcom: Add the Lenovo IdeaCentre Mini X") Fixes: ae5cee8e7349 ("arm64: dts: qcom: x1e80100-crd: Fix USB PHYs regulators") Fixes: 20676f7819d7 ("arm64: dts: qcom: x1e80100-qcp: Fix USB PHYs regulators") Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Fixes: 6516961352a1 ("arm64: dts: qcom: Add support for X1-based Asus Zenbook A14") Fixes: 45247fe17db2 ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree") Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Fixes: 0d72ccaa1e84 ("arm64: dts: qcom: Add support for X1-based Surface Pro 11") Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices") Fixes: 8cf65490cdb0 ("arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1") Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345") Fixes: 7b8a31e82b87 ("arm64: dts: qcom: Add X1E001DE Snapdragon Devkit for Windows") Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6") Fixes: e7733b42111c ("arm64: dts: qcom: Add support for Dell Inspiron 7441 / Latitude 7455") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-18-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 20 +++++++++---------- .../hamoa-lenovo-ideacentre-mini-01q8x10.dts | 20 +++++++++---------- .../boot/dts/qcom/x1-asus-vivobook-s15.dtsi | 20 +++++++++---------- .../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 20 +++++++++---------- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 20 +++++++++---------- arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 16 +++++++-------- .../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 12 +++++------ .../boot/dts/qcom/x1-microsoft-denali.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 20 +++++++++---------- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 20 +++++++++---------- .../dts/qcom/x1e80100-dell-xps13-9345.dts | 16 +++++++-------- .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 12 +++++------ .../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 16 +++++++-------- .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 16 +++++++-------- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 20 +++++++++---------- 15 files changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 9c5e77df0054..bc70fe5db96f 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -590,8 +590,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -611,8 +611,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -632,8 +632,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -670,15 +670,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts index bfb7cea56df9..284825008389 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-lenovo-ideacentre-mini-01q8x10.dts @@ -1101,8 +1101,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l1j>; + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1112,8 +1112,8 @@ &usb_1_ss0_qmpphy_out { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1138,8 +1138,8 @@ usb_1_ss1_qmpphy_out_dp: endpoint@0 { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1186,15 +1186,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi index 48c4ad648354..0dc7c1b5a14a 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-vivobook-s15.dtsi @@ -1226,8 +1226,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1256,8 +1256,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1277,8 +1277,8 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1342,15 +1342,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi index 66d566808f58..59cbbfbce490 100644 --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi @@ -1454,8 +1454,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1484,8 +1484,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1505,8 +1505,8 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1551,15 +1551,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi index 9602d65c8b3d..60db83b8985f 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1750,8 +1750,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1780,8 +1780,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1810,8 +1810,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1852,15 +1852,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi index d6de4da02dcd..4cda708455d8 100644 --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi @@ -1570,8 +1570,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1600,8 +1600,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1639,8 +1639,8 @@ &usb_mp_hsphy0 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1653,8 +1653,8 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi index 02708f23a865..dba8cee43e29 100644 --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi @@ -1466,8 +1466,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1496,8 +1496,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1533,8 +1533,8 @@ &usb_mp_hsphy0 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi index 7559557610ed..ce7d958ca687 100644 --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -1268,8 +1268,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1298,8 +1298,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index 2e38402e2c14..be1a8ac8c699 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1382,8 +1382,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1413,8 +1413,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1443,8 +1443,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1486,15 +1486,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 5d49df41be02..0bee2a3d6e7a 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1601,8 +1601,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1631,8 +1631,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1652,8 +1652,8 @@ &usb_1_ss1_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1717,15 +1717,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index ce7b10ea89b6..2be5a37c00cc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -1286,8 +1286,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1316,8 +1316,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1357,15 +1357,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index beb1475d7fa0..9eb2dfd99f20 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1564,8 +1564,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1594,8 +1594,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1624,8 +1624,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index f95b1f9f439d..e4a0b86847cd 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -1407,8 +1407,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p9>; + vdda-phy-supply = <&vreg_l1j_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1428,8 +1428,8 @@ &usb_1_ss0_qmpphy_out { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1497,16 +1497,16 @@ &usb_mp_hsphy1 { /* Right side USB-A (USB-SS 3) */ &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; /* Left side USB-A (USB-SS 4) */ &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p9>; + vdda-phy-supply = <&vreg_l3c_0p9>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 28342cb84ded..13d0f09e0c2a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1491,8 +1491,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l1j>; + vdda-phy-supply = <&vreg_l1j>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1521,8 +1521,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j>; - vdda-pll-supply = <&vreg_l2d>; + vdda-phy-supply = <&vreg_l2d>; + vdda-pll-supply = <&vreg_l2j>; status = "okay"; }; @@ -1565,15 +1565,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e>; - vdda-pll-supply = <&vreg_l3c>; + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l3e>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 8afbac349cc9..78380fec8839 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -1416,8 +1416,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1446,8 +1446,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1476,8 +1476,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1519,15 +1519,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; From 7c1d0ef2969e16a97bd03e8340f35a78c889120d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:17 +0200 Subject: [PATCH 847/864] arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 64a0277c9876 ("arm64: dts: qcom: Add PURWA-IOT-SOM platform") Fixes: d3f600dc452d ("arm64: dts: qcom: Add Lenovo ThinkBook 16 G7 QOY device tree") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-19-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi | 20 +++++++++---------- .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 20 +++++++++---------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi index fb2dcbc7c393..488e98413c3a 100644 --- a/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi @@ -588,8 +588,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -609,8 +609,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -630,8 +630,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -668,15 +668,15 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 9e6f679758a9..c2f21fcb1b09 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -1562,8 +1562,8 @@ &usb_1_ss0_hsphy { }; &usb_1_ss0_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l1j_0p8>; + vdda-phy-supply = <&vreg_l1j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1592,8 +1592,8 @@ &usb_1_ss1_hsphy { }; &usb_1_ss1_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay"; }; @@ -1632,8 +1632,8 @@ &usb_1_ss2_hsphy { }; &usb_1_ss2_qmpphy { - vdda-phy-supply = <&vreg_l2j_1p2>; - vdda-pll-supply = <&vreg_l2d_0p9>; + vdda-phy-supply = <&vreg_l2d_0p9>; + vdda-pll-supply = <&vreg_l2j_1p2>; /delete-property/ mode-switch; /delete-property/ orientation-switch; @@ -1686,8 +1686,8 @@ &usb_mp_hsphy0 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; @@ -1702,8 +1702,8 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l3e_1p2>; - vdda-pll-supply = <&vreg_l3c_0p8>; + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; status = "okay"; }; From 464fba94ac2e35b336e19c34336a07946da7128f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:18 +0200 Subject: [PATCH 848/864] arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 6fbdb3c1fac7 ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts") Fixes: a834911d50c1 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts") Fixes: 01061441029e ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board") Fixes: df260487f33c ("arm64: dts: qcom: add basic devicetree for Ayaneo Pocket S2 gaming console") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-20-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 0dc994f4e48d..6ddf30ecabfe 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1536,8 +1536,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 71c0355ece4b..41d0c7edc433 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1614,8 +1614,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index dd6e33d2dc5d..26045430d34a 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -886,8 +886,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 5709cfea1bfd..1fb78588a504 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1633,8 +1633,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3i_1p2>; - vdda-pll-supply = <&vreg_l3g_0p91>; + vdda-phy-supply = <&vreg_l3g_0p91>; + vdda-pll-supply = <&vreg_l3i_1p2>; status = "okay"; }; From 50c9658bc622888f9664a052fd98ef6026883ea5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:19 +0200 Subject: [PATCH 849/864] arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 2340f29e2b06 ("arm64: dts: qcom: sm8750: Add USB support for SM8750 MTP platform") Fixes: 530f824a4e18 ("arm64: dts: qcom: sm8750: Add USB support for SM8750 QRD platform") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-21-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 3837f6785320..9b5fbc004df4 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -1404,8 +1404,8 @@ &usb { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3g_1p2>; - vdda-pll-supply = <&vreg_l2d_0p88>; + vdda-phy-supply = <&vreg_l2d_0p88>; + vdda-pll-supply = <&vreg_l3g_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 801c46d55602..b56317cfa9fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -1132,8 +1132,8 @@ &usb { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3g_1p2>; - vdda-pll-supply = <&vreg_l2d_0p88>; + vdda-phy-supply = <&vreg_l2d_0p88>; + vdda-pll-supply = <&vreg_l3g_1p2>; status = "okay"; }; From 9d883d21fc12c873eee2f864f706c38a289bef59 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:20 +0200 Subject: [PATCH 850/864] arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 6339e41fa39b ("arm64: dts: qcom: sar2130p: add QAR2130P board file") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-22-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 74778a5b19ba..80428c0b3b4e 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -551,8 +551,8 @@ &usb_1_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3a_1p2>; - vdda-pll-supply = <&vreg_l1a_0p91>; + vdda-phy-supply = <&vreg_l1a_0p91>; + vdda-pll-supply = <&vreg_l3a_1p2>; status = "okay"; }; From c1dfdea72a9f59b1bdad64b8ec9f918b6c1a721f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:21 +0200 Subject: [PATCH 851/864] arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.2V to vdda-phy and 0.88V to vdda-pll. Fix it by swapping the two supplies back. Fixes: b2f036a67580 ("arm64: dts: qcom: kaanpaali: Add USB support for MTP platform") Fixes: 01d15f5f6996 ("arm64: dts: qcom: kaanpaali: Add USB support for QRD platform") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-23-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index 7ccff3d03b78..6d817381bb37 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -1389,8 +1389,8 @@ &usb_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l1d_1p2>; - vdda-pll-supply = <&vreg_l4f_0p8>; + vdda-phy-supply = <&vreg_l4f_0p8>; + vdda-pll-supply = <&vreg_l1d_1p2>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts index 6efbe45605a0..abd3e9f8a3eb 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -884,8 +884,8 @@ &usb_hsphy { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l1d_1p2>; - vdda-pll-supply = <&vreg_l4f_0p8>; + vdda-phy-supply = <&vreg_l4f_0p8>; + vdda-pll-supply = <&vreg_l1d_1p2>; status = "okay"; }; From c3c6b388edba50aad0d41b0b2a5e50482e320611 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:22 +0200 Subject: [PATCH 852/864] arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be the lower voltage (~0.8V) and the vdda-pll supply to be the higher voltage (~1.2V), as used by the DisplayPort QMP PHY on this SoC. But these two supplies are swapped for the USB QMP PHYs on this board, feeding 1.2V to vdda-phy and 0.72V/0.83V to vdda-pll. Fix it by swapping the two supplies back. Fixes: c8b63029455b ("arm64: dts: qcom: glymur-crd: Enable USB support") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-24-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 47fa3ae301ac..e27c697e3170 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -1167,8 +1167,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l3f_e0_0p72>; + vdda-phy-supply = <&vreg_l3f_e0_0p72>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l2f_e0_0p82>; status = "okay"; @@ -1196,8 +1196,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l1h_e0_0p89>; + vdda-phy-supply = <&vreg_l1h_e0_0p89>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l2f_e0_0p82>; status = "okay"; @@ -1243,16 +1243,16 @@ &usb_mp_hsphy1 { }; &usb_mp_qmpphy0 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; + vdda-phy-supply = <&vreg_l2h_e0_0p72>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l4f_e1_1p08>; status = "okay"; }; &usb_mp_qmpphy1 { - vdda-phy-supply = <&vreg_l4h_e0_1p2>; - vdda-pll-supply = <&vreg_l2h_e0_0p72>; + vdda-phy-supply = <&vreg_l2h_e0_0p72>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; refgen-supply = <&vreg_l4f_e1_1p08>; status = "okay"; From 932113c3c77814b4001ad37ea4383b93bc385284 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:23 +0200 Subject: [PATCH 853/864] arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be the lower voltage (~0.8V) and the vdda-pll supply to be the higher voltage (~1.2V), as used by the PCIe and UFS QMP PHYs on this SoC. But these two supplies are swapped for the USB QMP PHYs on these boards, feeding 1.14V to vdda-phy and 0.72V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 76326da895b8 ("arm64: dts: qcom: lemans: Refactor ride/ride-r3 boards based on daughter cards") Fixes: 7bd68ef80661 ("arm64: dts: qcom: lemans-evk: Enable first USB controller in device mode") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-25-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++-- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 0c53640c42a6..a45485b54a5b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -1170,8 +1170,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l1c>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index cefb8ff00806..144f117ba511 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -1103,8 +1103,8 @@ &usb_0_hsphy { }; &usb_0_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l1c>; status = "okay"; }; @@ -1126,8 +1126,8 @@ &usb_1_hsphy { }; &usb_1_qmpphy { - vdda-phy-supply = <&vreg_l1c>; - vdda-pll-supply = <&vreg_l7a>; + vdda-phy-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l1c>; status = "okay"; }; From 6b1195eeb204b455973fb05e10563a63bdd71c57 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:24 +0200 Subject: [PATCH 854/864] arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be the lower voltage (~0.8V) and the vdda-pll supply to be the higher voltage (~1.2V), as used by the UFS QMP PHY on this SoC. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.15V to vdda-phy and 0.72V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 49dab7311f57 ("arm64: dts: qcom: eliza-mtp: Enable USB and ADSP support") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-26-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/eliza-mtp.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza-mtp.dts b/arch/arm64/boot/dts/qcom/eliza-mtp.dts index 5abc23b9b676..868ae6c34830 100644 --- a/arch/arm64/boot/dts/qcom/eliza-mtp.dts +++ b/arch/arm64/boot/dts/qcom/eliza-mtp.dts @@ -579,8 +579,8 @@ &usb { }; &usb_dp_qmpphy { - vdda-phy-supply = <&vreg_l3g>; - vdda-pll-supply = <&vreg_l7k>; + vdda-phy-supply = <&vreg_l7k>; + vdda-pll-supply = <&vreg_l3g>; status = "okay"; }; From 3b50c16faa8452fd7ff021919c669c7b38227ca4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:25 +0200 Subject: [PATCH 855/864] arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB and UFS QMP PHYs on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 12dd4ebda47a ("arm64: dts: qcom: Fix usb entries for SA8155p adp board") Fixes: 5b85e8f2225c ("arm64: dts: qcom: sa8155p-adp: Add base dts file") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-27-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 388d5ecee949..3e22ee8b5092 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -428,8 +428,8 @@ &ufs_mem_hc { &ufs_mem_phy { status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vreg_l5a_0p88>; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l8c_1p2>; }; &usb_1 { @@ -474,8 +474,8 @@ &usb_2_hsphy { &usb_2_qmpphy { status = "okay"; - vdda-phy-supply = <&vreg_l8c_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; + vdda-phy-supply = <&vdda_usb_ss_dp_core_1>; + vdda-pll-supply = <&vreg_l8c_1p2>; }; &pcie0 { From b426fedcef8c277574bd7beed0ae9d482c03605a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 3 Aug 2026 08:34:26 +0200 Subject: [PATCH 856/864] arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies The QMP PHY expects the vdda-phy supply to be around 0.88V and the vdda-pll supply to be 1.2V. But these two supplies are swapped for the USB QMP PHY on this board, feeding 1.2V to vdda-phy and 0.9V to vdda-pll. Fix it by swapping the two supplies back. Fixes: 0f9e6db8a223 ("arm64: dts: qcom: talos-evk: Add support for QCS615 talos evk board") Reported-by: Konrad Dybcio Assisted-by: Claude:opus-4-8 Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20260803-phy-supply-fix-v1-28-5880630cde3e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index a057a7271480..a31bed7fad07 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -597,8 +597,8 @@ &usb_qmpphy { }; &usb_qmpphy_2 { - vdda-phy-supply = <&vreg_l11a>; - vdda-pll-supply = <&vreg_l5a>; + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l11a>; status = "okay"; }; From 197df050a10fe216971b45a79f07195c86a02236 Mon Sep 17 00:00:00 2001 From: Meghana Malladi Date: Mon, 6 Jul 2026 14:52:29 +0530 Subject: [PATCH 857/864] arm64: dts: ti: k3-am64: Fix MDIO clock reference for ICSSG0 node MDIO clock index changed from 62:3 to 81:0 to match proper clock definition in the SoC device tree. Clock Id 81:0 belongs to ICSSG0 core clock, where as 62 belongs to EQEP2 device. See: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am64x/clocks.html Fixes: c9087e3898a1d0 ("arm64: dts: ti: k3-am64-main: Add ICSSG nodes") Signed-off-by: Meghana Malladi Link: https://patch.msgid.link/20260706092229.82674-1-m-malladi@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 1b1d3970888b..a9a83781d40f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1401,7 +1401,7 @@ tx_pru0_1: txpru@c000 { icssg0_mdio: mdio@32400 { compatible = "ti,davinci_mdio"; reg = <0x32400 0x100>; - clocks = <&k3_clks 62 3>; + clocks = <&k3_clks 81 0>; clock-names = "fck"; #address-cells = <1>; #size-cells = <0>; From c8c3575e3952c85cfd47f6b8080de6f4edc1462d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 6 Aug 2026 09:02:46 +0200 Subject: [PATCH 858/864] arm64: dts: ti: Correct white-space style Correct a few white-space issues, like missing space before bracket '{' character or spurious space, which will be flagged by dt-check-style ("redundant-whitespace" warning). No functional changes. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260806070245.40219-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts | 2 +- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts index adf4da7dfa2d..a1a878d88e96 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-sm.dts @@ -54,7 +54,7 @@ AM65X_IOPAD(0x01d8, PIN_OUTPUT, 7) /* (AH12) GPIO1_22 */ >; }; - main_spi0_pins: main-spi0-default-pins { + main_spi0_pins: main-spi0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts index dc0d3cf2f985..3e2377160d82 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts @@ -143,7 +143,7 @@ &main_cpsw0 { }; /* Aquila ETH_2 SGMII PHY */ -&main_cpsw0_port8 { +&main_cpsw0_port8 { phy-handle = <&cpsw0_port8_phy4>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 689ba2ff81f7..d66e71db4697 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -1068,7 +1068,7 @@ &dss_ports { #address-cells = <1>; #size-cells = <0>; - port@0 { + port@0 { reg = <0>; dpi0_out: endpoint { From 0c2a8eed95160e41b367a1fa605a2c1b24a9639a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tom=C3=A1=C5=A1=20Macholda?= Date: Tue, 7 Jul 2026 23:08:29 +0200 Subject: [PATCH 859/864] arm64: dts: turris-mox: fix usb3 phys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After commit 00e6d608fe80b0f6 ("arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node") swapped USB3 PHY order, USB initialization breaks on Turris MOX. This regression was exposed by commit 91ddf6f722084383 ("phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register access") which made USB2 devices not work at all. Fix the issue by explicitly adding all USB3 PHYs and PHY names to Turris MOX device-tree. Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Signed-off-by: Tomáš Macholda Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index f4d73c8b1a6d..bd00e7df87c6 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -290,7 +290,8 @@ connector { &usb3 { status = "okay"; - phys = <&comphy2 0>; + phys = <&usb2_utmi_otg_phy>, <&comphy2 0>; + phy-names = "usb2-phy", "usb3-phy"; }; &mdio { From ef65cf08bd1aa723de2854d02fb8eb8cca273c90 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 8 Jul 2026 17:50:03 -0700 Subject: [PATCH 860/864] ARM: dts: helios4: add vcc-supply to EEPROM The at24 driver requests a 'vcc' supply for the EEPROM, producing 'supply vcc not found, using dummy regulator' at boot when the property is missing. The EEPROM sits on the Helios 4 and is powered by the same always-on 3.3V rail used by other on-board I2C devices. Add vcc-supply = <®_3p3v> to silence the warning. Fixes: ced8025b569e ("ARM: dts: armada388-helios4") Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-388-helios4.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/marvell/armada-388-helios4.dts b/arch/arm/boot/dts/marvell/armada-388-helios4.dts index ec134e22bae3..61fc3adab54b 100644 --- a/arch/arm/boot/dts/marvell/armada-388-helios4.dts +++ b/arch/arm/boot/dts/marvell/armada-388-helios4.dts @@ -201,6 +201,10 @@ temp_sensor: temp@4c { reg = <0x4c>; vcc-supply = <®_3p3v>; }; + + eeprom@53 { + vcc-supply = <®_3p3v>; + }; }; i2c@11100 { From c23988f84496e937dd255564cb30bec67608dcc6 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 8 Jul 2026 17:50:04 -0700 Subject: [PATCH 861/864] ARM: dts: helios4: add vcc-supply to GPIO expander The pca953x driver requests a 'vcc' supply, producing: pca953x 0-0020: supply vcc not found, using dummy regulator The PCA9655 (PCA9555-compatible) expander is powered by the same always-on 3.3V rail as the other I2C devices on the bus. Add vcc-supply = <®_3p3v> to silence the warning. Fixes: ced8025b569e ("ARM: dts: armada388-helios4") Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-388-helios4.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/marvell/armada-388-helios4.dts b/arch/arm/boot/dts/marvell/armada-388-helios4.dts index 61fc3adab54b..21df1b9e3900 100644 --- a/arch/arm/boot/dts/marvell/armada-388-helios4.dts +++ b/arch/arm/boot/dts/marvell/armada-388-helios4.dts @@ -169,6 +169,7 @@ expander0: gpio-expander@20 { gpio-controller; #gpio-cells = <2>; reg = <0x20>; + vcc-supply = <®_3p3v>; pinctrl-names = "default"; pinctrl-0 = <&pca0_pins>; interrupt-parent = <&gpio0>; From 7a90520e8c9a8f48fe6f3e741cf34d8c2b6dbc61 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Wed, 8 Jul 2026 17:50:05 -0700 Subject: [PATCH 862/864] ARM: dts: helios4: add SATA regulator supplies The ahci-mvebu driver and libahci_platform request three supplies on SATA controller and port nodes: - ahci-supply (controller power) - phy-supply (PHY power) - target-supply (disk power per port) Without them the regulator core prints notices at boot, e.g.: supply ahci not found, using dummy regulator supply phy not found, using dummy regulator supply target not found, using dummy regulator The SATA controller and PHY inside the Armada 388 SoC are powered by the 3.3V I/O rail; the four disk bays are powered by the 5V HDD rail. Wire the existing fixed regulators accordingly. Fixes: ced8025b569e ("ARM: dts: armada388-helios4") Assisted-by: opencode:big-pickle Signed-off-by: Rosen Penev Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/marvell/armada-388-helios4.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/marvell/armada-388-helios4.dts b/arch/arm/boot/dts/marvell/armada-388-helios4.dts index 21df1b9e3900..003b0708e965 100644 --- a/arch/arm/boot/dts/marvell/armada-388-helios4.dts +++ b/arch/arm/boot/dts/marvell/armada-388-helios4.dts @@ -222,13 +222,17 @@ sata@a8000 { status = "okay"; #address-cells = <1>; #size-cells = <0>; + ahci-supply = <®_3p3v>; + phy-supply = <®_3p3v>; sata0: sata-port@0 { reg = <0>; + target-supply = <®_5p0v_hdd>; }; sata1: sata-port@1 { reg = <1>; + target-supply = <®_5p0v_hdd>; }; }; @@ -236,13 +240,17 @@ sata@e0000 { status = "okay"; #address-cells = <1>; #size-cells = <0>; + ahci-supply = <®_3p3v>; + phy-supply = <®_3p3v>; sata2: sata-port@0 { reg = <0>; + target-supply = <®_5p0v_hdd>; }; sata3: sata-port@1 { reg = <1>; + target-supply = <®_5p0v_hdd>; }; }; From 9e758d3be022700b829e63442ba755f0db233231 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 3 Aug 2026 11:17:41 +0200 Subject: [PATCH 863/864] Documentation/process: maintainer-soc: Mention expectation about dt-check-style Any new DTS code should pass dt-check-style 'relaxed' mode without warnings and should have addressed most of applicable 'strict' mode ones. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20260803091740.232536-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Arnd Bergmann --- Documentation/process/maintainer-soc.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/process/maintainer-soc.rst b/Documentation/process/maintainer-soc.rst index fa91dfc53783..96a87794583b 100644 --- a/Documentation/process/maintainer-soc.rst +++ b/Documentation/process/maintainer-soc.rst @@ -170,6 +170,10 @@ For new platforms, or additions to existing ones, ``make dtbs_check`` should not add any new warnings. For RISC-V and Samsung SoC, ``make dtbs_check W=1`` is required to not add any new warnings. +Additionally new code must not have any scripts/dtc/dt-check-style warnings in +'relaxed' mode and should have addressed most of the warnings in 'strict' mode +(the latter mode might produce false positives). + Branches and Pull Requests ~~~~~~~~~~~~~~~~~~~~~~~~~~ From 1f5d8228ca2c06ee1baa81b40cdba824ed768d95 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 10 Aug 2026 16:59:07 +0200 Subject: [PATCH 864/864] Revert "riscv: dts: spacemit: k3: add i2s0-i2s5 nodes" This reverts commit cd01c677869affe1b01403ca2fad8fc0fe85e8bd, which caused a build failure: Lexical error: ../arch/riscv/boot/dts/spacemit/k3.dtsi:1181.20-39 Unexpected 'CLK_MPMU_I2S_SYSCLK' Signed-off-by: Arnd Bergmann --- arch/riscv/boot/dts/spacemit/k3.dtsi | 119 --------------------------- 1 file changed, 119 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi index 0eb24fac4733..c3f2dce0969c 100644 --- a/arch/riscv/boot/dts/spacemit/k3.dtsi +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -1170,125 +1170,6 @@ spi1: spi@d4040800 { status = "disabled"; }; - i2s0: i2s@d4026000 { - compatible = "spacemit,k3-i2s"; - reg = <0x0 0xd4026000 0x0 0x30>; - clocks = <&syscon_mpmu CLK_MPMU_I2S0_SYSCLK>, - <&syscon_apbc CLK_APBC_I2S0_BCLK>, - <&syscon_apbc CLK_APBC_I2S0_BUS>, - <&syscon_apbc CLK_APBC_I2S0>, - <&syscon_mpmu CLK_MPMU_I2S0_SYSCLK_DIV>, - <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, - <&syscon_mpmu CLK_MPMU_I2S_BCLK>; - clock-names = "sysclk", "bclk", "bus", "func", - "sysclk_div", "c_sysclk", "c_bclk"; - dmas = <&pdma 21>, <&pdma 22>; - dma-names = "tx", "rx"; - resets = <&syscon_apbc RESET_APBC_I2S0>; - #sound-dai-cells = <0>; - - status = "disabled"; - }; - - i2s1: i2s@d4026800 { - compatible = "spacemit,k3-i2s"; - reg = <0x0 0xd4026800 0x0 0x30>; - clocks = <&syscon_mpmu CLK_MPMU_I2S1_SYSCLK>, - <&syscon_apbc CLK_APBC_I2S1_BCLK>, - <&syscon_apbc CLK_APBC_I2S1_BUS>, - <&syscon_apbc CLK_APBC_I2S1>, - <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, - <&syscon_mpmu CLK_MPMU_I2S_BCLK>; - clock-names = "sysclk", "bclk", "bus", "func", - "c_sysclk", "c_bclk"; - dmas = <&pdma 23>, <&pdma 24>; - dma-names = "tx", "rx"; - resets = <&syscon_apbc RESET_APBC_I2S1>; - #sound-dai-cells = <0>; - - status = "disabled"; - }; - - i2s2: i2s@d4027000 { - compatible = "spacemit,k3-i2s"; - reg = <0x0 0xd4027000 0x0 0x30>; - clocks = <&syscon_mpmu CLK_MPMU_I2S2_SYSCLK>, - <&syscon_apbc CLK_APBC_I2S2_BCLK>, - <&syscon_apbc CLK_APBC_I2S2_BUS>, - <&syscon_apbc CLK_APBC_I2S2>, - <&syscon_mpmu CLK_MPMU_I2S2_SYSCLK_DIV>, - <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, - <&syscon_mpmu CLK_MPMU_I2S_BCLK>; - clock-names = "sysclk", "bclk", "bus", "func", - "sysclk_div", "c_sysclk", "c_bclk"; - dmas = <&pdma 56>, <&pdma 57>; - dma-names = "tx", "rx"; - resets = <&syscon_apbc RESET_APBC_I2S2>; - #sound-dai-cells = <0>; - - status = "disabled"; - }; - - i2s3: i2s@d4027800 { - compatible = "spacemit,k3-i2s"; - reg = <0x0 0xd4027800 0x0 0x30>; - clocks = <&syscon_mpmu CLK_MPMU_I2S3_SYSCLK>, - <&syscon_apbc CLK_APBC_I2S3_BCLK>, - <&syscon_apbc CLK_APBC_I2S3_BUS>, - <&syscon_apbc CLK_APBC_I2S3>, - <&syscon_mpmu CLK_MPMU_I2S3_SYSCLK_DIV>, - <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, - <&syscon_mpmu CLK_MPMU_I2S_BCLK>; - clock-names = "sysclk", "bclk", "bus", "func", - "sysclk_div", "c_sysclk", "c_bclk"; - dmas = <&pdma 58>, <&pdma 59>; - dma-names = "tx", "rx"; - resets = <&syscon_apbc RESET_APBC_I2S3>; - #sound-dai-cells = <0>; - - status = "disabled"; - }; - - i2s4: i2s@d4041000 { - compatible = "spacemit,k3-i2s"; - reg = <0x0 0xd4041000 0x0 0x30>; - clocks = <&syscon_mpmu CLK_MPMU_I2S4_SYSCLK>, - <&syscon_apbc CLK_APBC_I2S4_BCLK>, - <&syscon_apbc CLK_APBC_I2S4_BUS>, - <&syscon_apbc CLK_APBC_I2S4>, - <&syscon_mpmu CLK_MPMU_I2S4_SYSCLK_DIV>, - <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, - <&syscon_mpmu CLK_MPMU_I2S_BCLK>; - clock-names = "sysclk", "bclk", "bus", "func", - "sysclk_div", "c_sysclk", "c_bclk"; - dmas = <&pdma 60>, <&pdma 61>; - dma-names = "tx", "rx"; - resets = <&syscon_apbc RESET_APBC_I2S4>; - #sound-dai-cells = <0>; - - status = "disabled"; - }; - - i2s5: i2s@d4041800 { - compatible = "spacemit,k3-i2s"; - reg = <0x0 0xd4041800 0x0 0x30>; - clocks = <&syscon_mpmu CLK_MPMU_I2S5_SYSCLK>, - <&syscon_apbc CLK_APBC_I2S5_BCLK>, - <&syscon_apbc CLK_APBC_I2S5_BUS>, - <&syscon_apbc CLK_APBC_I2S5>, - <&syscon_mpmu CLK_MPMU_I2S5_SYSCLK_DIV>, - <&syscon_mpmu CLK_MPMU_I2S_SYSCLK>, - <&syscon_mpmu CLK_MPMU_I2S_BCLK>; - clock-names = "sysclk", "bclk", "bus", "func", - "sysclk_div", "c_sysclk", "c_bclk"; - dmas = <&pdma 62>, <&pdma 63>; - dma-names = "tx", "rx"; - resets = <&syscon_apbc RESET_APBC_I2S5>; - #sound-dai-cells = <0>; - - status = "disabled"; - }; - syscon_mpmu: system-controller@d4050000 { compatible = "spacemit,k3-syscon-mpmu"; reg = <0x0 0xd4050000 0x0 0x10000>;