From cbe415e116ed1cd9ad2a115683688b797cafb14a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 24 Aug 2026 12:23:30 +0530 Subject: [PATCH] clk: qcom: segcc-nord: Add EMAC CNOC APB clocks for Nord SoC Add the EMAC0 and EMAC1 CNOC APB clocks to the SE_GCC clock controller on the Qualcomm Nord SoC. These branch clocks gate the config NoC APB access to the two EMAC controllers and are required for register access to the Ethernet MACs. Signed-off-by: Taniya Das Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Tested-by: Shawn Guo Link: https://patch.msgid.link/20260824-nords_emac_apb_clk-v1-2-290767386bf5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/segcc-nord.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/clk/qcom/segcc-nord.c b/drivers/clk/qcom/segcc-nord.c index 98b53311d333..ef97da3852e3 100644 --- a/drivers/clk/qcom/segcc-nord.c +++ b/drivers/clk/qcom/segcc-nord.c @@ -747,6 +747,21 @@ static struct clk_branch se_gcc_emac0_cc_sgmiiphy_tx_clk = { }, }; +static struct clk_branch se_gcc_emac0_cnoc_apb_clk = { + .halt_reg = 0x24018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x24018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x24018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac0_cnoc_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch se_gcc_emac0_phy_aux_clk = { .halt_reg = 0x2402c, .halt_check = BRANCH_HALT, @@ -894,6 +909,21 @@ static struct clk_branch se_gcc_emac1_cc_sgmiiphy_tx_clk = { }, }; +static struct clk_branch se_gcc_emac1_cnoc_apb_clk = { + .halt_reg = 0x25018, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x25018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x25018, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data) { + .name = "se_gcc_emac1_cnoc_apb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch se_gcc_emac1_phy_aux_clk = { .halt_reg = 0x2502c, .halt_check = BRANCH_HALT, @@ -1458,6 +1488,7 @@ static struct clk_regmap *se_gcc_nord_clocks[] = { [SE_GCC_EMAC0_AXI_CLK] = &se_gcc_emac0_axi_clk.clkr, [SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac0_cc_sgmiiphy_rx_clk.clkr, [SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac0_cc_sgmiiphy_tx_clk.clkr, + [SE_GCC_EMAC0_CNOC_APB_CLK] = &se_gcc_emac0_cnoc_apb_clk.clkr, [SE_GCC_EMAC0_PHY_AUX_CLK] = &se_gcc_emac0_phy_aux_clk.clkr, [SE_GCC_EMAC0_PHY_AUX_CLK_SRC] = &se_gcc_emac0_phy_aux_clk_src.clkr, [SE_GCC_EMAC0_PTP_CLK] = &se_gcc_emac0_ptp_clk.clkr, @@ -1471,6 +1502,7 @@ static struct clk_regmap *se_gcc_nord_clocks[] = { [SE_GCC_EMAC1_AXI_CLK] = &se_gcc_emac1_axi_clk.clkr, [SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK] = &se_gcc_emac1_cc_sgmiiphy_rx_clk.clkr, [SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK] = &se_gcc_emac1_cc_sgmiiphy_tx_clk.clkr, + [SE_GCC_EMAC1_CNOC_APB_CLK] = &se_gcc_emac1_cnoc_apb_clk.clkr, [SE_GCC_EMAC1_PHY_AUX_CLK] = &se_gcc_emac1_phy_aux_clk.clkr, [SE_GCC_EMAC1_PHY_AUX_CLK_SRC] = &se_gcc_emac1_phy_aux_clk_src.clkr, [SE_GCC_EMAC1_PTP_CLK] = &se_gcc_emac1_ptp_clk.clkr,