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clk: meson: axg: spread spectrum is on mpll2

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[ Upstream commit dc4e62d373 ]

After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.

Fixes: 78b4af312f ("clk: meson-axg: add clock controller drivers")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Jerome Brunet 2019-05-13 14:31:11 +02:00 committed by Greg Kroah-Hartman
parent 3dffd74823
commit cbd69e7ae1
1 changed files with 5 additions and 5 deletions
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10
drivers/clk/meson/axg.c
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@ -461,11 +461,6 @@ static struct clk_regmap axg_mpll0_div = {
.shift = 16,
.width = 9,
},
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift = 25,
.width = 1,
},
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 0,
@ -560,6 +555,11 @@ static struct clk_regmap axg_mpll2_div = {
.shift = 16,
.width = 9,
},
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift = 25,
.width = 1,
},
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 2,